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TARGET_ARCH_MAX/stm32f407xx.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
89:552587b429a1 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f407xx.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 89:552587b429a1 5 * @version V2.1.0
bogdanm 89:552587b429a1 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
bogdanm 89:552587b429a1 8 *
bogdanm 89:552587b429a1 9 * This file contains:
bogdanm 89:552587b429a1 10 * - Data structures and the address mapping for all peripherals
bogdanm 89:552587b429a1 11 * - Peripheral's registers declarations and bits definition
bogdanm 89:552587b429a1 12 * - Macros to access peripheral’s registers hardware
bogdanm 89:552587b429a1 13 *
bogdanm 89:552587b429a1 14 ******************************************************************************
bogdanm 89:552587b429a1 15 * @attention
bogdanm 89:552587b429a1 16 *
bogdanm 89:552587b429a1 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 18 *
bogdanm 89:552587b429a1 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 20 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 22 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 25 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 27 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 28 * without specific prior written permission.
bogdanm 89:552587b429a1 29 *
bogdanm 89:552587b429a1 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 40 *
bogdanm 89:552587b429a1 41 ******************************************************************************
bogdanm 89:552587b429a1 42 */
bogdanm 89:552587b429a1 43
bogdanm 89:552587b429a1 44 /** @addtogroup CMSIS
bogdanm 89:552587b429a1 45 * @{
bogdanm 89:552587b429a1 46 */
bogdanm 89:552587b429a1 47
bogdanm 89:552587b429a1 48 /** @addtogroup stm32f407xx
bogdanm 89:552587b429a1 49 * @{
bogdanm 89:552587b429a1 50 */
bogdanm 89:552587b429a1 51
bogdanm 89:552587b429a1 52 #ifndef __STM32F407xx_H
bogdanm 89:552587b429a1 53 #define __STM32F407xx_H
bogdanm 89:552587b429a1 54
bogdanm 89:552587b429a1 55 #ifdef __cplusplus
bogdanm 89:552587b429a1 56 extern "C" {
bogdanm 89:552587b429a1 57 #endif /* __cplusplus */
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59
bogdanm 89:552587b429a1 60 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 89:552587b429a1 61 * @{
bogdanm 89:552587b429a1 62 */
bogdanm 89:552587b429a1 63
bogdanm 89:552587b429a1 64 /**
bogdanm 89:552587b429a1 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 89:552587b429a1 66 */
bogdanm 89:552587b429a1 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 89:552587b429a1 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
bogdanm 89:552587b429a1 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
bogdanm 89:552587b429a1 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 89:552587b429a1 71 #define __FPU_PRESENT 1 /*!< FPU present */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 /**
bogdanm 89:552587b429a1 74 * @}
bogdanm 89:552587b429a1 75 */
bogdanm 89:552587b429a1 76
bogdanm 89:552587b429a1 77 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 89:552587b429a1 78 * @{
bogdanm 89:552587b429a1 79 */
bogdanm 89:552587b429a1 80
bogdanm 89:552587b429a1 81 /**
bogdanm 89:552587b429a1 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm 89:552587b429a1 83 * in @ref Library_configuration_section
bogdanm 89:552587b429a1 84 */
bogdanm 89:552587b429a1 85 typedef enum
bogdanm 89:552587b429a1 86 {
bogdanm 89:552587b429a1 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 89:552587b429a1 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 89:552587b429a1 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 89:552587b429a1 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 89:552587b429a1 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 89:552587b429a1 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 89:552587b429a1 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 89:552587b429a1 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 89:552587b429a1 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 89:552587b429a1 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 89:552587b429a1 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 89:552587b429a1 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 89:552587b429a1 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
bogdanm 89:552587b429a1 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
bogdanm 89:552587b429a1 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 89:552587b429a1 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 89:552587b429a1 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 89:552587b429a1 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 89:552587b429a1 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 89:552587b429a1 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 89:552587b429a1 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 89:552587b429a1 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
bogdanm 89:552587b429a1 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
bogdanm 89:552587b429a1 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
bogdanm 89:552587b429a1 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
bogdanm 89:552587b429a1 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
bogdanm 89:552587b429a1 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
bogdanm 89:552587b429a1 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
bogdanm 89:552587b429a1 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
bogdanm 89:552587b429a1 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
bogdanm 89:552587b429a1 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
bogdanm 89:552587b429a1 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 89:552587b429a1 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 89:552587b429a1 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 89:552587b429a1 121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
bogdanm 89:552587b429a1 122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
bogdanm 89:552587b429a1 123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 89:552587b429a1 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 89:552587b429a1 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 89:552587b429a1 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 89:552587b429a1 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 89:552587b429a1 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 89:552587b429a1 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 89:552587b429a1 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 89:552587b429a1 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 89:552587b429a1 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 89:552587b429a1 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 89:552587b429a1 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 89:552587b429a1 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 89:552587b429a1 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 89:552587b429a1 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 89:552587b429a1 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 89:552587b429a1 139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
bogdanm 89:552587b429a1 140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
bogdanm 89:552587b429a1 141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
bogdanm 89:552587b429a1 142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
bogdanm 89:552587b429a1 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 89:552587b429a1 144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
bogdanm 89:552587b429a1 145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 89:552587b429a1 146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 89:552587b429a1 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 89:552587b429a1 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 89:552587b429a1 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 89:552587b429a1 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 89:552587b429a1 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 89:552587b429a1 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
bogdanm 89:552587b429a1 153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
bogdanm 89:552587b429a1 154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
bogdanm 89:552587b429a1 155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
bogdanm 89:552587b429a1 156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
bogdanm 89:552587b429a1 157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
bogdanm 89:552587b429a1 158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
bogdanm 89:552587b429a1 159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
bogdanm 89:552587b429a1 160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
bogdanm 89:552587b429a1 161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
bogdanm 89:552587b429a1 162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
bogdanm 89:552587b429a1 163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
bogdanm 89:552587b429a1 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
bogdanm 89:552587b429a1 165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
bogdanm 89:552587b429a1 166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
bogdanm 89:552587b429a1 167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
bogdanm 89:552587b429a1 168 USART6_IRQn = 71, /*!< USART6 global interrupt */
bogdanm 89:552587b429a1 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
bogdanm 89:552587b429a1 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
bogdanm 89:552587b429a1 171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
bogdanm 89:552587b429a1 172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
bogdanm 89:552587b429a1 173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
bogdanm 89:552587b429a1 174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
bogdanm 89:552587b429a1 175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
bogdanm 89:552587b429a1 176 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
bogdanm 89:552587b429a1 177 FPU_IRQn = 81 /*!< FPU global interrupt */
bogdanm 89:552587b429a1 178 } IRQn_Type;
bogdanm 89:552587b429a1 179
bogdanm 89:552587b429a1 180 /**
bogdanm 89:552587b429a1 181 * @}
bogdanm 89:552587b429a1 182 */
bogdanm 89:552587b429a1 183
bogdanm 89:552587b429a1 184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 89:552587b429a1 185 #include "system_stm32f4xx.h"
bogdanm 89:552587b429a1 186 #include <stdint.h>
bogdanm 89:552587b429a1 187
bogdanm 89:552587b429a1 188 /** @addtogroup Peripheral_registers_structures
bogdanm 89:552587b429a1 189 * @{
bogdanm 89:552587b429a1 190 */
bogdanm 89:552587b429a1 191
bogdanm 89:552587b429a1 192 /**
bogdanm 89:552587b429a1 193 * @brief Analog to Digital Converter
bogdanm 89:552587b429a1 194 */
bogdanm 89:552587b429a1 195
bogdanm 89:552587b429a1 196 typedef struct
bogdanm 89:552587b429a1 197 {
bogdanm 89:552587b429a1 198 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
bogdanm 89:552587b429a1 199 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
bogdanm 89:552587b429a1 200 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
bogdanm 89:552587b429a1 201 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
bogdanm 89:552587b429a1 202 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
bogdanm 89:552587b429a1 203 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
bogdanm 89:552587b429a1 204 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
bogdanm 89:552587b429a1 205 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
bogdanm 89:552587b429a1 206 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
bogdanm 89:552587b429a1 207 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
bogdanm 89:552587b429a1 208 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
bogdanm 89:552587b429a1 209 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
bogdanm 89:552587b429a1 210 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
bogdanm 89:552587b429a1 211 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
bogdanm 89:552587b429a1 212 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
bogdanm 89:552587b429a1 213 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
bogdanm 89:552587b429a1 214 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
bogdanm 89:552587b429a1 215 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
bogdanm 89:552587b429a1 216 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
bogdanm 89:552587b429a1 217 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
bogdanm 89:552587b429a1 218 } ADC_TypeDef;
bogdanm 89:552587b429a1 219
bogdanm 89:552587b429a1 220 typedef struct
bogdanm 89:552587b429a1 221 {
bogdanm 89:552587b429a1 222 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
bogdanm 89:552587b429a1 223 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
bogdanm 89:552587b429a1 224 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 89:552587b429a1 225 AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm 89:552587b429a1 226 } ADC_Common_TypeDef;
bogdanm 89:552587b429a1 227
bogdanm 89:552587b429a1 228
bogdanm 89:552587b429a1 229 /**
bogdanm 89:552587b429a1 230 * @brief Controller Area Network TxMailBox
bogdanm 89:552587b429a1 231 */
bogdanm 89:552587b429a1 232
bogdanm 89:552587b429a1 233 typedef struct
bogdanm 89:552587b429a1 234 {
bogdanm 89:552587b429a1 235 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 89:552587b429a1 236 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 89:552587b429a1 237 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 89:552587b429a1 238 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 89:552587b429a1 239 } CAN_TxMailBox_TypeDef;
bogdanm 89:552587b429a1 240
bogdanm 89:552587b429a1 241 /**
bogdanm 89:552587b429a1 242 * @brief Controller Area Network FIFOMailBox
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244
bogdanm 89:552587b429a1 245 typedef struct
bogdanm 89:552587b429a1 246 {
bogdanm 89:552587b429a1 247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 89:552587b429a1 248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 89:552587b429a1 249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 89:552587b429a1 250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 89:552587b429a1 251 } CAN_FIFOMailBox_TypeDef;
bogdanm 89:552587b429a1 252
bogdanm 89:552587b429a1 253 /**
bogdanm 89:552587b429a1 254 * @brief Controller Area Network FilterRegister
bogdanm 89:552587b429a1 255 */
bogdanm 89:552587b429a1 256
bogdanm 89:552587b429a1 257 typedef struct
bogdanm 89:552587b429a1 258 {
bogdanm 89:552587b429a1 259 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 89:552587b429a1 260 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 89:552587b429a1 261 } CAN_FilterRegister_TypeDef;
bogdanm 89:552587b429a1 262
bogdanm 89:552587b429a1 263 /**
bogdanm 89:552587b429a1 264 * @brief Controller Area Network
bogdanm 89:552587b429a1 265 */
bogdanm 89:552587b429a1 266
bogdanm 89:552587b429a1 267 typedef struct
bogdanm 89:552587b429a1 268 {
bogdanm 89:552587b429a1 269 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 270 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 89:552587b429a1 271 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 89:552587b429a1 272 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 89:552587b429a1 273 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 89:552587b429a1 274 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 89:552587b429a1 275 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 89:552587b429a1 276 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 89:552587b429a1 277 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 89:552587b429a1 278 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 89:552587b429a1 279 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 89:552587b429a1 280 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 89:552587b429a1 281 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 89:552587b429a1 282 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 89:552587b429a1 283 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 89:552587b429a1 284 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 89:552587b429a1 285 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 89:552587b429a1 286 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 89:552587b429a1 287 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 89:552587b429a1 288 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 89:552587b429a1 289 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 89:552587b429a1 290 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 89:552587b429a1 291 } CAN_TypeDef;
bogdanm 89:552587b429a1 292
bogdanm 89:552587b429a1 293 /**
bogdanm 89:552587b429a1 294 * @brief CRC calculation unit
bogdanm 89:552587b429a1 295 */
bogdanm 89:552587b429a1 296
bogdanm 89:552587b429a1 297 typedef struct
bogdanm 89:552587b429a1 298 {
bogdanm 89:552587b429a1 299 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 89:552587b429a1 300 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 89:552587b429a1 301 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 89:552587b429a1 302 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 89:552587b429a1 303 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 89:552587b429a1 304 } CRC_TypeDef;
bogdanm 89:552587b429a1 305
bogdanm 89:552587b429a1 306 /**
bogdanm 89:552587b429a1 307 * @brief Digital to Analog Converter
bogdanm 89:552587b429a1 308 */
bogdanm 89:552587b429a1 309
bogdanm 89:552587b429a1 310 typedef struct
bogdanm 89:552587b429a1 311 {
bogdanm 89:552587b429a1 312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 89:552587b429a1 314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 89:552587b429a1 315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 89:552587b429a1 316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 89:552587b429a1 317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 89:552587b429a1 318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 89:552587b429a1 319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 89:552587b429a1 320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 89:552587b429a1 321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 89:552587b429a1 322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 89:552587b429a1 323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 89:552587b429a1 324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 89:552587b429a1 325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 89:552587b429a1 326 } DAC_TypeDef;
bogdanm 89:552587b429a1 327
bogdanm 89:552587b429a1 328 /**
bogdanm 89:552587b429a1 329 * @brief Debug MCU
bogdanm 89:552587b429a1 330 */
bogdanm 89:552587b429a1 331
bogdanm 89:552587b429a1 332 typedef struct
bogdanm 89:552587b429a1 333 {
bogdanm 89:552587b429a1 334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 89:552587b429a1 335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 89:552587b429a1 336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 89:552587b429a1 337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 89:552587b429a1 338 }DBGMCU_TypeDef;
bogdanm 89:552587b429a1 339
bogdanm 89:552587b429a1 340 /**
bogdanm 89:552587b429a1 341 * @brief DCMI
bogdanm 89:552587b429a1 342 */
bogdanm 89:552587b429a1 343
bogdanm 89:552587b429a1 344 typedef struct
bogdanm 89:552587b429a1 345 {
bogdanm 89:552587b429a1 346 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
bogdanm 89:552587b429a1 347 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
bogdanm 89:552587b429a1 348 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
bogdanm 89:552587b429a1 349 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
bogdanm 89:552587b429a1 350 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
bogdanm 89:552587b429a1 351 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
bogdanm 89:552587b429a1 352 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
bogdanm 89:552587b429a1 353 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
bogdanm 89:552587b429a1 354 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
bogdanm 89:552587b429a1 355 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
bogdanm 89:552587b429a1 356 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
bogdanm 89:552587b429a1 357 } DCMI_TypeDef;
bogdanm 89:552587b429a1 358
bogdanm 89:552587b429a1 359 /**
bogdanm 89:552587b429a1 360 * @brief DMA Controller
bogdanm 89:552587b429a1 361 */
bogdanm 89:552587b429a1 362
bogdanm 89:552587b429a1 363 typedef struct
bogdanm 89:552587b429a1 364 {
bogdanm 89:552587b429a1 365 __IO uint32_t CR; /*!< DMA stream x configuration register */
bogdanm 89:552587b429a1 366 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
bogdanm 89:552587b429a1 367 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
bogdanm 89:552587b429a1 368 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
bogdanm 89:552587b429a1 369 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
bogdanm 89:552587b429a1 370 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
bogdanm 89:552587b429a1 371 } DMA_Stream_TypeDef;
bogdanm 89:552587b429a1 372
bogdanm 89:552587b429a1 373 typedef struct
bogdanm 89:552587b429a1 374 {
bogdanm 89:552587b429a1 375 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
bogdanm 89:552587b429a1 376 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
bogdanm 89:552587b429a1 377 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
bogdanm 89:552587b429a1 378 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
bogdanm 89:552587b429a1 379 } DMA_TypeDef;
bogdanm 89:552587b429a1 380
bogdanm 89:552587b429a1 381
bogdanm 89:552587b429a1 382 /**
bogdanm 89:552587b429a1 383 * @brief Ethernet MAC
bogdanm 89:552587b429a1 384 */
bogdanm 89:552587b429a1 385
bogdanm 89:552587b429a1 386 typedef struct
bogdanm 89:552587b429a1 387 {
bogdanm 89:552587b429a1 388 __IO uint32_t MACCR;
bogdanm 89:552587b429a1 389 __IO uint32_t MACFFR;
bogdanm 89:552587b429a1 390 __IO uint32_t MACHTHR;
bogdanm 89:552587b429a1 391 __IO uint32_t MACHTLR;
bogdanm 89:552587b429a1 392 __IO uint32_t MACMIIAR;
bogdanm 89:552587b429a1 393 __IO uint32_t MACMIIDR;
bogdanm 89:552587b429a1 394 __IO uint32_t MACFCR;
bogdanm 89:552587b429a1 395 __IO uint32_t MACVLANTR; /* 8 */
bogdanm 89:552587b429a1 396 uint32_t RESERVED0[2];
bogdanm 89:552587b429a1 397 __IO uint32_t MACRWUFFR; /* 11 */
bogdanm 89:552587b429a1 398 __IO uint32_t MACPMTCSR;
bogdanm 89:552587b429a1 399 uint32_t RESERVED1[2];
bogdanm 89:552587b429a1 400 __IO uint32_t MACSR; /* 15 */
bogdanm 89:552587b429a1 401 __IO uint32_t MACIMR;
bogdanm 89:552587b429a1 402 __IO uint32_t MACA0HR;
bogdanm 89:552587b429a1 403 __IO uint32_t MACA0LR;
bogdanm 89:552587b429a1 404 __IO uint32_t MACA1HR;
bogdanm 89:552587b429a1 405 __IO uint32_t MACA1LR;
bogdanm 89:552587b429a1 406 __IO uint32_t MACA2HR;
bogdanm 89:552587b429a1 407 __IO uint32_t MACA2LR;
bogdanm 89:552587b429a1 408 __IO uint32_t MACA3HR;
bogdanm 89:552587b429a1 409 __IO uint32_t MACA3LR; /* 24 */
bogdanm 89:552587b429a1 410 uint32_t RESERVED2[40];
bogdanm 89:552587b429a1 411 __IO uint32_t MMCCR; /* 65 */
bogdanm 89:552587b429a1 412 __IO uint32_t MMCRIR;
bogdanm 89:552587b429a1 413 __IO uint32_t MMCTIR;
bogdanm 89:552587b429a1 414 __IO uint32_t MMCRIMR;
bogdanm 89:552587b429a1 415 __IO uint32_t MMCTIMR; /* 69 */
bogdanm 89:552587b429a1 416 uint32_t RESERVED3[14];
bogdanm 89:552587b429a1 417 __IO uint32_t MMCTGFSCCR; /* 84 */
bogdanm 89:552587b429a1 418 __IO uint32_t MMCTGFMSCCR;
bogdanm 89:552587b429a1 419 uint32_t RESERVED4[5];
bogdanm 89:552587b429a1 420 __IO uint32_t MMCTGFCR;
bogdanm 89:552587b429a1 421 uint32_t RESERVED5[10];
bogdanm 89:552587b429a1 422 __IO uint32_t MMCRFCECR;
bogdanm 89:552587b429a1 423 __IO uint32_t MMCRFAECR;
bogdanm 89:552587b429a1 424 uint32_t RESERVED6[10];
bogdanm 89:552587b429a1 425 __IO uint32_t MMCRGUFCR;
bogdanm 89:552587b429a1 426 uint32_t RESERVED7[334];
bogdanm 89:552587b429a1 427 __IO uint32_t PTPTSCR;
bogdanm 89:552587b429a1 428 __IO uint32_t PTPSSIR;
bogdanm 89:552587b429a1 429 __IO uint32_t PTPTSHR;
bogdanm 89:552587b429a1 430 __IO uint32_t PTPTSLR;
bogdanm 89:552587b429a1 431 __IO uint32_t PTPTSHUR;
bogdanm 89:552587b429a1 432 __IO uint32_t PTPTSLUR;
bogdanm 89:552587b429a1 433 __IO uint32_t PTPTSAR;
bogdanm 89:552587b429a1 434 __IO uint32_t PTPTTHR;
bogdanm 89:552587b429a1 435 __IO uint32_t PTPTTLR;
bogdanm 89:552587b429a1 436 __IO uint32_t RESERVED8;
bogdanm 89:552587b429a1 437 __IO uint32_t PTPTSSR;
bogdanm 89:552587b429a1 438 uint32_t RESERVED9[565];
bogdanm 89:552587b429a1 439 __IO uint32_t DMABMR;
bogdanm 89:552587b429a1 440 __IO uint32_t DMATPDR;
bogdanm 89:552587b429a1 441 __IO uint32_t DMARPDR;
bogdanm 89:552587b429a1 442 __IO uint32_t DMARDLAR;
bogdanm 89:552587b429a1 443 __IO uint32_t DMATDLAR;
bogdanm 89:552587b429a1 444 __IO uint32_t DMASR;
bogdanm 89:552587b429a1 445 __IO uint32_t DMAOMR;
bogdanm 89:552587b429a1 446 __IO uint32_t DMAIER;
bogdanm 89:552587b429a1 447 __IO uint32_t DMAMFBOCR;
bogdanm 89:552587b429a1 448 __IO uint32_t DMARSWTR;
bogdanm 89:552587b429a1 449 uint32_t RESERVED10[8];
bogdanm 89:552587b429a1 450 __IO uint32_t DMACHTDR;
bogdanm 89:552587b429a1 451 __IO uint32_t DMACHRDR;
bogdanm 89:552587b429a1 452 __IO uint32_t DMACHTBAR;
bogdanm 89:552587b429a1 453 __IO uint32_t DMACHRBAR;
bogdanm 89:552587b429a1 454 } ETH_TypeDef;
bogdanm 89:552587b429a1 455
bogdanm 89:552587b429a1 456 /**
bogdanm 89:552587b429a1 457 * @brief External Interrupt/Event Controller
bogdanm 89:552587b429a1 458 */
bogdanm 89:552587b429a1 459
bogdanm 89:552587b429a1 460 typedef struct
bogdanm 89:552587b429a1 461 {
bogdanm 89:552587b429a1 462 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 89:552587b429a1 463 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 89:552587b429a1 464 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 89:552587b429a1 465 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 89:552587b429a1 466 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 89:552587b429a1 467 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 89:552587b429a1 468 } EXTI_TypeDef;
bogdanm 89:552587b429a1 469
bogdanm 89:552587b429a1 470 /**
bogdanm 89:552587b429a1 471 * @brief FLASH Registers
bogdanm 89:552587b429a1 472 */
bogdanm 89:552587b429a1 473
bogdanm 89:552587b429a1 474 typedef struct
bogdanm 89:552587b429a1 475 {
bogdanm 89:552587b429a1 476 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 477 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 89:552587b429a1 478 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 89:552587b429a1 479 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 89:552587b429a1 480 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 89:552587b429a1 481 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
bogdanm 89:552587b429a1 482 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
bogdanm 89:552587b429a1 483 } FLASH_TypeDef;
bogdanm 89:552587b429a1 484
bogdanm 89:552587b429a1 485
bogdanm 89:552587b429a1 486 /**
bogdanm 89:552587b429a1 487 * @brief Flexible Static Memory Controller
bogdanm 89:552587b429a1 488 */
bogdanm 89:552587b429a1 489
bogdanm 89:552587b429a1 490 typedef struct
bogdanm 89:552587b429a1 491 {
bogdanm 89:552587b429a1 492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
bogdanm 89:552587b429a1 493 } FSMC_Bank1_TypeDef;
bogdanm 89:552587b429a1 494
bogdanm 89:552587b429a1 495 /**
bogdanm 89:552587b429a1 496 * @brief Flexible Static Memory Controller Bank1E
bogdanm 89:552587b429a1 497 */
bogdanm 89:552587b429a1 498
bogdanm 89:552587b429a1 499 typedef struct
bogdanm 89:552587b429a1 500 {
bogdanm 89:552587b429a1 501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
bogdanm 89:552587b429a1 502 } FSMC_Bank1E_TypeDef;
bogdanm 89:552587b429a1 503
bogdanm 89:552587b429a1 504 /**
bogdanm 89:552587b429a1 505 * @brief Flexible Static Memory Controller Bank2
bogdanm 89:552587b429a1 506 */
bogdanm 89:552587b429a1 507
bogdanm 89:552587b429a1 508 typedef struct
bogdanm 89:552587b429a1 509 {
bogdanm 89:552587b429a1 510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
bogdanm 89:552587b429a1 511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
bogdanm 89:552587b429a1 512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
bogdanm 89:552587b429a1 513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
bogdanm 89:552587b429a1 514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
bogdanm 89:552587b429a1 515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
bogdanm 89:552587b429a1 516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
bogdanm 89:552587b429a1 517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
bogdanm 89:552587b429a1 518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
bogdanm 89:552587b429a1 519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
bogdanm 89:552587b429a1 520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
bogdanm 89:552587b429a1 521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
bogdanm 89:552587b429a1 522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
bogdanm 89:552587b429a1 523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
bogdanm 89:552587b429a1 524 } FSMC_Bank2_3_TypeDef;
bogdanm 89:552587b429a1 525
bogdanm 89:552587b429a1 526 /**
bogdanm 89:552587b429a1 527 * @brief Flexible Static Memory Controller Bank4
bogdanm 89:552587b429a1 528 */
bogdanm 89:552587b429a1 529
bogdanm 89:552587b429a1 530 typedef struct
bogdanm 89:552587b429a1 531 {
bogdanm 89:552587b429a1 532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
bogdanm 89:552587b429a1 533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
bogdanm 89:552587b429a1 534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
bogdanm 89:552587b429a1 535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
bogdanm 89:552587b429a1 536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
bogdanm 89:552587b429a1 537 } FSMC_Bank4_TypeDef;
bogdanm 89:552587b429a1 538
bogdanm 89:552587b429a1 539
bogdanm 89:552587b429a1 540 /**
bogdanm 89:552587b429a1 541 * @brief General Purpose I/O
bogdanm 89:552587b429a1 542 */
bogdanm 89:552587b429a1 543
bogdanm 89:552587b429a1 544 typedef struct
bogdanm 89:552587b429a1 545 {
bogdanm 89:552587b429a1 546 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 89:552587b429a1 547 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 89:552587b429a1 548 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 89:552587b429a1 549 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 89:552587b429a1 550 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 89:552587b429a1 551 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 89:552587b429a1 552 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
bogdanm 89:552587b429a1 553 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
bogdanm 89:552587b429a1 554 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 89:552587b429a1 555 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 89:552587b429a1 556 } GPIO_TypeDef;
bogdanm 89:552587b429a1 557
bogdanm 89:552587b429a1 558 /**
bogdanm 89:552587b429a1 559 * @brief System configuration controller
bogdanm 89:552587b429a1 560 */
bogdanm 89:552587b429a1 561
bogdanm 89:552587b429a1 562 typedef struct
bogdanm 89:552587b429a1 563 {
bogdanm 89:552587b429a1 564 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
bogdanm 89:552587b429a1 565 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
bogdanm 89:552587b429a1 566 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
bogdanm 89:552587b429a1 567 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 89:552587b429a1 568 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
bogdanm 89:552587b429a1 569 } SYSCFG_TypeDef;
bogdanm 89:552587b429a1 570
bogdanm 89:552587b429a1 571 /**
bogdanm 89:552587b429a1 572 * @brief Inter-integrated Circuit Interface
bogdanm 89:552587b429a1 573 */
bogdanm 89:552587b429a1 574
bogdanm 89:552587b429a1 575 typedef struct
bogdanm 89:552587b429a1 576 {
bogdanm 89:552587b429a1 577 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 89:552587b429a1 578 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 89:552587b429a1 579 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
bogdanm 89:552587b429a1 580 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
bogdanm 89:552587b429a1 581 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
bogdanm 89:552587b429a1 582 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
bogdanm 89:552587b429a1 583 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
bogdanm 89:552587b429a1 584 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
bogdanm 89:552587b429a1 585 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
bogdanm 89:552587b429a1 586 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
bogdanm 89:552587b429a1 587 } I2C_TypeDef;
bogdanm 89:552587b429a1 588
bogdanm 89:552587b429a1 589 /**
bogdanm 89:552587b429a1 590 * @brief Independent WATCHDOG
bogdanm 89:552587b429a1 591 */
bogdanm 89:552587b429a1 592
bogdanm 89:552587b429a1 593 typedef struct
bogdanm 89:552587b429a1 594 {
bogdanm 89:552587b429a1 595 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 89:552587b429a1 596 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 89:552587b429a1 597 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 89:552587b429a1 598 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 89:552587b429a1 599 } IWDG_TypeDef;
bogdanm 89:552587b429a1 600
bogdanm 89:552587b429a1 601 /**
bogdanm 89:552587b429a1 602 * @brief Power Control
bogdanm 89:552587b429a1 603 */
bogdanm 89:552587b429a1 604
bogdanm 89:552587b429a1 605 typedef struct
bogdanm 89:552587b429a1 606 {
bogdanm 89:552587b429a1 607 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 608 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 89:552587b429a1 609 } PWR_TypeDef;
bogdanm 89:552587b429a1 610
bogdanm 89:552587b429a1 611 /**
bogdanm 89:552587b429a1 612 * @brief Reset and Clock Control
bogdanm 89:552587b429a1 613 */
bogdanm 89:552587b429a1 614
bogdanm 89:552587b429a1 615 typedef struct
bogdanm 89:552587b429a1 616 {
bogdanm 89:552587b429a1 617 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 618 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
bogdanm 89:552587b429a1 619 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
bogdanm 89:552587b429a1 620 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
bogdanm 89:552587b429a1 621 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
bogdanm 89:552587b429a1 622 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
bogdanm 89:552587b429a1 623 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
bogdanm 89:552587b429a1 624 uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 89:552587b429a1 625 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
bogdanm 89:552587b429a1 626 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 89:552587b429a1 627 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
bogdanm 89:552587b429a1 628 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
bogdanm 89:552587b429a1 629 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
bogdanm 89:552587b429a1 630 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
bogdanm 89:552587b429a1 631 uint32_t RESERVED2; /*!< Reserved, 0x3C */
bogdanm 89:552587b429a1 632 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
bogdanm 89:552587b429a1 633 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
bogdanm 89:552587b429a1 634 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
bogdanm 89:552587b429a1 635 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
bogdanm 89:552587b429a1 636 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
bogdanm 89:552587b429a1 637 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
bogdanm 89:552587b429a1 638 uint32_t RESERVED4; /*!< Reserved, 0x5C */
bogdanm 89:552587b429a1 639 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
bogdanm 89:552587b429a1 640 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
bogdanm 89:552587b429a1 641 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
bogdanm 89:552587b429a1 642 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
bogdanm 89:552587b429a1 643 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
bogdanm 89:552587b429a1 644 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
bogdanm 89:552587b429a1 645 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
bogdanm 89:552587b429a1 646 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
bogdanm 89:552587b429a1 647
bogdanm 89:552587b429a1 648 } RCC_TypeDef;
bogdanm 89:552587b429a1 649
bogdanm 89:552587b429a1 650 /**
bogdanm 89:552587b429a1 651 * @brief Real-Time Clock
bogdanm 89:552587b429a1 652 */
bogdanm 89:552587b429a1 653
bogdanm 89:552587b429a1 654 typedef struct
bogdanm 89:552587b429a1 655 {
bogdanm 89:552587b429a1 656 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 89:552587b429a1 657 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 89:552587b429a1 658 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 89:552587b429a1 659 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 89:552587b429a1 660 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 89:552587b429a1 661 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 89:552587b429a1 662 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
bogdanm 89:552587b429a1 663 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 89:552587b429a1 664 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 89:552587b429a1 665 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 89:552587b429a1 666 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 89:552587b429a1 667 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 89:552587b429a1 668 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 89:552587b429a1 669 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 89:552587b429a1 670 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 89:552587b429a1 671 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 89:552587b429a1 672 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 89:552587b429a1 673 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 89:552587b429a1 674 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 89:552587b429a1 675 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 89:552587b429a1 676 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
bogdanm 89:552587b429a1 677 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 89:552587b429a1 678 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 89:552587b429a1 679 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 89:552587b429a1 680 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 89:552587b429a1 681 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 89:552587b429a1 682 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 89:552587b429a1 683 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 89:552587b429a1 684 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 89:552587b429a1 685 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 89:552587b429a1 686 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 89:552587b429a1 687 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 89:552587b429a1 688 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 89:552587b429a1 689 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 89:552587b429a1 690 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 89:552587b429a1 691 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 89:552587b429a1 692 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
bogdanm 89:552587b429a1 693 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
bogdanm 89:552587b429a1 694 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
bogdanm 89:552587b429a1 695 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
bogdanm 89:552587b429a1 696 } RTC_TypeDef;
bogdanm 89:552587b429a1 697
bogdanm 89:552587b429a1 698
bogdanm 89:552587b429a1 699 /**
bogdanm 89:552587b429a1 700 * @brief SD host Interface
bogdanm 89:552587b429a1 701 */
bogdanm 89:552587b429a1 702
bogdanm 89:552587b429a1 703 typedef struct
bogdanm 89:552587b429a1 704 {
bogdanm 89:552587b429a1 705 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 706 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
bogdanm 89:552587b429a1 707 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
bogdanm 89:552587b429a1 708 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
bogdanm 89:552587b429a1 709 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
bogdanm 89:552587b429a1 710 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
bogdanm 89:552587b429a1 711 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
bogdanm 89:552587b429a1 712 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
bogdanm 89:552587b429a1 713 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
bogdanm 89:552587b429a1 714 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
bogdanm 89:552587b429a1 715 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
bogdanm 89:552587b429a1 716 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
bogdanm 89:552587b429a1 717 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
bogdanm 89:552587b429a1 718 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
bogdanm 89:552587b429a1 719 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
bogdanm 89:552587b429a1 720 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
bogdanm 89:552587b429a1 721 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
bogdanm 89:552587b429a1 722 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
bogdanm 89:552587b429a1 723 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
bogdanm 89:552587b429a1 724 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
bogdanm 89:552587b429a1 725 } SDIO_TypeDef;
bogdanm 89:552587b429a1 726
bogdanm 89:552587b429a1 727 /**
bogdanm 89:552587b429a1 728 * @brief Serial Peripheral Interface
bogdanm 89:552587b429a1 729 */
bogdanm 89:552587b429a1 730
bogdanm 89:552587b429a1 731 typedef struct
bogdanm 89:552587b429a1 732 {
bogdanm 89:552587b429a1 733 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 89:552587b429a1 734 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
bogdanm 89:552587b429a1 735 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
bogdanm 89:552587b429a1 736 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 89:552587b429a1 737 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 89:552587b429a1 738 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 89:552587b429a1 739 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 89:552587b429a1 740 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 89:552587b429a1 741 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 89:552587b429a1 742 } SPI_TypeDef;
bogdanm 89:552587b429a1 743
bogdanm 89:552587b429a1 744 /**
bogdanm 89:552587b429a1 745 * @brief TIM
bogdanm 89:552587b429a1 746 */
bogdanm 89:552587b429a1 747
bogdanm 89:552587b429a1 748 typedef struct
bogdanm 89:552587b429a1 749 {
bogdanm 89:552587b429a1 750 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 89:552587b429a1 751 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 89:552587b429a1 752 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 89:552587b429a1 753 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 89:552587b429a1 754 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 89:552587b429a1 755 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 89:552587b429a1 756 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 89:552587b429a1 757 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 89:552587b429a1 758 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 89:552587b429a1 759 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 89:552587b429a1 760 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 89:552587b429a1 761 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 89:552587b429a1 762 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 89:552587b429a1 763 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 89:552587b429a1 764 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 89:552587b429a1 765 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 89:552587b429a1 766 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 89:552587b429a1 767 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 89:552587b429a1 768 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 89:552587b429a1 769 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 89:552587b429a1 770 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 89:552587b429a1 771 } TIM_TypeDef;
bogdanm 89:552587b429a1 772
bogdanm 89:552587b429a1 773 /**
bogdanm 89:552587b429a1 774 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 89:552587b429a1 775 */
bogdanm 89:552587b429a1 776
bogdanm 89:552587b429a1 777 typedef struct
bogdanm 89:552587b429a1 778 {
bogdanm 89:552587b429a1 779 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
bogdanm 89:552587b429a1 780 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
bogdanm 89:552587b429a1 781 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
bogdanm 89:552587b429a1 782 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
bogdanm 89:552587b429a1 783 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
bogdanm 89:552587b429a1 784 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
bogdanm 89:552587b429a1 785 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
bogdanm 89:552587b429a1 786 } USART_TypeDef;
bogdanm 89:552587b429a1 787
bogdanm 89:552587b429a1 788 /**
bogdanm 89:552587b429a1 789 * @brief Window WATCHDOG
bogdanm 89:552587b429a1 790 */
bogdanm 89:552587b429a1 791
bogdanm 89:552587b429a1 792 typedef struct
bogdanm 89:552587b429a1 793 {
bogdanm 89:552587b429a1 794 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 795 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 89:552587b429a1 796 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 89:552587b429a1 797 } WWDG_TypeDef;
bogdanm 89:552587b429a1 798
bogdanm 89:552587b429a1 799 /**
bogdanm 89:552587b429a1 800 * @brief RNG
bogdanm 89:552587b429a1 801 */
bogdanm 89:552587b429a1 802
bogdanm 89:552587b429a1 803 typedef struct
bogdanm 89:552587b429a1 804 {
bogdanm 89:552587b429a1 805 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 89:552587b429a1 806 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 89:552587b429a1 807 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 89:552587b429a1 808 } RNG_TypeDef;
bogdanm 89:552587b429a1 809
bogdanm 89:552587b429a1 810
bogdanm 89:552587b429a1 811
bogdanm 89:552587b429a1 812 /**
bogdanm 89:552587b429a1 813 * @brief __USB_OTG_Core_register
bogdanm 89:552587b429a1 814 */
bogdanm 89:552587b429a1 815 typedef struct
bogdanm 89:552587b429a1 816 {
bogdanm 89:552587b429a1 817 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
bogdanm 89:552587b429a1 818 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
bogdanm 89:552587b429a1 819 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
bogdanm 89:552587b429a1 820 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
bogdanm 89:552587b429a1 821 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
bogdanm 89:552587b429a1 822 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
bogdanm 89:552587b429a1 823 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
bogdanm 89:552587b429a1 824 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
bogdanm 89:552587b429a1 825 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
bogdanm 89:552587b429a1 826 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
bogdanm 89:552587b429a1 827 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
bogdanm 89:552587b429a1 828 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
bogdanm 89:552587b429a1 829 uint32_t Reserved30[2]; /* Reserved 030h*/
bogdanm 89:552587b429a1 830 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
bogdanm 89:552587b429a1 831 __IO uint32_t CID; /* User ID Register 03Ch*/
bogdanm 89:552587b429a1 832 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
bogdanm 89:552587b429a1 833 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
bogdanm 89:552587b429a1 834 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
bogdanm 89:552587b429a1 835 }
bogdanm 89:552587b429a1 836 USB_OTG_GlobalTypeDef;
bogdanm 89:552587b429a1 837
bogdanm 89:552587b429a1 838
bogdanm 89:552587b429a1 839
bogdanm 89:552587b429a1 840 /**
bogdanm 89:552587b429a1 841 * @brief __device_Registers
bogdanm 89:552587b429a1 842 */
bogdanm 89:552587b429a1 843 typedef struct
bogdanm 89:552587b429a1 844 {
bogdanm 89:552587b429a1 845 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
bogdanm 89:552587b429a1 846 __IO uint32_t DCTL; /* dev Control Register 804h*/
bogdanm 89:552587b429a1 847 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
bogdanm 89:552587b429a1 848 uint32_t Reserved0C; /* Reserved 80Ch*/
bogdanm 89:552587b429a1 849 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
bogdanm 89:552587b429a1 850 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
bogdanm 89:552587b429a1 851 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
bogdanm 89:552587b429a1 852 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
bogdanm 89:552587b429a1 853 uint32_t Reserved20; /* Reserved 820h*/
bogdanm 89:552587b429a1 854 uint32_t Reserved9; /* Reserved 824h*/
bogdanm 89:552587b429a1 855 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
bogdanm 89:552587b429a1 856 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
bogdanm 89:552587b429a1 857 __IO uint32_t DTHRCTL; /* dev thr 830h*/
bogdanm 89:552587b429a1 858 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
bogdanm 89:552587b429a1 859 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
bogdanm 89:552587b429a1 860 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
bogdanm 89:552587b429a1 861 uint32_t Reserved40; /* dedicated EP mask 840h*/
bogdanm 89:552587b429a1 862 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
bogdanm 89:552587b429a1 863 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
bogdanm 89:552587b429a1 864 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
bogdanm 89:552587b429a1 865 }
bogdanm 89:552587b429a1 866 USB_OTG_DeviceTypeDef;
bogdanm 89:552587b429a1 867
bogdanm 89:552587b429a1 868
bogdanm 89:552587b429a1 869 /**
bogdanm 89:552587b429a1 870 * @brief __IN_Endpoint-Specific_Register
bogdanm 89:552587b429a1 871 */
bogdanm 89:552587b429a1 872 typedef struct
bogdanm 89:552587b429a1 873 {
bogdanm 89:552587b429a1 874 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
bogdanm 89:552587b429a1 875 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
bogdanm 89:552587b429a1 876 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
bogdanm 89:552587b429a1 877 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
bogdanm 89:552587b429a1 878 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
bogdanm 89:552587b429a1 879 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
bogdanm 89:552587b429a1 880 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
bogdanm 89:552587b429a1 881 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
bogdanm 89:552587b429a1 882 }
bogdanm 89:552587b429a1 883 USB_OTG_INEndpointTypeDef;
bogdanm 89:552587b429a1 884
bogdanm 89:552587b429a1 885
bogdanm 89:552587b429a1 886 /**
bogdanm 89:552587b429a1 887 * @brief __OUT_Endpoint-Specific_Registers
bogdanm 89:552587b429a1 888 */
bogdanm 89:552587b429a1 889 typedef struct
bogdanm 89:552587b429a1 890 {
bogdanm 89:552587b429a1 891 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
bogdanm 89:552587b429a1 892 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
bogdanm 89:552587b429a1 893 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
bogdanm 89:552587b429a1 894 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
bogdanm 89:552587b429a1 895 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
bogdanm 89:552587b429a1 896 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
bogdanm 89:552587b429a1 897 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
bogdanm 89:552587b429a1 898 }
bogdanm 89:552587b429a1 899 USB_OTG_OUTEndpointTypeDef;
bogdanm 89:552587b429a1 900
bogdanm 89:552587b429a1 901
bogdanm 89:552587b429a1 902 /**
bogdanm 89:552587b429a1 903 * @brief __Host_Mode_Register_Structures
bogdanm 89:552587b429a1 904 */
bogdanm 89:552587b429a1 905 typedef struct
bogdanm 89:552587b429a1 906 {
bogdanm 89:552587b429a1 907 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
bogdanm 89:552587b429a1 908 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
bogdanm 89:552587b429a1 909 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
bogdanm 89:552587b429a1 910 uint32_t Reserved40C; /* Reserved 40Ch*/
bogdanm 89:552587b429a1 911 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
bogdanm 89:552587b429a1 912 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
bogdanm 89:552587b429a1 913 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
bogdanm 89:552587b429a1 914 }
bogdanm 89:552587b429a1 915 USB_OTG_HostTypeDef;
bogdanm 89:552587b429a1 916
bogdanm 89:552587b429a1 917
bogdanm 89:552587b429a1 918 /**
bogdanm 89:552587b429a1 919 * @brief __Host_Channel_Specific_Registers
bogdanm 89:552587b429a1 920 */
bogdanm 89:552587b429a1 921 typedef struct
bogdanm 89:552587b429a1 922 {
bogdanm 89:552587b429a1 923 __IO uint32_t HCCHAR;
bogdanm 89:552587b429a1 924 __IO uint32_t HCSPLT;
bogdanm 89:552587b429a1 925 __IO uint32_t HCINT;
bogdanm 89:552587b429a1 926 __IO uint32_t HCINTMSK;
bogdanm 89:552587b429a1 927 __IO uint32_t HCTSIZ;
bogdanm 89:552587b429a1 928 __IO uint32_t HCDMA;
bogdanm 89:552587b429a1 929 uint32_t Reserved[2];
bogdanm 89:552587b429a1 930 }
bogdanm 89:552587b429a1 931 USB_OTG_HostChannelTypeDef;
bogdanm 89:552587b429a1 932
bogdanm 89:552587b429a1 933
bogdanm 89:552587b429a1 934 /**
bogdanm 89:552587b429a1 935 * @brief Peripheral_memory_map
bogdanm 89:552587b429a1 936 */
bogdanm 89:552587b429a1 937 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
bogdanm 89:552587b429a1 938 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
bogdanm 89:552587b429a1 939 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
bogdanm 89:552587b429a1 940 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
bogdanm 89:552587b429a1 941 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
bogdanm 89:552587b429a1 942 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 89:552587b429a1 943 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
bogdanm 89:552587b429a1 944 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
bogdanm 89:552587b429a1 945 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
bogdanm 89:552587b429a1 946 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
bogdanm 89:552587b429a1 947 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
bogdanm 89:552587b429a1 948 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
bogdanm 89:552587b429a1 949 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 89:552587b429a1 950 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
bogdanm 89:552587b429a1 951 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
bogdanm 89:552587b429a1 952 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
bogdanm 89:552587b429a1 953
bogdanm 89:552587b429a1 954 /* Legacy defines */
bogdanm 89:552587b429a1 955 #define SRAM_BASE SRAM1_BASE
bogdanm 89:552587b429a1 956 #define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm 89:552587b429a1 957
bogdanm 89:552587b429a1 958
bogdanm 89:552587b429a1 959 /*!< Peripheral memory map */
bogdanm 89:552587b429a1 960 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 89:552587b429a1 961 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 89:552587b429a1 962 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 89:552587b429a1 963 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 89:552587b429a1 964
bogdanm 89:552587b429a1 965 /*!< APB1 peripherals */
bogdanm 89:552587b429a1 966 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm 89:552587b429a1 967 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm 89:552587b429a1 968 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm 89:552587b429a1 969 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm 89:552587b429a1 970 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm 89:552587b429a1 971 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm 89:552587b429a1 972 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
bogdanm 89:552587b429a1 973 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
bogdanm 89:552587b429a1 974 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
bogdanm 89:552587b429a1 975 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm 89:552587b429a1 976 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm 89:552587b429a1 977 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm 89:552587b429a1 978 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
bogdanm 89:552587b429a1 979 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm 89:552587b429a1 980 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm 89:552587b429a1 981 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
bogdanm 89:552587b429a1 982 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm 89:552587b429a1 983 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm 89:552587b429a1 984 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm 89:552587b429a1 985 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm 89:552587b429a1 986 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm 89:552587b429a1 987 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm 89:552587b429a1 988 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm 89:552587b429a1 989 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm 89:552587b429a1 990 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
bogdanm 89:552587b429a1 991 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm 89:552587b429a1 992 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm 89:552587b429a1 993
bogdanm 89:552587b429a1 994 /*!< APB2 peripherals */
bogdanm 89:552587b429a1 995 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm 89:552587b429a1 996 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm 89:552587b429a1 997 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm 89:552587b429a1 998 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm 89:552587b429a1 999 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm 89:552587b429a1 1000 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
bogdanm 89:552587b429a1 1001 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
bogdanm 89:552587b429a1 1002 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
bogdanm 89:552587b429a1 1003 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm 89:552587b429a1 1004 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm 89:552587b429a1 1005 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm 89:552587b429a1 1006 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm 89:552587b429a1 1007 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm 89:552587b429a1 1008 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm 89:552587b429a1 1009 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm 89:552587b429a1 1010
bogdanm 89:552587b429a1 1011 /*!< AHB1 peripherals */
bogdanm 89:552587b429a1 1012 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
bogdanm 89:552587b429a1 1013 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm 89:552587b429a1 1014 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
bogdanm 89:552587b429a1 1015 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
bogdanm 89:552587b429a1 1016 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm 89:552587b429a1 1017 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
bogdanm 89:552587b429a1 1018 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
bogdanm 89:552587b429a1 1019 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
bogdanm 89:552587b429a1 1020 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
bogdanm 89:552587b429a1 1021 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm 89:552587b429a1 1022 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
bogdanm 89:552587b429a1 1023 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
bogdanm 89:552587b429a1 1024 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
bogdanm 89:552587b429a1 1025 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
bogdanm 89:552587b429a1 1026 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
bogdanm 89:552587b429a1 1027 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
bogdanm 89:552587b429a1 1028 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
bogdanm 89:552587b429a1 1029 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
bogdanm 89:552587b429a1 1030 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
bogdanm 89:552587b429a1 1031 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
bogdanm 89:552587b429a1 1032 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
bogdanm 89:552587b429a1 1033 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
bogdanm 89:552587b429a1 1034 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
bogdanm 89:552587b429a1 1035 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
bogdanm 89:552587b429a1 1036 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
bogdanm 89:552587b429a1 1037 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
bogdanm 89:552587b429a1 1038 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
bogdanm 89:552587b429a1 1039 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
bogdanm 89:552587b429a1 1040 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
bogdanm 89:552587b429a1 1041 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
bogdanm 89:552587b429a1 1042 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
bogdanm 89:552587b429a1 1043 #define ETH_MAC_BASE (ETH_BASE)
bogdanm 89:552587b429a1 1044 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
bogdanm 89:552587b429a1 1045 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
bogdanm 89:552587b429a1 1046 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
bogdanm 89:552587b429a1 1047
bogdanm 89:552587b429a1 1048 /*!< AHB2 peripherals */
bogdanm 89:552587b429a1 1049 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
bogdanm 89:552587b429a1 1050 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
bogdanm 89:552587b429a1 1051
bogdanm 89:552587b429a1 1052 /*!< FSMC Bankx registers base address */
bogdanm 89:552587b429a1 1053 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
bogdanm 89:552587b429a1 1054 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
bogdanm 89:552587b429a1 1055 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
bogdanm 89:552587b429a1 1056 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
bogdanm 89:552587b429a1 1057
bogdanm 89:552587b429a1 1058 /* Debug MCU registers base address */
bogdanm 89:552587b429a1 1059 #define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm 89:552587b429a1 1060
bogdanm 89:552587b429a1 1061 /*!< USB registers base address */
bogdanm 89:552587b429a1 1062 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
bogdanm 89:552587b429a1 1063 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
bogdanm 89:552587b429a1 1064
bogdanm 89:552587b429a1 1065 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
bogdanm 89:552587b429a1 1066 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
bogdanm 89:552587b429a1 1067 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
bogdanm 89:552587b429a1 1068 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
bogdanm 89:552587b429a1 1069 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
bogdanm 89:552587b429a1 1070 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
bogdanm 89:552587b429a1 1071 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
bogdanm 89:552587b429a1 1072 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
bogdanm 89:552587b429a1 1073 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
bogdanm 89:552587b429a1 1074 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
bogdanm 89:552587b429a1 1075 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
bogdanm 89:552587b429a1 1076 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
bogdanm 89:552587b429a1 1077
bogdanm 89:552587b429a1 1078 /**
bogdanm 89:552587b429a1 1079 * @}
bogdanm 89:552587b429a1 1080 */
bogdanm 89:552587b429a1 1081
bogdanm 89:552587b429a1 1082 /** @addtogroup Peripheral_declaration
bogdanm 89:552587b429a1 1083 * @{
bogdanm 89:552587b429a1 1084 */
bogdanm 89:552587b429a1 1085 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 89:552587b429a1 1086 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 89:552587b429a1 1087 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 89:552587b429a1 1088 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 89:552587b429a1 1089 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 89:552587b429a1 1090 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 89:552587b429a1 1091 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm 89:552587b429a1 1092 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm 89:552587b429a1 1093 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 89:552587b429a1 1094 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 89:552587b429a1 1095 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 89:552587b429a1 1096 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 89:552587b429a1 1097 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 89:552587b429a1 1098 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 89:552587b429a1 1099 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 89:552587b429a1 1100 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 89:552587b429a1 1101 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 89:552587b429a1 1102 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 89:552587b429a1 1103 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 89:552587b429a1 1104 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 89:552587b429a1 1105 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 89:552587b429a1 1106 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 89:552587b429a1 1107 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 89:552587b429a1 1108 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 89:552587b429a1 1109 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm 89:552587b429a1 1110 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 89:552587b429a1 1111 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 89:552587b429a1 1112 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 89:552587b429a1 1113 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 89:552587b429a1 1114 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 89:552587b429a1 1115 #define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm 89:552587b429a1 1116 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 89:552587b429a1 1117 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 89:552587b429a1 1118 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 89:552587b429a1 1119 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 89:552587b429a1 1120 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 89:552587b429a1 1121 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 89:552587b429a1 1122 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 89:552587b429a1 1123 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 89:552587b429a1 1124 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 89:552587b429a1 1125 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 89:552587b429a1 1126 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 89:552587b429a1 1127 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 89:552587b429a1 1128 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 89:552587b429a1 1129 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 89:552587b429a1 1130 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 89:552587b429a1 1131 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 89:552587b429a1 1132 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 89:552587b429a1 1133 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm 89:552587b429a1 1134 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 89:552587b429a1 1135 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
bogdanm 89:552587b429a1 1136 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 89:552587b429a1 1137 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 89:552587b429a1 1138 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 89:552587b429a1 1139 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 89:552587b429a1 1140 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm 89:552587b429a1 1141 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm 89:552587b429a1 1142 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm 89:552587b429a1 1143 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm 89:552587b429a1 1144 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm 89:552587b429a1 1145 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm 89:552587b429a1 1146 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm 89:552587b429a1 1147 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm 89:552587b429a1 1148 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 89:552587b429a1 1149 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm 89:552587b429a1 1150 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm 89:552587b429a1 1151 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm 89:552587b429a1 1152 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm 89:552587b429a1 1153 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm 89:552587b429a1 1154 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm 89:552587b429a1 1155 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 89:552587b429a1 1156 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm 89:552587b429a1 1157 #define ETH ((ETH_TypeDef *) ETH_BASE)
bogdanm 89:552587b429a1 1158 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
bogdanm 89:552587b429a1 1159 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 89:552587b429a1 1160 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm 89:552587b429a1 1161 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm 89:552587b429a1 1162 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
bogdanm 89:552587b429a1 1163 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm 89:552587b429a1 1164
bogdanm 89:552587b429a1 1165 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 89:552587b429a1 1166
bogdanm 89:552587b429a1 1167 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
bogdanm 89:552587b429a1 1168 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
bogdanm 89:552587b429a1 1169
bogdanm 89:552587b429a1 1170 /**
bogdanm 89:552587b429a1 1171 * @}
bogdanm 89:552587b429a1 1172 */
bogdanm 89:552587b429a1 1173
bogdanm 89:552587b429a1 1174 /** @addtogroup Exported_constants
bogdanm 89:552587b429a1 1175 * @{
bogdanm 89:552587b429a1 1176 */
bogdanm 89:552587b429a1 1177
bogdanm 89:552587b429a1 1178 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 89:552587b429a1 1179 * @{
bogdanm 89:552587b429a1 1180 */
bogdanm 89:552587b429a1 1181
bogdanm 89:552587b429a1 1182 /******************************************************************************/
bogdanm 89:552587b429a1 1183 /* Peripheral Registers_Bits_Definition */
bogdanm 89:552587b429a1 1184 /******************************************************************************/
bogdanm 89:552587b429a1 1185
bogdanm 89:552587b429a1 1186 /******************************************************************************/
bogdanm 89:552587b429a1 1187 /* */
bogdanm 89:552587b429a1 1188 /* Analog to Digital Converter */
bogdanm 89:552587b429a1 1189 /* */
bogdanm 89:552587b429a1 1190 /******************************************************************************/
bogdanm 89:552587b429a1 1191 /******************** Bit definition for ADC_SR register ********************/
bogdanm 89:552587b429a1 1192 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
bogdanm 89:552587b429a1 1193 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
bogdanm 89:552587b429a1 1194 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
bogdanm 89:552587b429a1 1195 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
bogdanm 89:552587b429a1 1196 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
bogdanm 89:552587b429a1 1197 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
bogdanm 89:552587b429a1 1198
bogdanm 89:552587b429a1 1199 /******************* Bit definition for ADC_CR1 register ********************/
bogdanm 89:552587b429a1 1200 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 89:552587b429a1 1201 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1202 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1203 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1204 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1205 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1206 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
bogdanm 89:552587b429a1 1207 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
bogdanm 89:552587b429a1 1208 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
bogdanm 89:552587b429a1 1209 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
bogdanm 89:552587b429a1 1210 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
bogdanm 89:552587b429a1 1211 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
bogdanm 89:552587b429a1 1212 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
bogdanm 89:552587b429a1 1213 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
bogdanm 89:552587b429a1 1214 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
bogdanm 89:552587b429a1 1215 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1216 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1217 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1218 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
bogdanm 89:552587b429a1 1219 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
bogdanm 89:552587b429a1 1220 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
bogdanm 89:552587b429a1 1221 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1222 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1223 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
bogdanm 89:552587b429a1 1224
bogdanm 89:552587b429a1 1225 /******************* Bit definition for ADC_CR2 register ********************/
bogdanm 89:552587b429a1 1226 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
bogdanm 89:552587b429a1 1227 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
bogdanm 89:552587b429a1 1228 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
bogdanm 89:552587b429a1 1229 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
bogdanm 89:552587b429a1 1230 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
bogdanm 89:552587b429a1 1231 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
bogdanm 89:552587b429a1 1232 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
bogdanm 89:552587b429a1 1233 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1234 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1235 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1236 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1237 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
bogdanm 89:552587b429a1 1238 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1239 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1240 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
bogdanm 89:552587b429a1 1241 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
bogdanm 89:552587b429a1 1242 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1243 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1244 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1245 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1246 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
bogdanm 89:552587b429a1 1247 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1248 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1249 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
bogdanm 89:552587b429a1 1250
bogdanm 89:552587b429a1 1251 /****************** Bit definition for ADC_SMPR1 register *******************/
bogdanm 89:552587b429a1 1252 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
bogdanm 89:552587b429a1 1253 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1254 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1255 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1256 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
bogdanm 89:552587b429a1 1257 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 89:552587b429a1 1258 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 89:552587b429a1 1259 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 89:552587b429a1 1260 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
bogdanm 89:552587b429a1 1261 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 89:552587b429a1 1262 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 89:552587b429a1 1263 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 89:552587b429a1 1264 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
bogdanm 89:552587b429a1 1265 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 89:552587b429a1 1266 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 89:552587b429a1 1267 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 89:552587b429a1 1268 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
bogdanm 89:552587b429a1 1269 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1270 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1271 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1272 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
bogdanm 89:552587b429a1 1273 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1274 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1275 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1276 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
bogdanm 89:552587b429a1 1277 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1278 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1279 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1280 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
bogdanm 89:552587b429a1 1281 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1282 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1283 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1284 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
bogdanm 89:552587b429a1 1285 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1286 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1287 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1288
bogdanm 89:552587b429a1 1289 /****************** Bit definition for ADC_SMPR2 register *******************/
bogdanm 89:552587b429a1 1290 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
bogdanm 89:552587b429a1 1291 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1292 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1293 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1294 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
bogdanm 89:552587b429a1 1295 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 89:552587b429a1 1296 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 89:552587b429a1 1297 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 89:552587b429a1 1298 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
bogdanm 89:552587b429a1 1299 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 89:552587b429a1 1300 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 89:552587b429a1 1301 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 89:552587b429a1 1302 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
bogdanm 89:552587b429a1 1303 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 89:552587b429a1 1304 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 89:552587b429a1 1305 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 89:552587b429a1 1306 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
bogdanm 89:552587b429a1 1307 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1308 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1309 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1310 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
bogdanm 89:552587b429a1 1311 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1312 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1313 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1314 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
bogdanm 89:552587b429a1 1315 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1316 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1317 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1318 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
bogdanm 89:552587b429a1 1319 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1320 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1321 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1322 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
bogdanm 89:552587b429a1 1323 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1324 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1325 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1326 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
bogdanm 89:552587b429a1 1327 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1328 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1329 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1330
bogdanm 89:552587b429a1 1331 /****************** Bit definition for ADC_JOFR1 register *******************/
bogdanm 89:552587b429a1 1332 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
bogdanm 89:552587b429a1 1333
bogdanm 89:552587b429a1 1334 /****************** Bit definition for ADC_JOFR2 register *******************/
bogdanm 89:552587b429a1 1335 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
bogdanm 89:552587b429a1 1336
bogdanm 89:552587b429a1 1337 /****************** Bit definition for ADC_JOFR3 register *******************/
bogdanm 89:552587b429a1 1338 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
bogdanm 89:552587b429a1 1339
bogdanm 89:552587b429a1 1340 /****************** Bit definition for ADC_JOFR4 register *******************/
bogdanm 89:552587b429a1 1341 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
bogdanm 89:552587b429a1 1342
bogdanm 89:552587b429a1 1343 /******************* Bit definition for ADC_HTR register ********************/
bogdanm 89:552587b429a1 1344 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
bogdanm 89:552587b429a1 1345
bogdanm 89:552587b429a1 1346 /******************* Bit definition for ADC_LTR register ********************/
bogdanm 89:552587b429a1 1347 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
bogdanm 89:552587b429a1 1348
bogdanm 89:552587b429a1 1349 /******************* Bit definition for ADC_SQR1 register *******************/
bogdanm 89:552587b429a1 1350 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
bogdanm 89:552587b429a1 1351 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1352 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1353 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1354 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1355 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1356 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
bogdanm 89:552587b429a1 1357 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 89:552587b429a1 1358 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 89:552587b429a1 1359 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 89:552587b429a1 1360 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 89:552587b429a1 1361 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 89:552587b429a1 1362 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
bogdanm 89:552587b429a1 1363 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 1364 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 1365 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1366 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1367 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1368 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
bogdanm 89:552587b429a1 1369 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1370 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1371 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1372 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1373 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1374 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
bogdanm 89:552587b429a1 1375 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1376 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1377 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1378 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1379
bogdanm 89:552587b429a1 1380 /******************* Bit definition for ADC_SQR2 register *******************/
bogdanm 89:552587b429a1 1381 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
bogdanm 89:552587b429a1 1382 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1383 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1384 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1385 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1386 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1387 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
bogdanm 89:552587b429a1 1388 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 89:552587b429a1 1389 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 89:552587b429a1 1390 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 89:552587b429a1 1391 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 89:552587b429a1 1392 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 89:552587b429a1 1393 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
bogdanm 89:552587b429a1 1394 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 1395 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 1396 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1397 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1398 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1399 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
bogdanm 89:552587b429a1 1400 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1401 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1402 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1403 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1404 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1405 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
bogdanm 89:552587b429a1 1406 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1407 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1408 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1409 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1410 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1411 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
bogdanm 89:552587b429a1 1412 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1413 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1414 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1415 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1416 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1417
bogdanm 89:552587b429a1 1418 /******************* Bit definition for ADC_SQR3 register *******************/
bogdanm 89:552587b429a1 1419 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
bogdanm 89:552587b429a1 1420 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1421 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1422 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1423 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1424 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1425 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
bogdanm 89:552587b429a1 1426 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 89:552587b429a1 1427 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 89:552587b429a1 1428 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 89:552587b429a1 1429 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 89:552587b429a1 1430 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 89:552587b429a1 1431 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
bogdanm 89:552587b429a1 1432 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 1433 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 1434 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1435 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1436 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1437 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
bogdanm 89:552587b429a1 1438 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1439 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1440 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1441 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1442 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1443 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
bogdanm 89:552587b429a1 1444 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1445 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1446 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1447 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1448 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1449 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
bogdanm 89:552587b429a1 1450 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1451 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1452 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1453 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1454 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1455
bogdanm 89:552587b429a1 1456 /******************* Bit definition for ADC_JSQR register *******************/
bogdanm 89:552587b429a1 1457 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
bogdanm 89:552587b429a1 1458 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1459 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1460 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1461 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1462 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1463 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
bogdanm 89:552587b429a1 1464 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 89:552587b429a1 1465 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 89:552587b429a1 1466 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 89:552587b429a1 1467 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 89:552587b429a1 1468 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 89:552587b429a1 1469 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
bogdanm 89:552587b429a1 1470 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 1471 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 1472 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1473 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1474 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1475 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
bogdanm 89:552587b429a1 1476 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1477 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1478 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1479 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1480 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 89:552587b429a1 1481 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
bogdanm 89:552587b429a1 1482 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1483 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1484
bogdanm 89:552587b429a1 1485 /******************* Bit definition for ADC_JDR1 register *******************/
bogdanm 89:552587b429a1 1486 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 89:552587b429a1 1487
bogdanm 89:552587b429a1 1488 /******************* Bit definition for ADC_JDR2 register *******************/
bogdanm 89:552587b429a1 1489 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 89:552587b429a1 1490
bogdanm 89:552587b429a1 1491 /******************* Bit definition for ADC_JDR3 register *******************/
bogdanm 89:552587b429a1 1492 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 89:552587b429a1 1493
bogdanm 89:552587b429a1 1494 /******************* Bit definition for ADC_JDR4 register *******************/
bogdanm 89:552587b429a1 1495 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 89:552587b429a1 1496
bogdanm 89:552587b429a1 1497 /******************** Bit definition for ADC_DR register ********************/
bogdanm 89:552587b429a1 1498 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
bogdanm 89:552587b429a1 1499 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
bogdanm 89:552587b429a1 1500
bogdanm 89:552587b429a1 1501 /******************* Bit definition for ADC_CSR register ********************/
bogdanm 89:552587b429a1 1502 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
bogdanm 89:552587b429a1 1503 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
bogdanm 89:552587b429a1 1504 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
bogdanm 89:552587b429a1 1505 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
bogdanm 89:552587b429a1 1506 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
bogdanm 89:552587b429a1 1507 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
bogdanm 89:552587b429a1 1508 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
bogdanm 89:552587b429a1 1509 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
bogdanm 89:552587b429a1 1510 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
bogdanm 89:552587b429a1 1511 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
bogdanm 89:552587b429a1 1512 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
bogdanm 89:552587b429a1 1513 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
bogdanm 89:552587b429a1 1514 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
bogdanm 89:552587b429a1 1515 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
bogdanm 89:552587b429a1 1516 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
bogdanm 89:552587b429a1 1517 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
bogdanm 89:552587b429a1 1518 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
bogdanm 89:552587b429a1 1519 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
bogdanm 89:552587b429a1 1520
bogdanm 89:552587b429a1 1521 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 89:552587b429a1 1522 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
bogdanm 89:552587b429a1 1523 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 1524 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 1525 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 1526 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 1527 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 1528 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
bogdanm 89:552587b429a1 1529 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 1530 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 1531 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 1532 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 1533 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
bogdanm 89:552587b429a1 1534 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
bogdanm 89:552587b429a1 1535 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1536 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1537 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
bogdanm 89:552587b429a1 1538 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1539 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1540 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
bogdanm 89:552587b429a1 1541 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
bogdanm 89:552587b429a1 1542
bogdanm 89:552587b429a1 1543 /******************* Bit definition for ADC_CDR register ********************/
bogdanm 89:552587b429a1 1544 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
bogdanm 89:552587b429a1 1545 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
bogdanm 89:552587b429a1 1546
bogdanm 89:552587b429a1 1547 /******************************************************************************/
bogdanm 89:552587b429a1 1548 /* */
bogdanm 89:552587b429a1 1549 /* Controller Area Network */
bogdanm 89:552587b429a1 1550 /* */
bogdanm 89:552587b429a1 1551 /******************************************************************************/
bogdanm 89:552587b429a1 1552 /*!<CAN control and status registers */
bogdanm 89:552587b429a1 1553 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 89:552587b429a1 1554 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
bogdanm 89:552587b429a1 1555 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
bogdanm 89:552587b429a1 1556 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
bogdanm 89:552587b429a1 1557 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
bogdanm 89:552587b429a1 1558 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
bogdanm 89:552587b429a1 1559 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
bogdanm 89:552587b429a1 1560 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
bogdanm 89:552587b429a1 1561 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
bogdanm 89:552587b429a1 1562 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
bogdanm 89:552587b429a1 1563 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
bogdanm 89:552587b429a1 1564 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 89:552587b429a1 1565 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
bogdanm 89:552587b429a1 1566 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
bogdanm 89:552587b429a1 1567 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
bogdanm 89:552587b429a1 1568 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
bogdanm 89:552587b429a1 1569 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
bogdanm 89:552587b429a1 1570 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
bogdanm 89:552587b429a1 1571 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
bogdanm 89:552587b429a1 1572 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
bogdanm 89:552587b429a1 1573 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
bogdanm 89:552587b429a1 1574
bogdanm 89:552587b429a1 1575 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 89:552587b429a1 1576 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 89:552587b429a1 1577 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 89:552587b429a1 1578 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 89:552587b429a1 1579 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 89:552587b429a1 1580 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 89:552587b429a1 1581 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 89:552587b429a1 1582 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 89:552587b429a1 1583 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 89:552587b429a1 1584 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 89:552587b429a1 1585 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 89:552587b429a1 1586 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 89:552587b429a1 1587 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 89:552587b429a1 1588 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 89:552587b429a1 1589 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 89:552587b429a1 1590 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 89:552587b429a1 1591 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 89:552587b429a1 1592
bogdanm 89:552587b429a1 1593 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 89:552587b429a1 1594 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 89:552587b429a1 1595 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 89:552587b429a1 1596 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 89:552587b429a1 1597
bogdanm 89:552587b429a1 1598 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 89:552587b429a1 1599 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 89:552587b429a1 1600 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 89:552587b429a1 1601 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 89:552587b429a1 1602
bogdanm 89:552587b429a1 1603 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 89:552587b429a1 1604 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
bogdanm 89:552587b429a1 1605 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
bogdanm 89:552587b429a1 1606 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
bogdanm 89:552587b429a1 1607 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
bogdanm 89:552587b429a1 1608
bogdanm 89:552587b429a1 1609 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 89:552587b429a1 1610 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
bogdanm 89:552587b429a1 1611 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
bogdanm 89:552587b429a1 1612 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
bogdanm 89:552587b429a1 1613 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
bogdanm 89:552587b429a1 1614
bogdanm 89:552587b429a1 1615 /******************** Bit definition for CAN_IER register *******************/
bogdanm 89:552587b429a1 1616 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 89:552587b429a1 1617 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 89:552587b429a1 1618 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 89:552587b429a1 1619 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 89:552587b429a1 1620 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 89:552587b429a1 1621 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 89:552587b429a1 1622 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 89:552587b429a1 1623 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 89:552587b429a1 1624 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 89:552587b429a1 1625 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 89:552587b429a1 1626 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 89:552587b429a1 1627 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 89:552587b429a1 1628 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 89:552587b429a1 1629 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 89:552587b429a1 1630 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
bogdanm 89:552587b429a1 1631 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
bogdanm 89:552587b429a1 1632 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
bogdanm 89:552587b429a1 1633 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
bogdanm 89:552587b429a1 1634 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
bogdanm 89:552587b429a1 1635
bogdanm 89:552587b429a1 1636
bogdanm 89:552587b429a1 1637 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 89:552587b429a1 1638 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 89:552587b429a1 1639 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 89:552587b429a1 1640 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 89:552587b429a1 1641
bogdanm 89:552587b429a1 1642 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 89:552587b429a1 1643 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 1644 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 1645 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 1646
bogdanm 89:552587b429a1 1647 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 89:552587b429a1 1648 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 89:552587b429a1 1649
bogdanm 89:552587b429a1 1650 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 89:552587b429a1 1651 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 89:552587b429a1 1652 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 89:552587b429a1 1653 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1654 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1655 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1656 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 1657 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 89:552587b429a1 1658 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1659 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1660 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 1661 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 89:552587b429a1 1662 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 1663 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 1664 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 89:552587b429a1 1665 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 89:552587b429a1 1666
bogdanm 89:552587b429a1 1667
bogdanm 89:552587b429a1 1668 /*!<Mailbox registers */
bogdanm 89:552587b429a1 1669 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 89:552587b429a1 1670 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 89:552587b429a1 1671 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 89:552587b429a1 1672 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 89:552587b429a1 1673 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 89:552587b429a1 1674 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 89:552587b429a1 1675
bogdanm 89:552587b429a1 1676 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 89:552587b429a1 1677 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 89:552587b429a1 1678 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 89:552587b429a1 1679 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 89:552587b429a1 1680
bogdanm 89:552587b429a1 1681 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 89:552587b429a1 1682 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 89:552587b429a1 1683 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 89:552587b429a1 1684 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 89:552587b429a1 1685 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 89:552587b429a1 1686
bogdanm 89:552587b429a1 1687 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 89:552587b429a1 1688 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 89:552587b429a1 1689 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 89:552587b429a1 1690 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 89:552587b429a1 1691 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 89:552587b429a1 1692
bogdanm 89:552587b429a1 1693 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 89:552587b429a1 1694 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 89:552587b429a1 1695 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 89:552587b429a1 1696 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 89:552587b429a1 1697 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 89:552587b429a1 1698 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 89:552587b429a1 1699
bogdanm 89:552587b429a1 1700 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 89:552587b429a1 1701 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 89:552587b429a1 1702 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 89:552587b429a1 1703 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 89:552587b429a1 1704
bogdanm 89:552587b429a1 1705 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 89:552587b429a1 1706 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 89:552587b429a1 1707 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 89:552587b429a1 1708 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 89:552587b429a1 1709 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 89:552587b429a1 1710
bogdanm 89:552587b429a1 1711 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 89:552587b429a1 1712 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 89:552587b429a1 1713 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 89:552587b429a1 1714 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 89:552587b429a1 1715 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 89:552587b429a1 1716
bogdanm 89:552587b429a1 1717 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 89:552587b429a1 1718 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 89:552587b429a1 1719 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 89:552587b429a1 1720 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 89:552587b429a1 1721 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 89:552587b429a1 1722 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 89:552587b429a1 1723
bogdanm 89:552587b429a1 1724 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 89:552587b429a1 1725 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 89:552587b429a1 1726 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 89:552587b429a1 1727 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 89:552587b429a1 1728
bogdanm 89:552587b429a1 1729 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 89:552587b429a1 1730 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 89:552587b429a1 1731 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 89:552587b429a1 1732 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 89:552587b429a1 1733 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 89:552587b429a1 1734
bogdanm 89:552587b429a1 1735 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 89:552587b429a1 1736 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 89:552587b429a1 1737 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 89:552587b429a1 1738 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 89:552587b429a1 1739 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 89:552587b429a1 1740
bogdanm 89:552587b429a1 1741 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 89:552587b429a1 1742 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 89:552587b429a1 1743 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 89:552587b429a1 1744 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 89:552587b429a1 1745 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 89:552587b429a1 1746
bogdanm 89:552587b429a1 1747 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 89:552587b429a1 1748 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 89:552587b429a1 1749 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 89:552587b429a1 1750 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 89:552587b429a1 1751
bogdanm 89:552587b429a1 1752 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 89:552587b429a1 1753 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 89:552587b429a1 1754 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 89:552587b429a1 1755 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 89:552587b429a1 1756 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 89:552587b429a1 1757
bogdanm 89:552587b429a1 1758 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 89:552587b429a1 1759 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 89:552587b429a1 1760 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 89:552587b429a1 1761 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 89:552587b429a1 1762 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 89:552587b429a1 1763
bogdanm 89:552587b429a1 1764 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 89:552587b429a1 1765 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 89:552587b429a1 1766 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 89:552587b429a1 1767 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 89:552587b429a1 1768 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 89:552587b429a1 1769
bogdanm 89:552587b429a1 1770 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 89:552587b429a1 1771 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 89:552587b429a1 1772 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 89:552587b429a1 1773 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 89:552587b429a1 1774
bogdanm 89:552587b429a1 1775 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 89:552587b429a1 1776 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 89:552587b429a1 1777 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 89:552587b429a1 1778 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 89:552587b429a1 1779 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 89:552587b429a1 1780
bogdanm 89:552587b429a1 1781 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 89:552587b429a1 1782 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 89:552587b429a1 1783 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 89:552587b429a1 1784 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 89:552587b429a1 1785 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 89:552587b429a1 1786
bogdanm 89:552587b429a1 1787 /*!<CAN filter registers */
bogdanm 89:552587b429a1 1788 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 89:552587b429a1 1789 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
bogdanm 89:552587b429a1 1790 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
bogdanm 89:552587b429a1 1791
bogdanm 89:552587b429a1 1792 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 89:552587b429a1 1793 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
bogdanm 89:552587b429a1 1794 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
bogdanm 89:552587b429a1 1795 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
bogdanm 89:552587b429a1 1796 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
bogdanm 89:552587b429a1 1797 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
bogdanm 89:552587b429a1 1798 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
bogdanm 89:552587b429a1 1799 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
bogdanm 89:552587b429a1 1800 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
bogdanm 89:552587b429a1 1801 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
bogdanm 89:552587b429a1 1802 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
bogdanm 89:552587b429a1 1803 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
bogdanm 89:552587b429a1 1804 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
bogdanm 89:552587b429a1 1805 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
bogdanm 89:552587b429a1 1806 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
bogdanm 89:552587b429a1 1807 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
bogdanm 89:552587b429a1 1808
bogdanm 89:552587b429a1 1809 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 89:552587b429a1 1810 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
bogdanm 89:552587b429a1 1811 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
bogdanm 89:552587b429a1 1812 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
bogdanm 89:552587b429a1 1813 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
bogdanm 89:552587b429a1 1814 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
bogdanm 89:552587b429a1 1815 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
bogdanm 89:552587b429a1 1816 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
bogdanm 89:552587b429a1 1817 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
bogdanm 89:552587b429a1 1818 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
bogdanm 89:552587b429a1 1819 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
bogdanm 89:552587b429a1 1820 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
bogdanm 89:552587b429a1 1821 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
bogdanm 89:552587b429a1 1822 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
bogdanm 89:552587b429a1 1823 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
bogdanm 89:552587b429a1 1824 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
bogdanm 89:552587b429a1 1825
bogdanm 89:552587b429a1 1826 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 89:552587b429a1 1827 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
bogdanm 89:552587b429a1 1828 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
bogdanm 89:552587b429a1 1829 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
bogdanm 89:552587b429a1 1830 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
bogdanm 89:552587b429a1 1831 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
bogdanm 89:552587b429a1 1832 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
bogdanm 89:552587b429a1 1833 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
bogdanm 89:552587b429a1 1834 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
bogdanm 89:552587b429a1 1835 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
bogdanm 89:552587b429a1 1836 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
bogdanm 89:552587b429a1 1837 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
bogdanm 89:552587b429a1 1838 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
bogdanm 89:552587b429a1 1839 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
bogdanm 89:552587b429a1 1840 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
bogdanm 89:552587b429a1 1841 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 89:552587b429a1 1842
bogdanm 89:552587b429a1 1843 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 89:552587b429a1 1844 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
bogdanm 89:552587b429a1 1845 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
bogdanm 89:552587b429a1 1846 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
bogdanm 89:552587b429a1 1847 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
bogdanm 89:552587b429a1 1848 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
bogdanm 89:552587b429a1 1849 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
bogdanm 89:552587b429a1 1850 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
bogdanm 89:552587b429a1 1851 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
bogdanm 89:552587b429a1 1852 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
bogdanm 89:552587b429a1 1853 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
bogdanm 89:552587b429a1 1854 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
bogdanm 89:552587b429a1 1855 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
bogdanm 89:552587b429a1 1856 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
bogdanm 89:552587b429a1 1857 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
bogdanm 89:552587b429a1 1858 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
bogdanm 89:552587b429a1 1859
bogdanm 89:552587b429a1 1860 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 89:552587b429a1 1861 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 1862 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 1863 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 1864 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 1865 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 1866 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 1867 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 1868 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 1869 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 1870 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 1871 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 1872 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 1873 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 1874 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 1875 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 1876 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 1877 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 1878 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 1879 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 1880 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 1881 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 1882 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 1883 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 1884 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 1885 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 1886 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 1887 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 1888 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 1889 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 1890 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 1891 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 1892 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 1893
bogdanm 89:552587b429a1 1894 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 89:552587b429a1 1895 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 1896 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 1897 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 1898 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 1899 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 1900 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 1901 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 1902 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 1903 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 1904 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 1905 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 1906 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 1907 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 1908 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 1909 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 1910 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 1911 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 1912 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 1913 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 1914 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 1915 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 1916 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 1917 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 1918 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 1919 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 1920 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 1921 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 1922 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 1923 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 1924 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 1925 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 1926 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 1927
bogdanm 89:552587b429a1 1928 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 89:552587b429a1 1929 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 1930 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 1931 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 1932 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 1933 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 1934 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 1935 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 1936 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 1937 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 1938 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 1939 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 1940 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 1941 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 1942 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 1943 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 1944 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 1945 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 1946 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 1947 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 1948 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 1949 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 1950 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 1951 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 1952 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 1953 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 1954 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 1955 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 1956 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 1957 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 1958 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 1959 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 1960 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 1961
bogdanm 89:552587b429a1 1962 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 89:552587b429a1 1963 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 1964 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 1965 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 1966 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 1967 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 1968 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 1969 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 1970 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 1971 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 1972 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 1973 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 1974 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 1975 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 1976 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 1977 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 1978 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 1979 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 1980 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 1981 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 1982 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 1983 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 1984 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 1985 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 1986 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 1987 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 1988 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 1989 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 1990 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 1991 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 1992 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 1993 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 1994 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 1995
bogdanm 89:552587b429a1 1996 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 89:552587b429a1 1997 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 1998 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 1999 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2000 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2001 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2002 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2003 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2004 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2005 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2006 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2007 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2008 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2009 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2010 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2011 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2012 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2013 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2014 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2015 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2016 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2017 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2018 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2019 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2020 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2021 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2022 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2023 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2024 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2025 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2026 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2027 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2028 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2029
bogdanm 89:552587b429a1 2030 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 89:552587b429a1 2031 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2032 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2033 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2034 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2035 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2036 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2037 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2038 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2039 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2040 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2041 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2042 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2043 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2044 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2045 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2046 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2047 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2048 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2049 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2050 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2051 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2052 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2053 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2054 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2055 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2056 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2057 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2058 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2059 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2060 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2061 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2062 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2063
bogdanm 89:552587b429a1 2064 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 89:552587b429a1 2065 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2066 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2067 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2068 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2069 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2070 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2071 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2072 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2073 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2074 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2075 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2076 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2077 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2078 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2079 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2080 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2081 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2082 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2083 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2084 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2085 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2086 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2087 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2088 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2089 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2090 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2091 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2092 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2093 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2094 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2095 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2096 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2097
bogdanm 89:552587b429a1 2098 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 89:552587b429a1 2099 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2100 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2101 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2102 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2103 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2104 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2105 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2106 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2107 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2108 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2109 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2110 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2111 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2112 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2113 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2114 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2115 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2116 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2117 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2118 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2119 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2120 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2121 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2122 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2123 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2124 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2125 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2126 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2127 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2128 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2129 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2130 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2131
bogdanm 89:552587b429a1 2132 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 89:552587b429a1 2133 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2134 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2135 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2136 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2137 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2138 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2139 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2140 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2141 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2142 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2143 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2144 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2145 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2146 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2147 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2148 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2149 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2150 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2151 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2152 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2153 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2154 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2155 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2156 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2157 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2158 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2159 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2160 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2161 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2162 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2163 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2164 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2165
bogdanm 89:552587b429a1 2166 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 89:552587b429a1 2167 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2168 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2169 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2170 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2171 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2172 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2173 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2174 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2175 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2176 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2177 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2178 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2179 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2180 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2181 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2182 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2183 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2184 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2185 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2186 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2187 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2188 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2189 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2190 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2191 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2192 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2193 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2194 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2195 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2196 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2197 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2198 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2199
bogdanm 89:552587b429a1 2200 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 89:552587b429a1 2201 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2202 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2203 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2204 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2205 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2206 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2207 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2208 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2209 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2210 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2211 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2212 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2213 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2214 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2215 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2216 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2217 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2218 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2219 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2220 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2221 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2222 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2223 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2224 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2225 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2226 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2227 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2228 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2229 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2230 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2231 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2232 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2233
bogdanm 89:552587b429a1 2234 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 89:552587b429a1 2235 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2236 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2237 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2238 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2239 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2240 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2241 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2242 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2243 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2244 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2245 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2246 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2247 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2248 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2249 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2250 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2251 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2252 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2253 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2254 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2255 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2256 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2257 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2258 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2259 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2260 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2261 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2262 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2263 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2264 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2265 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2266 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2267
bogdanm 89:552587b429a1 2268 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 89:552587b429a1 2269 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2270 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2271 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2272 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2273 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2274 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2275 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2276 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2277 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2278 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2279 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2280 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2281 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2282 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2283 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2284 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2285 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2286 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2287 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2288 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2289 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2290 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2291 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2292 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2293 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2294 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2295 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2296 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2297 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2298 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2299 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2300 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2301
bogdanm 89:552587b429a1 2302 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 89:552587b429a1 2303 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2304 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2305 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2306 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2307 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2308 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2309 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2310 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2311 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2312 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2313 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2314 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2315 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2316 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2317 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2318 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2319 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2320 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2321 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2322 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2323 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2324 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2325 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2326 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2327 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2328 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2329 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2330 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2331 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2332 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2333 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2334 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2335
bogdanm 89:552587b429a1 2336 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 89:552587b429a1 2337 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2338 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2339 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2340 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2341 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2342 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2343 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2344 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2345 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2346 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2347 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2348 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2349 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2350 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2351 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2352 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2353 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2354 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2355 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2356 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2357 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2358 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2359 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2360 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2361 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2362 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2363 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2364 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2365 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2366 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2367 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2368 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2369
bogdanm 89:552587b429a1 2370 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 89:552587b429a1 2371 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2372 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2373 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2374 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2375 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2376 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2377 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2378 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2379 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2380 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2381 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2382 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2383 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2384 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2385 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2386 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2387 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2388 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2389 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2390 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2391 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2392 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2393 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2394 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2395 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2396 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2397 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2398 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2399 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2400 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2401 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2402 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2403
bogdanm 89:552587b429a1 2404 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 89:552587b429a1 2405 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2406 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2407 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2408 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2409 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2410 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2411 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2412 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2413 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2414 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2415 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2416 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2417 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2418 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2419 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2420 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2421 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2422 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2423 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2424 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2425 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2426 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2427 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2428 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2429 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2430 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2431 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2432 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2433 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2434 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2435 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2436 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2437
bogdanm 89:552587b429a1 2438 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 89:552587b429a1 2439 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2440 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2441 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2442 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2443 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2444 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2445 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2446 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2447 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2448 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2449 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2450 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2451 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2452 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2453 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2454 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2455 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2456 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2457 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2458 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2459 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2460 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2461 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2462 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2463 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2464 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2465 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2466 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2467 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2468 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2469 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2470 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2471
bogdanm 89:552587b429a1 2472 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 89:552587b429a1 2473 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2474 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2475 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2476 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2477 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2478 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2479 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2480 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2481 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2482 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2483 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2484 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2485 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2486 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2487 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2488 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2489 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2490 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2491 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2492 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2493 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2494 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2495 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2496 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2497 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2498 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2499 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2500 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2501 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2502 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2503 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2504 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2505
bogdanm 89:552587b429a1 2506 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 89:552587b429a1 2507 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2508 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2509 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2510 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2511 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2512 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2513 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2514 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2515 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2516 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2517 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2518 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2519 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2520 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2521 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2522 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2523 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2524 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2525 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2526 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2527 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2528 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2529 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2530 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2531 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2532 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2533 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2534 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2535 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2536 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2537 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2538 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2539
bogdanm 89:552587b429a1 2540 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 89:552587b429a1 2541 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2542 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2543 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2544 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2545 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2546 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2547 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2548 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2549 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2550 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2551 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2552 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2553 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2554 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2555 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2556 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2557 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2558 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2559 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2560 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2561 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2562 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2563 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2564 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2565 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2566 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2567 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2568 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2569 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2570 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2571 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2572 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2573
bogdanm 89:552587b429a1 2574 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 89:552587b429a1 2575 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2576 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2577 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2578 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2579 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2580 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2581 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2582 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2583 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2584 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2585 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2586 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2587 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2588 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2589 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2590 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2591 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2592 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2593 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2594 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2595 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2596 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2597 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2598 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2599 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2600 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2601 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2602 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2603 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2604 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2605 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2606 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2607
bogdanm 89:552587b429a1 2608 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 89:552587b429a1 2609 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2610 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2611 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2612 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2613 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2614 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2615 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2616 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2617 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2618 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2619 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2620 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2621 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2622 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2623 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2624 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2625 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2626 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2627 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2628 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2629 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2630 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2631 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2632 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2633 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2634 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2635 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2636 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2637 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2638 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2639 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2640 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2641
bogdanm 89:552587b429a1 2642 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 89:552587b429a1 2643 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2644 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2645 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2646 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2647 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2648 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2649 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2650 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2651 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2652 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2653 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2654 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2655 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2656 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2657 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2658 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2659 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2660 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2661 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2662 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2663 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2664 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2665 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2666 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2667 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2668 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2669 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2670 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2671 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2672 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2673 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2674 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2675
bogdanm 89:552587b429a1 2676 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 89:552587b429a1 2677 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2678 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2679 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2680 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2681 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2682 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2683 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2684 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2685 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2686 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2687 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2688 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2689 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2690 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2691 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2692 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2693 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2694 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2695 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2696 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2697 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2698 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2699 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2700 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2701 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2702 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2703 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2704 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2705 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2706 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2707 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2708 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2709
bogdanm 89:552587b429a1 2710 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 89:552587b429a1 2711 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2712 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2713 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2714 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2715 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2716 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2717 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2718 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2719 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2720 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2721 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2722 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2723 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2724 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2725 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2726 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2727 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2728 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2729 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2730 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2731 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2732 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2733 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2734 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2735 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2736 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2737 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2738 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2739 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2740 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2741 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2742 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2743
bogdanm 89:552587b429a1 2744 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 89:552587b429a1 2745 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2746 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2747 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2748 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2749 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2750 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2751 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2752 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2753 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2754 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2755 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2756 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2757 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2758 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2759 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2760 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2761 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2762 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2763 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2764 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2765 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2766 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2767 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2768 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2769 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2770 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2771 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2772 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2773 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2774 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2775 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2776 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2777
bogdanm 89:552587b429a1 2778 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 89:552587b429a1 2779 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 89:552587b429a1 2780 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 89:552587b429a1 2781 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 89:552587b429a1 2782 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 89:552587b429a1 2783 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 89:552587b429a1 2784 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 89:552587b429a1 2785 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 89:552587b429a1 2786 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 89:552587b429a1 2787 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 89:552587b429a1 2788 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 89:552587b429a1 2789 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 89:552587b429a1 2790 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 89:552587b429a1 2791 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 89:552587b429a1 2792 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 89:552587b429a1 2793 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 89:552587b429a1 2794 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 89:552587b429a1 2795 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 89:552587b429a1 2796 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 89:552587b429a1 2797 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 89:552587b429a1 2798 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 89:552587b429a1 2799 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 89:552587b429a1 2800 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 89:552587b429a1 2801 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 89:552587b429a1 2802 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 89:552587b429a1 2803 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 89:552587b429a1 2804 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 89:552587b429a1 2805 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 89:552587b429a1 2806 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 89:552587b429a1 2807 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 89:552587b429a1 2808 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 89:552587b429a1 2809 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 89:552587b429a1 2810 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 89:552587b429a1 2811
bogdanm 89:552587b429a1 2812 /******************************************************************************/
bogdanm 89:552587b429a1 2813 /* */
bogdanm 89:552587b429a1 2814 /* CRC calculation unit */
bogdanm 89:552587b429a1 2815 /* */
bogdanm 89:552587b429a1 2816 /******************************************************************************/
bogdanm 89:552587b429a1 2817 /******************* Bit definition for CRC_DR register *********************/
bogdanm 89:552587b429a1 2818 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 89:552587b429a1 2819
bogdanm 89:552587b429a1 2820
bogdanm 89:552587b429a1 2821 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 89:552587b429a1 2822 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 89:552587b429a1 2823
bogdanm 89:552587b429a1 2824
bogdanm 89:552587b429a1 2825 /******************** Bit definition for CRC_CR register ********************/
bogdanm 89:552587b429a1 2826 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
bogdanm 89:552587b429a1 2827
bogdanm 89:552587b429a1 2828
bogdanm 89:552587b429a1 2829 /******************************************************************************/
bogdanm 89:552587b429a1 2830 /* */
bogdanm 89:552587b429a1 2831 /* Digital to Analog Converter */
bogdanm 89:552587b429a1 2832 /* */
bogdanm 89:552587b429a1 2833 /******************************************************************************/
bogdanm 89:552587b429a1 2834 /******************** Bit definition for DAC_CR register ********************/
bogdanm 89:552587b429a1 2835 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
bogdanm 89:552587b429a1 2836 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
bogdanm 89:552587b429a1 2837 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
bogdanm 89:552587b429a1 2838
bogdanm 89:552587b429a1 2839 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 89:552587b429a1 2840 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 89:552587b429a1 2841 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 89:552587b429a1 2842 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 89:552587b429a1 2843
bogdanm 89:552587b429a1 2844 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 89:552587b429a1 2845 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 89:552587b429a1 2846 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 89:552587b429a1 2847
bogdanm 89:552587b429a1 2848 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 89:552587b429a1 2849 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 2850 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 2851 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 2852 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 2853
bogdanm 89:552587b429a1 2854 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
bogdanm 89:552587b429a1 2855 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
bogdanm 89:552587b429a1 2856 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
bogdanm 89:552587b429a1 2857 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
bogdanm 89:552587b429a1 2858
bogdanm 89:552587b429a1 2859 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 89:552587b429a1 2860 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
bogdanm 89:552587b429a1 2861 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
bogdanm 89:552587b429a1 2862 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
bogdanm 89:552587b429a1 2863
bogdanm 89:552587b429a1 2864 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 89:552587b429a1 2865 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 89:552587b429a1 2866 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 89:552587b429a1 2867
bogdanm 89:552587b429a1 2868 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 89:552587b429a1 2869 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 2870 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 2871 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 2872 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 2873
bogdanm 89:552587b429a1 2874 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
bogdanm 89:552587b429a1 2875
bogdanm 89:552587b429a1 2876 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 89:552587b429a1 2877 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
bogdanm 89:552587b429a1 2878 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
bogdanm 89:552587b429a1 2879
bogdanm 89:552587b429a1 2880 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 89:552587b429a1 2881 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 89:552587b429a1 2882
bogdanm 89:552587b429a1 2883 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 89:552587b429a1 2884 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 89:552587b429a1 2885
bogdanm 89:552587b429a1 2886 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 89:552587b429a1 2887 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 89:552587b429a1 2888
bogdanm 89:552587b429a1 2889 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 89:552587b429a1 2890 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 89:552587b429a1 2891
bogdanm 89:552587b429a1 2892 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 89:552587b429a1 2893 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 89:552587b429a1 2894
bogdanm 89:552587b429a1 2895 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 89:552587b429a1 2896 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 89:552587b429a1 2897
bogdanm 89:552587b429a1 2898 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 89:552587b429a1 2899 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 89:552587b429a1 2900 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 89:552587b429a1 2901
bogdanm 89:552587b429a1 2902 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 89:552587b429a1 2903 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 89:552587b429a1 2904 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 89:552587b429a1 2905
bogdanm 89:552587b429a1 2906 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 89:552587b429a1 2907 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 89:552587b429a1 2908 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 89:552587b429a1 2909
bogdanm 89:552587b429a1 2910 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 89:552587b429a1 2911 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
bogdanm 89:552587b429a1 2912
bogdanm 89:552587b429a1 2913 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 89:552587b429a1 2914 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
bogdanm 89:552587b429a1 2915
bogdanm 89:552587b429a1 2916 /******************** Bit definition for DAC_SR register ********************/
bogdanm 89:552587b429a1 2917 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
bogdanm 89:552587b429a1 2918 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
bogdanm 89:552587b429a1 2919
bogdanm 89:552587b429a1 2920 /******************************************************************************/
bogdanm 89:552587b429a1 2921 /* */
bogdanm 89:552587b429a1 2922 /* Debug MCU */
bogdanm 89:552587b429a1 2923 /* */
bogdanm 89:552587b429a1 2924 /******************************************************************************/
bogdanm 89:552587b429a1 2925
bogdanm 89:552587b429a1 2926 /******************************************************************************/
bogdanm 89:552587b429a1 2927 /* */
bogdanm 89:552587b429a1 2928 /* DCMI */
bogdanm 89:552587b429a1 2929 /* */
bogdanm 89:552587b429a1 2930 /******************************************************************************/
bogdanm 89:552587b429a1 2931 /******************** Bits definition for DCMI_CR register ******************/
bogdanm 89:552587b429a1 2932 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2933 #define DCMI_CR_CM ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2934 #define DCMI_CR_CROP ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2935 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 2936 #define DCMI_CR_ESS ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 2937 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 2938 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 2939 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 2940 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 2941 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 2942 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 2943 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 2944 #define DCMI_CR_CRE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 2945 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 2946
bogdanm 89:552587b429a1 2947 /******************** Bits definition for DCMI_SR register ******************/
bogdanm 89:552587b429a1 2948 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2949 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2950 #define DCMI_SR_FNE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2951
bogdanm 89:552587b429a1 2952 /******************** Bits definition for DCMI_RISR register ****************/
bogdanm 89:552587b429a1 2953 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2954 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2955 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2956 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 2957 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 2958
bogdanm 89:552587b429a1 2959 /******************** Bits definition for DCMI_IER register *****************/
bogdanm 89:552587b429a1 2960 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2961 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2962 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2963 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 2964 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 2965
bogdanm 89:552587b429a1 2966 /******************** Bits definition for DCMI_MISR register ****************/
bogdanm 89:552587b429a1 2967 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2968 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2969 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2970 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 2971 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 2972
bogdanm 89:552587b429a1 2973 /******************** Bits definition for DCMI_ICR register *****************/
bogdanm 89:552587b429a1 2974 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 2975 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 2976 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 2977 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 2978 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 2979
bogdanm 89:552587b429a1 2980 /******************************************************************************/
bogdanm 89:552587b429a1 2981 /* */
bogdanm 89:552587b429a1 2982 /* DMA Controller */
bogdanm 89:552587b429a1 2983 /* */
bogdanm 89:552587b429a1 2984 /******************************************************************************/
bogdanm 89:552587b429a1 2985 /******************** Bits definition for DMA_SxCR register *****************/
bogdanm 89:552587b429a1 2986 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
bogdanm 89:552587b429a1 2987 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 2988 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 2989 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 2990 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
bogdanm 89:552587b429a1 2991 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 2992 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 2993 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
bogdanm 89:552587b429a1 2994 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 2995 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 2996 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 2997 #define DMA_SxCR_CT ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 2998 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 2999 #define DMA_SxCR_PL ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 3000 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3001 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 3002 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 3003 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
bogdanm 89:552587b429a1 3004 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 3005 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 3006 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
bogdanm 89:552587b429a1 3007 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3008 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 3009 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3010 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3011 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3012 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 3013 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3014 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3015 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3016 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3017 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3018 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3019 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3020 #define DMA_SxCR_EN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3021
bogdanm 89:552587b429a1 3022 /******************** Bits definition for DMA_SxCNDTR register **************/
bogdanm 89:552587b429a1 3023 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
bogdanm 89:552587b429a1 3024 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3025 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3026 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3027 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3028 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3029 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3030 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3031 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3032 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3033 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3034 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3035 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3036 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 3037 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 3038 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 3039 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 3040
bogdanm 89:552587b429a1 3041 /******************** Bits definition for DMA_SxFCR register ****************/
bogdanm 89:552587b429a1 3042 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3043 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
bogdanm 89:552587b429a1 3044 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3045 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3046 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3047 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3048 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 3049 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3050 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3051
bogdanm 89:552587b429a1 3052 /******************** Bits definition for DMA_LISR register *****************/
bogdanm 89:552587b429a1 3053 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3054 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3055 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3056 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3057 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3058 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3059 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3060 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3061 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3062 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3063 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3064 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3065 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3066 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3067 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3068 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3069 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3070 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3071 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3072 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3073
bogdanm 89:552587b429a1 3074 /******************** Bits definition for DMA_HISR register *****************/
bogdanm 89:552587b429a1 3075 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3076 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3077 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3078 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3079 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3080 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3081 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3082 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3083 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3084 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3085 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3086 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3087 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3088 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3089 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3090 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3091 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3092 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3093 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3094 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3095
bogdanm 89:552587b429a1 3096 /******************** Bits definition for DMA_LIFCR register ****************/
bogdanm 89:552587b429a1 3097 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3098 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3099 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3100 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3101 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3102 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3103 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3104 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3105 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3106 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3107 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3108 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3109 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3110 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3111 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3112 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3113 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3114 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3115 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3116 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3117
bogdanm 89:552587b429a1 3118 /******************** Bits definition for DMA_HIFCR register ****************/
bogdanm 89:552587b429a1 3119 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3120 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3121 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3122 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3123 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3124 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3125 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3126 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3127 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3128 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3129 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3130 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3131 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3132 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3133 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3134 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3135 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3136 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3137 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3138 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3139
bogdanm 89:552587b429a1 3140
bogdanm 89:552587b429a1 3141 /******************************************************************************/
bogdanm 89:552587b429a1 3142 /* */
bogdanm 89:552587b429a1 3143 /* External Interrupt/Event Controller */
bogdanm 89:552587b429a1 3144 /* */
bogdanm 89:552587b429a1 3145 /******************************************************************************/
bogdanm 89:552587b429a1 3146 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 89:552587b429a1 3147 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 89:552587b429a1 3148 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 89:552587b429a1 3149 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 89:552587b429a1 3150 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 89:552587b429a1 3151 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 89:552587b429a1 3152 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 89:552587b429a1 3153 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 89:552587b429a1 3154 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 89:552587b429a1 3155 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 89:552587b429a1 3156 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 89:552587b429a1 3157 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 89:552587b429a1 3158 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 89:552587b429a1 3159 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 89:552587b429a1 3160 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 89:552587b429a1 3161 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 89:552587b429a1 3162 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 89:552587b429a1 3163 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 89:552587b429a1 3164 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 89:552587b429a1 3165 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 89:552587b429a1 3166 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 89:552587b429a1 3167
bogdanm 89:552587b429a1 3168 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 89:552587b429a1 3169 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 89:552587b429a1 3170 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 89:552587b429a1 3171 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 89:552587b429a1 3172 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 89:552587b429a1 3173 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 89:552587b429a1 3174 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 89:552587b429a1 3175 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 89:552587b429a1 3176 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 89:552587b429a1 3177 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 89:552587b429a1 3178 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 89:552587b429a1 3179 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 89:552587b429a1 3180 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 89:552587b429a1 3181 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 89:552587b429a1 3182 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 89:552587b429a1 3183 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 89:552587b429a1 3184 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 89:552587b429a1 3185 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 89:552587b429a1 3186 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 89:552587b429a1 3187 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 89:552587b429a1 3188 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 89:552587b429a1 3189
bogdanm 89:552587b429a1 3190 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 89:552587b429a1 3191 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 89:552587b429a1 3192 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 89:552587b429a1 3193 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 89:552587b429a1 3194 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 89:552587b429a1 3195 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 89:552587b429a1 3196 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 89:552587b429a1 3197 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 89:552587b429a1 3198 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 89:552587b429a1 3199 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 89:552587b429a1 3200 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 89:552587b429a1 3201 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 89:552587b429a1 3202 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 89:552587b429a1 3203 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 89:552587b429a1 3204 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 89:552587b429a1 3205 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 89:552587b429a1 3206 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 89:552587b429a1 3207 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 89:552587b429a1 3208 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 89:552587b429a1 3209 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 89:552587b429a1 3210 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 89:552587b429a1 3211
bogdanm 89:552587b429a1 3212 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 89:552587b429a1 3213 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 89:552587b429a1 3214 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 89:552587b429a1 3215 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 89:552587b429a1 3216 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 89:552587b429a1 3217 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 89:552587b429a1 3218 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 89:552587b429a1 3219 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 89:552587b429a1 3220 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 89:552587b429a1 3221 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 89:552587b429a1 3222 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 89:552587b429a1 3223 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 89:552587b429a1 3224 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 89:552587b429a1 3225 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 89:552587b429a1 3226 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 89:552587b429a1 3227 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 89:552587b429a1 3228 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 89:552587b429a1 3229 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 89:552587b429a1 3230 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 89:552587b429a1 3231 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 89:552587b429a1 3232 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 89:552587b429a1 3233
bogdanm 89:552587b429a1 3234 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 89:552587b429a1 3235 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 89:552587b429a1 3236 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 89:552587b429a1 3237 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 89:552587b429a1 3238 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 89:552587b429a1 3239 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 89:552587b429a1 3240 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 89:552587b429a1 3241 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 89:552587b429a1 3242 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 89:552587b429a1 3243 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 89:552587b429a1 3244 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 89:552587b429a1 3245 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 89:552587b429a1 3246 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 89:552587b429a1 3247 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 89:552587b429a1 3248 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 89:552587b429a1 3249 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 89:552587b429a1 3250 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 89:552587b429a1 3251 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 89:552587b429a1 3252 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 89:552587b429a1 3253 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 89:552587b429a1 3254 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 89:552587b429a1 3255
bogdanm 89:552587b429a1 3256 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 89:552587b429a1 3257 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 89:552587b429a1 3258 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 89:552587b429a1 3259 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 89:552587b429a1 3260 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 89:552587b429a1 3261 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 89:552587b429a1 3262 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 89:552587b429a1 3263 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 89:552587b429a1 3264 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 89:552587b429a1 3265 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 89:552587b429a1 3266 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 89:552587b429a1 3267 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 89:552587b429a1 3268 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 89:552587b429a1 3269 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 89:552587b429a1 3270 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 89:552587b429a1 3271 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 89:552587b429a1 3272 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 89:552587b429a1 3273 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 89:552587b429a1 3274 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 89:552587b429a1 3275 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 89:552587b429a1 3276 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 89:552587b429a1 3277
bogdanm 89:552587b429a1 3278 /******************************************************************************/
bogdanm 89:552587b429a1 3279 /* */
bogdanm 89:552587b429a1 3280 /* FLASH */
bogdanm 89:552587b429a1 3281 /* */
bogdanm 89:552587b429a1 3282 /******************************************************************************/
bogdanm 89:552587b429a1 3283 /******************* Bits definition for FLASH_ACR register *****************/
bogdanm 89:552587b429a1 3284 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 3285 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 3286 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3287 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3288 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 3289 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3290 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
bogdanm 89:552587b429a1 3291 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
bogdanm 89:552587b429a1 3292 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
bogdanm 89:552587b429a1 3293
bogdanm 89:552587b429a1 3294 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3295 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3296 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3297 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3298 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 3299 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
bogdanm 89:552587b429a1 3300 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
bogdanm 89:552587b429a1 3301
bogdanm 89:552587b429a1 3302 /******************* Bits definition for FLASH_SR register ******************/
bogdanm 89:552587b429a1 3303 #define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3304 #define FLASH_SR_SOP ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3305 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3306 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3307 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3308 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3309 #define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3310
bogdanm 89:552587b429a1 3311 /******************* Bits definition for FLASH_CR register ******************/
bogdanm 89:552587b429a1 3312 #define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3313 #define FLASH_CR_SER ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3314 #define FLASH_CR_MER ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3315 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
bogdanm 89:552587b429a1 3316 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3317 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 3318 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3319 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3320 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3321 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 3322 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3323 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3324 #define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3325 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3326 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 3327
bogdanm 89:552587b429a1 3328 /******************* Bits definition for FLASH_OPTCR register ***************/
bogdanm 89:552587b429a1 3329 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 3330 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 3331 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 3332 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 3333 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 3334
bogdanm 89:552587b429a1 3335 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 3336 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 3337 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 3338 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
bogdanm 89:552587b429a1 3339 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 3340 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 3341 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 3342 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 3343 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 3344 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 3345 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 3346 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 3347 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
bogdanm 89:552587b429a1 3348 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3349 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 3350 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3351 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3352 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3353 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3354 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3355 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 3356 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3357 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3358 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3359 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3360
bogdanm 89:552587b429a1 3361 /****************** Bits definition for FLASH_OPTCR1 register ***************/
bogdanm 89:552587b429a1 3362 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
bogdanm 89:552587b429a1 3363 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 3364 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 3365 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 3366 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 3367 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 3368 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 3369 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 3370 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 3371 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 3372 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 3373 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 3374 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 3375
bogdanm 89:552587b429a1 3376 /******************************************************************************/
bogdanm 89:552587b429a1 3377 /* */
bogdanm 89:552587b429a1 3378 /* Flexible Static Memory Controller */
bogdanm 89:552587b429a1 3379 /* */
bogdanm 89:552587b429a1 3380 /******************************************************************************/
bogdanm 89:552587b429a1 3381 /****************** Bit definition for FSMC_BCR1 register *******************/
bogdanm 89:552587b429a1 3382 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 89:552587b429a1 3383 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 89:552587b429a1 3384
bogdanm 89:552587b429a1 3385 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 89:552587b429a1 3386 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 89:552587b429a1 3387 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 89:552587b429a1 3388
bogdanm 89:552587b429a1 3389 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 89:552587b429a1 3390 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3391 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3392
bogdanm 89:552587b429a1 3393 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 89:552587b429a1 3394 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 89:552587b429a1 3395 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 89:552587b429a1 3396 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 89:552587b429a1 3397 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 89:552587b429a1 3398 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 89:552587b429a1 3399 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 89:552587b429a1 3400 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 89:552587b429a1 3401 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 89:552587b429a1 3402 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 89:552587b429a1 3403
bogdanm 89:552587b429a1 3404 /****************** Bit definition for FSMC_BCR2 register *******************/
bogdanm 89:552587b429a1 3405 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 89:552587b429a1 3406 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 89:552587b429a1 3407
bogdanm 89:552587b429a1 3408 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 89:552587b429a1 3409 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 89:552587b429a1 3410 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 89:552587b429a1 3411
bogdanm 89:552587b429a1 3412 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 89:552587b429a1 3413 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3414 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3415
bogdanm 89:552587b429a1 3416 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 89:552587b429a1 3417 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 89:552587b429a1 3418 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 89:552587b429a1 3419 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 89:552587b429a1 3420 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 89:552587b429a1 3421 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 89:552587b429a1 3422 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 89:552587b429a1 3423 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 89:552587b429a1 3424 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 89:552587b429a1 3425 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 89:552587b429a1 3426
bogdanm 89:552587b429a1 3427 /****************** Bit definition for FSMC_BCR3 register *******************/
bogdanm 89:552587b429a1 3428 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 89:552587b429a1 3429 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 89:552587b429a1 3430
bogdanm 89:552587b429a1 3431 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 89:552587b429a1 3432 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 89:552587b429a1 3433 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 89:552587b429a1 3434
bogdanm 89:552587b429a1 3435 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 89:552587b429a1 3436 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3437 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3438
bogdanm 89:552587b429a1 3439 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 89:552587b429a1 3440 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 89:552587b429a1 3441 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 89:552587b429a1 3442 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 89:552587b429a1 3443 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 89:552587b429a1 3444 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 89:552587b429a1 3445 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 89:552587b429a1 3446 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 89:552587b429a1 3447 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 89:552587b429a1 3448 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 89:552587b429a1 3449
bogdanm 89:552587b429a1 3450 /****************** Bit definition for FSMC_BCR4 register *******************/
bogdanm 89:552587b429a1 3451 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 89:552587b429a1 3452 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 89:552587b429a1 3453
bogdanm 89:552587b429a1 3454 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 89:552587b429a1 3455 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 89:552587b429a1 3456 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 89:552587b429a1 3457
bogdanm 89:552587b429a1 3458 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 89:552587b429a1 3459 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3460 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3461
bogdanm 89:552587b429a1 3462 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 89:552587b429a1 3463 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 89:552587b429a1 3464 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 89:552587b429a1 3465 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 89:552587b429a1 3466 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 89:552587b429a1 3467 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 89:552587b429a1 3468 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 89:552587b429a1 3469 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 89:552587b429a1 3470 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 89:552587b429a1 3471 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 89:552587b429a1 3472
bogdanm 89:552587b429a1 3473 /****************** Bit definition for FSMC_BTR1 register ******************/
bogdanm 89:552587b429a1 3474 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3475 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3476 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3477 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3478 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3479
bogdanm 89:552587b429a1 3480 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3481 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3482 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3483 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3484 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3485
bogdanm 89:552587b429a1 3486 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3487 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3488 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3489 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3490 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3491
bogdanm 89:552587b429a1 3492 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 89:552587b429a1 3493 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3494 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3495 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3496 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3497
bogdanm 89:552587b429a1 3498 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3499 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3500 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3501 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3502 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3503
bogdanm 89:552587b429a1 3504 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3505 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3506 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3507 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3508 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3509
bogdanm 89:552587b429a1 3510 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3511 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3512 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3513
bogdanm 89:552587b429a1 3514 /****************** Bit definition for FSMC_BTR2 register *******************/
bogdanm 89:552587b429a1 3515 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3516 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3517 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3518 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3519 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3520
bogdanm 89:552587b429a1 3521 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3522 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3523 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3524 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3525 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3526
bogdanm 89:552587b429a1 3527 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3528 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3529 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3530 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3531 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3532
bogdanm 89:552587b429a1 3533 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 89:552587b429a1 3534 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3535 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3536 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3537 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3538
bogdanm 89:552587b429a1 3539 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3540 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3541 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3542 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3543 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3544
bogdanm 89:552587b429a1 3545 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3546 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3547 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3548 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3549 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3550
bogdanm 89:552587b429a1 3551 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3552 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3553 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3554
bogdanm 89:552587b429a1 3555 /******************* Bit definition for FSMC_BTR3 register *******************/
bogdanm 89:552587b429a1 3556 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3557 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3558 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3559 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3560 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3561
bogdanm 89:552587b429a1 3562 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3563 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3564 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3565 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3566 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3567
bogdanm 89:552587b429a1 3568 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3569 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3570 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3571 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3572 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3573
bogdanm 89:552587b429a1 3574 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 89:552587b429a1 3575 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3576 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3577 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3578 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3579
bogdanm 89:552587b429a1 3580 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3581 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3582 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3583 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3584 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3585
bogdanm 89:552587b429a1 3586 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3587 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3588 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3589 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3590 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3591
bogdanm 89:552587b429a1 3592 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3593 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3594 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3595
bogdanm 89:552587b429a1 3596 /****************** Bit definition for FSMC_BTR4 register *******************/
bogdanm 89:552587b429a1 3597 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3598 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3599 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3600 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3601 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3602
bogdanm 89:552587b429a1 3603 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3604 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3605 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3606 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3607 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3608
bogdanm 89:552587b429a1 3609 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3610 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3611 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3612 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3613 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3614
bogdanm 89:552587b429a1 3615 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 89:552587b429a1 3616 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3617 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3618 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3619 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3620
bogdanm 89:552587b429a1 3621 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3622 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3623 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3624 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3625 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3626
bogdanm 89:552587b429a1 3627 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3628 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3629 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3630 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3631 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3632
bogdanm 89:552587b429a1 3633 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3634 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3635 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3636
bogdanm 89:552587b429a1 3637 /****************** Bit definition for FSMC_BWTR1 register ******************/
bogdanm 89:552587b429a1 3638 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3639 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3640 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3641 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3642 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3643
bogdanm 89:552587b429a1 3644 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3645 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3646 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3647 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3648 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3649
bogdanm 89:552587b429a1 3650 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3651 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3652 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3653 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3654 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3655
bogdanm 89:552587b429a1 3656 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3657 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3658 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3659 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3660 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3661
bogdanm 89:552587b429a1 3662 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3663 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3664 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3665 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3666 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3667
bogdanm 89:552587b429a1 3668 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3669 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3670 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3671
bogdanm 89:552587b429a1 3672 /****************** Bit definition for FSMC_BWTR2 register ******************/
bogdanm 89:552587b429a1 3673 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3674 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3675 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3676 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3677 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3678
bogdanm 89:552587b429a1 3679 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3680 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3681 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3682 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3683 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3684
bogdanm 89:552587b429a1 3685 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3686 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3687 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3688 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3689 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3690
bogdanm 89:552587b429a1 3691 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3692 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3693 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
bogdanm 89:552587b429a1 3694 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3695 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3696
bogdanm 89:552587b429a1 3697 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3698 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3699 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3700 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3701 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3702
bogdanm 89:552587b429a1 3703 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3704 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3705 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3706
bogdanm 89:552587b429a1 3707 /****************** Bit definition for FSMC_BWTR3 register ******************/
bogdanm 89:552587b429a1 3708 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3709 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3710 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3711 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3712 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3713
bogdanm 89:552587b429a1 3714 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3715 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3716 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3717 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3718 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3719
bogdanm 89:552587b429a1 3720 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3721 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3722 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3723 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3724 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3725
bogdanm 89:552587b429a1 3726 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3727 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3728 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3729 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3730 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3731
bogdanm 89:552587b429a1 3732 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3733 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3734 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3735 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3736 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3737
bogdanm 89:552587b429a1 3738 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3739 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3740 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3741
bogdanm 89:552587b429a1 3742 /****************** Bit definition for FSMC_BWTR4 register ******************/
bogdanm 89:552587b429a1 3743 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 89:552587b429a1 3744 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3745 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3746 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3747 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3748
bogdanm 89:552587b429a1 3749 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 89:552587b429a1 3750 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3751 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3752 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 3753 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 3754
bogdanm 89:552587b429a1 3755 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 89:552587b429a1 3756 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3757 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3758 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3759 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3760
bogdanm 89:552587b429a1 3761 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 89:552587b429a1 3762 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3763 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3764 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3765 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3766
bogdanm 89:552587b429a1 3767 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 89:552587b429a1 3768 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3769 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3770 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3771 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3772
bogdanm 89:552587b429a1 3773 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 89:552587b429a1 3774 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3775 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3776
bogdanm 89:552587b429a1 3777 /****************** Bit definition for FSMC_PCR2 register *******************/
bogdanm 89:552587b429a1 3778 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 89:552587b429a1 3779 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 89:552587b429a1 3780 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 89:552587b429a1 3781
bogdanm 89:552587b429a1 3782 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 89:552587b429a1 3783 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3784 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3785
bogdanm 89:552587b429a1 3786 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 89:552587b429a1 3787
bogdanm 89:552587b429a1 3788 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 89:552587b429a1 3789 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 89:552587b429a1 3790 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 89:552587b429a1 3791 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 89:552587b429a1 3792 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3793
bogdanm 89:552587b429a1 3794 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 89:552587b429a1 3795 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3796 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3797 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3798 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3799
bogdanm 89:552587b429a1 3800 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
bogdanm 89:552587b429a1 3801 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3802 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3803 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3804
bogdanm 89:552587b429a1 3805 /****************** Bit definition for FSMC_PCR3 register *******************/
bogdanm 89:552587b429a1 3806 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 89:552587b429a1 3807 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 89:552587b429a1 3808 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 89:552587b429a1 3809
bogdanm 89:552587b429a1 3810 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 89:552587b429a1 3811 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3812 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3813
bogdanm 89:552587b429a1 3814 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 89:552587b429a1 3815
bogdanm 89:552587b429a1 3816 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 89:552587b429a1 3817 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 89:552587b429a1 3818 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 89:552587b429a1 3819 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 89:552587b429a1 3820 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3821
bogdanm 89:552587b429a1 3822 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 89:552587b429a1 3823 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3824 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3825 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3826 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3827
bogdanm 89:552587b429a1 3828 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 89:552587b429a1 3829 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3830 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3831 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3832
bogdanm 89:552587b429a1 3833 /****************** Bit definition for FSMC_PCR4 register *******************/
bogdanm 89:552587b429a1 3834 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 89:552587b429a1 3835 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 89:552587b429a1 3836 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 89:552587b429a1 3837
bogdanm 89:552587b429a1 3838 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 89:552587b429a1 3839 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 3840 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 3841
bogdanm 89:552587b429a1 3842 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 89:552587b429a1 3843
bogdanm 89:552587b429a1 3844 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 89:552587b429a1 3845 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 89:552587b429a1 3846 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 89:552587b429a1 3847 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 89:552587b429a1 3848 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3849
bogdanm 89:552587b429a1 3850 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 89:552587b429a1 3851 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3852 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3853 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3854 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3855
bogdanm 89:552587b429a1 3856 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 89:552587b429a1 3857 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3858 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3859 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3860
bogdanm 89:552587b429a1 3861 /******************* Bit definition for FSMC_SR2 register *******************/
bogdanm 89:552587b429a1 3862 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 89:552587b429a1 3863 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 89:552587b429a1 3864 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 89:552587b429a1 3865 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 89:552587b429a1 3866 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 89:552587b429a1 3867 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 89:552587b429a1 3868 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 89:552587b429a1 3869
bogdanm 89:552587b429a1 3870 /******************* Bit definition for FSMC_SR3 register *******************/
bogdanm 89:552587b429a1 3871 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 89:552587b429a1 3872 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 89:552587b429a1 3873 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 89:552587b429a1 3874 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 89:552587b429a1 3875 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 89:552587b429a1 3876 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 89:552587b429a1 3877 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 89:552587b429a1 3878
bogdanm 89:552587b429a1 3879 /******************* Bit definition for FSMC_SR4 register *******************/
bogdanm 89:552587b429a1 3880 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 89:552587b429a1 3881 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
bogdanm 89:552587b429a1 3882 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 89:552587b429a1 3883 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 89:552587b429a1 3884 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 89:552587b429a1 3885 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 89:552587b429a1 3886 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
bogdanm 89:552587b429a1 3887
bogdanm 89:552587b429a1 3888 /****************** Bit definition for FSMC_PMEM2 register ******************/
bogdanm 89:552587b429a1 3889 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
bogdanm 89:552587b429a1 3890 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3891 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3892 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3893 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3894 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 3895 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 3896 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 3897 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 3898
bogdanm 89:552587b429a1 3899 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
bogdanm 89:552587b429a1 3900 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3901 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3902 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3903 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3904 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3905 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3906 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3907 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3908
bogdanm 89:552587b429a1 3909 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
bogdanm 89:552587b429a1 3910 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3911 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3912 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3913 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3914 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3915 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3916 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3917 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3918
bogdanm 89:552587b429a1 3919 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
bogdanm 89:552587b429a1 3920 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3921 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3922 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3923 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3924 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3925 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3926 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3927 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3928
bogdanm 89:552587b429a1 3929 /****************** Bit definition for FSMC_PMEM3 register ******************/
bogdanm 89:552587b429a1 3930 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
bogdanm 89:552587b429a1 3931 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3932 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3933 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3934 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3935 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 3936 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 3937 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 3938 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 3939
bogdanm 89:552587b429a1 3940 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
bogdanm 89:552587b429a1 3941 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3942 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3943 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3944 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3945 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3946 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3947 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3948 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3949
bogdanm 89:552587b429a1 3950 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
bogdanm 89:552587b429a1 3951 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3952 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3953 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3954 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3955 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3956 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3957 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3958 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3959
bogdanm 89:552587b429a1 3960 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
bogdanm 89:552587b429a1 3961 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3962 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3963 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3964 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3965 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3966 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3967 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3968 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3969
bogdanm 89:552587b429a1 3970 /****************** Bit definition for FSMC_PMEM4 register ******************/
bogdanm 89:552587b429a1 3971 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
bogdanm 89:552587b429a1 3972 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 3973 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 3974 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 3975 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 3976 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 3977 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 3978 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 3979 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 3980
bogdanm 89:552587b429a1 3981 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
bogdanm 89:552587b429a1 3982 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 3983 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 3984 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 3985 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 3986 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3987 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3988 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3989 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 3990
bogdanm 89:552587b429a1 3991 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
bogdanm 89:552587b429a1 3992 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 3993 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 3994 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 3995 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 3996 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 3997 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 3998 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 3999 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4000
bogdanm 89:552587b429a1 4001 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
bogdanm 89:552587b429a1 4002 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4003 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4004 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4005 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4006 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4007 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4008 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4009 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4010
bogdanm 89:552587b429a1 4011 /****************** Bit definition for FSMC_PATT2 register ******************/
bogdanm 89:552587b429a1 4012 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
bogdanm 89:552587b429a1 4013 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4014 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4015 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4016 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4017 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4018 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4019 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 4020 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 4021
bogdanm 89:552587b429a1 4022 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
bogdanm 89:552587b429a1 4023 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 4024 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 4025 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 4026 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 4027 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4028 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4029 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4030 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4031
bogdanm 89:552587b429a1 4032 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
bogdanm 89:552587b429a1 4033 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4034 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4035 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4036 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4037 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4038 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4039 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4040 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4041
bogdanm 89:552587b429a1 4042 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
bogdanm 89:552587b429a1 4043 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4044 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4045 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4046 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4047 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4048 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4049 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4050 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4051
bogdanm 89:552587b429a1 4052 /****************** Bit definition for FSMC_PATT3 register ******************/
bogdanm 89:552587b429a1 4053 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
bogdanm 89:552587b429a1 4054 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4055 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4056 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4057 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4058 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4059 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4060 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 4061 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 4062
bogdanm 89:552587b429a1 4063 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
bogdanm 89:552587b429a1 4064 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 4065 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 4066 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 4067 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 4068 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4069 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4070 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4071 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4072
bogdanm 89:552587b429a1 4073 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
bogdanm 89:552587b429a1 4074 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4075 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4076 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4077 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4078 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4079 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4080 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4081 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4082
bogdanm 89:552587b429a1 4083 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
bogdanm 89:552587b429a1 4084 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4085 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4086 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4087 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4088 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4089 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4090 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4091 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4092
bogdanm 89:552587b429a1 4093 /****************** Bit definition for FSMC_PATT4 register ******************/
bogdanm 89:552587b429a1 4094 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
bogdanm 89:552587b429a1 4095 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4096 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4097 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4098 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4099 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4100 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4101 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 4102 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 4103
bogdanm 89:552587b429a1 4104 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
bogdanm 89:552587b429a1 4105 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 4106 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 4107 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 4108 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 4109 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4110 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4111 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4112 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4113
bogdanm 89:552587b429a1 4114 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
bogdanm 89:552587b429a1 4115 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4116 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4117 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4118 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4119 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4120 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4121 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4122 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4123
bogdanm 89:552587b429a1 4124 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
bogdanm 89:552587b429a1 4125 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4126 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4127 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4128 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4129 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4130 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4131 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4132 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4133
bogdanm 89:552587b429a1 4134 /****************** Bit definition for FSMC_PIO4 register *******************/
bogdanm 89:552587b429a1 4135 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
bogdanm 89:552587b429a1 4136 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4137 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4138 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4139 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4140 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4141 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4142 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 4143 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 4144
bogdanm 89:552587b429a1 4145 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
bogdanm 89:552587b429a1 4146 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 4147 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 4148 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 89:552587b429a1 4149 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 89:552587b429a1 4150 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4151 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4152 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4153 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4154
bogdanm 89:552587b429a1 4155 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
bogdanm 89:552587b429a1 4156 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4157 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4158 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4159 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4160 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4161 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4162 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4163 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4164
bogdanm 89:552587b429a1 4165 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
bogdanm 89:552587b429a1 4166 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 4167 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 4168 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 4169 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 4170 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 4171 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 4172 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 4173 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 4174
bogdanm 89:552587b429a1 4175 /****************** Bit definition for FSMC_ECCR2 register ******************/
bogdanm 89:552587b429a1 4176 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 89:552587b429a1 4177
bogdanm 89:552587b429a1 4178 /****************** Bit definition for FSMC_ECCR3 register ******************/
bogdanm 89:552587b429a1 4179 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 89:552587b429a1 4180
bogdanm 89:552587b429a1 4181 /******************************************************************************/
bogdanm 89:552587b429a1 4182 /* */
bogdanm 89:552587b429a1 4183 /* General Purpose I/O */
bogdanm 89:552587b429a1 4184 /* */
bogdanm 89:552587b429a1 4185 /******************************************************************************/
bogdanm 89:552587b429a1 4186 /****************** Bits definition for GPIO_MODER register *****************/
bogdanm 89:552587b429a1 4187 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 4188 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4189 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4190
bogdanm 89:552587b429a1 4191 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 4192 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4193 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4194
bogdanm 89:552587b429a1 4195 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 4196 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4197 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4198
bogdanm 89:552587b429a1 4199 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 4200 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4201 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4202
bogdanm 89:552587b429a1 4203 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 4204 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4205 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4206
bogdanm 89:552587b429a1 4207 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 89:552587b429a1 4208 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4209 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4210
bogdanm 89:552587b429a1 4211 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 89:552587b429a1 4212 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4213 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4214
bogdanm 89:552587b429a1 4215 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 89:552587b429a1 4216 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4217 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4218
bogdanm 89:552587b429a1 4219 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 4220 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4221 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4222
bogdanm 89:552587b429a1 4223 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 89:552587b429a1 4224 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4225 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4226
bogdanm 89:552587b429a1 4227 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 4228 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4229 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4230
bogdanm 89:552587b429a1 4231 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 89:552587b429a1 4232 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4233 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4234
bogdanm 89:552587b429a1 4235 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 89:552587b429a1 4236 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4237 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4238
bogdanm 89:552587b429a1 4239 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 89:552587b429a1 4240 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4241 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4242
bogdanm 89:552587b429a1 4243 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 4244 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4245 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4246
bogdanm 89:552587b429a1 4247 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 89:552587b429a1 4248 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4249 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 4250
bogdanm 89:552587b429a1 4251 /****************** Bits definition for GPIO_OTYPER register ****************/
bogdanm 89:552587b429a1 4252 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4253 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4254 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4255 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4256 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4257 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4258 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4259 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4260 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4261 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4262 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4263 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4264 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4265 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4266 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4267 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4268
bogdanm 89:552587b429a1 4269 /****************** Bits definition for GPIO_OSPEEDR register ***************/
bogdanm 89:552587b429a1 4270 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 4271 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4272 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4273
bogdanm 89:552587b429a1 4274 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 4275 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4276 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4277
bogdanm 89:552587b429a1 4278 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 4279 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4280 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4281
bogdanm 89:552587b429a1 4282 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 4283 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4284 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4285
bogdanm 89:552587b429a1 4286 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 4287 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4288 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4289
bogdanm 89:552587b429a1 4290 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 89:552587b429a1 4291 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4292 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4293
bogdanm 89:552587b429a1 4294 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 89:552587b429a1 4295 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4296 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4297
bogdanm 89:552587b429a1 4298 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 89:552587b429a1 4299 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4300 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4301
bogdanm 89:552587b429a1 4302 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 4303 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4304 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4305
bogdanm 89:552587b429a1 4306 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 89:552587b429a1 4307 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4308 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4309
bogdanm 89:552587b429a1 4310 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 4311 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4312 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4313
bogdanm 89:552587b429a1 4314 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 89:552587b429a1 4315 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4316 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4317
bogdanm 89:552587b429a1 4318 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 89:552587b429a1 4319 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4320 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4321
bogdanm 89:552587b429a1 4322 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 89:552587b429a1 4323 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4324 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4325
bogdanm 89:552587b429a1 4326 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 4327 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4328 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4329
bogdanm 89:552587b429a1 4330 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 89:552587b429a1 4331 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4332 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 4333
bogdanm 89:552587b429a1 4334 /****************** Bits definition for GPIO_PUPDR register *****************/
bogdanm 89:552587b429a1 4335 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 4336 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4337 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4338
bogdanm 89:552587b429a1 4339 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 4340 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4341 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4342
bogdanm 89:552587b429a1 4343 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 4344 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4345 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4346
bogdanm 89:552587b429a1 4347 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 4348 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4349 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4350
bogdanm 89:552587b429a1 4351 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 4352 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4353 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4354
bogdanm 89:552587b429a1 4355 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 89:552587b429a1 4356 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4357 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4358
bogdanm 89:552587b429a1 4359 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 89:552587b429a1 4360 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4361 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4362
bogdanm 89:552587b429a1 4363 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 89:552587b429a1 4364 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4365 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4366
bogdanm 89:552587b429a1 4367 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 4368 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4369 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4370
bogdanm 89:552587b429a1 4371 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 89:552587b429a1 4372 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4373 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4374
bogdanm 89:552587b429a1 4375 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 4376 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4377 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4378
bogdanm 89:552587b429a1 4379 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 89:552587b429a1 4380 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4381 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4382
bogdanm 89:552587b429a1 4383 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 89:552587b429a1 4384 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4385 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4386
bogdanm 89:552587b429a1 4387 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 89:552587b429a1 4388 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4389 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4390
bogdanm 89:552587b429a1 4391 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 4392 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4393 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4394
bogdanm 89:552587b429a1 4395 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 89:552587b429a1 4396 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4397 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 4398
bogdanm 89:552587b429a1 4399 /****************** Bits definition for GPIO_IDR register *******************/
bogdanm 89:552587b429a1 4400 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4401 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4402 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4403 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4404 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4405 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4406 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4407 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4408 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4409 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4410 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4411 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4412 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4413 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4414 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4415 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4416 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm 89:552587b429a1 4417 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm 89:552587b429a1 4418 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm 89:552587b429a1 4419 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm 89:552587b429a1 4420 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm 89:552587b429a1 4421 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm 89:552587b429a1 4422 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm 89:552587b429a1 4423 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm 89:552587b429a1 4424 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm 89:552587b429a1 4425 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm 89:552587b429a1 4426 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm 89:552587b429a1 4427 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm 89:552587b429a1 4428 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm 89:552587b429a1 4429 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm 89:552587b429a1 4430 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm 89:552587b429a1 4431 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm 89:552587b429a1 4432 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm 89:552587b429a1 4433
bogdanm 89:552587b429a1 4434 /****************** Bits definition for GPIO_ODR register *******************/
bogdanm 89:552587b429a1 4435 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4436 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4437 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4438 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4439 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4440 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4441 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4442 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4443 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4444 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4445 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4446 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4447 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4448 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4449 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4450 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4451 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm 89:552587b429a1 4452 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm 89:552587b429a1 4453 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm 89:552587b429a1 4454 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm 89:552587b429a1 4455 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm 89:552587b429a1 4456 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm 89:552587b429a1 4457 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm 89:552587b429a1 4458 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm 89:552587b429a1 4459 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm 89:552587b429a1 4460 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm 89:552587b429a1 4461 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm 89:552587b429a1 4462 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm 89:552587b429a1 4463 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm 89:552587b429a1 4464 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm 89:552587b429a1 4465 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm 89:552587b429a1 4466 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm 89:552587b429a1 4467 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm 89:552587b429a1 4468
bogdanm 89:552587b429a1 4469 /****************** Bits definition for GPIO_BSRR register ******************/
bogdanm 89:552587b429a1 4470 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4471 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4472 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4473 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4474 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4475 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4476 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4477 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4478 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4479 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4480 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4481 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4482 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4483 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4484 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4485 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4486 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4487 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4488 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4489 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4490 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4491 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4492 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4493 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4494 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4495 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4496 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4497 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4498 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4499 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4500 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4501 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 4502
bogdanm 89:552587b429a1 4503 /****************** Bit definition for GPIO_LCKR register *********************/
bogdanm 89:552587b429a1 4504 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4505 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4506 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4507 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4508 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4509 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4510 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4511 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4512 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4513 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4514 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4515 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4516 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4517 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4518 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4519 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4520 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4521
bogdanm 89:552587b429a1 4522 /******************************************************************************/
bogdanm 89:552587b429a1 4523 /* */
bogdanm 89:552587b429a1 4524 /* Inter-integrated Circuit Interface */
bogdanm 89:552587b429a1 4525 /* */
bogdanm 89:552587b429a1 4526 /******************************************************************************/
bogdanm 89:552587b429a1 4527 /******************* Bit definition for I2C_CR1 register ********************/
bogdanm 89:552587b429a1 4528 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
bogdanm 89:552587b429a1 4529 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
bogdanm 89:552587b429a1 4530 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
bogdanm 89:552587b429a1 4531 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
bogdanm 89:552587b429a1 4532 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
bogdanm 89:552587b429a1 4533 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
bogdanm 89:552587b429a1 4534 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
bogdanm 89:552587b429a1 4535 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
bogdanm 89:552587b429a1 4536 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
bogdanm 89:552587b429a1 4537 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
bogdanm 89:552587b429a1 4538 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
bogdanm 89:552587b429a1 4539 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
bogdanm 89:552587b429a1 4540 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
bogdanm 89:552587b429a1 4541 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
bogdanm 89:552587b429a1 4542
bogdanm 89:552587b429a1 4543 /******************* Bit definition for I2C_CR2 register ********************/
bogdanm 89:552587b429a1 4544 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
bogdanm 89:552587b429a1 4545 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4546 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4547 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4548 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4549 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4550 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4551
bogdanm 89:552587b429a1 4552 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
bogdanm 89:552587b429a1 4553 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
bogdanm 89:552587b429a1 4554 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
bogdanm 89:552587b429a1 4555 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
bogdanm 89:552587b429a1 4556 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
bogdanm 89:552587b429a1 4557
bogdanm 89:552587b429a1 4558 /******************* Bit definition for I2C_OAR1 register *******************/
bogdanm 89:552587b429a1 4559 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
bogdanm 89:552587b429a1 4560 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
bogdanm 89:552587b429a1 4561
bogdanm 89:552587b429a1 4562 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 4563 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 4564 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 4565 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 4566 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 4567 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 4568 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 4569 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 89:552587b429a1 4570 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
bogdanm 89:552587b429a1 4571 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
bogdanm 89:552587b429a1 4572
bogdanm 89:552587b429a1 4573 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
bogdanm 89:552587b429a1 4574
bogdanm 89:552587b429a1 4575 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 89:552587b429a1 4576 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
bogdanm 89:552587b429a1 4577 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
bogdanm 89:552587b429a1 4578
bogdanm 89:552587b429a1 4579 /******************** Bit definition for I2C_DR register ********************/
bogdanm 89:552587b429a1 4580 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
bogdanm 89:552587b429a1 4581
bogdanm 89:552587b429a1 4582 /******************* Bit definition for I2C_SR1 register ********************/
bogdanm 89:552587b429a1 4583 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
bogdanm 89:552587b429a1 4584 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
bogdanm 89:552587b429a1 4585 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
bogdanm 89:552587b429a1 4586 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
bogdanm 89:552587b429a1 4587 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
bogdanm 89:552587b429a1 4588 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
bogdanm 89:552587b429a1 4589 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
bogdanm 89:552587b429a1 4590 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
bogdanm 89:552587b429a1 4591 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
bogdanm 89:552587b429a1 4592 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
bogdanm 89:552587b429a1 4593 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
bogdanm 89:552587b429a1 4594 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
bogdanm 89:552587b429a1 4595 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
bogdanm 89:552587b429a1 4596 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
bogdanm 89:552587b429a1 4597
bogdanm 89:552587b429a1 4598 /******************* Bit definition for I2C_SR2 register ********************/
bogdanm 89:552587b429a1 4599 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
bogdanm 89:552587b429a1 4600 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
bogdanm 89:552587b429a1 4601 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
bogdanm 89:552587b429a1 4602 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
bogdanm 89:552587b429a1 4603 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
bogdanm 89:552587b429a1 4604 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
bogdanm 89:552587b429a1 4605 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
bogdanm 89:552587b429a1 4606 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
bogdanm 89:552587b429a1 4607
bogdanm 89:552587b429a1 4608 /******************* Bit definition for I2C_CCR register ********************/
bogdanm 89:552587b429a1 4609 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
bogdanm 89:552587b429a1 4610 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
bogdanm 89:552587b429a1 4611 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
bogdanm 89:552587b429a1 4612
bogdanm 89:552587b429a1 4613 /****************** Bit definition for I2C_TRISE register *******************/
bogdanm 89:552587b429a1 4614 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 89:552587b429a1 4615
bogdanm 89:552587b429a1 4616 /****************** Bit definition for I2C_FLTR register *******************/
bogdanm 89:552587b429a1 4617 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
bogdanm 89:552587b429a1 4618 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
bogdanm 89:552587b429a1 4619
bogdanm 89:552587b429a1 4620 /******************************************************************************/
bogdanm 89:552587b429a1 4621 /* */
bogdanm 89:552587b429a1 4622 /* Independent WATCHDOG */
bogdanm 89:552587b429a1 4623 /* */
bogdanm 89:552587b429a1 4624 /******************************************************************************/
bogdanm 89:552587b429a1 4625 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 89:552587b429a1 4626 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
bogdanm 89:552587b429a1 4627
bogdanm 89:552587b429a1 4628 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 89:552587b429a1 4629 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
bogdanm 89:552587b429a1 4630 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 89:552587b429a1 4631 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 89:552587b429a1 4632 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 89:552587b429a1 4633
bogdanm 89:552587b429a1 4634 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 89:552587b429a1 4635 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
bogdanm 89:552587b429a1 4636
bogdanm 89:552587b429a1 4637 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 89:552587b429a1 4638 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
bogdanm 89:552587b429a1 4639 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
bogdanm 89:552587b429a1 4640
bogdanm 89:552587b429a1 4641
bogdanm 89:552587b429a1 4642 /******************************************************************************/
bogdanm 89:552587b429a1 4643 /* */
bogdanm 89:552587b429a1 4644 /* Power Control */
bogdanm 89:552587b429a1 4645 /* */
bogdanm 89:552587b429a1 4646 /******************************************************************************/
bogdanm 89:552587b429a1 4647 /******************** Bit definition for PWR_CR register ********************/
bogdanm 89:552587b429a1 4648 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
bogdanm 89:552587b429a1 4649 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 89:552587b429a1 4650 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 89:552587b429a1 4651 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 89:552587b429a1 4652 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 89:552587b429a1 4653
bogdanm 89:552587b429a1 4654 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 89:552587b429a1 4655 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 89:552587b429a1 4656 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 89:552587b429a1 4657 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 89:552587b429a1 4658
bogdanm 89:552587b429a1 4659 /*!< PVD level configuration */
bogdanm 89:552587b429a1 4660 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 89:552587b429a1 4661 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 89:552587b429a1 4662 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 89:552587b429a1 4663 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 89:552587b429a1 4664 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 89:552587b429a1 4665 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 89:552587b429a1 4666 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 89:552587b429a1 4667 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 89:552587b429a1 4668
bogdanm 89:552587b429a1 4669 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 89:552587b429a1 4670 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
bogdanm 89:552587b429a1 4671 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
bogdanm 89:552587b429a1 4672 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 89:552587b429a1 4673 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 89:552587b429a1 4674
bogdanm 89:552587b429a1 4675 /* Legacy define */
bogdanm 89:552587b429a1 4676 #define PWR_CR_PMODE PWR_CR_VOS
bogdanm 89:552587b429a1 4677
bogdanm 89:552587b429a1 4678 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 89:552587b429a1 4679 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 89:552587b429a1 4680 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 89:552587b429a1 4681 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 89:552587b429a1 4682 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
bogdanm 89:552587b429a1 4683 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
bogdanm 89:552587b429a1 4684 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
bogdanm 89:552587b429a1 4685 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
bogdanm 89:552587b429a1 4686
bogdanm 89:552587b429a1 4687 /* Legacy define */
bogdanm 89:552587b429a1 4688 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm 89:552587b429a1 4689
bogdanm 89:552587b429a1 4690 /******************************************************************************/
bogdanm 89:552587b429a1 4691 /* */
bogdanm 89:552587b429a1 4692 /* Reset and Clock Control */
bogdanm 89:552587b429a1 4693 /* */
bogdanm 89:552587b429a1 4694 /******************************************************************************/
bogdanm 89:552587b429a1 4695 /******************** Bit definition for RCC_CR register ********************/
bogdanm 89:552587b429a1 4696 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4697 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4698
bogdanm 89:552587b429a1 4699 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 89:552587b429a1 4700 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 89:552587b429a1 4701 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 89:552587b429a1 4702 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 89:552587b429a1 4703 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 89:552587b429a1 4704 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 89:552587b429a1 4705
bogdanm 89:552587b429a1 4706 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 89:552587b429a1 4707 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 89:552587b429a1 4708 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 89:552587b429a1 4709 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 89:552587b429a1 4710 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 89:552587b429a1 4711 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 89:552587b429a1 4712 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 89:552587b429a1 4713 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 89:552587b429a1 4714 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 89:552587b429a1 4715
bogdanm 89:552587b429a1 4716 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4717 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4718 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4719 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4720 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4721 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4722 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4723 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4724
bogdanm 89:552587b429a1 4725 /******************** Bit definition for RCC_PLLCFGR register ***************/
bogdanm 89:552587b429a1 4726 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
bogdanm 89:552587b429a1 4727 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4728 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4729 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4730 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4731 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4732 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4733
bogdanm 89:552587b429a1 4734 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
bogdanm 89:552587b429a1 4735 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4736 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4737 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4738 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4739 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4740 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4741 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4742 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4743 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4744
bogdanm 89:552587b429a1 4745 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 4746 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4747 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4748
bogdanm 89:552587b429a1 4749 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4750 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4751 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 4752
bogdanm 89:552587b429a1 4753 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
bogdanm 89:552587b429a1 4754 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4755 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4756 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4757 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4758
bogdanm 89:552587b429a1 4759 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 89:552587b429a1 4760 /*!< SW configuration */
bogdanm 89:552587b429a1 4761 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 89:552587b429a1 4762 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 89:552587b429a1 4763 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 89:552587b429a1 4764
bogdanm 89:552587b429a1 4765 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 89:552587b429a1 4766 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 89:552587b429a1 4767 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 89:552587b429a1 4768
bogdanm 89:552587b429a1 4769 /*!< SWS configuration */
bogdanm 89:552587b429a1 4770 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 89:552587b429a1 4771 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 89:552587b429a1 4772 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 89:552587b429a1 4773
bogdanm 89:552587b429a1 4774 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 89:552587b429a1 4775 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 89:552587b429a1 4776 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 89:552587b429a1 4777
bogdanm 89:552587b429a1 4778 /*!< HPRE configuration */
bogdanm 89:552587b429a1 4779 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 89:552587b429a1 4780 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 89:552587b429a1 4781 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 89:552587b429a1 4782 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 89:552587b429a1 4783 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 89:552587b429a1 4784
bogdanm 89:552587b429a1 4785 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 89:552587b429a1 4786 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 89:552587b429a1 4787 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 89:552587b429a1 4788 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 89:552587b429a1 4789 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 89:552587b429a1 4790 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 89:552587b429a1 4791 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 89:552587b429a1 4792 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 89:552587b429a1 4793 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 89:552587b429a1 4794
bogdanm 89:552587b429a1 4795 /*!< PPRE1 configuration */
bogdanm 89:552587b429a1 4796 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 89:552587b429a1 4797 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 89:552587b429a1 4798 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 89:552587b429a1 4799 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 89:552587b429a1 4800
bogdanm 89:552587b429a1 4801 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 89:552587b429a1 4802 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
bogdanm 89:552587b429a1 4803 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
bogdanm 89:552587b429a1 4804 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
bogdanm 89:552587b429a1 4805 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
bogdanm 89:552587b429a1 4806
bogdanm 89:552587b429a1 4807 /*!< PPRE2 configuration */
bogdanm 89:552587b429a1 4808 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 89:552587b429a1 4809 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 89:552587b429a1 4810 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 89:552587b429a1 4811 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 89:552587b429a1 4812
bogdanm 89:552587b429a1 4813 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 89:552587b429a1 4814 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
bogdanm 89:552587b429a1 4815 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
bogdanm 89:552587b429a1 4816 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
bogdanm 89:552587b429a1 4817 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
bogdanm 89:552587b429a1 4818
bogdanm 89:552587b429a1 4819 /*!< RTCPRE configuration */
bogdanm 89:552587b429a1 4820 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
bogdanm 89:552587b429a1 4821 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4822 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4823 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4824 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4825 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4826
bogdanm 89:552587b429a1 4827 /*!< MCO1 configuration */
bogdanm 89:552587b429a1 4828 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
bogdanm 89:552587b429a1 4829 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4830 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4831
bogdanm 89:552587b429a1 4832 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4833
bogdanm 89:552587b429a1 4834 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
bogdanm 89:552587b429a1 4835 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 4836 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4837 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4838
bogdanm 89:552587b429a1 4839 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
bogdanm 89:552587b429a1 4840 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4841 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4842 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4843
bogdanm 89:552587b429a1 4844 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
bogdanm 89:552587b429a1 4845 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4846 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 4847
bogdanm 89:552587b429a1 4848 /******************** Bit definition for RCC_CIR register *******************/
bogdanm 89:552587b429a1 4849 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4850 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4851 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4852 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4853 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4854 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4855
bogdanm 89:552587b429a1 4856 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4857 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4858 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 4859 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 4860 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4861 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4862 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 4863
bogdanm 89:552587b429a1 4864 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4865 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4866 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4867 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4868 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4869 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4870
bogdanm 89:552587b429a1 4871 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4872
bogdanm 89:552587b429a1 4873 /******************** Bit definition for RCC_AHB1RSTR register **************/
bogdanm 89:552587b429a1 4874 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4875 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4876 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4877 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4878 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4879 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4880 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4881 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4882 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4883 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4884 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4885 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4886 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4887 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4888
bogdanm 89:552587b429a1 4889 /******************** Bit definition for RCC_AHB2RSTR register **************/
bogdanm 89:552587b429a1 4890 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4891 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4892 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4893
bogdanm 89:552587b429a1 4894 /******************** Bit definition for RCC_AHB3RSTR register **************/
bogdanm 89:552587b429a1 4895
bogdanm 89:552587b429a1 4896 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4897
bogdanm 89:552587b429a1 4898 /******************** Bit definition for RCC_APB1RSTR register **************/
bogdanm 89:552587b429a1 4899 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4900 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4901 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4902 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4903 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4904 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4905 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4906 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4907 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4908 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4909 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4910 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4911 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4912 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4913 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4914 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4915 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4916 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4917 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4918 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4919 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4920 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4921 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4922
bogdanm 89:552587b429a1 4923 /******************** Bit definition for RCC_APB2RSTR register **************/
bogdanm 89:552587b429a1 4924 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4925 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4926 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4927 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4928 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4929 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4930 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4931 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4932 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 4933 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4934 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4935
bogdanm 89:552587b429a1 4936 /* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm 89:552587b429a1 4937 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm 89:552587b429a1 4938
bogdanm 89:552587b429a1 4939 /******************** Bit definition for RCC_AHB1ENR register ***************/
bogdanm 89:552587b429a1 4940 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4941 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4942 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4943 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4944 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4945 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4946 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4947 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4948 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4949 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 4950 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4951 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4952 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4953 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4954
bogdanm 89:552587b429a1 4955 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4956 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4957 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 4958 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4959 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4960 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 4961
bogdanm 89:552587b429a1 4962 /******************** Bit definition for RCC_AHB2ENR register ***************/
bogdanm 89:552587b429a1 4963 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4964 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4965 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4966
bogdanm 89:552587b429a1 4967 /******************** Bit definition for RCC_AHB3ENR register ***************/
bogdanm 89:552587b429a1 4968
bogdanm 89:552587b429a1 4969 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4970
bogdanm 89:552587b429a1 4971 /******************** Bit definition for RCC_APB1ENR register ***************/
bogdanm 89:552587b429a1 4972 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4973 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4974 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 4975 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 4976 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 4977 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 4978 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 4979 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 4980 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 4981 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 4982 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 4983 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 4984 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 4985 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 4986 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 4987 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 4988 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 4989 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 4990 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 4991 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 4992 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 4993 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 4994 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 4995
bogdanm 89:552587b429a1 4996 /******************** Bit definition for RCC_APB2ENR register ***************/
bogdanm 89:552587b429a1 4997 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 4998 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 4999 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5000 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5001 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5002 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5003 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5004 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5005 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5006 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5007 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5008 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5009 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5010 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5011 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5012
bogdanm 89:552587b429a1 5013 /******************** Bit definition for RCC_AHB1LPENR register *************/
bogdanm 89:552587b429a1 5014 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5015 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5016 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5017 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5018 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5019 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5020 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5021 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5022 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5023 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5024 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5025 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5026 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5027 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5028 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5029 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5030 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5031 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5032 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5033 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5034 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5035 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5036 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5037
bogdanm 89:552587b429a1 5038 /******************** Bit definition for RCC_AHB2LPENR register *************/
bogdanm 89:552587b429a1 5039 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5040 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5041 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5042
bogdanm 89:552587b429a1 5043 /******************** Bit definition for RCC_AHB3LPENR register *************/
bogdanm 89:552587b429a1 5044
bogdanm 89:552587b429a1 5045 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5046
bogdanm 89:552587b429a1 5047 /******************** Bit definition for RCC_APB1LPENR register *************/
bogdanm 89:552587b429a1 5048 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5049 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5050 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5051 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5052 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5053 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5054 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5055 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5056 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5057 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5058 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5059 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5060 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5061 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5062 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5063 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5064 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5065 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5066 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 5067 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5068 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5069 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5070 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5071
bogdanm 89:552587b429a1 5072 /******************** Bit definition for RCC_APB2LPENR register *************/
bogdanm 89:552587b429a1 5073 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5074 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5075 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5076 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5077 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5078 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5079 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5080 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5081 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5082 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5083 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5084 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5085 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5086
bogdanm 89:552587b429a1 5087 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 89:552587b429a1 5088 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5089 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5090 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5091
bogdanm 89:552587b429a1 5092 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 5093 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5094 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5095
bogdanm 89:552587b429a1 5096 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5097 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5098
bogdanm 89:552587b429a1 5099 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 89:552587b429a1 5100 #define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5101 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5102 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 5103 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5104 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5105 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5106 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5107 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5108 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5109 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 5110
bogdanm 89:552587b429a1 5111 /******************** Bit definition for RCC_SSCGR register *****************/
bogdanm 89:552587b429a1 5112 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
bogdanm 89:552587b429a1 5113 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
bogdanm 89:552587b429a1 5114 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5115 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 5116
bogdanm 89:552587b429a1 5117 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
bogdanm 89:552587b429a1 5118 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
bogdanm 89:552587b429a1 5119 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5120 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5121 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5122 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5123 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5124 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5125 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5126 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5127 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5128
bogdanm 89:552587b429a1 5129 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
bogdanm 89:552587b429a1 5130 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5131 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5132 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5133
bogdanm 89:552587b429a1 5134 /******************************************************************************/
bogdanm 89:552587b429a1 5135 /* */
bogdanm 89:552587b429a1 5136 /* RNG */
bogdanm 89:552587b429a1 5137 /* */
bogdanm 89:552587b429a1 5138 /******************************************************************************/
bogdanm 89:552587b429a1 5139 /******************** Bits definition for RNG_CR register *******************/
bogdanm 89:552587b429a1 5140 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5141 #define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5142
bogdanm 89:552587b429a1 5143 /******************** Bits definition for RNG_SR register *******************/
bogdanm 89:552587b429a1 5144 #define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5145 #define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5146 #define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5147 #define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5148 #define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5149
bogdanm 89:552587b429a1 5150 /******************************************************************************/
bogdanm 89:552587b429a1 5151 /* */
bogdanm 89:552587b429a1 5152 /* Real-Time Clock (RTC) */
bogdanm 89:552587b429a1 5153 /* */
bogdanm 89:552587b429a1 5154 /******************************************************************************/
bogdanm 89:552587b429a1 5155 /******************** Bits definition for RTC_TR register *******************/
bogdanm 89:552587b429a1 5156 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5157 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 5158 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5159 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5160 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 89:552587b429a1 5161 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5162 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5163 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5164 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5165 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 89:552587b429a1 5166 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5167 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5168 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5169 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5170 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5171 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5172 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5173 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5174 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 89:552587b429a1 5175 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5176 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5177 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5178 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5179 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5180 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5181 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5182 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5183
bogdanm 89:552587b429a1 5184 /******************** Bits definition for RTC_DR register *******************/
bogdanm 89:552587b429a1 5185 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 89:552587b429a1 5186 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5187 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5188 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5189 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 5190 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 89:552587b429a1 5191 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5192 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5193 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5194 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5195 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 89:552587b429a1 5196 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5197 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5198 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5199 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5200 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5201 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5202 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5203 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5204 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5205 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 5206 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5207 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5208 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5209 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5210 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5211 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5212 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5213
bogdanm 89:552587b429a1 5214 /******************** Bits definition for RTC_CR register *******************/
bogdanm 89:552587b429a1 5215 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 5216 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 89:552587b429a1 5217 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5218 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5219 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5220 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5221 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5222 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5223 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5224 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5225 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5226 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5227 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5228 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5229 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5230 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5231 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5232 #define RTC_CR_DCE ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5233 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5234 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5235 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5236 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5237 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 89:552587b429a1 5238 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5239 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5240 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5241
bogdanm 89:552587b429a1 5242 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 89:552587b429a1 5243 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5244 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5245 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5246 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5247 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5248 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5249 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5250 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5251 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5252 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5253 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5254 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5255 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5256 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5257 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5258 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5259
bogdanm 89:552587b429a1 5260 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 89:552587b429a1 5261 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 89:552587b429a1 5262 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
bogdanm 89:552587b429a1 5263
bogdanm 89:552587b429a1 5264 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 89:552587b429a1 5265 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 89:552587b429a1 5266
bogdanm 89:552587b429a1 5267 /******************** Bits definition for RTC_CALIBR register ***************/
bogdanm 89:552587b429a1 5268 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5269 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
bogdanm 89:552587b429a1 5270
bogdanm 89:552587b429a1 5271 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 89:552587b429a1 5272 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 5273 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5274 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 5275 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5276 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5277 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 89:552587b429a1 5278 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 5279 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5280 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5281 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5282 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 5283 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5284 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 5285 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5286 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5287 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 89:552587b429a1 5288 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5289 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5290 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5291 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5292 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5293 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 89:552587b429a1 5294 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5295 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5296 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5297 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5298 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5299 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5300 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5301 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5302 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5303 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 89:552587b429a1 5304 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5305 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5306 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5307 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5308 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5309 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5310 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5311 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5312
bogdanm 89:552587b429a1 5313 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 89:552587b429a1 5314 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 5315 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 89:552587b429a1 5316 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 5317 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 5318 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 5319 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 89:552587b429a1 5320 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 5321 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5322 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5323 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5324 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 5325 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5326 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 5327 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5328 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5329 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 89:552587b429a1 5330 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5331 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5332 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5333 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5334 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5335 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 89:552587b429a1 5336 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5337 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5338 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5339 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5340 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5341 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5342 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5343 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5344 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5345 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 89:552587b429a1 5346 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5347 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5348 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5349 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5350 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5351 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5352 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5353 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5354
bogdanm 89:552587b429a1 5355 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 89:552587b429a1 5356 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 89:552587b429a1 5357
bogdanm 89:552587b429a1 5358 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 89:552587b429a1 5359 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 89:552587b429a1 5360
bogdanm 89:552587b429a1 5361 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 89:552587b429a1 5362 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 89:552587b429a1 5363 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 89:552587b429a1 5364
bogdanm 89:552587b429a1 5365 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 89:552587b429a1 5366 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 5367 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 89:552587b429a1 5368 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 5369 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 5370 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 89:552587b429a1 5371 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5372 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5373 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5374 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 5375 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 89:552587b429a1 5376 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5377 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5378 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5379 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5380 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5381 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5382 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5383 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5384 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 89:552587b429a1 5385 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5386 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5387 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5388 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5389 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5390 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5391 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5392 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5393
bogdanm 89:552587b429a1 5394 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 89:552587b429a1 5395 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 89:552587b429a1 5396 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5397 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5398 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5399 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5400 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 89:552587b429a1 5401 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5402 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5403 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5404 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5405 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 5406 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5407 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5408 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 89:552587b429a1 5409 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5410 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5411 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5412 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5413
bogdanm 89:552587b429a1 5414 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 89:552587b429a1 5415 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 89:552587b429a1 5416
bogdanm 89:552587b429a1 5417 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 89:552587b429a1 5418 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5419 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5420 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5421 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 89:552587b429a1 5422 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5423 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5424 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5425 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5426 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5427 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 5428 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 5429 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5430 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5431
bogdanm 89:552587b429a1 5432 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 89:552587b429a1 5433 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 5434 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 5435 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 5436 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 5437 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 89:552587b429a1 5438 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 5439 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 5440 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 89:552587b429a1 5441 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 5442 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 5443 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 89:552587b429a1 5444 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 5445 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 5446 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 5447 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 5448 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 5449 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 5450 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5451 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5452 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5453
bogdanm 89:552587b429a1 5454 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 89:552587b429a1 5455 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 89:552587b429a1 5456 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 5457 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5458 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5459 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5460 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 89:552587b429a1 5461
bogdanm 89:552587b429a1 5462 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 89:552587b429a1 5463 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 89:552587b429a1 5464 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 89:552587b429a1 5465 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 5466 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 5467 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 89:552587b429a1 5468 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 89:552587b429a1 5469
bogdanm 89:552587b429a1 5470 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 89:552587b429a1 5471 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5472
bogdanm 89:552587b429a1 5473 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 89:552587b429a1 5474 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5475
bogdanm 89:552587b429a1 5476 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 89:552587b429a1 5477 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5478
bogdanm 89:552587b429a1 5479 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 89:552587b429a1 5480 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5481
bogdanm 89:552587b429a1 5482 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 89:552587b429a1 5483 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5484
bogdanm 89:552587b429a1 5485 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 89:552587b429a1 5486 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5487
bogdanm 89:552587b429a1 5488 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 89:552587b429a1 5489 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5490
bogdanm 89:552587b429a1 5491 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 89:552587b429a1 5492 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5493
bogdanm 89:552587b429a1 5494 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 89:552587b429a1 5495 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5496
bogdanm 89:552587b429a1 5497 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 89:552587b429a1 5498 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5499
bogdanm 89:552587b429a1 5500 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 89:552587b429a1 5501 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5502
bogdanm 89:552587b429a1 5503 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 89:552587b429a1 5504 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5505
bogdanm 89:552587b429a1 5506 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 89:552587b429a1 5507 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5508
bogdanm 89:552587b429a1 5509 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 89:552587b429a1 5510 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5511
bogdanm 89:552587b429a1 5512 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 89:552587b429a1 5513 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5514
bogdanm 89:552587b429a1 5515 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 89:552587b429a1 5516 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5517
bogdanm 89:552587b429a1 5518 /******************** Bits definition for RTC_BKP16R register ***************/
bogdanm 89:552587b429a1 5519 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5520
bogdanm 89:552587b429a1 5521 /******************** Bits definition for RTC_BKP17R register ***************/
bogdanm 89:552587b429a1 5522 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5523
bogdanm 89:552587b429a1 5524 /******************** Bits definition for RTC_BKP18R register ***************/
bogdanm 89:552587b429a1 5525 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5526
bogdanm 89:552587b429a1 5527 /******************** Bits definition for RTC_BKP19R register ***************/
bogdanm 89:552587b429a1 5528 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm 89:552587b429a1 5529
bogdanm 89:552587b429a1 5530
bogdanm 89:552587b429a1 5531
bogdanm 89:552587b429a1 5532 /******************************************************************************/
bogdanm 89:552587b429a1 5533 /* */
bogdanm 89:552587b429a1 5534 /* SD host Interface */
bogdanm 89:552587b429a1 5535 /* */
bogdanm 89:552587b429a1 5536 /******************************************************************************/
bogdanm 89:552587b429a1 5537 /****************** Bit definition for SDIO_POWER register ******************/
bogdanm 89:552587b429a1 5538 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
bogdanm 89:552587b429a1 5539 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 89:552587b429a1 5540 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 89:552587b429a1 5541
bogdanm 89:552587b429a1 5542 /****************** Bit definition for SDIO_CLKCR register ******************/
bogdanm 89:552587b429a1 5543 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
bogdanm 89:552587b429a1 5544 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
bogdanm 89:552587b429a1 5545 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
bogdanm 89:552587b429a1 5546 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
bogdanm 89:552587b429a1 5547
bogdanm 89:552587b429a1 5548 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
bogdanm 89:552587b429a1 5549 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
bogdanm 89:552587b429a1 5550 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
bogdanm 89:552587b429a1 5551
bogdanm 89:552587b429a1 5552 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
bogdanm 89:552587b429a1 5553 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
bogdanm 89:552587b429a1 5554
bogdanm 89:552587b429a1 5555 /******************* Bit definition for SDIO_ARG register *******************/
bogdanm 89:552587b429a1 5556 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
bogdanm 89:552587b429a1 5557
bogdanm 89:552587b429a1 5558 /******************* Bit definition for SDIO_CMD register *******************/
bogdanm 89:552587b429a1 5559 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
bogdanm 89:552587b429a1 5560
bogdanm 89:552587b429a1 5561 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
bogdanm 89:552587b429a1 5562 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
bogdanm 89:552587b429a1 5563 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
bogdanm 89:552587b429a1 5564
bogdanm 89:552587b429a1 5565 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
bogdanm 89:552587b429a1 5566 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
bogdanm 89:552587b429a1 5567 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
bogdanm 89:552587b429a1 5568 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
bogdanm 89:552587b429a1 5569 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
bogdanm 89:552587b429a1 5570 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
bogdanm 89:552587b429a1 5571 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
bogdanm 89:552587b429a1 5572
bogdanm 89:552587b429a1 5573 /***************** Bit definition for SDIO_RESPCMD register *****************/
bogdanm 89:552587b429a1 5574 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
bogdanm 89:552587b429a1 5575
bogdanm 89:552587b429a1 5576 /****************** Bit definition for SDIO_RESP0 register ******************/
bogdanm 89:552587b429a1 5577 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 89:552587b429a1 5578
bogdanm 89:552587b429a1 5579 /****************** Bit definition for SDIO_RESP1 register ******************/
bogdanm 89:552587b429a1 5580 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 89:552587b429a1 5581
bogdanm 89:552587b429a1 5582 /****************** Bit definition for SDIO_RESP2 register ******************/
bogdanm 89:552587b429a1 5583 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 89:552587b429a1 5584
bogdanm 89:552587b429a1 5585 /****************** Bit definition for SDIO_RESP3 register ******************/
bogdanm 89:552587b429a1 5586 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 89:552587b429a1 5587
bogdanm 89:552587b429a1 5588 /****************** Bit definition for SDIO_RESP4 register ******************/
bogdanm 89:552587b429a1 5589 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 89:552587b429a1 5590
bogdanm 89:552587b429a1 5591 /****************** Bit definition for SDIO_DTIMER register *****************/
bogdanm 89:552587b429a1 5592 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
bogdanm 89:552587b429a1 5593
bogdanm 89:552587b429a1 5594 /****************** Bit definition for SDIO_DLEN register *******************/
bogdanm 89:552587b429a1 5595 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
bogdanm 89:552587b429a1 5596
bogdanm 89:552587b429a1 5597 /****************** Bit definition for SDIO_DCTRL register ******************/
bogdanm 89:552587b429a1 5598 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
bogdanm 89:552587b429a1 5599 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
bogdanm 89:552587b429a1 5600 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
bogdanm 89:552587b429a1 5601 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
bogdanm 89:552587b429a1 5602
bogdanm 89:552587b429a1 5603 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
bogdanm 89:552587b429a1 5604 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 5605 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 5606 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 5607 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 89:552587b429a1 5608
bogdanm 89:552587b429a1 5609 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
bogdanm 89:552587b429a1 5610 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
bogdanm 89:552587b429a1 5611 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
bogdanm 89:552587b429a1 5612 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
bogdanm 89:552587b429a1 5613
bogdanm 89:552587b429a1 5614 /****************** Bit definition for SDIO_DCOUNT register *****************/
bogdanm 89:552587b429a1 5615 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
bogdanm 89:552587b429a1 5616
bogdanm 89:552587b429a1 5617 /****************** Bit definition for SDIO_STA register ********************/
bogdanm 89:552587b429a1 5618 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
bogdanm 89:552587b429a1 5619 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
bogdanm 89:552587b429a1 5620 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
bogdanm 89:552587b429a1 5621 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
bogdanm 89:552587b429a1 5622 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
bogdanm 89:552587b429a1 5623 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
bogdanm 89:552587b429a1 5624 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
bogdanm 89:552587b429a1 5625 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
bogdanm 89:552587b429a1 5626 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
bogdanm 89:552587b429a1 5627 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
bogdanm 89:552587b429a1 5628 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
bogdanm 89:552587b429a1 5629 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
bogdanm 89:552587b429a1 5630 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
bogdanm 89:552587b429a1 5631 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
bogdanm 89:552587b429a1 5632 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
bogdanm 89:552587b429a1 5633 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
bogdanm 89:552587b429a1 5634 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
bogdanm 89:552587b429a1 5635 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
bogdanm 89:552587b429a1 5636 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
bogdanm 89:552587b429a1 5637 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
bogdanm 89:552587b429a1 5638 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
bogdanm 89:552587b429a1 5639 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
bogdanm 89:552587b429a1 5640 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
bogdanm 89:552587b429a1 5641 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
bogdanm 89:552587b429a1 5642
bogdanm 89:552587b429a1 5643 /******************* Bit definition for SDIO_ICR register *******************/
bogdanm 89:552587b429a1 5644 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
bogdanm 89:552587b429a1 5645 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
bogdanm 89:552587b429a1 5646 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
bogdanm 89:552587b429a1 5647 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
bogdanm 89:552587b429a1 5648 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
bogdanm 89:552587b429a1 5649 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
bogdanm 89:552587b429a1 5650 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
bogdanm 89:552587b429a1 5651 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
bogdanm 89:552587b429a1 5652 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
bogdanm 89:552587b429a1 5653 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
bogdanm 89:552587b429a1 5654 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
bogdanm 89:552587b429a1 5655 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
bogdanm 89:552587b429a1 5656 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
bogdanm 89:552587b429a1 5657
bogdanm 89:552587b429a1 5658 /****************** Bit definition for SDIO_MASK register *******************/
bogdanm 89:552587b429a1 5659 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
bogdanm 89:552587b429a1 5660 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
bogdanm 89:552587b429a1 5661 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
bogdanm 89:552587b429a1 5662 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
bogdanm 89:552587b429a1 5663 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
bogdanm 89:552587b429a1 5664 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
bogdanm 89:552587b429a1 5665 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
bogdanm 89:552587b429a1 5666 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
bogdanm 89:552587b429a1 5667 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
bogdanm 89:552587b429a1 5668 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
bogdanm 89:552587b429a1 5669 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
bogdanm 89:552587b429a1 5670 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
bogdanm 89:552587b429a1 5671 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
bogdanm 89:552587b429a1 5672 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
bogdanm 89:552587b429a1 5673 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
bogdanm 89:552587b429a1 5674 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
bogdanm 89:552587b429a1 5675 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
bogdanm 89:552587b429a1 5676 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
bogdanm 89:552587b429a1 5677 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
bogdanm 89:552587b429a1 5678 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
bogdanm 89:552587b429a1 5679 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
bogdanm 89:552587b429a1 5680 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
bogdanm 89:552587b429a1 5681 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
bogdanm 89:552587b429a1 5682 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
bogdanm 89:552587b429a1 5683
bogdanm 89:552587b429a1 5684 /***************** Bit definition for SDIO_FIFOCNT register *****************/
bogdanm 89:552587b429a1 5685 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
bogdanm 89:552587b429a1 5686
bogdanm 89:552587b429a1 5687 /****************** Bit definition for SDIO_FIFO register *******************/
bogdanm 89:552587b429a1 5688 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
bogdanm 89:552587b429a1 5689
bogdanm 89:552587b429a1 5690 /******************************************************************************/
bogdanm 89:552587b429a1 5691 /* */
bogdanm 89:552587b429a1 5692 /* Serial Peripheral Interface */
bogdanm 89:552587b429a1 5693 /* */
bogdanm 89:552587b429a1 5694 /******************************************************************************/
bogdanm 89:552587b429a1 5695 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 89:552587b429a1 5696 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
bogdanm 89:552587b429a1 5697 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
bogdanm 89:552587b429a1 5698 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
bogdanm 89:552587b429a1 5699
bogdanm 89:552587b429a1 5700 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
bogdanm 89:552587b429a1 5701 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 89:552587b429a1 5702 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 89:552587b429a1 5703 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 89:552587b429a1 5704
bogdanm 89:552587b429a1 5705 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
bogdanm 89:552587b429a1 5706 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
bogdanm 89:552587b429a1 5707 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
bogdanm 89:552587b429a1 5708 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
bogdanm 89:552587b429a1 5709 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
bogdanm 89:552587b429a1 5710 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
bogdanm 89:552587b429a1 5711 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
bogdanm 89:552587b429a1 5712 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
bogdanm 89:552587b429a1 5713 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
bogdanm 89:552587b429a1 5714 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
bogdanm 89:552587b429a1 5715
bogdanm 89:552587b429a1 5716 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 89:552587b429a1 5717 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
bogdanm 89:552587b429a1 5718 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
bogdanm 89:552587b429a1 5719 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
bogdanm 89:552587b429a1 5720 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
bogdanm 89:552587b429a1 5721 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
bogdanm 89:552587b429a1 5722 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
bogdanm 89:552587b429a1 5723 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
bogdanm 89:552587b429a1 5724
bogdanm 89:552587b429a1 5725 /******************** Bit definition for SPI_SR register ********************/
bogdanm 89:552587b429a1 5726 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
bogdanm 89:552587b429a1 5727 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
bogdanm 89:552587b429a1 5728 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
bogdanm 89:552587b429a1 5729 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
bogdanm 89:552587b429a1 5730 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
bogdanm 89:552587b429a1 5731 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
bogdanm 89:552587b429a1 5732 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
bogdanm 89:552587b429a1 5733 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
bogdanm 89:552587b429a1 5734 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
bogdanm 89:552587b429a1 5735
bogdanm 89:552587b429a1 5736 /******************** Bit definition for SPI_DR register ********************/
bogdanm 89:552587b429a1 5737 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
bogdanm 89:552587b429a1 5738
bogdanm 89:552587b429a1 5739 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 89:552587b429a1 5740 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
bogdanm 89:552587b429a1 5741
bogdanm 89:552587b429a1 5742 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 89:552587b429a1 5743 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
bogdanm 89:552587b429a1 5744
bogdanm 89:552587b429a1 5745 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 89:552587b429a1 5746 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
bogdanm 89:552587b429a1 5747
bogdanm 89:552587b429a1 5748 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 89:552587b429a1 5749 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
bogdanm 89:552587b429a1 5750
bogdanm 89:552587b429a1 5751 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 89:552587b429a1 5752 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 89:552587b429a1 5753 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 89:552587b429a1 5754
bogdanm 89:552587b429a1 5755 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
bogdanm 89:552587b429a1 5756
bogdanm 89:552587b429a1 5757 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 89:552587b429a1 5758 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 5759 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 5760
bogdanm 89:552587b429a1 5761 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
bogdanm 89:552587b429a1 5762
bogdanm 89:552587b429a1 5763 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 89:552587b429a1 5764 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 89:552587b429a1 5765 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 89:552587b429a1 5766
bogdanm 89:552587b429a1 5767 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
bogdanm 89:552587b429a1 5768 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
bogdanm 89:552587b429a1 5769
bogdanm 89:552587b429a1 5770 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 89:552587b429a1 5771 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
bogdanm 89:552587b429a1 5772 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
bogdanm 89:552587b429a1 5773 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
bogdanm 89:552587b429a1 5774
bogdanm 89:552587b429a1 5775 /******************************************************************************/
bogdanm 89:552587b429a1 5776 /* */
bogdanm 89:552587b429a1 5777 /* SYSCFG */
bogdanm 89:552587b429a1 5778 /* */
bogdanm 89:552587b429a1 5779 /******************************************************************************/
bogdanm 89:552587b429a1 5780 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
bogdanm 89:552587b429a1 5781 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
bogdanm 89:552587b429a1 5782 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 5783 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 5784 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 5785
bogdanm 89:552587b429a1 5786 /****************** Bit definition for SYSCFG_PMC register ******************/
bogdanm 89:552587b429a1 5787 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
bogdanm 89:552587b429a1 5788 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
bogdanm 89:552587b429a1 5789 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
bogdanm 89:552587b429a1 5790
bogdanm 89:552587b429a1 5791 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 89:552587b429a1 5792 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
bogdanm 89:552587b429a1 5793 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
bogdanm 89:552587b429a1 5794 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
bogdanm 89:552587b429a1 5795 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
bogdanm 89:552587b429a1 5796 /**
bogdanm 89:552587b429a1 5797 * @brief EXTI0 configuration
bogdanm 89:552587b429a1 5798 */
bogdanm 89:552587b429a1 5799 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
bogdanm 89:552587b429a1 5800 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
bogdanm 89:552587b429a1 5801 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
bogdanm 89:552587b429a1 5802 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
bogdanm 89:552587b429a1 5803 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
bogdanm 89:552587b429a1 5804 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
bogdanm 89:552587b429a1 5805 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
bogdanm 89:552587b429a1 5806 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
bogdanm 89:552587b429a1 5807 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
bogdanm 89:552587b429a1 5808
bogdanm 89:552587b429a1 5809 /**
bogdanm 89:552587b429a1 5810 * @brief EXTI1 configuration
bogdanm 89:552587b429a1 5811 */
bogdanm 89:552587b429a1 5812 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
bogdanm 89:552587b429a1 5813 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
bogdanm 89:552587b429a1 5814 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
bogdanm 89:552587b429a1 5815 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
bogdanm 89:552587b429a1 5816 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
bogdanm 89:552587b429a1 5817 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
bogdanm 89:552587b429a1 5818 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
bogdanm 89:552587b429a1 5819 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
bogdanm 89:552587b429a1 5820 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
bogdanm 89:552587b429a1 5821
bogdanm 89:552587b429a1 5822 /**
bogdanm 89:552587b429a1 5823 * @brief EXTI2 configuration
bogdanm 89:552587b429a1 5824 */
bogdanm 89:552587b429a1 5825 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
bogdanm 89:552587b429a1 5826 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
bogdanm 89:552587b429a1 5827 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
bogdanm 89:552587b429a1 5828 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
bogdanm 89:552587b429a1 5829 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
bogdanm 89:552587b429a1 5830 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
bogdanm 89:552587b429a1 5831 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
bogdanm 89:552587b429a1 5832 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
bogdanm 89:552587b429a1 5833 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
bogdanm 89:552587b429a1 5834
bogdanm 89:552587b429a1 5835 /**
bogdanm 89:552587b429a1 5836 * @brief EXTI3 configuration
bogdanm 89:552587b429a1 5837 */
bogdanm 89:552587b429a1 5838 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
bogdanm 89:552587b429a1 5839 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
bogdanm 89:552587b429a1 5840 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
bogdanm 89:552587b429a1 5841 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
bogdanm 89:552587b429a1 5842 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
bogdanm 89:552587b429a1 5843 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
bogdanm 89:552587b429a1 5844 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
bogdanm 89:552587b429a1 5845 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
bogdanm 89:552587b429a1 5846 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
bogdanm 89:552587b429a1 5847
bogdanm 89:552587b429a1 5848 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 89:552587b429a1 5849 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
bogdanm 89:552587b429a1 5850 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
bogdanm 89:552587b429a1 5851 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
bogdanm 89:552587b429a1 5852 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
bogdanm 89:552587b429a1 5853 /**
bogdanm 89:552587b429a1 5854 * @brief EXTI4 configuration
bogdanm 89:552587b429a1 5855 */
bogdanm 89:552587b429a1 5856 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
bogdanm 89:552587b429a1 5857 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
bogdanm 89:552587b429a1 5858 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
bogdanm 89:552587b429a1 5859 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
bogdanm 89:552587b429a1 5860 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
bogdanm 89:552587b429a1 5861 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
bogdanm 89:552587b429a1 5862 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
bogdanm 89:552587b429a1 5863 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
bogdanm 89:552587b429a1 5864 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
bogdanm 89:552587b429a1 5865
bogdanm 89:552587b429a1 5866 /**
bogdanm 89:552587b429a1 5867 * @brief EXTI5 configuration
bogdanm 89:552587b429a1 5868 */
bogdanm 89:552587b429a1 5869 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
bogdanm 89:552587b429a1 5870 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
bogdanm 89:552587b429a1 5871 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
bogdanm 89:552587b429a1 5872 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
bogdanm 89:552587b429a1 5873 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
bogdanm 89:552587b429a1 5874 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
bogdanm 89:552587b429a1 5875 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
bogdanm 89:552587b429a1 5876 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
bogdanm 89:552587b429a1 5877 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
bogdanm 89:552587b429a1 5878
bogdanm 89:552587b429a1 5879 /**
bogdanm 89:552587b429a1 5880 * @brief EXTI6 configuration
bogdanm 89:552587b429a1 5881 */
bogdanm 89:552587b429a1 5882 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
bogdanm 89:552587b429a1 5883 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
bogdanm 89:552587b429a1 5884 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
bogdanm 89:552587b429a1 5885 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
bogdanm 89:552587b429a1 5886 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
bogdanm 89:552587b429a1 5887 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
bogdanm 89:552587b429a1 5888 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
bogdanm 89:552587b429a1 5889 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
bogdanm 89:552587b429a1 5890 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
bogdanm 89:552587b429a1 5891
bogdanm 89:552587b429a1 5892 /**
bogdanm 89:552587b429a1 5893 * @brief EXTI7 configuration
bogdanm 89:552587b429a1 5894 */
bogdanm 89:552587b429a1 5895 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
bogdanm 89:552587b429a1 5896 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
bogdanm 89:552587b429a1 5897 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
bogdanm 89:552587b429a1 5898 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
bogdanm 89:552587b429a1 5899 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
bogdanm 89:552587b429a1 5900 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
bogdanm 89:552587b429a1 5901 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
bogdanm 89:552587b429a1 5902 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
bogdanm 89:552587b429a1 5903 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
bogdanm 89:552587b429a1 5904
bogdanm 89:552587b429a1 5905
bogdanm 89:552587b429a1 5906 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 89:552587b429a1 5907 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
bogdanm 89:552587b429a1 5908 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
bogdanm 89:552587b429a1 5909 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
bogdanm 89:552587b429a1 5910 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
bogdanm 89:552587b429a1 5911
bogdanm 89:552587b429a1 5912 /**
bogdanm 89:552587b429a1 5913 * @brief EXTI8 configuration
bogdanm 89:552587b429a1 5914 */
bogdanm 89:552587b429a1 5915 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
bogdanm 89:552587b429a1 5916 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
bogdanm 89:552587b429a1 5917 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
bogdanm 89:552587b429a1 5918 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
bogdanm 89:552587b429a1 5919 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
bogdanm 89:552587b429a1 5920 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
bogdanm 89:552587b429a1 5921 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
bogdanm 89:552587b429a1 5922 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
bogdanm 89:552587b429a1 5923 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
bogdanm 89:552587b429a1 5924
bogdanm 89:552587b429a1 5925 /**
bogdanm 89:552587b429a1 5926 * @brief EXTI9 configuration
bogdanm 89:552587b429a1 5927 */
bogdanm 89:552587b429a1 5928 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
bogdanm 89:552587b429a1 5929 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
bogdanm 89:552587b429a1 5930 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
bogdanm 89:552587b429a1 5931 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
bogdanm 89:552587b429a1 5932 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
bogdanm 89:552587b429a1 5933 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
bogdanm 89:552587b429a1 5934 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
bogdanm 89:552587b429a1 5935 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
bogdanm 89:552587b429a1 5936 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
bogdanm 89:552587b429a1 5937
bogdanm 89:552587b429a1 5938 /**
bogdanm 89:552587b429a1 5939 * @brief EXTI10 configuration
bogdanm 89:552587b429a1 5940 */
bogdanm 89:552587b429a1 5941 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
bogdanm 89:552587b429a1 5942 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
bogdanm 89:552587b429a1 5943 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
bogdanm 89:552587b429a1 5944 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
bogdanm 89:552587b429a1 5945 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
bogdanm 89:552587b429a1 5946 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
bogdanm 89:552587b429a1 5947 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
bogdanm 89:552587b429a1 5948 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
bogdanm 89:552587b429a1 5949 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
bogdanm 89:552587b429a1 5950
bogdanm 89:552587b429a1 5951 /**
bogdanm 89:552587b429a1 5952 * @brief EXTI11 configuration
bogdanm 89:552587b429a1 5953 */
bogdanm 89:552587b429a1 5954 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
bogdanm 89:552587b429a1 5955 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
bogdanm 89:552587b429a1 5956 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
bogdanm 89:552587b429a1 5957 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
bogdanm 89:552587b429a1 5958 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
bogdanm 89:552587b429a1 5959 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
bogdanm 89:552587b429a1 5960 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
bogdanm 89:552587b429a1 5961 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
bogdanm 89:552587b429a1 5962 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
bogdanm 89:552587b429a1 5963
bogdanm 89:552587b429a1 5964 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
bogdanm 89:552587b429a1 5965 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
bogdanm 89:552587b429a1 5966 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
bogdanm 89:552587b429a1 5967 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
bogdanm 89:552587b429a1 5968 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
bogdanm 89:552587b429a1 5969 /**
bogdanm 89:552587b429a1 5970 * @brief EXTI12 configuration
bogdanm 89:552587b429a1 5971 */
bogdanm 89:552587b429a1 5972 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
bogdanm 89:552587b429a1 5973 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
bogdanm 89:552587b429a1 5974 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
bogdanm 89:552587b429a1 5975 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
bogdanm 89:552587b429a1 5976 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
bogdanm 89:552587b429a1 5977 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
bogdanm 89:552587b429a1 5978 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
bogdanm 89:552587b429a1 5979 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
bogdanm 89:552587b429a1 5980
bogdanm 89:552587b429a1 5981 /**
bogdanm 89:552587b429a1 5982 * @brief EXTI13 configuration
bogdanm 89:552587b429a1 5983 */
bogdanm 89:552587b429a1 5984 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
bogdanm 89:552587b429a1 5985 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
bogdanm 89:552587b429a1 5986 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
bogdanm 89:552587b429a1 5987 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
bogdanm 89:552587b429a1 5988 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
bogdanm 89:552587b429a1 5989 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
bogdanm 89:552587b429a1 5990 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
bogdanm 89:552587b429a1 5991 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
bogdanm 89:552587b429a1 5992
bogdanm 89:552587b429a1 5993 /**
bogdanm 89:552587b429a1 5994 * @brief EXTI14 configuration
bogdanm 89:552587b429a1 5995 */
bogdanm 89:552587b429a1 5996 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
bogdanm 89:552587b429a1 5997 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
bogdanm 89:552587b429a1 5998 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
bogdanm 89:552587b429a1 5999 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
bogdanm 89:552587b429a1 6000 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
bogdanm 89:552587b429a1 6001 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
bogdanm 89:552587b429a1 6002 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
bogdanm 89:552587b429a1 6003 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
bogdanm 89:552587b429a1 6004
bogdanm 89:552587b429a1 6005 /**
bogdanm 89:552587b429a1 6006 * @brief EXTI15 configuration
bogdanm 89:552587b429a1 6007 */
bogdanm 89:552587b429a1 6008 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
bogdanm 89:552587b429a1 6009 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
bogdanm 89:552587b429a1 6010 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
bogdanm 89:552587b429a1 6011 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
bogdanm 89:552587b429a1 6012 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
bogdanm 89:552587b429a1 6013 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
bogdanm 89:552587b429a1 6014 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
bogdanm 89:552587b429a1 6015 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
bogdanm 89:552587b429a1 6016
bogdanm 89:552587b429a1 6017 /****************** Bit definition for SYSCFG_CMPCR register ****************/
bogdanm 89:552587b429a1 6018 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
bogdanm 89:552587b429a1 6019 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
bogdanm 89:552587b429a1 6020
bogdanm 89:552587b429a1 6021 /******************************************************************************/
bogdanm 89:552587b429a1 6022 /* */
bogdanm 89:552587b429a1 6023 /* TIM */
bogdanm 89:552587b429a1 6024 /* */
bogdanm 89:552587b429a1 6025 /******************************************************************************/
bogdanm 89:552587b429a1 6026 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 89:552587b429a1 6027 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
bogdanm 89:552587b429a1 6028 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
bogdanm 89:552587b429a1 6029 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
bogdanm 89:552587b429a1 6030 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
bogdanm 89:552587b429a1 6031 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
bogdanm 89:552587b429a1 6032
bogdanm 89:552587b429a1 6033 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 89:552587b429a1 6034 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
bogdanm 89:552587b429a1 6035 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
bogdanm 89:552587b429a1 6036
bogdanm 89:552587b429a1 6037 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
bogdanm 89:552587b429a1 6038
bogdanm 89:552587b429a1 6039 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
bogdanm 89:552587b429a1 6040 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6041 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6042
bogdanm 89:552587b429a1 6043 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 89:552587b429a1 6044 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
bogdanm 89:552587b429a1 6045 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
bogdanm 89:552587b429a1 6046 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
bogdanm 89:552587b429a1 6047
bogdanm 89:552587b429a1 6048 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 89:552587b429a1 6049 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6050 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6051 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6052
bogdanm 89:552587b429a1 6053 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
bogdanm 89:552587b429a1 6054 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 89:552587b429a1 6055 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 89:552587b429a1 6056 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 89:552587b429a1 6057 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 89:552587b429a1 6058 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 89:552587b429a1 6059 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 89:552587b429a1 6060 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 89:552587b429a1 6061
bogdanm 89:552587b429a1 6062 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 89:552587b429a1 6063 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 89:552587b429a1 6064 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6065 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6066 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 89:552587b429a1 6067
bogdanm 89:552587b429a1 6068 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 89:552587b429a1 6069 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6070 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6071 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6072
bogdanm 89:552587b429a1 6073 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
bogdanm 89:552587b429a1 6074
bogdanm 89:552587b429a1 6075 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 89:552587b429a1 6076 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6077 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6078 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 89:552587b429a1 6079 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 89:552587b429a1 6080
bogdanm 89:552587b429a1 6081 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 89:552587b429a1 6082 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6083 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6084
bogdanm 89:552587b429a1 6085 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
bogdanm 89:552587b429a1 6086 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
bogdanm 89:552587b429a1 6087
bogdanm 89:552587b429a1 6088 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 89:552587b429a1 6089 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
bogdanm 89:552587b429a1 6090 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 89:552587b429a1 6091 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 89:552587b429a1 6092 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 89:552587b429a1 6093 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 89:552587b429a1 6094 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
bogdanm 89:552587b429a1 6095 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
bogdanm 89:552587b429a1 6096 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
bogdanm 89:552587b429a1 6097 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
bogdanm 89:552587b429a1 6098 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 89:552587b429a1 6099 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 89:552587b429a1 6100 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 89:552587b429a1 6101 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 89:552587b429a1 6102 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
bogdanm 89:552587b429a1 6103 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
bogdanm 89:552587b429a1 6104
bogdanm 89:552587b429a1 6105 /******************** Bit definition for TIM_SR register ********************/
bogdanm 89:552587b429a1 6106 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
bogdanm 89:552587b429a1 6107 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 89:552587b429a1 6108 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 89:552587b429a1 6109 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 89:552587b429a1 6110 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 89:552587b429a1 6111 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
bogdanm 89:552587b429a1 6112 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
bogdanm 89:552587b429a1 6113 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
bogdanm 89:552587b429a1 6114 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 89:552587b429a1 6115 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 89:552587b429a1 6116 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 89:552587b429a1 6117 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 89:552587b429a1 6118
bogdanm 89:552587b429a1 6119 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 89:552587b429a1 6120 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
bogdanm 89:552587b429a1 6121 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
bogdanm 89:552587b429a1 6122 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
bogdanm 89:552587b429a1 6123 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
bogdanm 89:552587b429a1 6124 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
bogdanm 89:552587b429a1 6125 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
bogdanm 89:552587b429a1 6126 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
bogdanm 89:552587b429a1 6127 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
bogdanm 89:552587b429a1 6128
bogdanm 89:552587b429a1 6129 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 89:552587b429a1 6130 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 89:552587b429a1 6131 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6132 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6133
bogdanm 89:552587b429a1 6134 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
bogdanm 89:552587b429a1 6135 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
bogdanm 89:552587b429a1 6136
bogdanm 89:552587b429a1 6137 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 89:552587b429a1 6138 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6139 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6140 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6141
bogdanm 89:552587b429a1 6142 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
bogdanm 89:552587b429a1 6143
bogdanm 89:552587b429a1 6144 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 89:552587b429a1 6145 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6146 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6147
bogdanm 89:552587b429a1 6148 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
bogdanm 89:552587b429a1 6149 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
bogdanm 89:552587b429a1 6150
bogdanm 89:552587b429a1 6151 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 89:552587b429a1 6152 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6153 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6154 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 89:552587b429a1 6155
bogdanm 89:552587b429a1 6156 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
bogdanm 89:552587b429a1 6157
bogdanm 89:552587b429a1 6158 /*----------------------------------------------------------------------------*/
bogdanm 89:552587b429a1 6159
bogdanm 89:552587b429a1 6160 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 89:552587b429a1 6161 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 89:552587b429a1 6162 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 89:552587b429a1 6163
bogdanm 89:552587b429a1 6164 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 89:552587b429a1 6165 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6166 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6167 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6168 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 89:552587b429a1 6169
bogdanm 89:552587b429a1 6170 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 89:552587b429a1 6171 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 89:552587b429a1 6172 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 89:552587b429a1 6173
bogdanm 89:552587b429a1 6174 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 89:552587b429a1 6175 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6176 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6177 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 89:552587b429a1 6178 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 89:552587b429a1 6179
bogdanm 89:552587b429a1 6180 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 89:552587b429a1 6181 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 89:552587b429a1 6182 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6183 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6184
bogdanm 89:552587b429a1 6185 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
bogdanm 89:552587b429a1 6186 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
bogdanm 89:552587b429a1 6187
bogdanm 89:552587b429a1 6188 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 89:552587b429a1 6189 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6190 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6191 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6192
bogdanm 89:552587b429a1 6193 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
bogdanm 89:552587b429a1 6194
bogdanm 89:552587b429a1 6195 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 89:552587b429a1 6196 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6197 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6198
bogdanm 89:552587b429a1 6199 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
bogdanm 89:552587b429a1 6200 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
bogdanm 89:552587b429a1 6201
bogdanm 89:552587b429a1 6202 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 89:552587b429a1 6203 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6204 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6205 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 89:552587b429a1 6206
bogdanm 89:552587b429a1 6207 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
bogdanm 89:552587b429a1 6208
bogdanm 89:552587b429a1 6209 /*----------------------------------------------------------------------------*/
bogdanm 89:552587b429a1 6210
bogdanm 89:552587b429a1 6211 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 89:552587b429a1 6212 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 89:552587b429a1 6213 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 89:552587b429a1 6214
bogdanm 89:552587b429a1 6215 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 89:552587b429a1 6216 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6217 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6218 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6219 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 89:552587b429a1 6220
bogdanm 89:552587b429a1 6221 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 89:552587b429a1 6222 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 89:552587b429a1 6223 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 89:552587b429a1 6224
bogdanm 89:552587b429a1 6225 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 89:552587b429a1 6226 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6227 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6228 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 89:552587b429a1 6229 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 89:552587b429a1 6230
bogdanm 89:552587b429a1 6231 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 89:552587b429a1 6232 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
bogdanm 89:552587b429a1 6233 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
bogdanm 89:552587b429a1 6234 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 89:552587b429a1 6235 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 89:552587b429a1 6236 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
bogdanm 89:552587b429a1 6237 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
bogdanm 89:552587b429a1 6238 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 89:552587b429a1 6239 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 89:552587b429a1 6240 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
bogdanm 89:552587b429a1 6241 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
bogdanm 89:552587b429a1 6242 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 89:552587b429a1 6243 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 89:552587b429a1 6244 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
bogdanm 89:552587b429a1 6245 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
bogdanm 89:552587b429a1 6246 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 89:552587b429a1 6247
bogdanm 89:552587b429a1 6248 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 89:552587b429a1 6249 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
bogdanm 89:552587b429a1 6250
bogdanm 89:552587b429a1 6251 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 89:552587b429a1 6252 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
bogdanm 89:552587b429a1 6253
bogdanm 89:552587b429a1 6254 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 89:552587b429a1 6255 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
bogdanm 89:552587b429a1 6256
bogdanm 89:552587b429a1 6257 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 89:552587b429a1 6258 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
bogdanm 89:552587b429a1 6259
bogdanm 89:552587b429a1 6260 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 89:552587b429a1 6261 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
bogdanm 89:552587b429a1 6262
bogdanm 89:552587b429a1 6263 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 89:552587b429a1 6264 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
bogdanm 89:552587b429a1 6265
bogdanm 89:552587b429a1 6266 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 89:552587b429a1 6267 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
bogdanm 89:552587b429a1 6268
bogdanm 89:552587b429a1 6269 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 89:552587b429a1 6270 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
bogdanm 89:552587b429a1 6271
bogdanm 89:552587b429a1 6272 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 89:552587b429a1 6273 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 89:552587b429a1 6274 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6275 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6276 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 89:552587b429a1 6277 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 89:552587b429a1 6278 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 89:552587b429a1 6279 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 89:552587b429a1 6280 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 89:552587b429a1 6281 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 89:552587b429a1 6282
bogdanm 89:552587b429a1 6283 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 89:552587b429a1 6284 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6285 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6286
bogdanm 89:552587b429a1 6287 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
bogdanm 89:552587b429a1 6288 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
bogdanm 89:552587b429a1 6289 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
bogdanm 89:552587b429a1 6290 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
bogdanm 89:552587b429a1 6291 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
bogdanm 89:552587b429a1 6292 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
bogdanm 89:552587b429a1 6293
bogdanm 89:552587b429a1 6294 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 89:552587b429a1 6295 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 89:552587b429a1 6296 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6297 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6298 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 89:552587b429a1 6299 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 89:552587b429a1 6300 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 89:552587b429a1 6301
bogdanm 89:552587b429a1 6302 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 89:552587b429a1 6303 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 89:552587b429a1 6304 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 89:552587b429a1 6305 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 89:552587b429a1 6306 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 89:552587b429a1 6307 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
bogdanm 89:552587b429a1 6308
bogdanm 89:552587b429a1 6309 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 89:552587b429a1 6310 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
bogdanm 89:552587b429a1 6311
bogdanm 89:552587b429a1 6312 /******************* Bit definition for TIM_OR register *********************/
bogdanm 89:552587b429a1 6313 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
bogdanm 89:552587b429a1 6314 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
bogdanm 89:552587b429a1 6315 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
bogdanm 89:552587b429a1 6316 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
bogdanm 89:552587b429a1 6317 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 89:552587b429a1 6318 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 89:552587b429a1 6319
bogdanm 89:552587b429a1 6320
bogdanm 89:552587b429a1 6321 /******************************************************************************/
bogdanm 89:552587b429a1 6322 /* */
bogdanm 89:552587b429a1 6323 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 89:552587b429a1 6324 /* */
bogdanm 89:552587b429a1 6325 /******************************************************************************/
bogdanm 89:552587b429a1 6326 /******************* Bit definition for USART_SR register *******************/
bogdanm 89:552587b429a1 6327 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
bogdanm 89:552587b429a1 6328 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
bogdanm 89:552587b429a1 6329 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
bogdanm 89:552587b429a1 6330 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
bogdanm 89:552587b429a1 6331 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
bogdanm 89:552587b429a1 6332 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
bogdanm 89:552587b429a1 6333 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
bogdanm 89:552587b429a1 6334 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
bogdanm 89:552587b429a1 6335 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
bogdanm 89:552587b429a1 6336 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
bogdanm 89:552587b429a1 6337
bogdanm 89:552587b429a1 6338 /******************* Bit definition for USART_DR register *******************/
bogdanm 89:552587b429a1 6339 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
bogdanm 89:552587b429a1 6340
bogdanm 89:552587b429a1 6341 /****************** Bit definition for USART_BRR register *******************/
bogdanm 89:552587b429a1 6342 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
bogdanm 89:552587b429a1 6343 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
bogdanm 89:552587b429a1 6344
bogdanm 89:552587b429a1 6345 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 89:552587b429a1 6346 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
bogdanm 89:552587b429a1 6347 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
bogdanm 89:552587b429a1 6348 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
bogdanm 89:552587b429a1 6349 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
bogdanm 89:552587b429a1 6350 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
bogdanm 89:552587b429a1 6351 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
bogdanm 89:552587b429a1 6352 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
bogdanm 89:552587b429a1 6353 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
bogdanm 89:552587b429a1 6354 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
bogdanm 89:552587b429a1 6355 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
bogdanm 89:552587b429a1 6356 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
bogdanm 89:552587b429a1 6357 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
bogdanm 89:552587b429a1 6358 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
bogdanm 89:552587b429a1 6359 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
bogdanm 89:552587b429a1 6360 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
bogdanm 89:552587b429a1 6361
bogdanm 89:552587b429a1 6362 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 89:552587b429a1 6363 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
bogdanm 89:552587b429a1 6364 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
bogdanm 89:552587b429a1 6365 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
bogdanm 89:552587b429a1 6366 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
bogdanm 89:552587b429a1 6367 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
bogdanm 89:552587b429a1 6368 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
bogdanm 89:552587b429a1 6369 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
bogdanm 89:552587b429a1 6370
bogdanm 89:552587b429a1 6371 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
bogdanm 89:552587b429a1 6372 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6373 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6374
bogdanm 89:552587b429a1 6375 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
bogdanm 89:552587b429a1 6376
bogdanm 89:552587b429a1 6377 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 89:552587b429a1 6378 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
bogdanm 89:552587b429a1 6379 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
bogdanm 89:552587b429a1 6380 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
bogdanm 89:552587b429a1 6381 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
bogdanm 89:552587b429a1 6382 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
bogdanm 89:552587b429a1 6383 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
bogdanm 89:552587b429a1 6384 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
bogdanm 89:552587b429a1 6385 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
bogdanm 89:552587b429a1 6386 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
bogdanm 89:552587b429a1 6387 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
bogdanm 89:552587b429a1 6388 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
bogdanm 89:552587b429a1 6389 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
bogdanm 89:552587b429a1 6390
bogdanm 89:552587b429a1 6391 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 89:552587b429a1 6392 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
bogdanm 89:552587b429a1 6393 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6394 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6395 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 89:552587b429a1 6396 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 89:552587b429a1 6397 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 89:552587b429a1 6398 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 89:552587b429a1 6399 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 89:552587b429a1 6400 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 89:552587b429a1 6401
bogdanm 89:552587b429a1 6402 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
bogdanm 89:552587b429a1 6403
bogdanm 89:552587b429a1 6404 /******************************************************************************/
bogdanm 89:552587b429a1 6405 /* */
bogdanm 89:552587b429a1 6406 /* Window WATCHDOG */
bogdanm 89:552587b429a1 6407 /* */
bogdanm 89:552587b429a1 6408 /******************************************************************************/
bogdanm 89:552587b429a1 6409 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 89:552587b429a1 6410 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 89:552587b429a1 6411 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 89:552587b429a1 6412 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 89:552587b429a1 6413 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 89:552587b429a1 6414 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
bogdanm 89:552587b429a1 6415 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
bogdanm 89:552587b429a1 6416 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
bogdanm 89:552587b429a1 6417 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
bogdanm 89:552587b429a1 6418
bogdanm 89:552587b429a1 6419 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
bogdanm 89:552587b429a1 6420
bogdanm 89:552587b429a1 6421 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 89:552587b429a1 6422 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 89:552587b429a1 6423 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6424 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6425 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 89:552587b429a1 6426 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 89:552587b429a1 6427 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 89:552587b429a1 6428 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 89:552587b429a1 6429 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 89:552587b429a1 6430
bogdanm 89:552587b429a1 6431 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 89:552587b429a1 6432 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
bogdanm 89:552587b429a1 6433 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
bogdanm 89:552587b429a1 6434
bogdanm 89:552587b429a1 6435 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 89:552587b429a1 6436
bogdanm 89:552587b429a1 6437 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 89:552587b429a1 6438 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 89:552587b429a1 6439
bogdanm 89:552587b429a1 6440
bogdanm 89:552587b429a1 6441 /******************************************************************************/
bogdanm 89:552587b429a1 6442 /* */
bogdanm 89:552587b429a1 6443 /* DBG */
bogdanm 89:552587b429a1 6444 /* */
bogdanm 89:552587b429a1 6445 /******************************************************************************/
bogdanm 89:552587b429a1 6446 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 89:552587b429a1 6447 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 89:552587b429a1 6448 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 89:552587b429a1 6449
bogdanm 89:552587b429a1 6450 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 89:552587b429a1 6451 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 6452 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 6453 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 6454 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 6455
bogdanm 89:552587b429a1 6456 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 6457 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 89:552587b429a1 6458 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 89:552587b429a1 6459
bogdanm 89:552587b429a1 6460 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 89:552587b429a1 6461 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 6462 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 6463 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 6464 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 6465 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 6466 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 6467 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 6468 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
bogdanm 89:552587b429a1 6469 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 6470 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 6471 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 6472 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 6473 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 6474 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 6475 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 6476 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm 89:552587b429a1 6477 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
bogdanm 89:552587b429a1 6478 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm 89:552587b429a1 6479 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm 89:552587b429a1 6480
bogdanm 89:552587b429a1 6481 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 89:552587b429a1 6482 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 6483 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 6484 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 6485 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 6486 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 6487
bogdanm 89:552587b429a1 6488 /******************************************************************************/
bogdanm 89:552587b429a1 6489 /* */
bogdanm 89:552587b429a1 6490 /* Ethernet MAC Registers bits definitions */
bogdanm 89:552587b429a1 6491 /* */
bogdanm 89:552587b429a1 6492 /******************************************************************************/
bogdanm 89:552587b429a1 6493 /* Bit definition for Ethernet MAC Control Register register */
bogdanm 89:552587b429a1 6494 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
bogdanm 89:552587b429a1 6495 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
bogdanm 89:552587b429a1 6496 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
bogdanm 89:552587b429a1 6497 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
bogdanm 89:552587b429a1 6498 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
bogdanm 89:552587b429a1 6499 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
bogdanm 89:552587b429a1 6500 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
bogdanm 89:552587b429a1 6501 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
bogdanm 89:552587b429a1 6502 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
bogdanm 89:552587b429a1 6503 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
bogdanm 89:552587b429a1 6504 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
bogdanm 89:552587b429a1 6505 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
bogdanm 89:552587b429a1 6506 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
bogdanm 89:552587b429a1 6507 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
bogdanm 89:552587b429a1 6508 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
bogdanm 89:552587b429a1 6509 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
bogdanm 89:552587b429a1 6510 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
bogdanm 89:552587b429a1 6511 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
bogdanm 89:552587b429a1 6512 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
bogdanm 89:552587b429a1 6513 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
bogdanm 89:552587b429a1 6514 a transmission attempt during retries after a collision: 0 =< r <2^k */
bogdanm 89:552587b429a1 6515 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
bogdanm 89:552587b429a1 6516 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
bogdanm 89:552587b429a1 6517 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
bogdanm 89:552587b429a1 6518 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
bogdanm 89:552587b429a1 6519 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
bogdanm 89:552587b429a1 6520 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
bogdanm 89:552587b429a1 6521 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
bogdanm 89:552587b429a1 6522
bogdanm 89:552587b429a1 6523 /* Bit definition for Ethernet MAC Frame Filter Register */
bogdanm 89:552587b429a1 6524 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
bogdanm 89:552587b429a1 6525 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
bogdanm 89:552587b429a1 6526 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
bogdanm 89:552587b429a1 6527 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
bogdanm 89:552587b429a1 6528 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
bogdanm 89:552587b429a1 6529 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
bogdanm 89:552587b429a1 6530 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
bogdanm 89:552587b429a1 6531 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
bogdanm 89:552587b429a1 6532 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
bogdanm 89:552587b429a1 6533 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
bogdanm 89:552587b429a1 6534 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
bogdanm 89:552587b429a1 6535 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
bogdanm 89:552587b429a1 6536 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
bogdanm 89:552587b429a1 6537 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
bogdanm 89:552587b429a1 6538
bogdanm 89:552587b429a1 6539 /* Bit definition for Ethernet MAC Hash Table High Register */
bogdanm 89:552587b429a1 6540 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
bogdanm 89:552587b429a1 6541
bogdanm 89:552587b429a1 6542 /* Bit definition for Ethernet MAC Hash Table Low Register */
bogdanm 89:552587b429a1 6543 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
bogdanm 89:552587b429a1 6544
bogdanm 89:552587b429a1 6545 /* Bit definition for Ethernet MAC MII Address Register */
bogdanm 89:552587b429a1 6546 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
bogdanm 89:552587b429a1 6547 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
bogdanm 89:552587b429a1 6548 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
bogdanm 89:552587b429a1 6549 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
bogdanm 89:552587b429a1 6550 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
bogdanm 89:552587b429a1 6551 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
bogdanm 89:552587b429a1 6552 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
bogdanm 89:552587b429a1 6553 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
bogdanm 89:552587b429a1 6554 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
bogdanm 89:552587b429a1 6555 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
bogdanm 89:552587b429a1 6556
bogdanm 89:552587b429a1 6557 /* Bit definition for Ethernet MAC MII Data Register */
bogdanm 89:552587b429a1 6558 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
bogdanm 89:552587b429a1 6559
bogdanm 89:552587b429a1 6560 /* Bit definition for Ethernet MAC Flow Control Register */
bogdanm 89:552587b429a1 6561 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
bogdanm 89:552587b429a1 6562 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
bogdanm 89:552587b429a1 6563 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
bogdanm 89:552587b429a1 6564 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
bogdanm 89:552587b429a1 6565 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
bogdanm 89:552587b429a1 6566 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
bogdanm 89:552587b429a1 6567 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
bogdanm 89:552587b429a1 6568 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
bogdanm 89:552587b429a1 6569 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
bogdanm 89:552587b429a1 6570 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
bogdanm 89:552587b429a1 6571 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
bogdanm 89:552587b429a1 6572
bogdanm 89:552587b429a1 6573 /* Bit definition for Ethernet MAC VLAN Tag Register */
bogdanm 89:552587b429a1 6574 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
bogdanm 89:552587b429a1 6575 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
bogdanm 89:552587b429a1 6576
bogdanm 89:552587b429a1 6577 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
bogdanm 89:552587b429a1 6578 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
bogdanm 89:552587b429a1 6579 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
bogdanm 89:552587b429a1 6580 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
bogdanm 89:552587b429a1 6581 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
bogdanm 89:552587b429a1 6582 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
bogdanm 89:552587b429a1 6583 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
bogdanm 89:552587b429a1 6584 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
bogdanm 89:552587b429a1 6585 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
bogdanm 89:552587b429a1 6586 RSVD - Filter1 Command - RSVD - Filter0 Command
bogdanm 89:552587b429a1 6587 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
bogdanm 89:552587b429a1 6588 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
bogdanm 89:552587b429a1 6589 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
bogdanm 89:552587b429a1 6590
bogdanm 89:552587b429a1 6591 /* Bit definition for Ethernet MAC PMT Control and Status Register */
bogdanm 89:552587b429a1 6592 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
bogdanm 89:552587b429a1 6593 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
bogdanm 89:552587b429a1 6594 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
bogdanm 89:552587b429a1 6595 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
bogdanm 89:552587b429a1 6596 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
bogdanm 89:552587b429a1 6597 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
bogdanm 89:552587b429a1 6598 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
bogdanm 89:552587b429a1 6599
bogdanm 89:552587b429a1 6600 /* Bit definition for Ethernet MAC Status Register */
bogdanm 89:552587b429a1 6601 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
bogdanm 89:552587b429a1 6602 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
bogdanm 89:552587b429a1 6603 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
bogdanm 89:552587b429a1 6604 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
bogdanm 89:552587b429a1 6605 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
bogdanm 89:552587b429a1 6606
bogdanm 89:552587b429a1 6607 /* Bit definition for Ethernet MAC Interrupt Mask Register */
bogdanm 89:552587b429a1 6608 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
bogdanm 89:552587b429a1 6609 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
bogdanm 89:552587b429a1 6610
bogdanm 89:552587b429a1 6611 /* Bit definition for Ethernet MAC Address0 High Register */
bogdanm 89:552587b429a1 6612 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
bogdanm 89:552587b429a1 6613
bogdanm 89:552587b429a1 6614 /* Bit definition for Ethernet MAC Address0 Low Register */
bogdanm 89:552587b429a1 6615 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
bogdanm 89:552587b429a1 6616
bogdanm 89:552587b429a1 6617 /* Bit definition for Ethernet MAC Address1 High Register */
bogdanm 89:552587b429a1 6618 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 89:552587b429a1 6619 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 89:552587b429a1 6620 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
bogdanm 89:552587b429a1 6621 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 89:552587b429a1 6622 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 89:552587b429a1 6623 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 89:552587b429a1 6624 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 89:552587b429a1 6625 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 89:552587b429a1 6626 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
bogdanm 89:552587b429a1 6627 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 89:552587b429a1 6628
bogdanm 89:552587b429a1 6629 /* Bit definition for Ethernet MAC Address1 Low Register */
bogdanm 89:552587b429a1 6630 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
bogdanm 89:552587b429a1 6631
bogdanm 89:552587b429a1 6632 /* Bit definition for Ethernet MAC Address2 High Register */
bogdanm 89:552587b429a1 6633 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 89:552587b429a1 6634 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 89:552587b429a1 6635 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 89:552587b429a1 6636 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 89:552587b429a1 6637 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 89:552587b429a1 6638 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 89:552587b429a1 6639 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 89:552587b429a1 6640 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 89:552587b429a1 6641 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 89:552587b429a1 6642 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 89:552587b429a1 6643
bogdanm 89:552587b429a1 6644 /* Bit definition for Ethernet MAC Address2 Low Register */
bogdanm 89:552587b429a1 6645 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
bogdanm 89:552587b429a1 6646
bogdanm 89:552587b429a1 6647 /* Bit definition for Ethernet MAC Address3 High Register */
bogdanm 89:552587b429a1 6648 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 89:552587b429a1 6649 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 89:552587b429a1 6650 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 89:552587b429a1 6651 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 89:552587b429a1 6652 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 89:552587b429a1 6653 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 89:552587b429a1 6654 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 89:552587b429a1 6655 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 89:552587b429a1 6656 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 89:552587b429a1 6657 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
bogdanm 89:552587b429a1 6658
bogdanm 89:552587b429a1 6659 /* Bit definition for Ethernet MAC Address3 Low Register */
bogdanm 89:552587b429a1 6660 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
bogdanm 89:552587b429a1 6661
bogdanm 89:552587b429a1 6662 /******************************************************************************/
bogdanm 89:552587b429a1 6663 /* Ethernet MMC Registers bits definition */
bogdanm 89:552587b429a1 6664 /******************************************************************************/
bogdanm 89:552587b429a1 6665
bogdanm 89:552587b429a1 6666 /* Bit definition for Ethernet MMC Contol Register */
bogdanm 89:552587b429a1 6667 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
bogdanm 89:552587b429a1 6668 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
bogdanm 89:552587b429a1 6669 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
bogdanm 89:552587b429a1 6670 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
bogdanm 89:552587b429a1 6671 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
bogdanm 89:552587b429a1 6672 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
bogdanm 89:552587b429a1 6673
bogdanm 89:552587b429a1 6674 /* Bit definition for Ethernet MMC Receive Interrupt Register */
bogdanm 89:552587b429a1 6675 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
bogdanm 89:552587b429a1 6676 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
bogdanm 89:552587b429a1 6677 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
bogdanm 89:552587b429a1 6678
bogdanm 89:552587b429a1 6679 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
bogdanm 89:552587b429a1 6680 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
bogdanm 89:552587b429a1 6681 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
bogdanm 89:552587b429a1 6682 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
bogdanm 89:552587b429a1 6683
bogdanm 89:552587b429a1 6684 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
bogdanm 89:552587b429a1 6685 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
bogdanm 89:552587b429a1 6686 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
bogdanm 89:552587b429a1 6687 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
bogdanm 89:552587b429a1 6688
bogdanm 89:552587b429a1 6689 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
bogdanm 89:552587b429a1 6690 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
bogdanm 89:552587b429a1 6691 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
bogdanm 89:552587b429a1 6692 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
bogdanm 89:552587b429a1 6693
bogdanm 89:552587b429a1 6694 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
bogdanm 89:552587b429a1 6695 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
bogdanm 89:552587b429a1 6696
bogdanm 89:552587b429a1 6697 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
bogdanm 89:552587b429a1 6698 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
bogdanm 89:552587b429a1 6699
bogdanm 89:552587b429a1 6700 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
bogdanm 89:552587b429a1 6701 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
bogdanm 89:552587b429a1 6702
bogdanm 89:552587b429a1 6703 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
bogdanm 89:552587b429a1 6704 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
bogdanm 89:552587b429a1 6705
bogdanm 89:552587b429a1 6706 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
bogdanm 89:552587b429a1 6707 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
bogdanm 89:552587b429a1 6708
bogdanm 89:552587b429a1 6709 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
bogdanm 89:552587b429a1 6710 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
bogdanm 89:552587b429a1 6711
bogdanm 89:552587b429a1 6712 /******************************************************************************/
bogdanm 89:552587b429a1 6713 /* Ethernet PTP Registers bits definition */
bogdanm 89:552587b429a1 6714 /******************************************************************************/
bogdanm 89:552587b429a1 6715
bogdanm 89:552587b429a1 6716 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
bogdanm 89:552587b429a1 6717 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
bogdanm 89:552587b429a1 6718 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
bogdanm 89:552587b429a1 6719 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
bogdanm 89:552587b429a1 6720 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
bogdanm 89:552587b429a1 6721 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
bogdanm 89:552587b429a1 6722 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
bogdanm 89:552587b429a1 6723 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
bogdanm 89:552587b429a1 6724 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
bogdanm 89:552587b429a1 6725 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
bogdanm 89:552587b429a1 6726
bogdanm 89:552587b429a1 6727 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
bogdanm 89:552587b429a1 6728 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
bogdanm 89:552587b429a1 6729 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
bogdanm 89:552587b429a1 6730 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
bogdanm 89:552587b429a1 6731 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
bogdanm 89:552587b429a1 6732 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
bogdanm 89:552587b429a1 6733
bogdanm 89:552587b429a1 6734 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
bogdanm 89:552587b429a1 6735 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
bogdanm 89:552587b429a1 6736
bogdanm 89:552587b429a1 6737 /* Bit definition for Ethernet PTP Time Stamp High Register */
bogdanm 89:552587b429a1 6738 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
bogdanm 89:552587b429a1 6739
bogdanm 89:552587b429a1 6740 /* Bit definition for Ethernet PTP Time Stamp Low Register */
bogdanm 89:552587b429a1 6741 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
bogdanm 89:552587b429a1 6742 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
bogdanm 89:552587b429a1 6743
bogdanm 89:552587b429a1 6744 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
bogdanm 89:552587b429a1 6745 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
bogdanm 89:552587b429a1 6746
bogdanm 89:552587b429a1 6747 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
bogdanm 89:552587b429a1 6748 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
bogdanm 89:552587b429a1 6749 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
bogdanm 89:552587b429a1 6750
bogdanm 89:552587b429a1 6751 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
bogdanm 89:552587b429a1 6752 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
bogdanm 89:552587b429a1 6753
bogdanm 89:552587b429a1 6754 /* Bit definition for Ethernet PTP Target Time High Register */
bogdanm 89:552587b429a1 6755 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
bogdanm 89:552587b429a1 6756
bogdanm 89:552587b429a1 6757 /* Bit definition for Ethernet PTP Target Time Low Register */
bogdanm 89:552587b429a1 6758 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
bogdanm 89:552587b429a1 6759
bogdanm 89:552587b429a1 6760 /* Bit definition for Ethernet PTP Time Stamp Status Register */
bogdanm 89:552587b429a1 6761 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
bogdanm 89:552587b429a1 6762 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
bogdanm 89:552587b429a1 6763
bogdanm 89:552587b429a1 6764 /******************************************************************************/
bogdanm 89:552587b429a1 6765 /* Ethernet DMA Registers bits definition */
bogdanm 89:552587b429a1 6766 /******************************************************************************/
bogdanm 89:552587b429a1 6767
bogdanm 89:552587b429a1 6768 /* Bit definition for Ethernet DMA Bus Mode Register */
bogdanm 89:552587b429a1 6769 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
bogdanm 89:552587b429a1 6770 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
bogdanm 89:552587b429a1 6771 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
bogdanm 89:552587b429a1 6772 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
bogdanm 89:552587b429a1 6773 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
bogdanm 89:552587b429a1 6774 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
bogdanm 89:552587b429a1 6775 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 89:552587b429a1 6776 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 89:552587b429a1 6777 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 89:552587b429a1 6778 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 89:552587b429a1 6779 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 89:552587b429a1 6780 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 89:552587b429a1 6781 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 89:552587b429a1 6782 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 89:552587b429a1 6783 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
bogdanm 89:552587b429a1 6784 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm 89:552587b429a1 6785 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
bogdanm 89:552587b429a1 6786 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 89:552587b429a1 6787 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
bogdanm 89:552587b429a1 6788 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
bogdanm 89:552587b429a1 6789 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
bogdanm 89:552587b429a1 6790 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 89:552587b429a1 6791 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
bogdanm 89:552587b429a1 6792 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
bogdanm 89:552587b429a1 6793 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
bogdanm 89:552587b429a1 6794 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 89:552587b429a1 6795 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 89:552587b429a1 6796 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 89:552587b429a1 6797 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 89:552587b429a1 6798 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 89:552587b429a1 6799 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 89:552587b429a1 6800 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 89:552587b429a1 6801 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 89:552587b429a1 6802 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
bogdanm 89:552587b429a1 6803 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
bogdanm 89:552587b429a1 6804 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
bogdanm 89:552587b429a1 6805 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
bogdanm 89:552587b429a1 6806 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
bogdanm 89:552587b429a1 6807 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
bogdanm 89:552587b429a1 6808
bogdanm 89:552587b429a1 6809 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
bogdanm 89:552587b429a1 6810 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
bogdanm 89:552587b429a1 6811
bogdanm 89:552587b429a1 6812 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
bogdanm 89:552587b429a1 6813 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
bogdanm 89:552587b429a1 6814
bogdanm 89:552587b429a1 6815 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
bogdanm 89:552587b429a1 6816 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
bogdanm 89:552587b429a1 6817
bogdanm 89:552587b429a1 6818 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
bogdanm 89:552587b429a1 6819 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
bogdanm 89:552587b429a1 6820
bogdanm 89:552587b429a1 6821 /* Bit definition for Ethernet DMA Status Register */
bogdanm 89:552587b429a1 6822 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
bogdanm 89:552587b429a1 6823 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
bogdanm 89:552587b429a1 6824 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
bogdanm 89:552587b429a1 6825 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
bogdanm 89:552587b429a1 6826 /* combination with EBS[2:0] for GetFlagStatus function */
bogdanm 89:552587b429a1 6827 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
bogdanm 89:552587b429a1 6828 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
bogdanm 89:552587b429a1 6829 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
bogdanm 89:552587b429a1 6830 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
bogdanm 89:552587b429a1 6831 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
bogdanm 89:552587b429a1 6832 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
bogdanm 89:552587b429a1 6833 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
bogdanm 89:552587b429a1 6834 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
bogdanm 89:552587b429a1 6835 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
bogdanm 89:552587b429a1 6836 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
bogdanm 89:552587b429a1 6837 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
bogdanm 89:552587b429a1 6838 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
bogdanm 89:552587b429a1 6839 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
bogdanm 89:552587b429a1 6840 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
bogdanm 89:552587b429a1 6841 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
bogdanm 89:552587b429a1 6842 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
bogdanm 89:552587b429a1 6843 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
bogdanm 89:552587b429a1 6844 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
bogdanm 89:552587b429a1 6845 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
bogdanm 89:552587b429a1 6846 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
bogdanm 89:552587b429a1 6847 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
bogdanm 89:552587b429a1 6848 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
bogdanm 89:552587b429a1 6849 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
bogdanm 89:552587b429a1 6850 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
bogdanm 89:552587b429a1 6851 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
bogdanm 89:552587b429a1 6852 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
bogdanm 89:552587b429a1 6853 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
bogdanm 89:552587b429a1 6854 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
bogdanm 89:552587b429a1 6855 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
bogdanm 89:552587b429a1 6856 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
bogdanm 89:552587b429a1 6857 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
bogdanm 89:552587b429a1 6858 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
bogdanm 89:552587b429a1 6859
bogdanm 89:552587b429a1 6860 /* Bit definition for Ethernet DMA Operation Mode Register */
bogdanm 89:552587b429a1 6861 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
bogdanm 89:552587b429a1 6862 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
bogdanm 89:552587b429a1 6863 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
bogdanm 89:552587b429a1 6864 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
bogdanm 89:552587b429a1 6865 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
bogdanm 89:552587b429a1 6866 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
bogdanm 89:552587b429a1 6867 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
bogdanm 89:552587b429a1 6868 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
bogdanm 89:552587b429a1 6869 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
bogdanm 89:552587b429a1 6870 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
bogdanm 89:552587b429a1 6871 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
bogdanm 89:552587b429a1 6872 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
bogdanm 89:552587b429a1 6873 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
bogdanm 89:552587b429a1 6874 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm 89:552587b429a1 6875 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
bogdanm 89:552587b429a1 6876 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
bogdanm 89:552587b429a1 6877 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
bogdanm 89:552587b429a1 6878 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
bogdanm 89:552587b429a1 6879 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
bogdanm 89:552587b429a1 6880 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
bogdanm 89:552587b429a1 6881 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
bogdanm 89:552587b429a1 6882 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm 89:552587b429a1 6883 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
bogdanm 89:552587b429a1 6884 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
bogdanm 89:552587b429a1 6885
bogdanm 89:552587b429a1 6886 /* Bit definition for Ethernet DMA Interrupt Enable Register */
bogdanm 89:552587b429a1 6887 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
bogdanm 89:552587b429a1 6888 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
bogdanm 89:552587b429a1 6889 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
bogdanm 89:552587b429a1 6890 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
bogdanm 89:552587b429a1 6891 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
bogdanm 89:552587b429a1 6892 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
bogdanm 89:552587b429a1 6893 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
bogdanm 89:552587b429a1 6894 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
bogdanm 89:552587b429a1 6895 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
bogdanm 89:552587b429a1 6896 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
bogdanm 89:552587b429a1 6897 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
bogdanm 89:552587b429a1 6898 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
bogdanm 89:552587b429a1 6899 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
bogdanm 89:552587b429a1 6900 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
bogdanm 89:552587b429a1 6901 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
bogdanm 89:552587b429a1 6902
bogdanm 89:552587b429a1 6903 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
bogdanm 89:552587b429a1 6904 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
bogdanm 89:552587b429a1 6905 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
bogdanm 89:552587b429a1 6906 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
bogdanm 89:552587b429a1 6907 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
bogdanm 89:552587b429a1 6908
bogdanm 89:552587b429a1 6909 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
bogdanm 89:552587b429a1 6910 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
bogdanm 89:552587b429a1 6911
bogdanm 89:552587b429a1 6912 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
bogdanm 89:552587b429a1 6913 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
bogdanm 89:552587b429a1 6914
bogdanm 89:552587b429a1 6915 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
bogdanm 89:552587b429a1 6916 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
bogdanm 89:552587b429a1 6917
bogdanm 89:552587b429a1 6918 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
bogdanm 89:552587b429a1 6919 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
bogdanm 89:552587b429a1 6920
bogdanm 89:552587b429a1 6921 /******************************************************************************/
bogdanm 89:552587b429a1 6922 /* */
bogdanm 89:552587b429a1 6923 /* USB_OTG */
bogdanm 89:552587b429a1 6924 /* */
bogdanm 89:552587b429a1 6925 /******************************************************************************/
bogdanm 89:552587b429a1 6926 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
bogdanm 89:552587b429a1 6927 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
bogdanm 89:552587b429a1 6928 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
bogdanm 89:552587b429a1 6929 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
bogdanm 89:552587b429a1 6930 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
bogdanm 89:552587b429a1 6931 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
bogdanm 89:552587b429a1 6932 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
bogdanm 89:552587b429a1 6933 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
bogdanm 89:552587b429a1 6934 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
bogdanm 89:552587b429a1 6935 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
bogdanm 89:552587b429a1 6936 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
bogdanm 89:552587b429a1 6937
bogdanm 89:552587b429a1 6938 /******************** Bit definition forUSB_OTG_HCFG register ********************/
bogdanm 89:552587b429a1 6939
bogdanm 89:552587b429a1 6940 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
bogdanm 89:552587b429a1 6941 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6942 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6943 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
bogdanm 89:552587b429a1 6944
bogdanm 89:552587b429a1 6945 /******************** Bit definition forUSB_OTG_DCFG register ********************/
bogdanm 89:552587b429a1 6946
bogdanm 89:552587b429a1 6947 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
bogdanm 89:552587b429a1 6948 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 6949 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 6950 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
bogdanm 89:552587b429a1 6951
bogdanm 89:552587b429a1 6952 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
bogdanm 89:552587b429a1 6953 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6954 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6955 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6956 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 89:552587b429a1 6957 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
bogdanm 89:552587b429a1 6958 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
bogdanm 89:552587b429a1 6959 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
bogdanm 89:552587b429a1 6960
bogdanm 89:552587b429a1 6961 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
bogdanm 89:552587b429a1 6962 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 89:552587b429a1 6963 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6964
bogdanm 89:552587b429a1 6965 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
bogdanm 89:552587b429a1 6966 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 6967 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 6968
bogdanm 89:552587b429a1 6969 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
bogdanm 89:552587b429a1 6970 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
bogdanm 89:552587b429a1 6971 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
bogdanm 89:552587b429a1 6972 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
bogdanm 89:552587b429a1 6973
bogdanm 89:552587b429a1 6974 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
bogdanm 89:552587b429a1 6975 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
bogdanm 89:552587b429a1 6976 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
bogdanm 89:552587b429a1 6977 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
bogdanm 89:552587b429a1 6978 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
bogdanm 89:552587b429a1 6979 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
bogdanm 89:552587b429a1 6980 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
bogdanm 89:552587b429a1 6981
bogdanm 89:552587b429a1 6982 /******************** Bit definition forUSB_OTG_DCTL register ********************/
bogdanm 89:552587b429a1 6983 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
bogdanm 89:552587b429a1 6984 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
bogdanm 89:552587b429a1 6985 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
bogdanm 89:552587b429a1 6986 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
bogdanm 89:552587b429a1 6987
bogdanm 89:552587b429a1 6988 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
bogdanm 89:552587b429a1 6989 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 89:552587b429a1 6990 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 89:552587b429a1 6991 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 89:552587b429a1 6992 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
bogdanm 89:552587b429a1 6993 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
bogdanm 89:552587b429a1 6994 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
bogdanm 89:552587b429a1 6995 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
bogdanm 89:552587b429a1 6996 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
bogdanm 89:552587b429a1 6997
bogdanm 89:552587b429a1 6998 /******************** Bit definition forUSB_OTG_HFIR register ********************/
bogdanm 89:552587b429a1 6999 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
bogdanm 89:552587b429a1 7000
bogdanm 89:552587b429a1 7001 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
bogdanm 89:552587b429a1 7002 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
bogdanm 89:552587b429a1 7003 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
bogdanm 89:552587b429a1 7004
bogdanm 89:552587b429a1 7005 /******************** Bit definition forUSB_OTG_DSTS register ********************/
bogdanm 89:552587b429a1 7006 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
bogdanm 89:552587b429a1 7007
bogdanm 89:552587b429a1 7008 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
bogdanm 89:552587b429a1 7009 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 89:552587b429a1 7010 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 89:552587b429a1 7011 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
bogdanm 89:552587b429a1 7012 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
bogdanm 89:552587b429a1 7013
bogdanm 89:552587b429a1 7014 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
bogdanm 89:552587b429a1 7015 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
bogdanm 89:552587b429a1 7016
bogdanm 89:552587b429a1 7017 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
bogdanm 89:552587b429a1 7018 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 89:552587b429a1 7019 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 89:552587b429a1 7020 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
bogdanm 89:552587b429a1 7021 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
bogdanm 89:552587b429a1 7022 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
bogdanm 89:552587b429a1 7023 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
bogdanm 89:552587b429a1 7024 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
bogdanm 89:552587b429a1 7025
bogdanm 89:552587b429a1 7026 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
bogdanm 89:552587b429a1 7027
bogdanm 89:552587b429a1 7028 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
bogdanm 89:552587b429a1 7029 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7030 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7031 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7032 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
bogdanm 89:552587b429a1 7033 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
bogdanm 89:552587b429a1 7034 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
bogdanm 89:552587b429a1 7035
bogdanm 89:552587b429a1 7036 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
bogdanm 89:552587b429a1 7037 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 7038 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 7039 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7040 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7041 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
bogdanm 89:552587b429a1 7042 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
bogdanm 89:552587b429a1 7043 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
bogdanm 89:552587b429a1 7044 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
bogdanm 89:552587b429a1 7045 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
bogdanm 89:552587b429a1 7046 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
bogdanm 89:552587b429a1 7047 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
bogdanm 89:552587b429a1 7048 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
bogdanm 89:552587b429a1 7049 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
bogdanm 89:552587b429a1 7050 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
bogdanm 89:552587b429a1 7051 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
bogdanm 89:552587b429a1 7052 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
bogdanm 89:552587b429a1 7053 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
bogdanm 89:552587b429a1 7054
bogdanm 89:552587b429a1 7055 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
bogdanm 89:552587b429a1 7056 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
bogdanm 89:552587b429a1 7057 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
bogdanm 89:552587b429a1 7058 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
bogdanm 89:552587b429a1 7059 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
bogdanm 89:552587b429a1 7060 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
bogdanm 89:552587b429a1 7061
bogdanm 89:552587b429a1 7062 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
bogdanm 89:552587b429a1 7063 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 89:552587b429a1 7064 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 89:552587b429a1 7065 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 89:552587b429a1 7066 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
bogdanm 89:552587b429a1 7067 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
bogdanm 89:552587b429a1 7068 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
bogdanm 89:552587b429a1 7069 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
bogdanm 89:552587b429a1 7070
bogdanm 89:552587b429a1 7071 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
bogdanm 89:552587b429a1 7072 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 89:552587b429a1 7073 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 89:552587b429a1 7074 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 89:552587b429a1 7075 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 89:552587b429a1 7076 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 89:552587b429a1 7077 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 89:552587b429a1 7078 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 89:552587b429a1 7079 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 89:552587b429a1 7080
bogdanm 89:552587b429a1 7081 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
bogdanm 89:552587b429a1 7082 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
bogdanm 89:552587b429a1 7083
bogdanm 89:552587b429a1 7084 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
bogdanm 89:552587b429a1 7085 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7086 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7087 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7088 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7089 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7090 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7091 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7092 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 7093
bogdanm 89:552587b429a1 7094 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
bogdanm 89:552587b429a1 7095 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7096 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7097 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7098 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7099 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7100 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7101 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7102 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 7103
bogdanm 89:552587b429a1 7104 /******************** Bit definition forUSB_OTG_HAINT register ********************/
bogdanm 89:552587b429a1 7105 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
bogdanm 89:552587b429a1 7106
bogdanm 89:552587b429a1 7107 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
bogdanm 89:552587b429a1 7108 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 89:552587b429a1 7109 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 89:552587b429a1 7110 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
bogdanm 89:552587b429a1 7111 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
bogdanm 89:552587b429a1 7112 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
bogdanm 89:552587b429a1 7113 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 89:552587b429a1 7114 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 89:552587b429a1 7115
bogdanm 89:552587b429a1 7116 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
bogdanm 89:552587b429a1 7117 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
bogdanm 89:552587b429a1 7118 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
bogdanm 89:552587b429a1 7119 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
bogdanm 89:552587b429a1 7120 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
bogdanm 89:552587b429a1 7121 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
bogdanm 89:552587b429a1 7122 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
bogdanm 89:552587b429a1 7123 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
bogdanm 89:552587b429a1 7124 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
bogdanm 89:552587b429a1 7125 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
bogdanm 89:552587b429a1 7126 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
bogdanm 89:552587b429a1 7127 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
bogdanm 89:552587b429a1 7128 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
bogdanm 89:552587b429a1 7129 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
bogdanm 89:552587b429a1 7130 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
bogdanm 89:552587b429a1 7131 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
bogdanm 89:552587b429a1 7132 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
bogdanm 89:552587b429a1 7133 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
bogdanm 89:552587b429a1 7134 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
bogdanm 89:552587b429a1 7135 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
bogdanm 89:552587b429a1 7136 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
bogdanm 89:552587b429a1 7137 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
bogdanm 89:552587b429a1 7138 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
bogdanm 89:552587b429a1 7139 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
bogdanm 89:552587b429a1 7140 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
bogdanm 89:552587b429a1 7141 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
bogdanm 89:552587b429a1 7142 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
bogdanm 89:552587b429a1 7143
bogdanm 89:552587b429a1 7144 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
bogdanm 89:552587b429a1 7145 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
bogdanm 89:552587b429a1 7146 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
bogdanm 89:552587b429a1 7147 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
bogdanm 89:552587b429a1 7148 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
bogdanm 89:552587b429a1 7149 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
bogdanm 89:552587b429a1 7150 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
bogdanm 89:552587b429a1 7151 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
bogdanm 89:552587b429a1 7152 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
bogdanm 89:552587b429a1 7153 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
bogdanm 89:552587b429a1 7154 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
bogdanm 89:552587b429a1 7155 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
bogdanm 89:552587b429a1 7156 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
bogdanm 89:552587b429a1 7157 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
bogdanm 89:552587b429a1 7158 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
bogdanm 89:552587b429a1 7159 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
bogdanm 89:552587b429a1 7160 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
bogdanm 89:552587b429a1 7161 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
bogdanm 89:552587b429a1 7162 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
bogdanm 89:552587b429a1 7163 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
bogdanm 89:552587b429a1 7164 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
bogdanm 89:552587b429a1 7165 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
bogdanm 89:552587b429a1 7166 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
bogdanm 89:552587b429a1 7167 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
bogdanm 89:552587b429a1 7168 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
bogdanm 89:552587b429a1 7169 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
bogdanm 89:552587b429a1 7170 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
bogdanm 89:552587b429a1 7171
bogdanm 89:552587b429a1 7172 /******************** Bit definition forUSB_OTG_DAINT register ********************/
bogdanm 89:552587b429a1 7173 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
bogdanm 89:552587b429a1 7174 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
bogdanm 89:552587b429a1 7175
bogdanm 89:552587b429a1 7176 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
bogdanm 89:552587b429a1 7177 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
bogdanm 89:552587b429a1 7178
bogdanm 89:552587b429a1 7179 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
bogdanm 89:552587b429a1 7180 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
bogdanm 89:552587b429a1 7181 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
bogdanm 89:552587b429a1 7182 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
bogdanm 89:552587b429a1 7183 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
bogdanm 89:552587b429a1 7184
bogdanm 89:552587b429a1 7185 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
bogdanm 89:552587b429a1 7186 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
bogdanm 89:552587b429a1 7187 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
bogdanm 89:552587b429a1 7188
bogdanm 89:552587b429a1 7189 /******************** Bit definition for OTG register ********************/
bogdanm 89:552587b429a1 7190
bogdanm 89:552587b429a1 7191 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 89:552587b429a1 7192 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7193 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7194 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7195 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 7196 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 89:552587b429a1 7197
bogdanm 89:552587b429a1 7198 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 89:552587b429a1 7199 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7200 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7201
bogdanm 89:552587b429a1 7202 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 89:552587b429a1 7203 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7204 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7205 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7206 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7207
bogdanm 89:552587b429a1 7208 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 89:552587b429a1 7209 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7210 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7211 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7212 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 7213
bogdanm 89:552587b429a1 7214 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 89:552587b429a1 7215 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7216 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7217 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7218 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7219
bogdanm 89:552587b429a1 7220 /******************** Bit definition for OTG register ********************/
bogdanm 89:552587b429a1 7221
bogdanm 89:552587b429a1 7222 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 89:552587b429a1 7223 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7224 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7225 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7226 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 7227 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 89:552587b429a1 7228
bogdanm 89:552587b429a1 7229 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 89:552587b429a1 7230 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7231 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7232
bogdanm 89:552587b429a1 7233 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 89:552587b429a1 7234 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7235 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7236 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7237 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7238
bogdanm 89:552587b429a1 7239 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 89:552587b429a1 7240 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7241 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7242 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7243 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 7244
bogdanm 89:552587b429a1 7245 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 89:552587b429a1 7246 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7247 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7248 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7249 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7250
bogdanm 89:552587b429a1 7251 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
bogdanm 89:552587b429a1 7252 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
bogdanm 89:552587b429a1 7253
bogdanm 89:552587b429a1 7254 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
bogdanm 89:552587b429a1 7255 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
bogdanm 89:552587b429a1 7256
bogdanm 89:552587b429a1 7257 /******************** Bit definition for OTG register ********************/
bogdanm 89:552587b429a1 7258 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
bogdanm 89:552587b429a1 7259 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
bogdanm 89:552587b429a1 7260 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
bogdanm 89:552587b429a1 7261 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
bogdanm 89:552587b429a1 7262
bogdanm 89:552587b429a1 7263 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
bogdanm 89:552587b429a1 7264 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
bogdanm 89:552587b429a1 7265
bogdanm 89:552587b429a1 7266 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
bogdanm 89:552587b429a1 7267 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
bogdanm 89:552587b429a1 7268
bogdanm 89:552587b429a1 7269 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
bogdanm 89:552587b429a1 7270 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7271 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7272 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7273 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7274 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7275 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7276 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7277 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 89:552587b429a1 7278
bogdanm 89:552587b429a1 7279 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
bogdanm 89:552587b429a1 7280 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7281 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7282 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7283 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7284 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7285 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7286 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7287
bogdanm 89:552587b429a1 7288 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
bogdanm 89:552587b429a1 7289 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
bogdanm 89:552587b429a1 7290 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
bogdanm 89:552587b429a1 7291
bogdanm 89:552587b429a1 7292 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
bogdanm 89:552587b429a1 7293 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 89:552587b429a1 7294 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 89:552587b429a1 7295 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
bogdanm 89:552587b429a1 7296 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
bogdanm 89:552587b429a1 7297 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
bogdanm 89:552587b429a1 7298 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
bogdanm 89:552587b429a1 7299 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
bogdanm 89:552587b429a1 7300 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
bogdanm 89:552587b429a1 7301 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
bogdanm 89:552587b429a1 7302 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
bogdanm 89:552587b429a1 7303
bogdanm 89:552587b429a1 7304 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
bogdanm 89:552587b429a1 7305 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7306 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7307 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7308 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7309 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7310 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7311 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7312 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
bogdanm 89:552587b429a1 7313 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
bogdanm 89:552587b429a1 7314 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
bogdanm 89:552587b429a1 7315
bogdanm 89:552587b429a1 7316 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
bogdanm 89:552587b429a1 7317 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
bogdanm 89:552587b429a1 7318
bogdanm 89:552587b429a1 7319 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
bogdanm 89:552587b429a1 7320 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
bogdanm 89:552587b429a1 7321 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
bogdanm 89:552587b429a1 7322
bogdanm 89:552587b429a1 7323 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
bogdanm 89:552587b429a1 7324 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
bogdanm 89:552587b429a1 7325 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
bogdanm 89:552587b429a1 7326 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
bogdanm 89:552587b429a1 7327 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
bogdanm 89:552587b429a1 7328 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
bogdanm 89:552587b429a1 7329 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
bogdanm 89:552587b429a1 7330
bogdanm 89:552587b429a1 7331 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
bogdanm 89:552587b429a1 7332 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
bogdanm 89:552587b429a1 7333 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
bogdanm 89:552587b429a1 7334
bogdanm 89:552587b429a1 7335 /******************** Bit definition forUSB_OTG_CID register ********************/
bogdanm 89:552587b429a1 7336 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
bogdanm 89:552587b429a1 7337
bogdanm 89:552587b429a1 7338 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
bogdanm 89:552587b429a1 7339 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 89:552587b429a1 7340 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 89:552587b429a1 7341 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 89:552587b429a1 7342 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 89:552587b429a1 7343 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 89:552587b429a1 7344 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 89:552587b429a1 7345 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 89:552587b429a1 7346 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 89:552587b429a1 7347 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 89:552587b429a1 7348
bogdanm 89:552587b429a1 7349 /******************** Bit definition forUSB_OTG_HPRT register ********************/
bogdanm 89:552587b429a1 7350 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
bogdanm 89:552587b429a1 7351 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
bogdanm 89:552587b429a1 7352 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
bogdanm 89:552587b429a1 7353 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
bogdanm 89:552587b429a1 7354 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
bogdanm 89:552587b429a1 7355 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
bogdanm 89:552587b429a1 7356 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
bogdanm 89:552587b429a1 7357 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
bogdanm 89:552587b429a1 7358 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
bogdanm 89:552587b429a1 7359
bogdanm 89:552587b429a1 7360 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
bogdanm 89:552587b429a1 7361 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 89:552587b429a1 7362 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 89:552587b429a1 7363 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
bogdanm 89:552587b429a1 7364
bogdanm 89:552587b429a1 7365 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
bogdanm 89:552587b429a1 7366 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7367 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7368 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7369 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7370
bogdanm 89:552587b429a1 7371 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
bogdanm 89:552587b429a1 7372 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7373 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7374
bogdanm 89:552587b429a1 7375 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
bogdanm 89:552587b429a1 7376 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 89:552587b429a1 7377 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 89:552587b429a1 7378 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
bogdanm 89:552587b429a1 7379 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 89:552587b429a1 7380 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 89:552587b429a1 7381 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 89:552587b429a1 7382 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 89:552587b429a1 7383 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 89:552587b429a1 7384 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
bogdanm 89:552587b429a1 7385 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 89:552587b429a1 7386 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
bogdanm 89:552587b429a1 7387
bogdanm 89:552587b429a1 7388 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
bogdanm 89:552587b429a1 7389 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
bogdanm 89:552587b429a1 7390 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
bogdanm 89:552587b429a1 7391
bogdanm 89:552587b429a1 7392 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
bogdanm 89:552587b429a1 7393 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 89:552587b429a1 7394 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 89:552587b429a1 7395 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
bogdanm 89:552587b429a1 7396 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 89:552587b429a1 7397
bogdanm 89:552587b429a1 7398 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 89:552587b429a1 7399 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7400 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7401 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 89:552587b429a1 7402
bogdanm 89:552587b429a1 7403 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
bogdanm 89:552587b429a1 7404 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7405 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7406 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7407 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7408 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 89:552587b429a1 7409 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 89:552587b429a1 7410 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 89:552587b429a1 7411 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 89:552587b429a1 7412 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 89:552587b429a1 7413 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 89:552587b429a1 7414
bogdanm 89:552587b429a1 7415 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
bogdanm 89:552587b429a1 7416 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 89:552587b429a1 7417
bogdanm 89:552587b429a1 7418 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
bogdanm 89:552587b429a1 7419 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 89:552587b429a1 7420 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7421 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7422 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7423 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
bogdanm 89:552587b429a1 7424 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
bogdanm 89:552587b429a1 7425
bogdanm 89:552587b429a1 7426 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 89:552587b429a1 7427 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7428 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7429
bogdanm 89:552587b429a1 7430 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
bogdanm 89:552587b429a1 7431 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7432 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7433
bogdanm 89:552587b429a1 7434 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
bogdanm 89:552587b429a1 7435 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7436 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7437 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 89:552587b429a1 7438 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 89:552587b429a1 7439 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
bogdanm 89:552587b429a1 7440 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7441 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7442 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
bogdanm 89:552587b429a1 7443 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
bogdanm 89:552587b429a1 7444 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
bogdanm 89:552587b429a1 7445
bogdanm 89:552587b429a1 7446 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
bogdanm 89:552587b429a1 7447
bogdanm 89:552587b429a1 7448 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
bogdanm 89:552587b429a1 7449 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 89:552587b429a1 7450 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 89:552587b429a1 7451 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 89:552587b429a1 7452 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 89:552587b429a1 7453 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 89:552587b429a1 7454 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 89:552587b429a1 7455 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 89:552587b429a1 7456
bogdanm 89:552587b429a1 7457 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
bogdanm 89:552587b429a1 7458 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
bogdanm 89:552587b429a1 7459 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
bogdanm 89:552587b429a1 7460 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
bogdanm 89:552587b429a1 7461 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
bogdanm 89:552587b429a1 7462 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
bogdanm 89:552587b429a1 7463 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
bogdanm 89:552587b429a1 7464 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
bogdanm 89:552587b429a1 7465
bogdanm 89:552587b429a1 7466 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
bogdanm 89:552587b429a1 7467 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7468 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7469 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
bogdanm 89:552587b429a1 7470 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
bogdanm 89:552587b429a1 7471
bogdanm 89:552587b429a1 7472 /******************** Bit definition forUSB_OTG_HCINT register ********************/
bogdanm 89:552587b429a1 7473 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
bogdanm 89:552587b429a1 7474 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
bogdanm 89:552587b429a1 7475 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 89:552587b429a1 7476 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
bogdanm 89:552587b429a1 7477 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
bogdanm 89:552587b429a1 7478 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
bogdanm 89:552587b429a1 7479 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
bogdanm 89:552587b429a1 7480 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
bogdanm 89:552587b429a1 7481 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
bogdanm 89:552587b429a1 7482 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
bogdanm 89:552587b429a1 7483 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
bogdanm 89:552587b429a1 7484
bogdanm 89:552587b429a1 7485 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
bogdanm 89:552587b429a1 7486 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 89:552587b429a1 7487 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 89:552587b429a1 7488 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
bogdanm 89:552587b429a1 7489 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
bogdanm 89:552587b429a1 7490 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
bogdanm 89:552587b429a1 7491 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
bogdanm 89:552587b429a1 7492 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
bogdanm 89:552587b429a1 7493 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
bogdanm 89:552587b429a1 7494 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
bogdanm 89:552587b429a1 7495 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
bogdanm 89:552587b429a1 7496 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
bogdanm 89:552587b429a1 7497
bogdanm 89:552587b429a1 7498 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
bogdanm 89:552587b429a1 7499 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
bogdanm 89:552587b429a1 7500 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
bogdanm 89:552587b429a1 7501 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 89:552587b429a1 7502 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
bogdanm 89:552587b429a1 7503 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
bogdanm 89:552587b429a1 7504 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
bogdanm 89:552587b429a1 7505 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
bogdanm 89:552587b429a1 7506 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
bogdanm 89:552587b429a1 7507 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
bogdanm 89:552587b429a1 7508 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
bogdanm 89:552587b429a1 7509 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
bogdanm 89:552587b429a1 7510
bogdanm 89:552587b429a1 7511 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
bogdanm 89:552587b429a1 7512
bogdanm 89:552587b429a1 7513 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 89:552587b429a1 7514 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 89:552587b429a1 7515 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
bogdanm 89:552587b429a1 7516 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
bogdanm 89:552587b429a1 7517 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 89:552587b429a1 7518 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 89:552587b429a1 7519 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
bogdanm 89:552587b429a1 7520 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
bogdanm 89:552587b429a1 7521 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7522 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7523
bogdanm 89:552587b429a1 7524 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
bogdanm 89:552587b429a1 7525 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 89:552587b429a1 7526
bogdanm 89:552587b429a1 7527 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
bogdanm 89:552587b429a1 7528 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 89:552587b429a1 7529
bogdanm 89:552587b429a1 7530 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
bogdanm 89:552587b429a1 7531 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
bogdanm 89:552587b429a1 7532
bogdanm 89:552587b429a1 7533 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
bogdanm 89:552587b429a1 7534 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
bogdanm 89:552587b429a1 7535 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
bogdanm 89:552587b429a1 7536
bogdanm 89:552587b429a1 7537 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
bogdanm 89:552587b429a1 7538
bogdanm 89:552587b429a1 7539 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
bogdanm 89:552587b429a1 7540 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 89:552587b429a1 7541 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 89:552587b429a1 7542 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 89:552587b429a1 7543 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 89:552587b429a1 7544 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 89:552587b429a1 7545 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7546 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7547 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
bogdanm 89:552587b429a1 7548 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 89:552587b429a1 7549 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 89:552587b429a1 7550 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 89:552587b429a1 7551 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 89:552587b429a1 7552 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 89:552587b429a1 7553
bogdanm 89:552587b429a1 7554 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
bogdanm 89:552587b429a1 7555 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 89:552587b429a1 7556 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 89:552587b429a1 7557 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
bogdanm 89:552587b429a1 7558 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
bogdanm 89:552587b429a1 7559 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
bogdanm 89:552587b429a1 7560 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
bogdanm 89:552587b429a1 7561
bogdanm 89:552587b429a1 7562 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
bogdanm 89:552587b429a1 7563
bogdanm 89:552587b429a1 7564 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 89:552587b429a1 7565 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 89:552587b429a1 7566
bogdanm 89:552587b429a1 7567 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
bogdanm 89:552587b429a1 7568 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 89:552587b429a1 7569 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 89:552587b429a1 7570
bogdanm 89:552587b429a1 7571 /******************** Bit definition for PCGCCTL register ********************/
bogdanm 89:552587b429a1 7572 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
bogdanm 89:552587b429a1 7573 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 89:552587b429a1 7574 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 89:552587b429a1 7575
bogdanm 89:552587b429a1 7576 /**
bogdanm 89:552587b429a1 7577 * @}
bogdanm 89:552587b429a1 7578 */
bogdanm 89:552587b429a1 7579
bogdanm 89:552587b429a1 7580 /**
bogdanm 89:552587b429a1 7581 * @}
bogdanm 89:552587b429a1 7582 */
bogdanm 89:552587b429a1 7583
bogdanm 89:552587b429a1 7584 /** @addtogroup Exported_macros
bogdanm 89:552587b429a1 7585 * @{
bogdanm 89:552587b429a1 7586 */
bogdanm 89:552587b429a1 7587
bogdanm 89:552587b429a1 7588 /******************************* ADC Instances ********************************/
bogdanm 89:552587b429a1 7589 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
bogdanm 89:552587b429a1 7590 ((INSTANCE) == ADC2) || \
bogdanm 89:552587b429a1 7591 ((INSTANCE) == ADC3))
bogdanm 89:552587b429a1 7592
bogdanm 89:552587b429a1 7593 /******************************* CAN Instances ********************************/
bogdanm 89:552587b429a1 7594 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
bogdanm 89:552587b429a1 7595 ((INSTANCE) == CAN2))
bogdanm 89:552587b429a1 7596
bogdanm 89:552587b429a1 7597 /******************************* CRC Instances ********************************/
bogdanm 89:552587b429a1 7598 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 89:552587b429a1 7599
bogdanm 89:552587b429a1 7600 /******************************* DAC Instances ********************************/
bogdanm 89:552587b429a1 7601 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 89:552587b429a1 7602
bogdanm 89:552587b429a1 7603 /******************************* DCMI Instances *******************************/
bogdanm 89:552587b429a1 7604 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
bogdanm 89:552587b429a1 7605
bogdanm 89:552587b429a1 7606 /******************************** DMA Instances *******************************/
bogdanm 89:552587b429a1 7607 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 89:552587b429a1 7608 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 89:552587b429a1 7609 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 89:552587b429a1 7610 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 89:552587b429a1 7611 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 89:552587b429a1 7612 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 89:552587b429a1 7613 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 89:552587b429a1 7614 ((INSTANCE) == DMA1_Stream7) || \
bogdanm 89:552587b429a1 7615 ((INSTANCE) == DMA2_Stream0) || \
bogdanm 89:552587b429a1 7616 ((INSTANCE) == DMA2_Stream1) || \
bogdanm 89:552587b429a1 7617 ((INSTANCE) == DMA2_Stream2) || \
bogdanm 89:552587b429a1 7618 ((INSTANCE) == DMA2_Stream3) || \
bogdanm 89:552587b429a1 7619 ((INSTANCE) == DMA2_Stream4) || \
bogdanm 89:552587b429a1 7620 ((INSTANCE) == DMA2_Stream5) || \
bogdanm 89:552587b429a1 7621 ((INSTANCE) == DMA2_Stream6) || \
bogdanm 89:552587b429a1 7622 ((INSTANCE) == DMA2_Stream7))
bogdanm 89:552587b429a1 7623
bogdanm 89:552587b429a1 7624 /******************************* GPIO Instances *******************************/
bogdanm 89:552587b429a1 7625 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 89:552587b429a1 7626 ((INSTANCE) == GPIOB) || \
bogdanm 89:552587b429a1 7627 ((INSTANCE) == GPIOC) || \
bogdanm 89:552587b429a1 7628 ((INSTANCE) == GPIOD) || \
bogdanm 89:552587b429a1 7629 ((INSTANCE) == GPIOE) || \
bogdanm 89:552587b429a1 7630 ((INSTANCE) == GPIOF) || \
bogdanm 89:552587b429a1 7631 ((INSTANCE) == GPIOG) || \
bogdanm 89:552587b429a1 7632 ((INSTANCE) == GPIOH) || \
bogdanm 89:552587b429a1 7633 ((INSTANCE) == GPIOI))
bogdanm 89:552587b429a1 7634
bogdanm 89:552587b429a1 7635 /******************************** I2C Instances *******************************/
bogdanm 89:552587b429a1 7636 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 89:552587b429a1 7637 ((INSTANCE) == I2C2) || \
bogdanm 89:552587b429a1 7638 ((INSTANCE) == I2C3))
bogdanm 89:552587b429a1 7639
bogdanm 89:552587b429a1 7640 /******************************** I2S Instances *******************************/
bogdanm 89:552587b429a1 7641 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
bogdanm 89:552587b429a1 7642 ((INSTANCE) == SPI3))
bogdanm 89:552587b429a1 7643
bogdanm 89:552587b429a1 7644 /*************************** I2S Extended Instances ***************************/
bogdanm 89:552587b429a1 7645 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
bogdanm 89:552587b429a1 7646 ((INSTANCE) == SPI3) || \
bogdanm 89:552587b429a1 7647 ((INSTANCE) == I2S2ext) || \
bogdanm 89:552587b429a1 7648 ((INSTANCE) == I2S3ext))
bogdanm 89:552587b429a1 7649
bogdanm 89:552587b429a1 7650 /******************************* RNG Instances ********************************/
bogdanm 89:552587b429a1 7651 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
bogdanm 89:552587b429a1 7652
bogdanm 89:552587b429a1 7653 /****************************** RTC Instances *********************************/
bogdanm 89:552587b429a1 7654 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 89:552587b429a1 7655
bogdanm 89:552587b429a1 7656 /******************************** SPI Instances *******************************/
bogdanm 89:552587b429a1 7657 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 89:552587b429a1 7658 ((INSTANCE) == SPI2) || \
bogdanm 89:552587b429a1 7659 ((INSTANCE) == SPI3))
bogdanm 89:552587b429a1 7660
bogdanm 89:552587b429a1 7661 /*************************** SPI Extended Instances ***************************/
bogdanm 89:552587b429a1 7662 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 89:552587b429a1 7663 ((INSTANCE) == SPI2) || \
bogdanm 89:552587b429a1 7664 ((INSTANCE) == SPI3) || \
bogdanm 89:552587b429a1 7665 ((INSTANCE) == I2S2ext) || \
bogdanm 89:552587b429a1 7666 ((INSTANCE) == I2S3ext))
bogdanm 89:552587b429a1 7667
bogdanm 89:552587b429a1 7668 /****************** TIM Instances : All supported instances *******************/
bogdanm 89:552587b429a1 7669 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7670 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7671 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7672 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7673 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7674 ((INSTANCE) == TIM6) || \
bogdanm 89:552587b429a1 7675 ((INSTANCE) == TIM7) || \
bogdanm 89:552587b429a1 7676 ((INSTANCE) == TIM8) || \
bogdanm 89:552587b429a1 7677 ((INSTANCE) == TIM9) || \
bogdanm 89:552587b429a1 7678 ((INSTANCE) == TIM10) || \
bogdanm 89:552587b429a1 7679 ((INSTANCE) == TIM11) || \
bogdanm 89:552587b429a1 7680 ((INSTANCE) == TIM12) || \
bogdanm 89:552587b429a1 7681 ((INSTANCE) == TIM13) || \
bogdanm 89:552587b429a1 7682 ((INSTANCE) == TIM14))
bogdanm 89:552587b429a1 7683
bogdanm 89:552587b429a1 7684 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 89:552587b429a1 7685 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7686 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7687 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7688 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7689 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7690 ((INSTANCE) == TIM8) || \
bogdanm 89:552587b429a1 7691 ((INSTANCE) == TIM9) || \
bogdanm 89:552587b429a1 7692 ((INSTANCE) == TIM10) || \
bogdanm 89:552587b429a1 7693 ((INSTANCE) == TIM11) || \
bogdanm 89:552587b429a1 7694 ((INSTANCE) == TIM12) || \
bogdanm 89:552587b429a1 7695 ((INSTANCE) == TIM13) || \
bogdanm 89:552587b429a1 7696 ((INSTANCE) == TIM14))
bogdanm 89:552587b429a1 7697
bogdanm 89:552587b429a1 7698 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 89:552587b429a1 7699 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7700 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7701 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7702 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7703 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7704 ((INSTANCE) == TIM8) || \
bogdanm 89:552587b429a1 7705 ((INSTANCE) == TIM9) || \
bogdanm 89:552587b429a1 7706 ((INSTANCE) == TIM12))
bogdanm 89:552587b429a1 7707
bogdanm 89:552587b429a1 7708 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 89:552587b429a1 7709 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7710 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7711 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7712 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7713 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7714 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7715
bogdanm 89:552587b429a1 7716 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 89:552587b429a1 7717 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7718 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7719 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7720 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7721 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7722 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7723
bogdanm 89:552587b429a1 7724 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 89:552587b429a1 7725 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7726 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7727
bogdanm 89:552587b429a1 7728 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 89:552587b429a1 7729 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7730 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7731 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7732 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7733 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7734 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7735
bogdanm 89:552587b429a1 7736 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 89:552587b429a1 7737 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7738 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7739 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7740 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7741 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7742 ((INSTANCE) == TIM6) || \
bogdanm 89:552587b429a1 7743 ((INSTANCE) == TIM7) || \
bogdanm 89:552587b429a1 7744 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7745
bogdanm 89:552587b429a1 7746 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 89:552587b429a1 7747 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7748 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7749 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7750 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7751 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7752 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7753
bogdanm 89:552587b429a1 7754 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 89:552587b429a1 7755 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7756 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7757 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7758 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7759 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7760 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7761
bogdanm 89:552587b429a1 7762 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 89:552587b429a1 7763 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7764 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7765 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7766 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7767 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7768 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7769
bogdanm 89:552587b429a1 7770 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 89:552587b429a1 7771 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7772 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7773 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7774 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7775 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7776 ((INSTANCE) == TIM6) || \
bogdanm 89:552587b429a1 7777 ((INSTANCE) == TIM7) || \
bogdanm 89:552587b429a1 7778 ((INSTANCE) == TIM8) || \
bogdanm 89:552587b429a1 7779 ((INSTANCE) == TIM9) || \
bogdanm 89:552587b429a1 7780 ((INSTANCE) == TIM12))
bogdanm 89:552587b429a1 7781
bogdanm 89:552587b429a1 7782 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 89:552587b429a1 7783 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7784 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7785 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7786 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7787 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7788 ((INSTANCE) == TIM8) || \
bogdanm 89:552587b429a1 7789 ((INSTANCE) == TIM9) || \
bogdanm 89:552587b429a1 7790 ((INSTANCE) == TIM12))
bogdanm 89:552587b429a1 7791
bogdanm 89:552587b429a1 7792 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 89:552587b429a1 7793 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7794 ((INSTANCE) == TIM5))
bogdanm 89:552587b429a1 7795
bogdanm 89:552587b429a1 7796 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 89:552587b429a1 7797 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 89:552587b429a1 7798 ((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7799 ((INSTANCE) == TIM3) || \
bogdanm 89:552587b429a1 7800 ((INSTANCE) == TIM4) || \
bogdanm 89:552587b429a1 7801 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7802 ((INSTANCE) == TIM8))
bogdanm 89:552587b429a1 7803
bogdanm 89:552587b429a1 7804 /****************** TIM Instances : remapping capability **********************/
bogdanm 89:552587b429a1 7805 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 89:552587b429a1 7806 ((INSTANCE) == TIM5) || \
bogdanm 89:552587b429a1 7807 ((INSTANCE) == TIM11))
bogdanm 89:552587b429a1 7808
bogdanm 89:552587b429a1 7809 /******************* TIM Instances : output(s) available **********************/
bogdanm 89:552587b429a1 7810 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 89:552587b429a1 7811 ((((INSTANCE) == TIM1) && \
bogdanm 89:552587b429a1 7812 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7813 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7814 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7815 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7816 || \
bogdanm 89:552587b429a1 7817 (((INSTANCE) == TIM2) && \
bogdanm 89:552587b429a1 7818 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7819 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7820 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7821 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7822 || \
bogdanm 89:552587b429a1 7823 (((INSTANCE) == TIM3) && \
bogdanm 89:552587b429a1 7824 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7825 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7826 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7827 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7828 || \
bogdanm 89:552587b429a1 7829 (((INSTANCE) == TIM4) && \
bogdanm 89:552587b429a1 7830 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7831 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7832 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7833 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7834 || \
bogdanm 89:552587b429a1 7835 (((INSTANCE) == TIM5) && \
bogdanm 89:552587b429a1 7836 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7837 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7838 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7839 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7840 || \
bogdanm 89:552587b429a1 7841 (((INSTANCE) == TIM8) && \
bogdanm 89:552587b429a1 7842 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7843 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7844 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 7845 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 89:552587b429a1 7846 || \
bogdanm 89:552587b429a1 7847 (((INSTANCE) == TIM9) && \
bogdanm 89:552587b429a1 7848 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7849 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 89:552587b429a1 7850 || \
bogdanm 89:552587b429a1 7851 (((INSTANCE) == TIM10) && \
bogdanm 89:552587b429a1 7852 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 89:552587b429a1 7853 || \
bogdanm 89:552587b429a1 7854 (((INSTANCE) == TIM11) && \
bogdanm 89:552587b429a1 7855 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 89:552587b429a1 7856 || \
bogdanm 89:552587b429a1 7857 (((INSTANCE) == TIM12) && \
bogdanm 89:552587b429a1 7858 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7859 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 89:552587b429a1 7860 || \
bogdanm 89:552587b429a1 7861 (((INSTANCE) == TIM13) && \
bogdanm 89:552587b429a1 7862 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 89:552587b429a1 7863 || \
bogdanm 89:552587b429a1 7864 (((INSTANCE) == TIM14) && \
bogdanm 89:552587b429a1 7865 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 89:552587b429a1 7866
bogdanm 89:552587b429a1 7867 /************ TIM Instances : complementary output(s) available ***************/
bogdanm 89:552587b429a1 7868 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 89:552587b429a1 7869 ((((INSTANCE) == TIM1) && \
bogdanm 89:552587b429a1 7870 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7871 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7872 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 89:552587b429a1 7873 || \
bogdanm 89:552587b429a1 7874 (((INSTANCE) == TIM8) && \
bogdanm 89:552587b429a1 7875 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 7876 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 7877 ((CHANNEL) == TIM_CHANNEL_3))))
bogdanm 89:552587b429a1 7878
bogdanm 89:552587b429a1 7879 /******************** USART Instances : Synchronous mode **********************/
bogdanm 89:552587b429a1 7880 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 89:552587b429a1 7881 ((INSTANCE) == USART2) || \
bogdanm 89:552587b429a1 7882 ((INSTANCE) == USART3) || \
bogdanm 89:552587b429a1 7883 ((INSTANCE) == USART6))
bogdanm 89:552587b429a1 7884
bogdanm 89:552587b429a1 7885 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 89:552587b429a1 7886 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 89:552587b429a1 7887 ((INSTANCE) == USART2) || \
bogdanm 89:552587b429a1 7888 ((INSTANCE) == USART3) || \
bogdanm 89:552587b429a1 7889 ((INSTANCE) == UART4) || \
bogdanm 89:552587b429a1 7890 ((INSTANCE) == UART5) || \
bogdanm 89:552587b429a1 7891 ((INSTANCE) == USART6))
bogdanm 89:552587b429a1 7892
bogdanm 89:552587b429a1 7893 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 89:552587b429a1 7894 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 89:552587b429a1 7895 ((INSTANCE) == USART2) || \
bogdanm 89:552587b429a1 7896 ((INSTANCE) == USART3) || \
bogdanm 89:552587b429a1 7897 ((INSTANCE) == USART6))
bogdanm 89:552587b429a1 7898
bogdanm 89:552587b429a1 7899 /********************* UART Instances : Smard card mode ***********************/
bogdanm 89:552587b429a1 7900 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 89:552587b429a1 7901 ((INSTANCE) == USART2) || \
bogdanm 89:552587b429a1 7902 ((INSTANCE) == USART3) || \
bogdanm 89:552587b429a1 7903 ((INSTANCE) == USART6))
bogdanm 89:552587b429a1 7904
bogdanm 89:552587b429a1 7905 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 89:552587b429a1 7906 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 89:552587b429a1 7907 ((INSTANCE) == USART2) || \
bogdanm 89:552587b429a1 7908 ((INSTANCE) == USART3) || \
bogdanm 89:552587b429a1 7909 ((INSTANCE) == UART4) || \
bogdanm 89:552587b429a1 7910 ((INSTANCE) == UART5) || \
bogdanm 89:552587b429a1 7911 ((INSTANCE) == USART6))
bogdanm 89:552587b429a1 7912
bogdanm 89:552587b429a1 7913 /****************************** IWDG Instances ********************************/
bogdanm 89:552587b429a1 7914 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 89:552587b429a1 7915
bogdanm 89:552587b429a1 7916 /****************************** WWDG Instances ********************************/
bogdanm 89:552587b429a1 7917 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 89:552587b429a1 7918
bogdanm 89:552587b429a1 7919 /******************************************************************************/
bogdanm 89:552587b429a1 7920 /* For a painless codes migration between the STM32F4xx device product */
bogdanm 89:552587b429a1 7921 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 89:552587b429a1 7922 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 89:552587b429a1 7923 /* No need to update developed interrupt code when moving across */
bogdanm 89:552587b429a1 7924 /* product lines within the same STM32F4 Family */
bogdanm 89:552587b429a1 7925 /******************************************************************************/
bogdanm 89:552587b429a1 7926
bogdanm 89:552587b429a1 7927 /* Aliases for __IRQn */
bogdanm 89:552587b429a1 7928 #define FMC_IRQn FSMC_IRQn
bogdanm 89:552587b429a1 7929
bogdanm 89:552587b429a1 7930 /* Aliases for __IRQHandler */
bogdanm 89:552587b429a1 7931 #define FMC_IRQHandler FSMC_IRQHandler
bogdanm 89:552587b429a1 7932
bogdanm 89:552587b429a1 7933 /**
bogdanm 89:552587b429a1 7934 * @}
bogdanm 89:552587b429a1 7935 */
bogdanm 89:552587b429a1 7936
bogdanm 89:552587b429a1 7937 /**
bogdanm 89:552587b429a1 7938 * @}
bogdanm 89:552587b429a1 7939 */
bogdanm 89:552587b429a1 7940
bogdanm 89:552587b429a1 7941 /**
bogdanm 89:552587b429a1 7942 * @}
bogdanm 89:552587b429a1 7943 */
bogdanm 89:552587b429a1 7944
bogdanm 89:552587b429a1 7945 #ifdef __cplusplus
bogdanm 89:552587b429a1 7946 }
bogdanm 89:552587b429a1 7947 #endif /* __cplusplus */
bogdanm 89:552587b429a1 7948
bogdanm 89:552587b429a1 7949 #endif /* __STM32F407xx_H */
bogdanm 89:552587b429a1 7950
bogdanm 89:552587b429a1 7951
bogdanm 89:552587b429a1 7952
bogdanm 89:552587b429a1 7953 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/