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TARGET_RZ_A1H/ceu_iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Nov 27 13:33:22 2014 +0000
- Revision:
- 92:4fc01daae5a5
Release 92 of the mbed libray
Main changes:
- nRF51822: fixed pin assignment issues
- ST targets moving to the STM32Cube driver
- LPC1439: fixed serial interrupt issue
- first Cortex-A platform supported in mbed (RZ_A1H)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 92:4fc01daae5a5 | 1 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 2 | * DISCLAIMER |
bogdanm | 92:4fc01daae5a5 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
bogdanm | 92:4fc01daae5a5 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
bogdanm | 92:4fc01daae5a5 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
bogdanm | 92:4fc01daae5a5 | 6 | * all applicable laws, including copyright laws. |
bogdanm | 92:4fc01daae5a5 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
bogdanm | 92:4fc01daae5a5 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
bogdanm | 92:4fc01daae5a5 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
bogdanm | 92:4fc01daae5a5 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
bogdanm | 92:4fc01daae5a5 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
bogdanm | 92:4fc01daae5a5 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
bogdanm | 92:4fc01daae5a5 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
bogdanm | 92:4fc01daae5a5 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
bogdanm | 92:4fc01daae5a5 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
bogdanm | 92:4fc01daae5a5 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
bogdanm | 92:4fc01daae5a5 | 17 | * and to discontinue the availability of this software. By using this software, |
bogdanm | 92:4fc01daae5a5 | 18 | * you agree to the additional terms and conditions found by accessing the |
bogdanm | 92:4fc01daae5a5 | 19 | * following link: |
bogdanm | 92:4fc01daae5a5 | 20 | * http://www.renesas.com/disclaimer* |
bogdanm | 92:4fc01daae5a5 | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
bogdanm | 92:4fc01daae5a5 | 22 | *******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 23 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 24 | * File Name : ceu_iodefine.h |
bogdanm | 92:4fc01daae5a5 | 25 | * $Rev: $ |
bogdanm | 92:4fc01daae5a5 | 26 | * $Date:: $ |
bogdanm | 92:4fc01daae5a5 | 27 | * Description : Definition of I/O Register (V1.00a) |
bogdanm | 92:4fc01daae5a5 | 28 | ******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 29 | #ifndef CEU_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 30 | #define CEU_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 31 | /* ->SEC M1.10.1 : Not magic number */ |
bogdanm | 92:4fc01daae5a5 | 32 | |
bogdanm | 92:4fc01daae5a5 | 33 | struct st_ceu |
bogdanm | 92:4fc01daae5a5 | 34 | { /* CEU */ |
bogdanm | 92:4fc01daae5a5 | 35 | /* start of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 36 | volatile uint32_t CAPSR; /* CAPSR */ |
bogdanm | 92:4fc01daae5a5 | 37 | volatile uint32_t CAPCR; /* CAPCR */ |
bogdanm | 92:4fc01daae5a5 | 38 | volatile uint32_t CAMCR; /* CAMCR */ |
bogdanm | 92:4fc01daae5a5 | 39 | volatile uint32_t CMCYR; /* CMCYR */ |
bogdanm | 92:4fc01daae5a5 | 40 | volatile uint32_t CAMOR_A; /* CAMOR_A */ |
bogdanm | 92:4fc01daae5a5 | 41 | volatile uint32_t CAPWR_A; /* CAPWR_A */ |
bogdanm | 92:4fc01daae5a5 | 42 | volatile uint32_t CAIFR; /* CAIFR */ |
bogdanm | 92:4fc01daae5a5 | 43 | volatile uint8_t dummy305[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 44 | volatile uint32_t CRCNTR; /* CRCNTR */ |
bogdanm | 92:4fc01daae5a5 | 45 | volatile uint32_t CRCMPR; /* CRCMPR */ |
bogdanm | 92:4fc01daae5a5 | 46 | volatile uint32_t CFLCR_A; /* CFLCR_A */ |
bogdanm | 92:4fc01daae5a5 | 47 | volatile uint32_t CFSZR_A; /* CFSZR_A */ |
bogdanm | 92:4fc01daae5a5 | 48 | volatile uint32_t CDWDR_A; /* CDWDR_A */ |
bogdanm | 92:4fc01daae5a5 | 49 | volatile uint32_t CDAYR_A; /* CDAYR_A */ |
bogdanm | 92:4fc01daae5a5 | 50 | volatile uint32_t CDACR_A; /* CDACR_A */ |
bogdanm | 92:4fc01daae5a5 | 51 | volatile uint32_t CDBYR_A; /* CDBYR_A */ |
bogdanm | 92:4fc01daae5a5 | 52 | volatile uint32_t CDBCR_A; /* CDBCR_A */ |
bogdanm | 92:4fc01daae5a5 | 53 | volatile uint32_t CBDSR_A; /* CBDSR_A */ |
bogdanm | 92:4fc01daae5a5 | 54 | volatile uint8_t dummy306[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 55 | volatile uint32_t CFWCR; /* CFWCR */ |
bogdanm | 92:4fc01daae5a5 | 56 | volatile uint32_t CLFCR_A; /* CLFCR_A */ |
bogdanm | 92:4fc01daae5a5 | 57 | volatile uint32_t CDOCR_A; /* CDOCR_A */ |
bogdanm | 92:4fc01daae5a5 | 58 | volatile uint8_t dummy307[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 59 | volatile uint32_t CEIER; /* CEIER */ |
bogdanm | 92:4fc01daae5a5 | 60 | volatile uint32_t CETCR; /* CETCR */ |
bogdanm | 92:4fc01daae5a5 | 61 | volatile uint8_t dummy308[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 62 | volatile uint32_t CSTSR; /* CSTSR */ |
bogdanm | 92:4fc01daae5a5 | 63 | volatile uint8_t dummy309[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 64 | volatile uint32_t CDSSR; /* CDSSR */ |
bogdanm | 92:4fc01daae5a5 | 65 | volatile uint8_t dummy310[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 66 | volatile uint32_t CDAYR2_A; /* CDAYR2_A */ |
bogdanm | 92:4fc01daae5a5 | 67 | volatile uint32_t CDACR2_A; /* CDACR2_A */ |
bogdanm | 92:4fc01daae5a5 | 68 | volatile uint32_t CDBYR2_A; /* CDBYR2_A */ |
bogdanm | 92:4fc01daae5a5 | 69 | volatile uint32_t CDBCR2_A; /* CDBCR2_A */ |
bogdanm | 92:4fc01daae5a5 | 70 | /* end of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 71 | volatile uint8_t dummy3110[3936]; /* */ |
bogdanm | 92:4fc01daae5a5 | 72 | /* start of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 73 | volatile uint8_t dummy3111[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 74 | volatile uint8_t dummy3112[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 75 | volatile uint8_t dummy3113[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 76 | volatile uint8_t dummy3114[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 77 | volatile uint32_t CAMOR_B; /* CAMOR_B */ |
bogdanm | 92:4fc01daae5a5 | 78 | volatile uint32_t CAPWR_B; /* CAPWR_B */ |
bogdanm | 92:4fc01daae5a5 | 79 | volatile uint8_t dummy3120[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 80 | volatile uint8_t dummy3121[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 81 | volatile uint8_t dummy3122[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 82 | volatile uint8_t dummy3123[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 83 | volatile uint32_t CFLCR_B; /* CFLCR_B */ |
bogdanm | 92:4fc01daae5a5 | 84 | volatile uint32_t CFSZR_B; /* CFSZR_B */ |
bogdanm | 92:4fc01daae5a5 | 85 | volatile uint32_t CDWDR_B; /* CDWDR_B */ |
bogdanm | 92:4fc01daae5a5 | 86 | volatile uint32_t CDAYR_B; /* CDAYR_B */ |
bogdanm | 92:4fc01daae5a5 | 87 | volatile uint32_t CDACR_B; /* CDACR_B */ |
bogdanm | 92:4fc01daae5a5 | 88 | volatile uint32_t CDBYR_B; /* CDBYR_B */ |
bogdanm | 92:4fc01daae5a5 | 89 | volatile uint32_t CDBCR_B; /* CDBCR_B */ |
bogdanm | 92:4fc01daae5a5 | 90 | volatile uint32_t CBDSR_B; /* CBDSR_B */ |
bogdanm | 92:4fc01daae5a5 | 91 | volatile uint8_t dummy3130[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 92 | volatile uint8_t dummy3131[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 93 | volatile uint32_t CLFCR_B; /* CLFCR_B */ |
bogdanm | 92:4fc01daae5a5 | 94 | volatile uint32_t CDOCR_B; /* CDOCR_B */ |
bogdanm | 92:4fc01daae5a5 | 95 | volatile uint8_t dummy3140[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 96 | volatile uint8_t dummy3141[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 97 | volatile uint8_t dummy3142[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 98 | volatile uint8_t dummy3143[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 99 | volatile uint8_t dummy3144[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 100 | volatile uint8_t dummy3145[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 101 | volatile uint8_t dummy3146[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 102 | volatile uint8_t dummy3147[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 103 | volatile uint32_t CDAYR2_B; /* CDAYR2_B */ |
bogdanm | 92:4fc01daae5a5 | 104 | volatile uint32_t CDACR2_B; /* CDACR2_B */ |
bogdanm | 92:4fc01daae5a5 | 105 | volatile uint32_t CDBYR2_B; /* CDBYR2_B */ |
bogdanm | 92:4fc01daae5a5 | 106 | volatile uint32_t CDBCR2_B; /* CDBCR2_B */ |
bogdanm | 92:4fc01daae5a5 | 107 | /* end of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 108 | volatile uint8_t dummy3150[3936]; /* */ |
bogdanm | 92:4fc01daae5a5 | 109 | /* start of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 110 | volatile uint8_t dummy3151[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 111 | volatile uint8_t dummy3152[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 112 | volatile uint8_t dummy3153[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 113 | volatile uint8_t dummy3154[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 114 | volatile uint32_t CAMOR_M; /* CAMOR_M */ |
bogdanm | 92:4fc01daae5a5 | 115 | volatile uint32_t CAPWR_M; /* CAPWR_M */ |
bogdanm | 92:4fc01daae5a5 | 116 | volatile uint8_t dummy3160[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 117 | volatile uint8_t dummy3161[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 118 | volatile uint8_t dummy3162[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 119 | volatile uint8_t dummy3163[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 120 | volatile uint32_t CFLCR_M; /* CFLCR_M */ |
bogdanm | 92:4fc01daae5a5 | 121 | volatile uint32_t CFSZR_M; /* CFSZR_M */ |
bogdanm | 92:4fc01daae5a5 | 122 | volatile uint32_t CDWDR_M; /* CDWDR_M */ |
bogdanm | 92:4fc01daae5a5 | 123 | volatile uint32_t CDAYR_M; /* CDAYR_M */ |
bogdanm | 92:4fc01daae5a5 | 124 | volatile uint32_t CDACR_M; /* CDACR_M */ |
bogdanm | 92:4fc01daae5a5 | 125 | volatile uint32_t CDBYR_M; /* CDBYR_M */ |
bogdanm | 92:4fc01daae5a5 | 126 | volatile uint32_t CDBCR_M; /* CDBCR_M */ |
bogdanm | 92:4fc01daae5a5 | 127 | volatile uint32_t CBDSR_M; /* CBDSR_M */ |
bogdanm | 92:4fc01daae5a5 | 128 | volatile uint8_t dummy3170[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 129 | volatile uint8_t dummy3171[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 130 | volatile uint32_t CLFCR_M; /* CLFCR_M */ |
bogdanm | 92:4fc01daae5a5 | 131 | volatile uint32_t CDOCR_M; /* CDOCR_M */ |
bogdanm | 92:4fc01daae5a5 | 132 | volatile uint8_t dummy3180[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 133 | volatile uint8_t dummy3181[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 134 | volatile uint8_t dummy3182[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 135 | volatile uint8_t dummy3183[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 136 | volatile uint8_t dummy3184[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 137 | volatile uint8_t dummy3185[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 138 | volatile uint8_t dummy3186[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 139 | volatile uint8_t dummy3187[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 140 | volatile uint32_t CDAYR2_M; /* CDAYR2_M */ |
bogdanm | 92:4fc01daae5a5 | 141 | volatile uint32_t CDACR2_M; /* CDACR2_M */ |
bogdanm | 92:4fc01daae5a5 | 142 | volatile uint32_t CDBYR2_M; /* CDBYR2_M */ |
bogdanm | 92:4fc01daae5a5 | 143 | volatile uint32_t CDBCR2_M; /* CDBCR2_M */ |
bogdanm | 92:4fc01daae5a5 | 144 | /* end of struct st_ceu_n */ |
bogdanm | 92:4fc01daae5a5 | 145 | }; |
bogdanm | 92:4fc01daae5a5 | 146 | |
bogdanm | 92:4fc01daae5a5 | 147 | |
bogdanm | 92:4fc01daae5a5 | 148 | struct st_ceu_n |
bogdanm | 92:4fc01daae5a5 | 149 | { |
bogdanm | 92:4fc01daae5a5 | 150 | volatile uint32_t not_common1; /* */ |
bogdanm | 92:4fc01daae5a5 | 151 | volatile uint32_t not_common2; /* */ |
bogdanm | 92:4fc01daae5a5 | 152 | volatile uint32_t not_common3; /* */ |
bogdanm | 92:4fc01daae5a5 | 153 | volatile uint32_t not_common4; /* */ |
bogdanm | 92:4fc01daae5a5 | 154 | volatile uint32_t CAMOR; /* CAMOR */ |
bogdanm | 92:4fc01daae5a5 | 155 | volatile uint32_t CAPWR; /* CAPWR */ |
bogdanm | 92:4fc01daae5a5 | 156 | volatile uint32_t not_common5; /* */ |
bogdanm | 92:4fc01daae5a5 | 157 | volatile uint8_t dummy322[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 158 | volatile uint32_t not_common6; /* */ |
bogdanm | 92:4fc01daae5a5 | 159 | volatile uint32_t not_common7; /* */ |
bogdanm | 92:4fc01daae5a5 | 160 | volatile uint32_t CFLCR; /* CFLCR */ |
bogdanm | 92:4fc01daae5a5 | 161 | volatile uint32_t CFSZR; /* CFSZR */ |
bogdanm | 92:4fc01daae5a5 | 162 | volatile uint32_t CDWDR; /* CDWDR */ |
bogdanm | 92:4fc01daae5a5 | 163 | volatile uint32_t CDAYR; /* CDAYR */ |
bogdanm | 92:4fc01daae5a5 | 164 | volatile uint32_t CDACR; /* CDACR */ |
bogdanm | 92:4fc01daae5a5 | 165 | volatile uint32_t CDBYR; /* CDBYR */ |
bogdanm | 92:4fc01daae5a5 | 166 | volatile uint32_t CDBCR; /* CDBCR */ |
bogdanm | 92:4fc01daae5a5 | 167 | volatile uint32_t CBDSR; /* CBDSR */ |
bogdanm | 92:4fc01daae5a5 | 168 | volatile uint8_t dummy323[12]; /* */ |
bogdanm | 92:4fc01daae5a5 | 169 | volatile uint32_t not_common8; /* */ |
bogdanm | 92:4fc01daae5a5 | 170 | volatile uint32_t CLFCR; /* CLFCR */ |
bogdanm | 92:4fc01daae5a5 | 171 | volatile uint32_t CDOCR; /* CDOCR */ |
bogdanm | 92:4fc01daae5a5 | 172 | volatile uint8_t dummy324[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 173 | volatile uint32_t not_common9; /* */ |
bogdanm | 92:4fc01daae5a5 | 174 | volatile uint32_t not_common10; /* */ |
bogdanm | 92:4fc01daae5a5 | 175 | volatile uint8_t dummy325[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 176 | volatile uint32_t not_common11; /* */ |
bogdanm | 92:4fc01daae5a5 | 177 | volatile uint8_t dummy326[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 178 | volatile uint32_t not_common12; /* */ |
bogdanm | 92:4fc01daae5a5 | 179 | volatile uint8_t dummy327[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 180 | volatile uint32_t CDAYR2; /* CDAYR2 */ |
bogdanm | 92:4fc01daae5a5 | 181 | volatile uint32_t CDACR2; /* CDACR2 */ |
bogdanm | 92:4fc01daae5a5 | 182 | volatile uint32_t CDBYR2; /* CDBYR2 */ |
bogdanm | 92:4fc01daae5a5 | 183 | volatile uint32_t CDBCR2; /* CDBCR2 */ |
bogdanm | 92:4fc01daae5a5 | 184 | }; |
bogdanm | 92:4fc01daae5a5 | 185 | |
bogdanm | 92:4fc01daae5a5 | 186 | |
bogdanm | 92:4fc01daae5a5 | 187 | #define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ |
bogdanm | 92:4fc01daae5a5 | 188 | |
bogdanm | 92:4fc01daae5a5 | 189 | |
bogdanm | 92:4fc01daae5a5 | 190 | /* Start of channnel array defines of CEU */ |
bogdanm | 92:4fc01daae5a5 | 191 | |
bogdanm | 92:4fc01daae5a5 | 192 | /* Channnel array defines of CEUn */ |
bogdanm | 92:4fc01daae5a5 | 193 | /*(Sample) value = CEUn[ channel ]->CAMOR; */ |
bogdanm | 92:4fc01daae5a5 | 194 | #define CEUn_COUNT 3 |
bogdanm | 92:4fc01daae5a5 | 195 | #define CEUn_ADDRESS_LIST \ |
bogdanm | 92:4fc01daae5a5 | 196 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
bogdanm | 92:4fc01daae5a5 | 197 | (volatile struct st_ceu_n*)&CEU_A, \ |
bogdanm | 92:4fc01daae5a5 | 198 | (volatile struct st_ceu_n*)&CEU_B, \ |
bogdanm | 92:4fc01daae5a5 | 199 | (volatile struct st_ceu_n*)&CEU_M \ |
bogdanm | 92:4fc01daae5a5 | 200 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
bogdanm | 92:4fc01daae5a5 | 201 | #define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ |
bogdanm | 92:4fc01daae5a5 | 202 | #define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ |
bogdanm | 92:4fc01daae5a5 | 203 | #define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ |
bogdanm | 92:4fc01daae5a5 | 204 | |
bogdanm | 92:4fc01daae5a5 | 205 | /* End of channnel array defines of CEU */ |
bogdanm | 92:4fc01daae5a5 | 206 | |
bogdanm | 92:4fc01daae5a5 | 207 | |
bogdanm | 92:4fc01daae5a5 | 208 | #define CEUCAPSR CEU.CAPSR |
bogdanm | 92:4fc01daae5a5 | 209 | #define CEUCAPCR CEU.CAPCR |
bogdanm | 92:4fc01daae5a5 | 210 | #define CEUCAMCR CEU.CAMCR |
bogdanm | 92:4fc01daae5a5 | 211 | #define CEUCMCYR CEU.CMCYR |
bogdanm | 92:4fc01daae5a5 | 212 | #define CEUCAMOR_A CEU.CAMOR_A |
bogdanm | 92:4fc01daae5a5 | 213 | #define CEUCAPWR_A CEU.CAPWR_A |
bogdanm | 92:4fc01daae5a5 | 214 | #define CEUCAIFR CEU.CAIFR |
bogdanm | 92:4fc01daae5a5 | 215 | #define CEUCRCNTR CEU.CRCNTR |
bogdanm | 92:4fc01daae5a5 | 216 | #define CEUCRCMPR CEU.CRCMPR |
bogdanm | 92:4fc01daae5a5 | 217 | #define CEUCFLCR_A CEU.CFLCR_A |
bogdanm | 92:4fc01daae5a5 | 218 | #define CEUCFSZR_A CEU.CFSZR_A |
bogdanm | 92:4fc01daae5a5 | 219 | #define CEUCDWDR_A CEU.CDWDR_A |
bogdanm | 92:4fc01daae5a5 | 220 | #define CEUCDAYR_A CEU.CDAYR_A |
bogdanm | 92:4fc01daae5a5 | 221 | #define CEUCDACR_A CEU.CDACR_A |
bogdanm | 92:4fc01daae5a5 | 222 | #define CEUCDBYR_A CEU.CDBYR_A |
bogdanm | 92:4fc01daae5a5 | 223 | #define CEUCDBCR_A CEU.CDBCR_A |
bogdanm | 92:4fc01daae5a5 | 224 | #define CEUCBDSR_A CEU.CBDSR_A |
bogdanm | 92:4fc01daae5a5 | 225 | #define CEUCFWCR CEU.CFWCR |
bogdanm | 92:4fc01daae5a5 | 226 | #define CEUCLFCR_A CEU.CLFCR_A |
bogdanm | 92:4fc01daae5a5 | 227 | #define CEUCDOCR_A CEU.CDOCR_A |
bogdanm | 92:4fc01daae5a5 | 228 | #define CEUCEIER CEU.CEIER |
bogdanm | 92:4fc01daae5a5 | 229 | #define CEUCETCR CEU.CETCR |
bogdanm | 92:4fc01daae5a5 | 230 | #define CEUCSTSR CEU.CSTSR |
bogdanm | 92:4fc01daae5a5 | 231 | #define CEUCDSSR CEU.CDSSR |
bogdanm | 92:4fc01daae5a5 | 232 | #define CEUCDAYR2_A CEU.CDAYR2_A |
bogdanm | 92:4fc01daae5a5 | 233 | #define CEUCDACR2_A CEU.CDACR2_A |
bogdanm | 92:4fc01daae5a5 | 234 | #define CEUCDBYR2_A CEU.CDBYR2_A |
bogdanm | 92:4fc01daae5a5 | 235 | #define CEUCDBCR2_A CEU.CDBCR2_A |
bogdanm | 92:4fc01daae5a5 | 236 | #define CEUCAMOR_B CEU.CAMOR_B |
bogdanm | 92:4fc01daae5a5 | 237 | #define CEUCAPWR_B CEU.CAPWR_B |
bogdanm | 92:4fc01daae5a5 | 238 | #define CEUCFLCR_B CEU.CFLCR_B |
bogdanm | 92:4fc01daae5a5 | 239 | #define CEUCFSZR_B CEU.CFSZR_B |
bogdanm | 92:4fc01daae5a5 | 240 | #define CEUCDWDR_B CEU.CDWDR_B |
bogdanm | 92:4fc01daae5a5 | 241 | #define CEUCDAYR_B CEU.CDAYR_B |
bogdanm | 92:4fc01daae5a5 | 242 | #define CEUCDACR_B CEU.CDACR_B |
bogdanm | 92:4fc01daae5a5 | 243 | #define CEUCDBYR_B CEU.CDBYR_B |
bogdanm | 92:4fc01daae5a5 | 244 | #define CEUCDBCR_B CEU.CDBCR_B |
bogdanm | 92:4fc01daae5a5 | 245 | #define CEUCBDSR_B CEU.CBDSR_B |
bogdanm | 92:4fc01daae5a5 | 246 | #define CEUCLFCR_B CEU.CLFCR_B |
bogdanm | 92:4fc01daae5a5 | 247 | #define CEUCDOCR_B CEU.CDOCR_B |
bogdanm | 92:4fc01daae5a5 | 248 | #define CEUCDAYR2_B CEU.CDAYR2_B |
bogdanm | 92:4fc01daae5a5 | 249 | #define CEUCDACR2_B CEU.CDACR2_B |
bogdanm | 92:4fc01daae5a5 | 250 | #define CEUCDBYR2_B CEU.CDBYR2_B |
bogdanm | 92:4fc01daae5a5 | 251 | #define CEUCDBCR2_B CEU.CDBCR2_B |
bogdanm | 92:4fc01daae5a5 | 252 | #define CEUCAMOR_M CEU.CAMOR_M |
bogdanm | 92:4fc01daae5a5 | 253 | #define CEUCAPWR_M CEU.CAPWR_M |
bogdanm | 92:4fc01daae5a5 | 254 | #define CEUCFLCR_M CEU.CFLCR_M |
bogdanm | 92:4fc01daae5a5 | 255 | #define CEUCFSZR_M CEU.CFSZR_M |
bogdanm | 92:4fc01daae5a5 | 256 | #define CEUCDWDR_M CEU.CDWDR_M |
bogdanm | 92:4fc01daae5a5 | 257 | #define CEUCDAYR_M CEU.CDAYR_M |
bogdanm | 92:4fc01daae5a5 | 258 | #define CEUCDACR_M CEU.CDACR_M |
bogdanm | 92:4fc01daae5a5 | 259 | #define CEUCDBYR_M CEU.CDBYR_M |
bogdanm | 92:4fc01daae5a5 | 260 | #define CEUCDBCR_M CEU.CDBCR_M |
bogdanm | 92:4fc01daae5a5 | 261 | #define CEUCBDSR_M CEU.CBDSR_M |
bogdanm | 92:4fc01daae5a5 | 262 | #define CEUCLFCR_M CEU.CLFCR_M |
bogdanm | 92:4fc01daae5a5 | 263 | #define CEUCDOCR_M CEU.CDOCR_M |
bogdanm | 92:4fc01daae5a5 | 264 | #define CEUCDAYR2_M CEU.CDAYR2_M |
bogdanm | 92:4fc01daae5a5 | 265 | #define CEUCDACR2_M CEU.CDACR2_M |
bogdanm | 92:4fc01daae5a5 | 266 | #define CEUCDBYR2_M CEU.CDBYR2_M |
bogdanm | 92:4fc01daae5a5 | 267 | #define CEUCDBCR2_M CEU.CDBCR2_M |
bogdanm | 92:4fc01daae5a5 | 268 | /* <-SEC M1.10.1 */ |
bogdanm | 92:4fc01daae5a5 | 269 | #endif |