Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_RZ_A1H/MBRZA1H.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Child:
97:433970e64889
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 24 * @file MBRZA1H.h
bogdanm 92:4fc01daae5a5 25 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
bogdanm 92:4fc01daae5a5 26 * Renesas MBRZA1H Device Series
bogdanm 92:4fc01daae5a5 27 * @version
bogdanm 92:4fc01daae5a5 28 * @date 19 Sept 2013
bogdanm 92:4fc01daae5a5 29 *
bogdanm 92:4fc01daae5a5 30 * @note
bogdanm 92:4fc01daae5a5 31 *
bogdanm 92:4fc01daae5a5 32 ******************************************************************************/
bogdanm 92:4fc01daae5a5 33
bogdanm 92:4fc01daae5a5 34 #ifndef __MBRZA1H_H__
bogdanm 92:4fc01daae5a5 35 #define __MBRZA1H_H__
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 38 extern "C" {
bogdanm 92:4fc01daae5a5 39 #endif
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 92:4fc01daae5a5 43
bogdanm 92:4fc01daae5a5 44 typedef enum IRQn
bogdanm 92:4fc01daae5a5 45 {
bogdanm 92:4fc01daae5a5 46 /****** SGI Interrupts Numbers ****************************************/
bogdanm 92:4fc01daae5a5 47 SGI0_IRQn = 0,
bogdanm 92:4fc01daae5a5 48 SGI1_IRQn = 1,
bogdanm 92:4fc01daae5a5 49 SGI2_IRQn = 2,
bogdanm 92:4fc01daae5a5 50 SGI3_IRQn = 3,
bogdanm 92:4fc01daae5a5 51 SGI4_IRQn = 4,
bogdanm 92:4fc01daae5a5 52 SGI5_IRQn = 5,
bogdanm 92:4fc01daae5a5 53 SGI6_IRQn = 6,
bogdanm 92:4fc01daae5a5 54 SGI7_IRQn = 7,
bogdanm 92:4fc01daae5a5 55 SGI8_IRQn = 8,
bogdanm 92:4fc01daae5a5 56 SGI9_IRQn = 9,
bogdanm 92:4fc01daae5a5 57 SGI10_IRQn = 10,
bogdanm 92:4fc01daae5a5 58 SGI11_IRQn = 11,
bogdanm 92:4fc01daae5a5 59 SGI12_IRQn = 12,
bogdanm 92:4fc01daae5a5 60 SGI13_IRQn = 13,
bogdanm 92:4fc01daae5a5 61 SGI14_IRQn = 14,
bogdanm 92:4fc01daae5a5 62 SGI15_IRQn = 15,
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
bogdanm 92:4fc01daae5a5 65 /* 16 - 578 */
bogdanm 92:4fc01daae5a5 66 PMUIRQ0_IRQn = 16,
bogdanm 92:4fc01daae5a5 67 COMMRX0_IRQn = 17,
bogdanm 92:4fc01daae5a5 68 COMMTX0_IRQn = 18,
bogdanm 92:4fc01daae5a5 69 CTIIRQ0_IRQn = 19,
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 IRQ0_IRQn = 32,
bogdanm 92:4fc01daae5a5 72 IRQ1_IRQn = 33,
bogdanm 92:4fc01daae5a5 73 IRQ2_IRQn = 34,
bogdanm 92:4fc01daae5a5 74 IRQ3_IRQn = 35,
bogdanm 92:4fc01daae5a5 75 IRQ4_IRQn = 36,
bogdanm 92:4fc01daae5a5 76 IRQ5_IRQn = 37,
bogdanm 92:4fc01daae5a5 77 IRQ6_IRQn = 38,
bogdanm 92:4fc01daae5a5 78 IRQ7_IRQn = 39,
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 PL310ERR_IRQn = 40,
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 83 DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 84 DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 85 DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 86 DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 87 DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 88 DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 89 DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 90 DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 91 DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 92 DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 93 DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 94 DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 95 DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 96 DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 97 DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 98 DMAERR_IRQn = 57, /*!< DMAC Interrupt */
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 /* 58-72 Reserved */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 USBI0_IRQn = 73,
bogdanm 92:4fc01daae5a5 103 USBI1_IRQn = 74,
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 S0_VI_VSYNC0_IRQn = 75,
bogdanm 92:4fc01daae5a5 106 S0_LO_VSYNC0_IRQn = 76,
bogdanm 92:4fc01daae5a5 107 S0_VSYNCERR0_IRQn = 77,
bogdanm 92:4fc01daae5a5 108 GR3_VLINE0_IRQn = 78,
bogdanm 92:4fc01daae5a5 109 S0_VFIELD0_IRQn = 79,
bogdanm 92:4fc01daae5a5 110 IV1_VBUFERR0_IRQn = 80,
bogdanm 92:4fc01daae5a5 111 IV3_VBUFERR0_IRQn = 81,
bogdanm 92:4fc01daae5a5 112 IV5_VBUFERR0_IRQn = 82,
bogdanm 92:4fc01daae5a5 113 IV6_VBUFERR0_IRQn = 83,
bogdanm 92:4fc01daae5a5 114 S0_WLINE0_IRQn = 84,
bogdanm 92:4fc01daae5a5 115 S1_VI_VSYNC0_IRQn = 85,
bogdanm 92:4fc01daae5a5 116 S1_LO_VSYNC0_IRQn = 86,
bogdanm 92:4fc01daae5a5 117 S1_VSYNCERR0_IRQn = 87,
bogdanm 92:4fc01daae5a5 118 S1_VFIELD0_IRQn = 88,
bogdanm 92:4fc01daae5a5 119 IV2_VBUFERR0_IRQn = 89,
bogdanm 92:4fc01daae5a5 120 IV4_VBUFERR0_IRQn = 90,
bogdanm 92:4fc01daae5a5 121 S1_WLINE0_IRQn = 91,
bogdanm 92:4fc01daae5a5 122 OIR_VI_VSYNC0_IRQn = 92,
bogdanm 92:4fc01daae5a5 123 OIR_LO_VSYNC0_IRQn = 93,
bogdanm 92:4fc01daae5a5 124 OIR_VSYNCERR0_IRQn = 94,
bogdanm 92:4fc01daae5a5 125 OIR_VFIELD0_IRQn = 95,
bogdanm 92:4fc01daae5a5 126 IV7_VBUFERR0_IRQn = 96,
bogdanm 92:4fc01daae5a5 127 IV8_VBUFERR0_IRQn = 97,
bogdanm 92:4fc01daae5a5 128 /* 98 Reserved */
bogdanm 92:4fc01daae5a5 129 S0_VI_VSYNC1_IRQn = 99,
bogdanm 92:4fc01daae5a5 130 S0_LO_VSYNC1_IRQn = 100,
bogdanm 92:4fc01daae5a5 131 S0_VSYNCERR1_IRQn = 101,
bogdanm 92:4fc01daae5a5 132 GR3_VLINE1_IRQn = 102,
bogdanm 92:4fc01daae5a5 133 S0_VFIELD1_IRQn = 103,
bogdanm 92:4fc01daae5a5 134 IV1_VBUFERR1_IRQn = 104,
bogdanm 92:4fc01daae5a5 135 IV3_VBUFERR1_IRQn = 105,
bogdanm 92:4fc01daae5a5 136 IV5_VBUFERR1_IRQn = 106,
bogdanm 92:4fc01daae5a5 137 IV6_VBUFERR1_IRQn = 107,
bogdanm 92:4fc01daae5a5 138 S0_WLINE1_IRQn = 108,
bogdanm 92:4fc01daae5a5 139 S1_VI_VSYNC1_IRQn = 109,
bogdanm 92:4fc01daae5a5 140 S1_LO_VSYNC1_IRQn = 110,
bogdanm 92:4fc01daae5a5 141 S1_VSYNCERR1_IRQn = 111,
bogdanm 92:4fc01daae5a5 142 S1_VFIELD1_IRQn = 112,
bogdanm 92:4fc01daae5a5 143 IV2_VBUFERR1_IRQn = 113,
bogdanm 92:4fc01daae5a5 144 IV4_VBUFERR1_IRQn = 114,
bogdanm 92:4fc01daae5a5 145 S1_WLINE1_IRQn = 115,
bogdanm 92:4fc01daae5a5 146 OIR_VI_VSYNC1_IRQn = 116,
bogdanm 92:4fc01daae5a5 147 OIR_LO_VSYNC1_IRQn = 117,
bogdanm 92:4fc01daae5a5 148 OIR_VSYNCERR1_IRQn = 118,
bogdanm 92:4fc01daae5a5 149 OIR_VFIELD1_IRQn = 119,
bogdanm 92:4fc01daae5a5 150 IV7_VBUFERR1_IRQn = 120,
bogdanm 92:4fc01daae5a5 151 IV8_VBUFERR1_IRQn = 121,
bogdanm 92:4fc01daae5a5 152 /* Reserved = 122 */
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 IMRDI_IRQn = 123,
bogdanm 92:4fc01daae5a5 155 IMR2I0_IRQn = 124,
bogdanm 92:4fc01daae5a5 156 IMR2I1_IRQn = 125,
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 JEDI_IRQn = 126,
bogdanm 92:4fc01daae5a5 159 JDTI_IRQn = 127,
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 CMP0_IRQn = 128,
bogdanm 92:4fc01daae5a5 162 CMP1_IRQn = 129,
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 INT0_IRQn = 130,
bogdanm 92:4fc01daae5a5 165 INT1_IRQn = 131,
bogdanm 92:4fc01daae5a5 166 INT2_IRQn = 132,
bogdanm 92:4fc01daae5a5 167 INT3_IRQn = 133,
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
bogdanm 92:4fc01daae5a5 170 OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 CMI_IRQn = 136,
bogdanm 92:4fc01daae5a5 173 WTOUT_IRQn = 137,
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 ITI_IRQn = 138,
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177 TGI0A_IRQn = 139,
bogdanm 92:4fc01daae5a5 178 TGI0B_IRQn = 140,
bogdanm 92:4fc01daae5a5 179 TGI0C_IRQn = 141,
bogdanm 92:4fc01daae5a5 180 TGI0D_IRQn = 142,
bogdanm 92:4fc01daae5a5 181 TGI0V_IRQn = 143,
bogdanm 92:4fc01daae5a5 182 TGI0E_IRQn = 144,
bogdanm 92:4fc01daae5a5 183 TGI0F_IRQn = 145,
bogdanm 92:4fc01daae5a5 184 TGI1A_IRQn = 146,
bogdanm 92:4fc01daae5a5 185 TGI1B_IRQn = 147,
bogdanm 92:4fc01daae5a5 186 TGI1V_IRQn = 148,
bogdanm 92:4fc01daae5a5 187 TGI1U_IRQn = 149,
bogdanm 92:4fc01daae5a5 188 TGI2A_IRQn = 150,
bogdanm 92:4fc01daae5a5 189 TGI2B_IRQn = 151,
bogdanm 92:4fc01daae5a5 190 TGI2V_IRQn = 152,
bogdanm 92:4fc01daae5a5 191 TGI2U_IRQn = 153,
bogdanm 92:4fc01daae5a5 192 TGI3A_IRQn = 154,
bogdanm 92:4fc01daae5a5 193 TGI3B_IRQn = 155,
bogdanm 92:4fc01daae5a5 194 TGI3C_IRQn = 156,
bogdanm 92:4fc01daae5a5 195 TGI3D_IRQn = 157,
bogdanm 92:4fc01daae5a5 196 TGI3V_IRQn = 158,
bogdanm 92:4fc01daae5a5 197 TGI4A_IRQn = 159,
bogdanm 92:4fc01daae5a5 198 TGI4B_IRQn = 160,
bogdanm 92:4fc01daae5a5 199 TGI4C_IRQn = 161,
bogdanm 92:4fc01daae5a5 200 TGI4D_IRQn = 162,
bogdanm 92:4fc01daae5a5 201 TGI4V_IRQn = 163,
bogdanm 92:4fc01daae5a5 202
bogdanm 92:4fc01daae5a5 203 CMI1_IRQn = 164,
bogdanm 92:4fc01daae5a5 204 CMI2_IRQn = 165,
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 SGDEI0_IRQn = 166,
bogdanm 92:4fc01daae5a5 207 SGDEI1_IRQn = 167,
bogdanm 92:4fc01daae5a5 208 SGDEI2_IRQn = 168,
bogdanm 92:4fc01daae5a5 209 SGDEI3_IRQn = 169,
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 ADI_IRQn = 170,
bogdanm 92:4fc01daae5a5 212 LMTI_IRQn = 171,
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 SSII0_IRQn = 172, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 215 SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 216 SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 217 SSII1_IRQn = 175, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 218 SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 219 SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 220 SSII2_IRQn = 178, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 221 SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 222 SSII3_IRQn = 180, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 223 SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 224 SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 225 SSII4_IRQn = 183, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 226 SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 227 SSII5_IRQn = 185, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 228 SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 229 SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 SPDIFI_IRQn = 188,
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 234 INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 235 INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 236 INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 237 INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 238 INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 239 INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 240 INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 241 INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 242 INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 243 INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 244 INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 245 INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 246 INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 247 INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 248 INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 249 INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 250 INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 251 INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 252 INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 253 INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 254 INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 255 INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 256 INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 257 INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 258 INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 259 INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 260 INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 261 INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 262 INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 263 INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 264 INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 267 SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 268 SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 269 SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 270 SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 271 SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 272 SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 273 SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 274 SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 275 SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 276 SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 277 SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 278 SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 279 SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 280 SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 281 SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 282 SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 283 SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 284 SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 285 SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 286 SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 287 SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 288 SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 289 SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 290 SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 291 SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 292 SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 293 SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 294 SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 295 SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 296 SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 297 SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 INTRCANGERR_IRQn = 253,
bogdanm 92:4fc01daae5a5 300 INTRCANGRECC_IRQn = 254,
bogdanm 92:4fc01daae5a5 301 INTRCAN0REC_IRQn = 255,
bogdanm 92:4fc01daae5a5 302 INTRCAN0ERR_IRQn = 256,
bogdanm 92:4fc01daae5a5 303 INTRCAN0TRX_IRQn = 257,
bogdanm 92:4fc01daae5a5 304 INTRCAN1REC_IRQn = 258,
bogdanm 92:4fc01daae5a5 305 INTRCAN1ERR_IRQn = 259,
bogdanm 92:4fc01daae5a5 306 INTRCAN1TRX_IRQn = 260,
bogdanm 92:4fc01daae5a5 307 INTRCAN2REC_IRQn = 261,
bogdanm 92:4fc01daae5a5 308 INTRCAN2ERR_IRQn = 262,
bogdanm 92:4fc01daae5a5 309 INTRCAN2TRX_IRQn = 263,
bogdanm 92:4fc01daae5a5 310 INTRCAN3REC_IRQn = 264,
bogdanm 92:4fc01daae5a5 311 INTRCAN3ERR_IRQn = 265,
bogdanm 92:4fc01daae5a5 312 INTRCAN3TRX_IRQn = 266,
bogdanm 92:4fc01daae5a5 313 INTRCAN4REC_IRQn = 267,
bogdanm 92:4fc01daae5a5 314 INTRCAN4ERR_IRQn = 268,
bogdanm 92:4fc01daae5a5 315 INTRCAN4TRX_IRQn = 269,
bogdanm 92:4fc01daae5a5 316
bogdanm 92:4fc01daae5a5 317 RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 318 RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 319 RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 320 RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 321 RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 322 RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 323 RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 324 RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 325 RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 326 RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 327 RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 328 RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 329 RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 330 RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 331 RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 IEBBTD_IRQn = 285,
bogdanm 92:4fc01daae5a5 334 IEBBTERR_IRQn = 286,
bogdanm 92:4fc01daae5a5 335 IEBBTSTA_IRQn = 287,
bogdanm 92:4fc01daae5a5 336 IEBBTV_IRQn = 288,
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 ISY_IRQn = 289,
bogdanm 92:4fc01daae5a5 339 IERR_IRQn = 290,
bogdanm 92:4fc01daae5a5 340 ITARG_IRQn = 291,
bogdanm 92:4fc01daae5a5 341 ISEC_IRQn = 292,
bogdanm 92:4fc01daae5a5 342 IBUF_IRQn = 293,
bogdanm 92:4fc01daae5a5 343 IREADY_IRQn = 294,
bogdanm 92:4fc01daae5a5 344
bogdanm 92:4fc01daae5a5 345 STERB_IRQn = 295,
bogdanm 92:4fc01daae5a5 346 FLTENDI_IRQn = 296,
bogdanm 92:4fc01daae5a5 347 FLTREQ0I_IRQn = 297,
bogdanm 92:4fc01daae5a5 348 FLTREQ1I_IRQn = 298,
bogdanm 92:4fc01daae5a5 349
bogdanm 92:4fc01daae5a5 350 MMC0_IRQn = 299,
bogdanm 92:4fc01daae5a5 351 MMC1_IRQn = 300,
bogdanm 92:4fc01daae5a5 352 MMC2_IRQn = 301,
bogdanm 92:4fc01daae5a5 353
bogdanm 92:4fc01daae5a5 354 SCHI0_3_IRQn = 302,
bogdanm 92:4fc01daae5a5 355 SDHI0_0_IRQn = 303,
bogdanm 92:4fc01daae5a5 356 SDHI0_1_IRQn = 304,
bogdanm 92:4fc01daae5a5 357 SCHI1_3_IRQn = 305,
bogdanm 92:4fc01daae5a5 358 SDHI1_0_IRQn = 306,
bogdanm 92:4fc01daae5a5 359 SDHI1_1_IRQn = 307,
bogdanm 92:4fc01daae5a5 360
bogdanm 92:4fc01daae5a5 361 ARM_IRQn = 308,
bogdanm 92:4fc01daae5a5 362 PRD_IRQn = 309,
bogdanm 92:4fc01daae5a5 363 CUP_IRQn = 310,
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 SCUAI0_IRQn = 311,
bogdanm 92:4fc01daae5a5 366 SCUAI1_IRQn = 312,
bogdanm 92:4fc01daae5a5 367 SCUFDI0_IRQn = 313,
bogdanm 92:4fc01daae5a5 368 SCUFDI1_IRQn = 314,
bogdanm 92:4fc01daae5a5 369 SCUFDI2_IRQn = 315,
bogdanm 92:4fc01daae5a5 370 SCUFDI3_IRQn = 316,
bogdanm 92:4fc01daae5a5 371 SCUFUI0_IRQn = 317,
bogdanm 92:4fc01daae5a5 372 SCUFUI1_IRQn = 318,
bogdanm 92:4fc01daae5a5 373 SCUFUI2_IRQn = 319,
bogdanm 92:4fc01daae5a5 374 SCUFUI3_IRQn = 320,
bogdanm 92:4fc01daae5a5 375 SCUDVI0_IRQn = 321,
bogdanm 92:4fc01daae5a5 376 SCUDVI1_IRQn = 322,
bogdanm 92:4fc01daae5a5 377 SCUDVI2_IRQn = 323,
bogdanm 92:4fc01daae5a5 378 SCUDVI3_IRQn = 324,
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 MLB_CINT_IRQn = 325,
bogdanm 92:4fc01daae5a5 381 MLB_SINT_IRQn = 326,
bogdanm 92:4fc01daae5a5 382
bogdanm 92:4fc01daae5a5 383 DRC10_IRQn = 327,
bogdanm 92:4fc01daae5a5 384 DRC11_IRQn = 328,
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /* 329-330 Reserved */
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 LINI0_INT_T_IRQn = 331,
bogdanm 92:4fc01daae5a5 389 LINI0_INT_R_IRQn = 332,
bogdanm 92:4fc01daae5a5 390 LINI0_INT_S_IRQn = 333,
bogdanm 92:4fc01daae5a5 391 LINI0_INT_M_IRQn = 334,
bogdanm 92:4fc01daae5a5 392 LINI1_INT_T_IRQn = 335,
bogdanm 92:4fc01daae5a5 393 LINI1_INT_R_IRQn = 336,
bogdanm 92:4fc01daae5a5 394 LINI1_INT_S_IRQn = 337,
bogdanm 92:4fc01daae5a5 395 LINI1_INT_M_IRQn = 338,
bogdanm 92:4fc01daae5a5 396
bogdanm 92:4fc01daae5a5 397 /* 339-346 Reserved */
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 SCIERI0_IRQn = 347,
bogdanm 92:4fc01daae5a5 400 SCIRXI0_IRQn = 348,
bogdanm 92:4fc01daae5a5 401 SCITXI0_IRQn = 349,
bogdanm 92:4fc01daae5a5 402 SCITEI0_IRQn = 350,
bogdanm 92:4fc01daae5a5 403 SCIERI1_IRQn = 351,
bogdanm 92:4fc01daae5a5 404 SCIRXI1_IRQn = 352,
bogdanm 92:4fc01daae5a5 405 SCITXI1_IRQn = 353,
bogdanm 92:4fc01daae5a5 406 SCITEI1_IRQn = 354,
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408 AVBI_DATA = 355,
bogdanm 92:4fc01daae5a5 409 AVBI_ERROR = 356,
bogdanm 92:4fc01daae5a5 410 AVBI_MANAGE = 357,
bogdanm 92:4fc01daae5a5 411 AVBI_MAC = 358,
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 ETHERI_IRQn = 359,
bogdanm 92:4fc01daae5a5 414
bogdanm 92:4fc01daae5a5 415 /* 360-363 Reserved */
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 CEUI_IRQn = 364,
bogdanm 92:4fc01daae5a5 418
bogdanm 92:4fc01daae5a5 419 /* 365-380 Reserved */
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421
bogdanm 92:4fc01daae5a5 422 H2XMLB_ERRINT_IRQn = 381,
bogdanm 92:4fc01daae5a5 423 H2XIC1_ERRINT_IRQn = 382,
bogdanm 92:4fc01daae5a5 424 X2HPERI1_ERRINT_IRQn = 383,
bogdanm 92:4fc01daae5a5 425 X2HPERR2_ERRINT_IRQn = 384,
bogdanm 92:4fc01daae5a5 426 X2HPERR34_ERRINT_IRQn= 385,
bogdanm 92:4fc01daae5a5 427 X2HPERR5_ERRINT_IRQn = 386,
bogdanm 92:4fc01daae5a5 428 X2HPERR67_ERRINT_IRQn= 387,
bogdanm 92:4fc01daae5a5 429 X2HDBGR_ERRINT_IRQn = 388,
bogdanm 92:4fc01daae5a5 430 X2HBSC_ERRINT_IRQn = 389,
bogdanm 92:4fc01daae5a5 431 X2HSPI1_ERRINT_IRQn = 390,
bogdanm 92:4fc01daae5a5 432 X2HSPI2_ERRINT_IRQn = 391,
bogdanm 92:4fc01daae5a5 433 PRRI_IRQn = 392,
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 IFEI0_IRQn = 393,
bogdanm 92:4fc01daae5a5 436 OFFI0_IRQn = 394,
bogdanm 92:4fc01daae5a5 437 PFVEI0_IRQn = 395,
bogdanm 92:4fc01daae5a5 438 IFEI1_IRQn = 396,
bogdanm 92:4fc01daae5a5 439 OFFI1_IRQn = 397,
bogdanm 92:4fc01daae5a5 440 PFVEI1_IRQn = 398,
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 /* 399-415 Reserved */
bogdanm 92:4fc01daae5a5 443 TINT0_IRQn = 416,
bogdanm 92:4fc01daae5a5 444 TINT1_IRQn = 417,
bogdanm 92:4fc01daae5a5 445 TINT2_IRQn = 418,
bogdanm 92:4fc01daae5a5 446 TINT3_IRQn = 419,
bogdanm 92:4fc01daae5a5 447 TINT4_IRQn = 420,
bogdanm 92:4fc01daae5a5 448 TINT5_IRQn = 421,
bogdanm 92:4fc01daae5a5 449 TINT6_IRQn = 422,
bogdanm 92:4fc01daae5a5 450 TINT7_IRQn = 423,
bogdanm 92:4fc01daae5a5 451 TINT8_IRQn = 424,
bogdanm 92:4fc01daae5a5 452 TINT9_IRQn = 425,
bogdanm 92:4fc01daae5a5 453 TINT10_IRQn = 426,
bogdanm 92:4fc01daae5a5 454 TINT11_IRQn = 427,
bogdanm 92:4fc01daae5a5 455 TINT12_IRQn = 428,
bogdanm 92:4fc01daae5a5 456 TINT13_IRQn = 429,
bogdanm 92:4fc01daae5a5 457 TINT14_IRQn = 430,
bogdanm 92:4fc01daae5a5 458 TINT15_IRQn = 431,
bogdanm 92:4fc01daae5a5 459 TINT16_IRQn = 432,
bogdanm 92:4fc01daae5a5 460 TINT17_IRQn = 433,
bogdanm 92:4fc01daae5a5 461 TINT18_IRQn = 434,
bogdanm 92:4fc01daae5a5 462 TINT19_IRQn = 435,
bogdanm 92:4fc01daae5a5 463 TINT20_IRQn = 436,
bogdanm 92:4fc01daae5a5 464 TINT21_IRQn = 437,
bogdanm 92:4fc01daae5a5 465 TINT22_IRQn = 438,
bogdanm 92:4fc01daae5a5 466 TINT23_IRQn = 439,
bogdanm 92:4fc01daae5a5 467 TINT24_IRQn = 440,
bogdanm 92:4fc01daae5a5 468 TINT25_IRQn = 441,
bogdanm 92:4fc01daae5a5 469 TINT26_IRQn = 442,
bogdanm 92:4fc01daae5a5 470 TINT27_IRQn = 443,
bogdanm 92:4fc01daae5a5 471 TINT28_IRQn = 444,
bogdanm 92:4fc01daae5a5 472 TINT29_IRQn = 445,
bogdanm 92:4fc01daae5a5 473 TINT30_IRQn = 446,
bogdanm 92:4fc01daae5a5 474 TINT31_IRQn = 447,
bogdanm 92:4fc01daae5a5 475 TINT32_IRQn = 448,
bogdanm 92:4fc01daae5a5 476 TINT33_IRQn = 449,
bogdanm 92:4fc01daae5a5 477 TINT34_IRQn = 450,
bogdanm 92:4fc01daae5a5 478 TINT35_IRQn = 451,
bogdanm 92:4fc01daae5a5 479 TINT36_IRQn = 452,
bogdanm 92:4fc01daae5a5 480 TINT37_IRQn = 453,
bogdanm 92:4fc01daae5a5 481 TINT38_IRQn = 454,
bogdanm 92:4fc01daae5a5 482 TINT39_IRQn = 455,
bogdanm 92:4fc01daae5a5 483 TINT40_IRQn = 456,
bogdanm 92:4fc01daae5a5 484 TINT41_IRQn = 457,
bogdanm 92:4fc01daae5a5 485 TINT42_IRQn = 458,
bogdanm 92:4fc01daae5a5 486 TINT43_IRQn = 459,
bogdanm 92:4fc01daae5a5 487 TINT44_IRQn = 460,
bogdanm 92:4fc01daae5a5 488 TINT45_IRQn = 461,
bogdanm 92:4fc01daae5a5 489 TINT46_IRQn = 462,
bogdanm 92:4fc01daae5a5 490 TINT47_IRQn = 463,
bogdanm 92:4fc01daae5a5 491 TINT48_IRQn = 464,
bogdanm 92:4fc01daae5a5 492 TINT49_IRQn = 465,
bogdanm 92:4fc01daae5a5 493 TINT50_IRQn = 466,
bogdanm 92:4fc01daae5a5 494 TINT51_IRQn = 467,
bogdanm 92:4fc01daae5a5 495 TINT52_IRQn = 468,
bogdanm 92:4fc01daae5a5 496 TINT53_IRQn = 469,
bogdanm 92:4fc01daae5a5 497 TINT54_IRQn = 470,
bogdanm 92:4fc01daae5a5 498 TINT55_IRQn = 471,
bogdanm 92:4fc01daae5a5 499 TINT56_IRQn = 472,
bogdanm 92:4fc01daae5a5 500 TINT57_IRQn = 473,
bogdanm 92:4fc01daae5a5 501 TINT58_IRQn = 474,
bogdanm 92:4fc01daae5a5 502 TINT59_IRQn = 475,
bogdanm 92:4fc01daae5a5 503 TINT60_IRQn = 476,
bogdanm 92:4fc01daae5a5 504 TINT61_IRQn = 477,
bogdanm 92:4fc01daae5a5 505 TINT62_IRQn = 478,
bogdanm 92:4fc01daae5a5 506 TINT63_IRQn = 479,
bogdanm 92:4fc01daae5a5 507 TINT64_IRQn = 480,
bogdanm 92:4fc01daae5a5 508 TINT65_IRQn = 481,
bogdanm 92:4fc01daae5a5 509 TINT66_IRQn = 482,
bogdanm 92:4fc01daae5a5 510 TINT67_IRQn = 483,
bogdanm 92:4fc01daae5a5 511 TINT68_IRQn = 484,
bogdanm 92:4fc01daae5a5 512 TINT69_IRQn = 485,
bogdanm 92:4fc01daae5a5 513 TINT70_IRQn = 486,
bogdanm 92:4fc01daae5a5 514 TINT71_IRQn = 487,
bogdanm 92:4fc01daae5a5 515 TINT72_IRQn = 488,
bogdanm 92:4fc01daae5a5 516 TINT73_IRQn = 489,
bogdanm 92:4fc01daae5a5 517 TINT74_IRQn = 490,
bogdanm 92:4fc01daae5a5 518 TINT75_IRQn = 491,
bogdanm 92:4fc01daae5a5 519 TINT76_IRQn = 492,
bogdanm 92:4fc01daae5a5 520 TINT77_IRQn = 493,
bogdanm 92:4fc01daae5a5 521 TINT78_IRQn = 494,
bogdanm 92:4fc01daae5a5 522 TINT79_IRQn = 495,
bogdanm 92:4fc01daae5a5 523 TINT80_IRQn = 496,
bogdanm 92:4fc01daae5a5 524 TINT81_IRQn = 497,
bogdanm 92:4fc01daae5a5 525 TINT82_IRQn = 498,
bogdanm 92:4fc01daae5a5 526 TINT83_IRQn = 499,
bogdanm 92:4fc01daae5a5 527 TINT84_IRQn = 500,
bogdanm 92:4fc01daae5a5 528 TINT85_IRQn = 501,
bogdanm 92:4fc01daae5a5 529 TINT86_IRQn = 502,
bogdanm 92:4fc01daae5a5 530 TINT87_IRQn = 503,
bogdanm 92:4fc01daae5a5 531 TINT88_IRQn = 504,
bogdanm 92:4fc01daae5a5 532 TINT89_IRQn = 505,
bogdanm 92:4fc01daae5a5 533 TINT90_IRQn = 506,
bogdanm 92:4fc01daae5a5 534 TINT91_IRQn = 507,
bogdanm 92:4fc01daae5a5 535 TINT92_IRQn = 508,
bogdanm 92:4fc01daae5a5 536 TINT93_IRQn = 509,
bogdanm 92:4fc01daae5a5 537 TINT94_IRQn = 510,
bogdanm 92:4fc01daae5a5 538 TINT95_IRQn = 511,
bogdanm 92:4fc01daae5a5 539 TINT96_IRQn = 512,
bogdanm 92:4fc01daae5a5 540 TINT97_IRQn = 513,
bogdanm 92:4fc01daae5a5 541 TINT98_IRQn = 514,
bogdanm 92:4fc01daae5a5 542 TINT99_IRQn = 515,
bogdanm 92:4fc01daae5a5 543 TINT100_IRQn = 516,
bogdanm 92:4fc01daae5a5 544 TINT101_IRQn = 517,
bogdanm 92:4fc01daae5a5 545 TINT102_IRQn = 518,
bogdanm 92:4fc01daae5a5 546 TINT103_IRQn = 519,
bogdanm 92:4fc01daae5a5 547 TINT104_IRQn = 520,
bogdanm 92:4fc01daae5a5 548 TINT105_IRQn = 521,
bogdanm 92:4fc01daae5a5 549 TINT106_IRQn = 522,
bogdanm 92:4fc01daae5a5 550 TINT107_IRQn = 523,
bogdanm 92:4fc01daae5a5 551 TINT108_IRQn = 524,
bogdanm 92:4fc01daae5a5 552 TINT109_IRQn = 525,
bogdanm 92:4fc01daae5a5 553 TINT110_IRQn = 526,
bogdanm 92:4fc01daae5a5 554 TINT111_IRQn = 527,
bogdanm 92:4fc01daae5a5 555 TINT112_IRQn = 528,
bogdanm 92:4fc01daae5a5 556 TINT113_IRQn = 529,
bogdanm 92:4fc01daae5a5 557 TINT114_IRQn = 530,
bogdanm 92:4fc01daae5a5 558 TINT115_IRQn = 531,
bogdanm 92:4fc01daae5a5 559 TINT116_IRQn = 532,
bogdanm 92:4fc01daae5a5 560 TINT117_IRQn = 533,
bogdanm 92:4fc01daae5a5 561 TINT118_IRQn = 534,
bogdanm 92:4fc01daae5a5 562 TINT119_IRQn = 535,
bogdanm 92:4fc01daae5a5 563 TINT120_IRQn = 536,
bogdanm 92:4fc01daae5a5 564 TINT121_IRQn = 537,
bogdanm 92:4fc01daae5a5 565 TINT122_IRQn = 538,
bogdanm 92:4fc01daae5a5 566 TINT123_IRQn = 539,
bogdanm 92:4fc01daae5a5 567 TINT124_IRQn = 540,
bogdanm 92:4fc01daae5a5 568 TINT125_IRQn = 541,
bogdanm 92:4fc01daae5a5 569 TINT126_IRQn = 542,
bogdanm 92:4fc01daae5a5 570 TINT127_IRQn = 543,
bogdanm 92:4fc01daae5a5 571 TINT128_IRQn = 544,
bogdanm 92:4fc01daae5a5 572 TINT129_IRQn = 545,
bogdanm 92:4fc01daae5a5 573 TINT130_IRQn = 546,
bogdanm 92:4fc01daae5a5 574 TINT131_IRQn = 547,
bogdanm 92:4fc01daae5a5 575 TINT132_IRQn = 548,
bogdanm 92:4fc01daae5a5 576 TINT133_IRQn = 549,
bogdanm 92:4fc01daae5a5 577 TINT134_IRQn = 550,
bogdanm 92:4fc01daae5a5 578 TINT135_IRQn = 551,
bogdanm 92:4fc01daae5a5 579 TINT136_IRQn = 552,
bogdanm 92:4fc01daae5a5 580 TINT137_IRQn = 553,
bogdanm 92:4fc01daae5a5 581 TINT138_IRQn = 554,
bogdanm 92:4fc01daae5a5 582 TINT139_IRQn = 555,
bogdanm 92:4fc01daae5a5 583 TINT140_IRQn = 556,
bogdanm 92:4fc01daae5a5 584 TINT141_IRQn = 557,
bogdanm 92:4fc01daae5a5 585 TINT142_IRQn = 558,
bogdanm 92:4fc01daae5a5 586 TINT143_IRQn = 559,
bogdanm 92:4fc01daae5a5 587 TINT144_IRQn = 560,
bogdanm 92:4fc01daae5a5 588 TINT145_IRQn = 561,
bogdanm 92:4fc01daae5a5 589 TINT146_IRQn = 562,
bogdanm 92:4fc01daae5a5 590 TINT147_IRQn = 563,
bogdanm 92:4fc01daae5a5 591 TINT148_IRQn = 564,
bogdanm 92:4fc01daae5a5 592 TINT149_IRQn = 565,
bogdanm 92:4fc01daae5a5 593 TINT150_IRQn = 566,
bogdanm 92:4fc01daae5a5 594 TINT151_IRQn = 567,
bogdanm 92:4fc01daae5a5 595 TINT152_IRQn = 568,
bogdanm 92:4fc01daae5a5 596 TINT153_IRQn = 569,
bogdanm 92:4fc01daae5a5 597 TINT154_IRQn = 570,
bogdanm 92:4fc01daae5a5 598 TINT155_IRQn = 571,
bogdanm 92:4fc01daae5a5 599 TINT156_IRQn = 572,
bogdanm 92:4fc01daae5a5 600 TINT157_IRQn = 573,
bogdanm 92:4fc01daae5a5 601 TINT158_IRQn = 574,
bogdanm 92:4fc01daae5a5 602 TINT159_IRQn = 575,
bogdanm 92:4fc01daae5a5 603 TINT160_IRQn = 576,
bogdanm 92:4fc01daae5a5 604 TINT161_IRQn = 577,
bogdanm 92:4fc01daae5a5 605 TINT162_IRQn = 578,
bogdanm 92:4fc01daae5a5 606 TINT163_IRQn = 579,
bogdanm 92:4fc01daae5a5 607 TINT164_IRQn = 580,
bogdanm 92:4fc01daae5a5 608 TINT165_IRQn = 581,
bogdanm 92:4fc01daae5a5 609 TINT166_IRQn = 582,
bogdanm 92:4fc01daae5a5 610 TINT167_IRQn = 583,
bogdanm 92:4fc01daae5a5 611 TINT168_IRQn = 584,
bogdanm 92:4fc01daae5a5 612 TINT169_IRQn = 585,
bogdanm 92:4fc01daae5a5 613 TINT170_IRQn = 586
bogdanm 92:4fc01daae5a5 614
bogdanm 92:4fc01daae5a5 615 } IRQn_Type;
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619 /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
bogdanm 92:4fc01daae5a5 620 #define __CA9_REV 0x0000 /*!< Core revision r0 */
bogdanm 92:4fc01daae5a5 621
bogdanm 92:4fc01daae5a5 622 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 92:4fc01daae5a5 623
bogdanm 92:4fc01daae5a5 624 #define __FPU_PRESENT 1 /*!< FPU present or not */
bogdanm 92:4fc01daae5a5 625
bogdanm 92:4fc01daae5a5 626 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 92:4fc01daae5a5 627 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 92:4fc01daae5a5 628
bogdanm 92:4fc01daae5a5 629 #include <core_ca9.h>
bogdanm 92:4fc01daae5a5 630 #include "system_MBRZA1H.h"
bogdanm 92:4fc01daae5a5 631
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633 /******************************************************************************/
bogdanm 92:4fc01daae5a5 634 /* Device Specific Peripheral Section */
bogdanm 92:4fc01daae5a5 635 /******************************************************************************/
bogdanm 92:4fc01daae5a5 636 /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
bogdanm 92:4fc01daae5a5 637 Renesas_RZ_A1 Device Specific Peripheral registers structures
bogdanm 92:4fc01daae5a5 638 @{
bogdanm 92:4fc01daae5a5 639 */
bogdanm 92:4fc01daae5a5 640
bogdanm 92:4fc01daae5a5 641 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 642 #pragma anon_unions
bogdanm 92:4fc01daae5a5 643 #endif
bogdanm 92:4fc01daae5a5 644
bogdanm 92:4fc01daae5a5 645 #include "pl310.h"
bogdanm 92:4fc01daae5a5 646 #include "gic.h"
bogdanm 92:4fc01daae5a5 647
bogdanm 92:4fc01daae5a5 648 #include "ostm_iodefine.h"
bogdanm 92:4fc01daae5a5 649 #include "gpio_iodefine.h"
bogdanm 92:4fc01daae5a5 650 #include "cpg_iodefine.h"
bogdanm 92:4fc01daae5a5 651 #include "l2c_iodefine.h"
bogdanm 92:4fc01daae5a5 652
bogdanm 92:4fc01daae5a5 653 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 654 #pragma no_anon_unions
bogdanm 92:4fc01daae5a5 655 #endif
bogdanm 92:4fc01daae5a5 656
bogdanm 92:4fc01daae5a5 657 /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659
bogdanm 92:4fc01daae5a5 660 /******************************************************************************/
bogdanm 92:4fc01daae5a5 661 /* Peripheral memory map */
bogdanm 92:4fc01daae5a5 662 /******************************************************************************/
bogdanm 92:4fc01daae5a5 663 /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
bogdanm 92:4fc01daae5a5 664 @{
bogdanm 92:4fc01daae5a5 665 */
bogdanm 92:4fc01daae5a5 666
bogdanm 92:4fc01daae5a5 667 /* R7S72100 CPU board */
bogdanm 92:4fc01daae5a5 668 #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
bogdanm 92:4fc01daae5a5 669 #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
bogdanm 92:4fc01daae5a5 670 #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
bogdanm 92:4fc01daae5a5 671 #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
bogdanm 92:4fc01daae5a5 672 #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
bogdanm 92:4fc01daae5a5 673 #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
bogdanm 92:4fc01daae5a5 674 #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
bogdanm 92:4fc01daae5a5 675 #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
bogdanm 92:4fc01daae5a5 676 #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
bogdanm 92:4fc01daae5a5 677 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
bogdanm 92:4fc01daae5a5 678 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
bogdanm 92:4fc01daae5a5 679 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
bogdanm 92:4fc01daae5a5 680 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
bogdanm 92:4fc01daae5a5 681 #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
bogdanm 92:4fc01daae5a5 682 #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
bogdanm 92:4fc01daae5a5 683 #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
bogdanm 92:4fc01daae5a5 684 #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
bogdanm 92:4fc01daae5a5 687 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
bogdanm 92:4fc01daae5a5 688 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 689 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 690 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 691 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 692 region.inner_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 693 region.outer_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 694 region.mem_t = NORMAL; \
bogdanm 92:4fc01daae5a5 695 region.sec_t = NON_SECURE; \
bogdanm 92:4fc01daae5a5 696 region.xn_t = EXECUTE; \
bogdanm 92:4fc01daae5a5 697 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 698 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 699 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 700 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 701
bogdanm 92:4fc01daae5a5 702 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 703 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 704 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 705 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 706 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 707 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 708 region.mem_t = NORMAL; \
bogdanm 92:4fc01daae5a5 709 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 710 region.xn_t = EXECUTE; \
bogdanm 92:4fc01daae5a5 711 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 712 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 713 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 714 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 715
bogdanm 92:4fc01daae5a5 716 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
bogdanm 92:4fc01daae5a5 717 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 718 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 719 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 720 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 721 region.inner_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 722 region.outer_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 723 region.mem_t = NORMAL; \
bogdanm 92:4fc01daae5a5 724 region.sec_t = NON_SECURE; \
bogdanm 92:4fc01daae5a5 725 region.xn_t = EXECUTE; \
bogdanm 92:4fc01daae5a5 726 region.priv_t = READ; \
bogdanm 92:4fc01daae5a5 727 region.user_t = READ; \
bogdanm 92:4fc01daae5a5 728 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 729 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 730
bogdanm 92:4fc01daae5a5 731 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
bogdanm 92:4fc01daae5a5 732 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 733 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 734 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 735 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 736 region.inner_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 737 region.outer_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 738 region.mem_t = NORMAL; \
bogdanm 92:4fc01daae5a5 739 region.sec_t = NON_SECURE; \
bogdanm 92:4fc01daae5a5 740 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 741 region.priv_t = READ; \
bogdanm 92:4fc01daae5a5 742 region.user_t = READ; \
bogdanm 92:4fc01daae5a5 743 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 744 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
bogdanm 92:4fc01daae5a5 747 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 748 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 749 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 750 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 751 region.inner_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 752 region.outer_norm_t = WB_WA; \
bogdanm 92:4fc01daae5a5 753 region.mem_t = NORMAL; \
bogdanm 92:4fc01daae5a5 754 region.sec_t = NON_SECURE; \
bogdanm 92:4fc01daae5a5 755 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 756 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 757 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 758 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 759 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 760 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
bogdanm 92:4fc01daae5a5 761 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 762 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 763 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 764 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 765 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 766 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 767 region.mem_t = STRONGLY_ORDERED; \
bogdanm 92:4fc01daae5a5 768 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 769 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 770 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 771 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 772 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 773 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 774
bogdanm 92:4fc01daae5a5 775 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
bogdanm 92:4fc01daae5a5 776 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 777 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 778 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 779 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 780 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 781 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 782 region.mem_t = STRONGLY_ORDERED; \
bogdanm 92:4fc01daae5a5 783 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 784 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 785 region.priv_t = READ; \
bogdanm 92:4fc01daae5a5 786 region.user_t = READ; \
bogdanm 92:4fc01daae5a5 787 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 788 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 789
bogdanm 92:4fc01daae5a5 790 //Sect_Device_RW. Sect_Device_RO, but writeable
bogdanm 92:4fc01daae5a5 791 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
bogdanm 92:4fc01daae5a5 792 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 793 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 794 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 795 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 796 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 797 region.mem_t = STRONGLY_ORDERED; \
bogdanm 92:4fc01daae5a5 798 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 799 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 800 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 801 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 802 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 803 __get_section_descriptor(&descriptor_l1, region);
bogdanm 92:4fc01daae5a5 804 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
bogdanm 92:4fc01daae5a5 805 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
bogdanm 92:4fc01daae5a5 806 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 807 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 808 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 809 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 810 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 811 region.mem_t = SHARED_DEVICE; \
bogdanm 92:4fc01daae5a5 812 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 813 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 814 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 815 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 816 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 817 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
bogdanm 92:4fc01daae5a5 818
bogdanm 92:4fc01daae5a5 819 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
bogdanm 92:4fc01daae5a5 820 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
bogdanm 92:4fc01daae5a5 821 region.domain = 0x0; \
bogdanm 92:4fc01daae5a5 822 region.e_t = ECC_DISABLED; \
bogdanm 92:4fc01daae5a5 823 region.g_t = GLOBAL; \
bogdanm 92:4fc01daae5a5 824 region.inner_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 825 region.outer_norm_t = NON_CACHEABLE; \
bogdanm 92:4fc01daae5a5 826 region.mem_t = SHARED_DEVICE; \
bogdanm 92:4fc01daae5a5 827 region.sec_t = SECURE; \
bogdanm 92:4fc01daae5a5 828 region.xn_t = NON_EXECUTE; \
bogdanm 92:4fc01daae5a5 829 region.priv_t = RW; \
bogdanm 92:4fc01daae5a5 830 region.user_t = RW; \
bogdanm 92:4fc01daae5a5 831 region.sh_t = NON_SHARED; \
bogdanm 92:4fc01daae5a5 832 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
bogdanm 92:4fc01daae5a5 833
bogdanm 92:4fc01daae5a5 834 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
bogdanm 92:4fc01daae5a5 835
bogdanm 92:4fc01daae5a5 836 /******************************************************************************/
bogdanm 92:4fc01daae5a5 837 /* Clock Settings */
bogdanm 92:4fc01daae5a5 838 /******************************************************************************/
bogdanm 92:4fc01daae5a5 839 /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
bogdanm 92:4fc01daae5a5 840 @{
bogdanm 92:4fc01daae5a5 841 */
bogdanm 92:4fc01daae5a5 842
bogdanm 92:4fc01daae5a5 843 /*
bogdanm 92:4fc01daae5a5 844 * Clock Mode 0 settings
bogdanm 92:4fc01daae5a5 845 * SW1-4(MD_CLK):ON
bogdanm 92:4fc01daae5a5 846 * SW1-5(MD_CLKS):ON
bogdanm 92:4fc01daae5a5 847 * FRQCR=0x1035
bogdanm 92:4fc01daae5a5 848 * CLKEN2 = 0b - unstable
bogdanm 92:4fc01daae5a5 849 * CLKEN[1:0]=01b - Output, Low, Low
bogdanm 92:4fc01daae5a5 850 * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
bogdanm 92:4fc01daae5a5 851 * FRQCR2=0x0001
bogdanm 92:4fc01daae5a5 852 * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
bogdanm 92:4fc01daae5a5 853 */
bogdanm 92:4fc01daae5a5 854 #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
bogdanm 92:4fc01daae5a5 855 #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
bogdanm 92:4fc01daae5a5 856 #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
bogdanm 92:4fc01daae5a5 857 #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
bogdanm 92:4fc01daae5a5 858 #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
bogdanm 92:4fc01daae5a5 859 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
bogdanm 92:4fc01daae5a5 860 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
bogdanm 92:4fc01daae5a5 861
bogdanm 92:4fc01daae5a5 862 /*
bogdanm 92:4fc01daae5a5 863 * Clock Mode 1 settings
bogdanm 92:4fc01daae5a5 864 * SW1-4(MD_CLK):OFF
bogdanm 92:4fc01daae5a5 865 * SW1-5(MD_CLKS):ON
bogdanm 92:4fc01daae5a5 866 * FRQCR=0x1335
bogdanm 92:4fc01daae5a5 867 * CLKEN2 = 0b - unstable
bogdanm 92:4fc01daae5a5 868 * CLKEN[1:0]=01b - Output, Low, Low
bogdanm 92:4fc01daae5a5 869 * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
bogdanm 92:4fc01daae5a5 870 * FRQCR2=0x0003
bogdanm 92:4fc01daae5a5 871 * GFC[1:0] =11b - graphic clock is 1/3 bus clock
bogdanm 92:4fc01daae5a5 872 */
bogdanm 92:4fc01daae5a5 873 #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
bogdanm 92:4fc01daae5a5 874 #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
bogdanm 92:4fc01daae5a5 875 #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
bogdanm 92:4fc01daae5a5 876 #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
bogdanm 92:4fc01daae5a5 877 #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
bogdanm 92:4fc01daae5a5 878 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
bogdanm 92:4fc01daae5a5 879 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
bogdanm 92:4fc01daae5a5 880
bogdanm 92:4fc01daae5a5 881 /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
bogdanm 92:4fc01daae5a5 882
bogdanm 92:4fc01daae5a5 883 /******************************************************************************/
bogdanm 92:4fc01daae5a5 884 /* CPG Settings */
bogdanm 92:4fc01daae5a5 885 /******************************************************************************/
bogdanm 92:4fc01daae5a5 886 /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
bogdanm 92:4fc01daae5a5 887 @{
bogdanm 92:4fc01daae5a5 888 */
bogdanm 92:4fc01daae5a5 889
bogdanm 92:4fc01daae5a5 890 #define CPG_FRQCR_SHIFT_CKOEN2 (14)
bogdanm 92:4fc01daae5a5 891 #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
bogdanm 92:4fc01daae5a5 892 #define CPG_FRQCR_SHIFT_CKOEN0 (12)
bogdanm 92:4fc01daae5a5 893 #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
bogdanm 92:4fc01daae5a5 894 #define CPG_FRQCR_SHIFT_IFC (8)
bogdanm 92:4fc01daae5a5 895 #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
bogdanm 92:4fc01daae5a5 896
bogdanm 92:4fc01daae5a5 897 #define CPG_FRQCR2_SHIFT_GFC (0)
bogdanm 92:4fc01daae5a5 898 #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
bogdanm 92:4fc01daae5a5 899
bogdanm 92:4fc01daae5a5 900
bogdanm 92:4fc01daae5a5 901 #define CPG_STBCR1_BIT_STBY (0x80u)
bogdanm 92:4fc01daae5a5 902 #define CPG_STBCR1_BIT_DEEP (0x40u)
bogdanm 92:4fc01daae5a5 903 #define CPG_STBCR2_BIT_HIZ (0x80u)
bogdanm 92:4fc01daae5a5 904 #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
bogdanm 92:4fc01daae5a5 905 #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
bogdanm 92:4fc01daae5a5 906 #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
bogdanm 92:4fc01daae5a5 907 #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
bogdanm 92:4fc01daae5a5 908 #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
bogdanm 92:4fc01daae5a5 909 #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
bogdanm 92:4fc01daae5a5 910 #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
bogdanm 92:4fc01daae5a5 911 #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
bogdanm 92:4fc01daae5a5 912 #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
bogdanm 92:4fc01daae5a5 913 #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
bogdanm 92:4fc01daae5a5 914 #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
bogdanm 92:4fc01daae5a5 915 #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
bogdanm 92:4fc01daae5a5 916 #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
bogdanm 92:4fc01daae5a5 917 #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
bogdanm 92:4fc01daae5a5 918 #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
bogdanm 92:4fc01daae5a5 919 #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
bogdanm 92:4fc01daae5a5 920 #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
bogdanm 92:4fc01daae5a5 921 #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
bogdanm 92:4fc01daae5a5 922 #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
bogdanm 92:4fc01daae5a5 923 #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
bogdanm 92:4fc01daae5a5 924 #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
bogdanm 92:4fc01daae5a5 925 #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
bogdanm 92:4fc01daae5a5 926 #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
bogdanm 92:4fc01daae5a5 927 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
bogdanm 92:4fc01daae5a5 928 #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
bogdanm 92:4fc01daae5a5 929 #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
bogdanm 92:4fc01daae5a5 930 #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
bogdanm 92:4fc01daae5a5 931 #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
bogdanm 92:4fc01daae5a5 932 #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
bogdanm 92:4fc01daae5a5 933 #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
bogdanm 92:4fc01daae5a5 934 #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
bogdanm 92:4fc01daae5a5 935 #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
bogdanm 92:4fc01daae5a5 936 #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
bogdanm 92:4fc01daae5a5 937 #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
bogdanm 92:4fc01daae5a5 938 #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
bogdanm 92:4fc01daae5a5 939 #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
bogdanm 92:4fc01daae5a5 940 #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
bogdanm 92:4fc01daae5a5 941 #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
bogdanm 92:4fc01daae5a5 942 #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
bogdanm 92:4fc01daae5a5 943 #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
bogdanm 92:4fc01daae5a5 944 #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
bogdanm 92:4fc01daae5a5 945 #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
bogdanm 92:4fc01daae5a5 946 #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
bogdanm 92:4fc01daae5a5 947 #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
bogdanm 92:4fc01daae5a5 948 #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
bogdanm 92:4fc01daae5a5 949 #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
bogdanm 92:4fc01daae5a5 950 #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
bogdanm 92:4fc01daae5a5 951 #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
bogdanm 92:4fc01daae5a5 952 #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
bogdanm 92:4fc01daae5a5 953 #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
bogdanm 92:4fc01daae5a5 954 #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
bogdanm 92:4fc01daae5a5 955 #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
bogdanm 92:4fc01daae5a5 956 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
bogdanm 92:4fc01daae5a5 957 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
bogdanm 92:4fc01daae5a5 958 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
bogdanm 92:4fc01daae5a5 959 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
bogdanm 92:4fc01daae5a5 960 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
bogdanm 92:4fc01daae5a5 961 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
bogdanm 92:4fc01daae5a5 962 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
bogdanm 92:4fc01daae5a5 963 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
bogdanm 92:4fc01daae5a5 964 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
bogdanm 92:4fc01daae5a5 965 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
bogdanm 92:4fc01daae5a5 966 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
bogdanm 92:4fc01daae5a5 967 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
bogdanm 92:4fc01daae5a5 968 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
bogdanm 92:4fc01daae5a5 969 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
bogdanm 92:4fc01daae5a5 970 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
bogdanm 92:4fc01daae5a5 971 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
bogdanm 92:4fc01daae5a5 972 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
bogdanm 92:4fc01daae5a5 973 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
bogdanm 92:4fc01daae5a5 974 #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
bogdanm 92:4fc01daae5a5 975 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
bogdanm 92:4fc01daae5a5 976 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
bogdanm 92:4fc01daae5a5 977 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
bogdanm 92:4fc01daae5a5 978 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
bogdanm 92:4fc01daae5a5 979 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
bogdanm 92:4fc01daae5a5 980 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
bogdanm 92:4fc01daae5a5 981 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
bogdanm 92:4fc01daae5a5 982 #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
bogdanm 92:4fc01daae5a5 983 #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
bogdanm 92:4fc01daae5a5 984 #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
bogdanm 92:4fc01daae5a5 985 #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
bogdanm 92:4fc01daae5a5 986 #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
bogdanm 92:4fc01daae5a5 987 #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
bogdanm 92:4fc01daae5a5 988 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
bogdanm 92:4fc01daae5a5 989 #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
bogdanm 92:4fc01daae5a5 990 #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
bogdanm 92:4fc01daae5a5 991 #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
bogdanm 92:4fc01daae5a5 992 #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
bogdanm 92:4fc01daae5a5 993 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
bogdanm 92:4fc01daae5a5 994 #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
bogdanm 92:4fc01daae5a5 995 #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
bogdanm 92:4fc01daae5a5 996 #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
bogdanm 92:4fc01daae5a5 997 #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
bogdanm 92:4fc01daae5a5 998 #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
bogdanm 92:4fc01daae5a5 999 #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
bogdanm 92:4fc01daae5a5 1000 #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
bogdanm 92:4fc01daae5a5 1001 #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
bogdanm 92:4fc01daae5a5 1002 #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
bogdanm 92:4fc01daae5a5 1003 #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
bogdanm 92:4fc01daae5a5 1004 #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
bogdanm 92:4fc01daae5a5 1005 #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
bogdanm 92:4fc01daae5a5 1006 #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
bogdanm 92:4fc01daae5a5 1007 #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
bogdanm 92:4fc01daae5a5 1008 #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
bogdanm 92:4fc01daae5a5 1009 #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
bogdanm 92:4fc01daae5a5 1010 #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
bogdanm 92:4fc01daae5a5 1011
bogdanm 92:4fc01daae5a5 1012 /*@}*/ /* end of group Renesas_RZ_A1_CPG */
bogdanm 92:4fc01daae5a5 1013
bogdanm 92:4fc01daae5a5 1014 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1015 /* GPIO Settings */
bogdanm 92:4fc01daae5a5 1016 /******************************************************************************/
bogdanm 92:4fc01daae5a5 1017 /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
bogdanm 92:4fc01daae5a5 1018 @{
bogdanm 92:4fc01daae5a5 1019 */
bogdanm 92:4fc01daae5a5 1020
bogdanm 92:4fc01daae5a5 1021 #define GPIO_BIT_N0 (1u << 0)
bogdanm 92:4fc01daae5a5 1022 #define GPIO_BIT_N1 (1u << 1)
bogdanm 92:4fc01daae5a5 1023 #define GPIO_BIT_N2 (1u << 2)
bogdanm 92:4fc01daae5a5 1024 #define GPIO_BIT_N3 (1u << 3)
bogdanm 92:4fc01daae5a5 1025 #define GPIO_BIT_N4 (1u << 4)
bogdanm 92:4fc01daae5a5 1026 #define GPIO_BIT_N5 (1u << 5)
bogdanm 92:4fc01daae5a5 1027 #define GPIO_BIT_N6 (1u << 6)
bogdanm 92:4fc01daae5a5 1028 #define GPIO_BIT_N7 (1u << 7)
bogdanm 92:4fc01daae5a5 1029 #define GPIO_BIT_N8 (1u << 8)
bogdanm 92:4fc01daae5a5 1030 #define GPIO_BIT_N9 (1u << 9)
bogdanm 92:4fc01daae5a5 1031 #define GPIO_BIT_N10 (1u << 10)
bogdanm 92:4fc01daae5a5 1032 #define GPIO_BIT_N11 (1u << 11)
bogdanm 92:4fc01daae5a5 1033 #define GPIO_BIT_N12 (1u << 12)
bogdanm 92:4fc01daae5a5 1034 #define GPIO_BIT_N13 (1u << 13)
bogdanm 92:4fc01daae5a5 1035 #define GPIO_BIT_N14 (1u << 14)
bogdanm 92:4fc01daae5a5 1036 #define GPIO_BIT_N15 (1u << 15)
bogdanm 92:4fc01daae5a5 1037
bogdanm 92:4fc01daae5a5 1038
bogdanm 92:4fc01daae5a5 1039 #define MD_BOOT10_MASK (0x3)
bogdanm 92:4fc01daae5a5 1040
bogdanm 92:4fc01daae5a5 1041 #define MD_BOOT10_BM0 (0x0)
bogdanm 92:4fc01daae5a5 1042 #define MD_BOOT10_BM1 (0x2)
bogdanm 92:4fc01daae5a5 1043 #define MD_BOOT10_BM3 (0x1)
bogdanm 92:4fc01daae5a5 1044 #define MD_BOOT10_BM4_5 (0x3)
bogdanm 92:4fc01daae5a5 1045
bogdanm 92:4fc01daae5a5 1046 #define MD_CLK (1u << 2)
bogdanm 92:4fc01daae5a5 1047 #define MD_CLKS (1u << 3)
bogdanm 92:4fc01daae5a5 1048
bogdanm 92:4fc01daae5a5 1049 /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
bogdanm 92:4fc01daae5a5 1050
bogdanm 92:4fc01daae5a5 1051 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 1052 }
bogdanm 92:4fc01daae5a5 1053 #endif
bogdanm 92:4fc01daae5a5 1054
bogdanm 92:4fc01daae5a5 1055 #endif // __MBRZA1H_H__