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TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:: bogdanm
Date:: Thu Nov 27 13:33:22 2014 +0000
Revision:: 92:4fc01daae5a5
Parent:: 86:04dd9b1680ae

Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f3xx_hal_rcc.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 12-Sept-2014
bogdanm	86:04dd9b1680ae	7	* @brief Header file of RCC HAL module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
bogdanm	86:04dd9b1680ae	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F3xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F3xx_HAL_RCC_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f3xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	86:04dd9b1680ae	53	/** @addtogroup RCC
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
bogdanm	86:04dd9b1680ae	57	/* Exported types ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	58
bogdanm	92:4fc01daae5a5	59	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	92:4fc01daae5a5	60	* @{
bogdanm	86:04dd9b1680ae	61	*/
bogdanm	86:04dd9b1680ae	62
bogdanm	86:04dd9b1680ae	63	/**
bogdanm	86:04dd9b1680ae	64	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	86:04dd9b1680ae	65	*/
bogdanm	86:04dd9b1680ae	66	typedef struct
bogdanm	86:04dd9b1680ae	67	{
bogdanm	86:04dd9b1680ae	68	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	86:04dd9b1680ae	69	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	86:04dd9b1680ae	70
bogdanm	86:04dd9b1680ae	71	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	86:04dd9b1680ae	72	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	86:04dd9b1680ae	73
bogdanm	86:04dd9b1680ae	74	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	86:04dd9b1680ae	75	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	86:04dd9b1680ae	76
bogdanm	86:04dd9b1680ae	77	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	86:04dd9b1680ae	78	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	86:04dd9b1680ae	79
bogdanm	86:04dd9b1680ae	80	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	86:04dd9b1680ae	81	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	86:04dd9b1680ae	82
bogdanm	86:04dd9b1680ae	83	}RCC_ClkInitTypeDef;
bogdanm	86:04dd9b1680ae	84
bogdanm	92:4fc01daae5a5	85	/**
bogdanm	92:4fc01daae5a5	86	* @}
bogdanm	92:4fc01daae5a5	87	*/
bogdanm	92:4fc01daae5a5	88
bogdanm	86:04dd9b1680ae	89	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	90	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	86:04dd9b1680ae	91	* @{
bogdanm	86:04dd9b1680ae	92	*/
bogdanm	86:04dd9b1680ae	93
bogdanm	92:4fc01daae5a5	94	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
bogdanm	86:04dd9b1680ae	95	* @brief RCC registers bit address in the alias region
bogdanm	86:04dd9b1680ae	96	* @{
bogdanm	86:04dd9b1680ae	97	*/
bogdanm	86:04dd9b1680ae	98	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	86:04dd9b1680ae	99	/* --- CR Register ---*/
bogdanm	86:04dd9b1680ae	100	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	86:04dd9b1680ae	101	/* Alias word address of HSION bit */
bogdanm	86:04dd9b1680ae	102	#define HSION_BitNumber 0
bogdanm	86:04dd9b1680ae	103	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm	86:04dd9b1680ae	104	/* Alias word address of HSEON bit */
bogdanm	86:04dd9b1680ae	105	#define HSEON_BitNumber 16
bogdanm	86:04dd9b1680ae	106	#define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	107	/* Alias word address of CSSON bit */
bogdanm	86:04dd9b1680ae	108	#define CSSON_BitNumber 19
bogdanm	86:04dd9b1680ae	109	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	110	/* Alias word address of PLLON bit */
bogdanm	86:04dd9b1680ae	111	#define PLLON_BitNumber 24
bogdanm	86:04dd9b1680ae	112	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	113
bogdanm	86:04dd9b1680ae	114	/* --- CFGR Register ---*/
bogdanm	86:04dd9b1680ae	115	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
bogdanm	86:04dd9b1680ae	116	/* Alias word address of PLLSRC bit */
bogdanm	86:04dd9b1680ae	117	#define PLLSRC_BitNumber 16
bogdanm	86:04dd9b1680ae	118	#define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
bogdanm	86:04dd9b1680ae	119
bogdanm	86:04dd9b1680ae	120	/* --- CIR Register ---*/
bogdanm	86:04dd9b1680ae	121	#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	86:04dd9b1680ae	122
bogdanm	86:04dd9b1680ae	123	/* --- BDCR Register ---*/
bogdanm	86:04dd9b1680ae	124	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
bogdanm	86:04dd9b1680ae	125	/* Alias word address of LSEON bit */
bogdanm	86:04dd9b1680ae	126	#define LSEON_BitNumber 0
bogdanm	86:04dd9b1680ae	127	#define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
bogdanm	86:04dd9b1680ae	128	/* Alias word address of RTCEN bit */
bogdanm	86:04dd9b1680ae	129	#define RTCEN_BitNumber 15
bogdanm	86:04dd9b1680ae	130	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm	86:04dd9b1680ae	131	/* Alias word address of BDRST bit */
bogdanm	86:04dd9b1680ae	132	#define BDRST_BitNumber 16
bogdanm	86:04dd9b1680ae	133	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm	86:04dd9b1680ae	134
bogdanm	86:04dd9b1680ae	135	/* --- CSR Register ---*/
bogdanm	86:04dd9b1680ae	136	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
bogdanm	86:04dd9b1680ae	137	/* Alias word address of LSION bit */
bogdanm	86:04dd9b1680ae	138	#define LSION_BitNumber 0
bogdanm	86:04dd9b1680ae	139	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm	86:04dd9b1680ae	140	/* Alias word address of RMVF bit */
bogdanm	86:04dd9b1680ae	141	#define RMVF_BitNumber 24
bogdanm	86:04dd9b1680ae	142	#define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
bogdanm	86:04dd9b1680ae	143
bogdanm	86:04dd9b1680ae	144	/* CR register byte 2 (Bits[23:16]) base address */
bogdanm	86:04dd9b1680ae	145	#define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
bogdanm	86:04dd9b1680ae	146
bogdanm	86:04dd9b1680ae	147	/* CIR register byte 1 (Bits[15:8]) base address */
bogdanm	86:04dd9b1680ae	148	#define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
bogdanm	86:04dd9b1680ae	149
bogdanm	86:04dd9b1680ae	150	/* CIR register byte 2 (Bits[23:16]) base address */
bogdanm	86:04dd9b1680ae	151	#define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
bogdanm	86:04dd9b1680ae	152
bogdanm	86:04dd9b1680ae	153	/* CSR register byte 1 (Bits[15:8]) base address */
bogdanm	86:04dd9b1680ae	154	#define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
bogdanm	86:04dd9b1680ae	155
bogdanm	86:04dd9b1680ae	156	/* BDCR register byte 0 (Bits[7:0] base address */
bogdanm	86:04dd9b1680ae	157	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm	86:04dd9b1680ae	158
bogdanm	92:4fc01daae5a5	159	/**
bogdanm	92:4fc01daae5a5	160	* @}
bogdanm	92:4fc01daae5a5	161	*/
bogdanm	92:4fc01daae5a5	162
bogdanm	92:4fc01daae5a5	163	/** @defgroup RCC_Timeout RCC Timeout
bogdanm	92:4fc01daae5a5	164	* @{
bogdanm	92:4fc01daae5a5	165	*/
bogdanm	86:04dd9b1680ae	166	/* LSE state change timeout */
bogdanm	86:04dd9b1680ae	167	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	86:04dd9b1680ae	168
bogdanm	86:04dd9b1680ae	169	/* Disable Backup domain write protection state change timeout */
bogdanm	86:04dd9b1680ae	170	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	86:04dd9b1680ae	171	/**
bogdanm	86:04dd9b1680ae	172	* @}
bogdanm	86:04dd9b1680ae	173	*/
bogdanm	86:04dd9b1680ae	174
bogdanm	92:4fc01daae5a5	175	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
bogdanm	86:04dd9b1680ae	176	* @{
bogdanm	86:04dd9b1680ae	177	*/
bogdanm	86:04dd9b1680ae	178	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	179	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	180	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	181	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	182	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	183
bogdanm	86:04dd9b1680ae	184	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	86:04dd9b1680ae	185	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	86:04dd9b1680ae	186	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	187	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	86:04dd9b1680ae	188	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
bogdanm	86:04dd9b1680ae	189	/**
bogdanm	86:04dd9b1680ae	190	* @}
bogdanm	86:04dd9b1680ae	191	*/
bogdanm	86:04dd9b1680ae	192
bogdanm	92:4fc01daae5a5	193	/** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm	86:04dd9b1680ae	194	* @{
bogdanm	86:04dd9b1680ae	195	*/
bogdanm	86:04dd9b1680ae	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	197	#define RCC_HSE_ON ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	198	#define RCC_HSE_BYPASS ((uint32_t)0x00000005)
bogdanm	86:04dd9b1680ae	199
bogdanm	86:04dd9b1680ae	200	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
bogdanm	86:04dd9b1680ae	201	((HSE) == RCC_HSE_BYPASS))
bogdanm	86:04dd9b1680ae	202	/**
bogdanm	86:04dd9b1680ae	203	* @}
bogdanm	86:04dd9b1680ae	204	*/
bogdanm	86:04dd9b1680ae	205
bogdanm	92:4fc01daae5a5	206	/** @defgroup RCC_LSE_Config RCC_LSE_Config
bogdanm	86:04dd9b1680ae	207	* @{
bogdanm	86:04dd9b1680ae	208	*/
bogdanm	86:04dd9b1680ae	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	210	#define RCC_LSE_ON ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	211	#define RCC_LSE_BYPASS ((uint32_t)0x00000005)
bogdanm	86:04dd9b1680ae	212
bogdanm	86:04dd9b1680ae	213	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
bogdanm	86:04dd9b1680ae	214	((LSE) == RCC_LSE_BYPASS))
bogdanm	86:04dd9b1680ae	215	/**
bogdanm	86:04dd9b1680ae	216	* @}
bogdanm	86:04dd9b1680ae	217	*/
bogdanm	86:04dd9b1680ae	218
bogdanm	92:4fc01daae5a5	219	/** @defgroup RCC_HSI_Config RCC HSI Config
bogdanm	86:04dd9b1680ae	220	* @{
bogdanm	86:04dd9b1680ae	221	*/
bogdanm	86:04dd9b1680ae	222	#define RCC_HSI_OFF ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	223	#define RCC_HSI_ON ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	224
bogdanm	86:04dd9b1680ae	225	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
bogdanm	92:4fc01daae5a5	226
bogdanm	92:4fc01daae5a5	227	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	92:4fc01daae5a5	228
bogdanm	92:4fc01daae5a5	229	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm	86:04dd9b1680ae	230	/**
bogdanm	86:04dd9b1680ae	231	* @}
bogdanm	86:04dd9b1680ae	232	*/
bogdanm	86:04dd9b1680ae	233
bogdanm	92:4fc01daae5a5	234	/** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm	86:04dd9b1680ae	235	* @{
bogdanm	86:04dd9b1680ae	236	*/
bogdanm	86:04dd9b1680ae	237	#define RCC_LSI_OFF ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	238	#define RCC_LSI_ON ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	239
bogdanm	86:04dd9b1680ae	240	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
bogdanm	86:04dd9b1680ae	241	/**
bogdanm	86:04dd9b1680ae	242	* @}
bogdanm	86:04dd9b1680ae	243	*/
bogdanm	86:04dd9b1680ae	244
bogdanm	92:4fc01daae5a5	245	/** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm	86:04dd9b1680ae	246	* @{
bogdanm	86:04dd9b1680ae	247	*/
bogdanm	86:04dd9b1680ae	248	#define RCC_PLL_NONE ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	249	#define RCC_PLL_OFF ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	250	#define RCC_PLL_ON ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	251
bogdanm	86:04dd9b1680ae	252	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
bogdanm	86:04dd9b1680ae	253	/**
bogdanm	86:04dd9b1680ae	254	* @}
bogdanm	86:04dd9b1680ae	255	*/
bogdanm	86:04dd9b1680ae	256
bogdanm	92:4fc01daae5a5	257	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm	86:04dd9b1680ae	258	* @{
bogdanm	86:04dd9b1680ae	259	*/
bogdanm	86:04dd9b1680ae	260	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm	86:04dd9b1680ae	261	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm	86:04dd9b1680ae	262	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm	86:04dd9b1680ae	263	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm	86:04dd9b1680ae	264	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm	86:04dd9b1680ae	265	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm	86:04dd9b1680ae	266	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm	86:04dd9b1680ae	267	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm	86:04dd9b1680ae	268	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm	86:04dd9b1680ae	269	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm	86:04dd9b1680ae	270	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm	86:04dd9b1680ae	271	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm	86:04dd9b1680ae	272	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm	86:04dd9b1680ae	273	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm	86:04dd9b1680ae	274	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm	86:04dd9b1680ae	275
bogdanm	86:04dd9b1680ae	276	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) \|\| ((MUL) == RCC_PLL_MUL3) \|\| \
bogdanm	86:04dd9b1680ae	277	((MUL) == RCC_PLL_MUL4) \|\| ((MUL) == RCC_PLL_MUL5) \|\| \
bogdanm	86:04dd9b1680ae	278	((MUL) == RCC_PLL_MUL6) \|\| ((MUL) == RCC_PLL_MUL7) \|\| \
bogdanm	86:04dd9b1680ae	279	((MUL) == RCC_PLL_MUL8) \|\| ((MUL) == RCC_PLL_MUL9) \|\| \
bogdanm	86:04dd9b1680ae	280	((MUL) == RCC_PLL_MUL10) \|\| ((MUL) == RCC_PLL_MUL11) \|\| \
bogdanm	86:04dd9b1680ae	281	((MUL) == RCC_PLL_MUL12) \|\| ((MUL) == RCC_PLL_MUL13) \|\| \
bogdanm	86:04dd9b1680ae	282	((MUL) == RCC_PLL_MUL14) \|\| ((MUL) == RCC_PLL_MUL15) \|\| \
bogdanm	86:04dd9b1680ae	283	((MUL) == RCC_PLL_MUL16))
bogdanm	86:04dd9b1680ae	284	/**
bogdanm	86:04dd9b1680ae	285	* @}
bogdanm	86:04dd9b1680ae	286	*/
bogdanm	86:04dd9b1680ae	287
bogdanm	92:4fc01daae5a5	288	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm	86:04dd9b1680ae	289	* @{
bogdanm	86:04dd9b1680ae	290	*/
bogdanm	86:04dd9b1680ae	291	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	292	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	293	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	294	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	295
bogdanm	86:04dd9b1680ae	296	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	297	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	298	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	299	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
bogdanm	86:04dd9b1680ae	300	/**
bogdanm	86:04dd9b1680ae	301	* @}
bogdanm	86:04dd9b1680ae	302	*/
bogdanm	86:04dd9b1680ae	303
bogdanm	92:4fc01daae5a5	304	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm	86:04dd9b1680ae	305	* @{
bogdanm	86:04dd9b1680ae	306	*/
bogdanm	86:04dd9b1680ae	307	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm	86:04dd9b1680ae	308	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm	86:04dd9b1680ae	309	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm	86:04dd9b1680ae	310
bogdanm	86:04dd9b1680ae	311	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	312	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	86:04dd9b1680ae	313	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	86:04dd9b1680ae	314	/**
bogdanm	86:04dd9b1680ae	315	* @}
bogdanm	86:04dd9b1680ae	316	*/
bogdanm	86:04dd9b1680ae	317
bogdanm	92:4fc01daae5a5	318	/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
bogdanm	86:04dd9b1680ae	319	* @{
bogdanm	86:04dd9b1680ae	320	*/
bogdanm	86:04dd9b1680ae	321	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm	86:04dd9b1680ae	322	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm	86:04dd9b1680ae	323	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm	86:04dd9b1680ae	324
bogdanm	86:04dd9b1680ae	325	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	86:04dd9b1680ae	326	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	86:04dd9b1680ae	327	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
bogdanm	86:04dd9b1680ae	328	/**
bogdanm	86:04dd9b1680ae	329	* @}
bogdanm	86:04dd9b1680ae	330	*/
bogdanm	86:04dd9b1680ae	331
bogdanm	92:4fc01daae5a5	332	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
bogdanm	86:04dd9b1680ae	333	* @{
bogdanm	86:04dd9b1680ae	334	*/
bogdanm	86:04dd9b1680ae	335	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm	86:04dd9b1680ae	336	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm	86:04dd9b1680ae	337	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm	86:04dd9b1680ae	338	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm	86:04dd9b1680ae	339	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm	86:04dd9b1680ae	340	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm	86:04dd9b1680ae	341	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm	86:04dd9b1680ae	342	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm	86:04dd9b1680ae	343	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm	86:04dd9b1680ae	344
bogdanm	86:04dd9b1680ae	345	#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) \|\| ((DIV) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	346	((DIV) == RCC_SYSCLK_DIV4) \|\| ((DIV) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	347	((DIV) == RCC_SYSCLK_DIV16) \|\| ((DIV) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	86:04dd9b1680ae	348	((DIV) == RCC_SYSCLK_DIV128) \|\| ((DIV) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	86:04dd9b1680ae	349	((DIV) == RCC_SYSCLK_DIV512))
bogdanm	86:04dd9b1680ae	350	/**
bogdanm	86:04dd9b1680ae	351	* @}
bogdanm	86:04dd9b1680ae	352	*/
bogdanm	86:04dd9b1680ae	353
bogdanm	92:4fc01daae5a5	354	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
bogdanm	86:04dd9b1680ae	355	* @{
bogdanm	86:04dd9b1680ae	356	*/
bogdanm	86:04dd9b1680ae	357	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm	86:04dd9b1680ae	358	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm	86:04dd9b1680ae	359	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm	86:04dd9b1680ae	360	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm	86:04dd9b1680ae	361	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm	86:04dd9b1680ae	362
bogdanm	86:04dd9b1680ae	363	#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) \|\| ((DIV) == RCC_HCLK_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	364	((DIV) == RCC_HCLK_DIV4) \|\| ((DIV) == RCC_HCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	365	((DIV) == RCC_HCLK_DIV16))
bogdanm	86:04dd9b1680ae	366	/**
bogdanm	86:04dd9b1680ae	367	* @}
bogdanm	86:04dd9b1680ae	368	*/
bogdanm	86:04dd9b1680ae	369
bogdanm	92:4fc01daae5a5	370	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm	86:04dd9b1680ae	371	* @{
bogdanm	86:04dd9b1680ae	372	*/
bogdanm	86:04dd9b1680ae	373	#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
bogdanm	86:04dd9b1680ae	374	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
bogdanm	86:04dd9b1680ae	375	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
bogdanm	86:04dd9b1680ae	376	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
bogdanm	86:04dd9b1680ae	377
bogdanm	86:04dd9b1680ae	378	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) \|\| \
bogdanm	86:04dd9b1680ae	379	((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	380	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
bogdanm	86:04dd9b1680ae	381	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm	86:04dd9b1680ae	382	/**
bogdanm	86:04dd9b1680ae	383	* @}
bogdanm	86:04dd9b1680ae	384	*/
bogdanm	86:04dd9b1680ae	385
bogdanm	92:4fc01daae5a5	386	/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
bogdanm	86:04dd9b1680ae	387	* @{
bogdanm	86:04dd9b1680ae	388	*/
bogdanm	86:04dd9b1680ae	389	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	86:04dd9b1680ae	390	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	86:04dd9b1680ae	391	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	86:04dd9b1680ae	392	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	86:04dd9b1680ae	393
bogdanm	86:04dd9b1680ae	394	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	395	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	396	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	397	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	398	/**
bogdanm	86:04dd9b1680ae	399	* @}
bogdanm	86:04dd9b1680ae	400	*/
bogdanm	86:04dd9b1680ae	401
bogdanm	92:4fc01daae5a5	402	/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
bogdanm	86:04dd9b1680ae	403	* @{
bogdanm	86:04dd9b1680ae	404	*/
bogdanm	86:04dd9b1680ae	405	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	86:04dd9b1680ae	406	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	86:04dd9b1680ae	407	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	86:04dd9b1680ae	408	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	86:04dd9b1680ae	409
bogdanm	86:04dd9b1680ae	410	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	411	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	412	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	413	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	414	/**
bogdanm	86:04dd9b1680ae	415	* @}
bogdanm	86:04dd9b1680ae	416	*/
bogdanm	86:04dd9b1680ae	417
bogdanm	92:4fc01daae5a5	418	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm	86:04dd9b1680ae	419	* @{
bogdanm	86:04dd9b1680ae	420	*/
bogdanm	86:04dd9b1680ae	421	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm	86:04dd9b1680ae	422	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm	86:04dd9b1680ae	423
bogdanm	86:04dd9b1680ae	424	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	425	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
bogdanm	86:04dd9b1680ae	426	/**
bogdanm	86:04dd9b1680ae	427	* @}
bogdanm	86:04dd9b1680ae	428	*/
bogdanm	86:04dd9b1680ae	429
bogdanm	92:4fc01daae5a5	430	/** @defgroup RCC_MCOx_Index RCC MCOx Index
bogdanm	86:04dd9b1680ae	431	* @{
bogdanm	86:04dd9b1680ae	432	*/
bogdanm	86:04dd9b1680ae	433	#define RCC_MCO ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	434
bogdanm	86:04dd9b1680ae	435	#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
bogdanm	86:04dd9b1680ae	436	/**
bogdanm	86:04dd9b1680ae	437	* @}
bogdanm	86:04dd9b1680ae	438	*/
bogdanm	86:04dd9b1680ae	439
bogdanm	92:4fc01daae5a5	440	/** @defgroup RCC_Interrupt RCC Interrupt
bogdanm	86:04dd9b1680ae	441	* @{
bogdanm	86:04dd9b1680ae	442	*/
bogdanm	86:04dd9b1680ae	443	#define RCC_IT_LSIRDY ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	444	#define RCC_IT_LSERDY ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	445	#define RCC_IT_HSIRDY ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	446	#define RCC_IT_HSERDY ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	447	#define RCC_IT_PLLRDY ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	448	#define RCC_IT_CSS ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	449	/**
bogdanm	86:04dd9b1680ae	450	* @}
bogdanm	86:04dd9b1680ae	451	*/
bogdanm	86:04dd9b1680ae	452
bogdanm	92:4fc01daae5a5	453	/** @defgroup RCC_Flag RCC Flag
bogdanm	86:04dd9b1680ae	454	* Elements values convention: 0XXYYYYYb
bogdanm	86:04dd9b1680ae	455	* - YYYYY : Flag position in the register
bogdanm	86:04dd9b1680ae	456	* - XX : Register index
bogdanm	86:04dd9b1680ae	457	* - 01: CR register
bogdanm	86:04dd9b1680ae	458	* - 10: BDCR register
bogdanm	86:04dd9b1680ae	459	* - 11: CSR register
bogdanm	86:04dd9b1680ae	460	* @{
bogdanm	86:04dd9b1680ae	461	*/
bogdanm	86:04dd9b1680ae	462	#define CR_REG_INDEX 1U
bogdanm	86:04dd9b1680ae	463	#define BDCR_REG_INDEX 2U
bogdanm	86:04dd9b1680ae	464	#define CSR_REG_INDEX 3U
bogdanm	86:04dd9b1680ae	465
bogdanm	86:04dd9b1680ae	466	/* Flags in the CR register */
bogdanm	86:04dd9b1680ae	467	#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
bogdanm	86:04dd9b1680ae	468	#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
bogdanm	86:04dd9b1680ae	469	#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
bogdanm	86:04dd9b1680ae	470
bogdanm	86:04dd9b1680ae	471	/* Flags in the BDCR register */
bogdanm	86:04dd9b1680ae	472	#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
bogdanm	86:04dd9b1680ae	473
bogdanm	86:04dd9b1680ae	474	/* Flags in the CSR register */
bogdanm	86:04dd9b1680ae	475	#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
bogdanm	86:04dd9b1680ae	476	#define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
bogdanm	86:04dd9b1680ae	477	#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
bogdanm	86:04dd9b1680ae	478	#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
bogdanm	86:04dd9b1680ae	479	#define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
bogdanm	86:04dd9b1680ae	480	#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
bogdanm	86:04dd9b1680ae	481	#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
bogdanm	86:04dd9b1680ae	482	#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
bogdanm	86:04dd9b1680ae	483	#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
bogdanm	86:04dd9b1680ae	484	/**
bogdanm	86:04dd9b1680ae	485	* @}
bogdanm	86:04dd9b1680ae	486	*/
bogdanm	86:04dd9b1680ae	487
bogdanm	86:04dd9b1680ae	488	/**
bogdanm	86:04dd9b1680ae	489	* @}
bogdanm	86:04dd9b1680ae	490	*/
bogdanm	86:04dd9b1680ae	491	/* Exported macro ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	492
bogdanm	92:4fc01daae5a5	493	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	92:4fc01daae5a5	494	* @{
bogdanm	92:4fc01daae5a5	495	*/
bogdanm	92:4fc01daae5a5	496
bogdanm	92:4fc01daae5a5	497	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm	92:4fc01daae5a5	498	* @brief Enable or disable the AHB peripheral clock.
bogdanm	86:04dd9b1680ae	499	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	500	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	501	* using it.
bogdanm	92:4fc01daae5a5	502	* @{
bogdanm	86:04dd9b1680ae	503	*/
bogdanm	86:04dd9b1680ae	504	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
bogdanm	86:04dd9b1680ae	505	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
bogdanm	86:04dd9b1680ae	506	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
bogdanm	86:04dd9b1680ae	507	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
bogdanm	86:04dd9b1680ae	508	#define __GPIOF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOFEN))
bogdanm	86:04dd9b1680ae	509	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
bogdanm	86:04dd9b1680ae	510	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
bogdanm	86:04dd9b1680ae	511	#define __SRAM_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_SRAMEN))
bogdanm	86:04dd9b1680ae	512	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
bogdanm	86:04dd9b1680ae	513	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
bogdanm	86:04dd9b1680ae	514
bogdanm	86:04dd9b1680ae	515	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
bogdanm	86:04dd9b1680ae	516	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
bogdanm	86:04dd9b1680ae	517	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
bogdanm	86:04dd9b1680ae	518	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	86:04dd9b1680ae	519	#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
bogdanm	86:04dd9b1680ae	520	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm	86:04dd9b1680ae	521	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm	86:04dd9b1680ae	522	#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm	86:04dd9b1680ae	523	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	86:04dd9b1680ae	524	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	92:4fc01daae5a5	525	/**
bogdanm	92:4fc01daae5a5	526	* @}
bogdanm	92:4fc01daae5a5	527	*/
bogdanm	86:04dd9b1680ae	528
bogdanm	92:4fc01daae5a5	529	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm	92:4fc01daae5a5	530	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	86:04dd9b1680ae	531	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	532	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	533	* using it.
bogdanm	92:4fc01daae5a5	534	* @{
bogdanm	86:04dd9b1680ae	535	*/
bogdanm	86:04dd9b1680ae	536	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	86:04dd9b1680ae	537	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	86:04dd9b1680ae	538	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	86:04dd9b1680ae	539	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	86:04dd9b1680ae	540	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
bogdanm	86:04dd9b1680ae	541	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	86:04dd9b1680ae	542	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
bogdanm	86:04dd9b1680ae	543	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC1EN))
bogdanm	86:04dd9b1680ae	544
bogdanm	86:04dd9b1680ae	545	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	86:04dd9b1680ae	546	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	86:04dd9b1680ae	547	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	86:04dd9b1680ae	548	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	86:04dd9b1680ae	549	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	86:04dd9b1680ae	550	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	86:04dd9b1680ae	551	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	86:04dd9b1680ae	552	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
bogdanm	92:4fc01daae5a5	553	/**
bogdanm	92:4fc01daae5a5	554	* @}
bogdanm	92:4fc01daae5a5	555	*/
bogdanm	92:4fc01daae5a5	556
bogdanm	92:4fc01daae5a5	557	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm	92:4fc01daae5a5	558	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	86:04dd9b1680ae	559	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	560	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	561	* using it.
bogdanm	92:4fc01daae5a5	562	* @{
bogdanm	86:04dd9b1680ae	563	*/
bogdanm	86:04dd9b1680ae	564	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
bogdanm	86:04dd9b1680ae	565	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
bogdanm	86:04dd9b1680ae	566	#define __TIM16_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM16EN))
bogdanm	86:04dd9b1680ae	567	#define __TIM17_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM17EN))
bogdanm	86:04dd9b1680ae	568	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	86:04dd9b1680ae	569
bogdanm	86:04dd9b1680ae	570	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm	86:04dd9b1680ae	571	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	86:04dd9b1680ae	572	#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
bogdanm	86:04dd9b1680ae	573	#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
bogdanm	86:04dd9b1680ae	574	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	92:4fc01daae5a5	575	/**
bogdanm	92:4fc01daae5a5	576	* @}
bogdanm	92:4fc01daae5a5	577	*/
bogdanm	86:04dd9b1680ae	578
bogdanm	92:4fc01daae5a5	579	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm	92:4fc01daae5a5	580	* @brief Force or release AHB peripheral reset.
bogdanm	92:4fc01daae5a5	581	* @{
bogdanm	86:04dd9b1680ae	582	*/
bogdanm	86:04dd9b1680ae	583	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	584	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
bogdanm	86:04dd9b1680ae	585	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
bogdanm	86:04dd9b1680ae	586	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
bogdanm	86:04dd9b1680ae	587	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	86:04dd9b1680ae	588	#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
bogdanm	86:04dd9b1680ae	589	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	86:04dd9b1680ae	590
bogdanm	86:04dd9b1680ae	591	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm	86:04dd9b1680ae	592	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
bogdanm	86:04dd9b1680ae	593	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
bogdanm	86:04dd9b1680ae	594	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
bogdanm	86:04dd9b1680ae	595	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	86:04dd9b1680ae	596	#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm	86:04dd9b1680ae	597	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	92:4fc01daae5a5	598	/**
bogdanm	92:4fc01daae5a5	599	* @}
bogdanm	92:4fc01daae5a5	600	*/
bogdanm	86:04dd9b1680ae	601
bogdanm	92:4fc01daae5a5	602	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm	92:4fc01daae5a5	603	* @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	604	* @{
bogdanm	86:04dd9b1680ae	605	*/
bogdanm	86:04dd9b1680ae	606	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	607	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	86:04dd9b1680ae	608	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	86:04dd9b1680ae	609	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	86:04dd9b1680ae	610	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	86:04dd9b1680ae	611	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	86:04dd9b1680ae	612	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	86:04dd9b1680ae	613	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	86:04dd9b1680ae	614	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC1RST))
bogdanm	86:04dd9b1680ae	615
bogdanm	86:04dd9b1680ae	616	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	86:04dd9b1680ae	617	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	86:04dd9b1680ae	618	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	86:04dd9b1680ae	619	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	86:04dd9b1680ae	620	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	86:04dd9b1680ae	621	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	86:04dd9b1680ae	622	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	86:04dd9b1680ae	623	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	86:04dd9b1680ae	624	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
bogdanm	92:4fc01daae5a5	625	/**
bogdanm	92:4fc01daae5a5	626	* @}
bogdanm	92:4fc01daae5a5	627	*/
bogdanm	86:04dd9b1680ae	628
bogdanm	92:4fc01daae5a5	629	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm	92:4fc01daae5a5	630	* @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	631	* @{
bogdanm	86:04dd9b1680ae	632	*/
bogdanm	86:04dd9b1680ae	633	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	86:04dd9b1680ae	634	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	86:04dd9b1680ae	635	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	86:04dd9b1680ae	636	#define __TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
bogdanm	86:04dd9b1680ae	637	#define __TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
bogdanm	86:04dd9b1680ae	638	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	86:04dd9b1680ae	639
bogdanm	86:04dd9b1680ae	640	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	86:04dd9b1680ae	641	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm	86:04dd9b1680ae	642	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	86:04dd9b1680ae	643	#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
bogdanm	86:04dd9b1680ae	644	#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
bogdanm	86:04dd9b1680ae	645	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	92:4fc01daae5a5	646	/**
bogdanm	92:4fc01daae5a5	647	* @}
bogdanm	92:4fc01daae5a5	648	*/
bogdanm	92:4fc01daae5a5	649
bogdanm	92:4fc01daae5a5	650	/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
bogdanm	92:4fc01daae5a5	651	* @{
bogdanm	92:4fc01daae5a5	652	*/
bogdanm	86:04dd9b1680ae	653
bogdanm	86:04dd9b1680ae	654	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	86:04dd9b1680ae	655	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	656	* It is used (enabled by hardware) as system clock source after startup
bogdanm	86:04dd9b1680ae	657	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	86:04dd9b1680ae	658	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	86:04dd9b1680ae	659	* Security System CSS is enabled).
bogdanm	86:04dd9b1680ae	660	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	86:04dd9b1680ae	661	* you have to select another source of the system clock then stop the HSI.
bogdanm	86:04dd9b1680ae	662	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	86:04dd9b1680ae	663	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	86:04dd9b1680ae	664	* system clock source.
bogdanm	86:04dd9b1680ae	665	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	86:04dd9b1680ae	666	* clock cycles.
bogdanm	86:04dd9b1680ae	667	*/
bogdanm	86:04dd9b1680ae	668	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t )CR_HSION_BB = ENABLE)
bogdanm	86:04dd9b1680ae	669	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t )CR_HSION_BB = DISABLE)
bogdanm	86:04dd9b1680ae	670
bogdanm	86:04dd9b1680ae	671
bogdanm	86:04dd9b1680ae	672	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	86:04dd9b1680ae	673	* @note The calibration is used to compensate for the variations in voltage
bogdanm	86:04dd9b1680ae	674	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	86:04dd9b1680ae	675	* @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm	86:04dd9b1680ae	676	* This parameter must be a number between 0 and 0x1F.
bogdanm	86:04dd9b1680ae	677	*/
bogdanm	86:04dd9b1680ae	678	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
bogdanm	86:04dd9b1680ae	679	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
bogdanm	92:4fc01daae5a5	680	/**
bogdanm	92:4fc01daae5a5	681	* @}
bogdanm	92:4fc01daae5a5	682	*/
bogdanm	86:04dd9b1680ae	683
bogdanm	92:4fc01daae5a5	684	/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
bogdanm	92:4fc01daae5a5	685	* @{
bogdanm	92:4fc01daae5a5	686	*/
bogdanm	86:04dd9b1680ae	687
bogdanm	86:04dd9b1680ae	688	/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	86:04dd9b1680ae	689	* @note After enabling the LSI, the application software should wait on
bogdanm	86:04dd9b1680ae	690	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	86:04dd9b1680ae	691	* be used to clock the IWDG and/or the RTC.
bogdanm	86:04dd9b1680ae	692	* @note LSI can not be disabled if the IWDG is running.
bogdanm	86:04dd9b1680ae	693	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	86:04dd9b1680ae	694	* clock cycles.
bogdanm	86:04dd9b1680ae	695	*/
bogdanm	86:04dd9b1680ae	696	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t )CSR_LSION_BB = ENABLE)
bogdanm	86:04dd9b1680ae	697	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t )CSR_LSION_BB = DISABLE)
bogdanm	92:4fc01daae5a5	698	/**
bogdanm	92:4fc01daae5a5	699	* @}
bogdanm	92:4fc01daae5a5	700	*/
bogdanm	92:4fc01daae5a5	701
bogdanm	92:4fc01daae5a5	702	/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
bogdanm	92:4fc01daae5a5	703	* @{
bogdanm	92:4fc01daae5a5	704	*/
bogdanm	86:04dd9b1680ae	705
bogdanm	86:04dd9b1680ae	706	/**
bogdanm	86:04dd9b1680ae	707	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	86:04dd9b1680ae	708	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	86:04dd9b1680ae	709	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	86:04dd9b1680ae	710	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	86:04dd9b1680ae	711	* @note HSE state can not be changed if it is used directly or through the
bogdanm	86:04dd9b1680ae	712	* PLL as system clock. In this case, you have to select another source
bogdanm	86:04dd9b1680ae	713	* of the system clock then change the HSE state (ex. disable it).
bogdanm	86:04dd9b1680ae	714	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	715	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm	86:04dd9b1680ae	716	* was previously enabled you have to enable it again after calling this
bogdanm	86:04dd9b1680ae	717	* function.
bogdanm	86:04dd9b1680ae	718	* @param __STATE__: specifies the new state of the HSE.
bogdanm	86:04dd9b1680ae	719	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	720	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	86:04dd9b1680ae	721	* 6 HSE oscillator clock cycles.
bogdanm	86:04dd9b1680ae	722	* @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm	86:04dd9b1680ae	723	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm	86:04dd9b1680ae	724	*/
bogdanm	86:04dd9b1680ae	725	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t )CR_BYTE2_ADDRESS = (__STATE__))
bogdanm	92:4fc01daae5a5	726	/**
bogdanm	92:4fc01daae5a5	727	* @}
bogdanm	92:4fc01daae5a5	728	*/
bogdanm	86:04dd9b1680ae	729
bogdanm	92:4fc01daae5a5	730	/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
bogdanm	92:4fc01daae5a5	731	* @{
bogdanm	92:4fc01daae5a5	732	*/
bogdanm	86:04dd9b1680ae	733	/**
bogdanm	86:04dd9b1680ae	734	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	86:04dd9b1680ae	735	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	86:04dd9b1680ae	736	* this domain after reset, you have to enable write access using
bogdanm	86:04dd9b1680ae	737	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	86:04dd9b1680ae	738	* (to be done once after reset).
bogdanm	86:04dd9b1680ae	739	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	86:04dd9b1680ae	740	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	86:04dd9b1680ae	741	* is stable and can be used to clock the RTC.
bogdanm	86:04dd9b1680ae	742	* @param __STATE__: specifies the new state of the LSE.
bogdanm	86:04dd9b1680ae	743	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	744	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	86:04dd9b1680ae	745	* 6 LSE oscillator clock cycles.
bogdanm	86:04dd9b1680ae	746	* @arg RCC_LSE_ON: turn ON the LSE oscillator
bogdanm	86:04dd9b1680ae	747	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
bogdanm	86:04dd9b1680ae	748	*/
bogdanm	86:04dd9b1680ae	749	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm	86:04dd9b1680ae	750	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON\|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
bogdanm	92:4fc01daae5a5	751	/**
bogdanm	92:4fc01daae5a5	752	* @}
bogdanm	92:4fc01daae5a5	753	*/
bogdanm	86:04dd9b1680ae	754
bogdanm	92:4fc01daae5a5	755	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
bogdanm	92:4fc01daae5a5	756	* @{
bogdanm	92:4fc01daae5a5	757	*/
bogdanm	86:04dd9b1680ae	758	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	86:04dd9b1680ae	759	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	86:04dd9b1680ae	760	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	761	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	86:04dd9b1680ae	762	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	86:04dd9b1680ae	763	*/
bogdanm	86:04dd9b1680ae	764	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	86:04dd9b1680ae	765	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm	86:04dd9b1680ae	766
bogdanm	86:04dd9b1680ae	767	/** @brief Macro to get the I2C1 clock source.
bogdanm	86:04dd9b1680ae	768	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	769	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	86:04dd9b1680ae	770	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	86:04dd9b1680ae	771	*/
bogdanm	86:04dd9b1680ae	772	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm	92:4fc01daae5a5	773	/**
bogdanm	92:4fc01daae5a5	774	* @}
bogdanm	92:4fc01daae5a5	775	*/
bogdanm	86:04dd9b1680ae	776
bogdanm	92:4fc01daae5a5	777	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm	92:4fc01daae5a5	778	* @{
bogdanm	92:4fc01daae5a5	779	*/
bogdanm	92:4fc01daae5a5	780
bogdanm	86:04dd9b1680ae	781	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	86:04dd9b1680ae	782	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	86:04dd9b1680ae	783	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	784	* @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm	86:04dd9b1680ae	785	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	86:04dd9b1680ae	786	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	86:04dd9b1680ae	787	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	86:04dd9b1680ae	788	*/
bogdanm	86:04dd9b1680ae	789	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	86:04dd9b1680ae	790	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm	86:04dd9b1680ae	791
bogdanm	86:04dd9b1680ae	792	/** @brief Macro to get the USART1 clock source.
bogdanm	86:04dd9b1680ae	793	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	794	* @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm	86:04dd9b1680ae	795	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	86:04dd9b1680ae	796	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	86:04dd9b1680ae	797	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	86:04dd9b1680ae	798	*/
bogdanm	86:04dd9b1680ae	799	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm	86:04dd9b1680ae	800
bogdanm	86:04dd9b1680ae	801	/** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm	86:04dd9b1680ae	802	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	86:04dd9b1680ae	803	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	804	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	86:04dd9b1680ae	805	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	86:04dd9b1680ae	806	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	86:04dd9b1680ae	807	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	86:04dd9b1680ae	808	*/
bogdanm	86:04dd9b1680ae	809	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	86:04dd9b1680ae	810	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
bogdanm	86:04dd9b1680ae	811
bogdanm	86:04dd9b1680ae	812	/** @brief Macro to get the USART2 clock source.
bogdanm	86:04dd9b1680ae	813	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	814	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	86:04dd9b1680ae	815	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	86:04dd9b1680ae	816	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	86:04dd9b1680ae	817	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	86:04dd9b1680ae	818	*/
bogdanm	86:04dd9b1680ae	819	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
bogdanm	86:04dd9b1680ae	820
bogdanm	86:04dd9b1680ae	821	/** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm	86:04dd9b1680ae	822	* @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm	86:04dd9b1680ae	823	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	824	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	86:04dd9b1680ae	825	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	86:04dd9b1680ae	826	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	86:04dd9b1680ae	827	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	86:04dd9b1680ae	828	*/
bogdanm	86:04dd9b1680ae	829	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm	86:04dd9b1680ae	830	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm	86:04dd9b1680ae	831
bogdanm	86:04dd9b1680ae	832	/** @brief Macro to get the USART3 clock source.
bogdanm	86:04dd9b1680ae	833	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	834	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	86:04dd9b1680ae	835	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	86:04dd9b1680ae	836	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	86:04dd9b1680ae	837	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	86:04dd9b1680ae	838	*/
bogdanm	86:04dd9b1680ae	839	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm	92:4fc01daae5a5	840	/**
bogdanm	92:4fc01daae5a5	841	* @}
bogdanm	92:4fc01daae5a5	842	*/
bogdanm	86:04dd9b1680ae	843
bogdanm	92:4fc01daae5a5	844	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm	92:4fc01daae5a5	845	* @{
bogdanm	92:4fc01daae5a5	846	*/
bogdanm	86:04dd9b1680ae	847	/** @brief Macros to enable or disable the the RTC clock.
bogdanm	86:04dd9b1680ae	848	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	86:04dd9b1680ae	849	*/
bogdanm	86:04dd9b1680ae	850	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t )BDCR_RTCEN_BB = ENABLE)
bogdanm	86:04dd9b1680ae	851	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t )BDCR_RTCEN_BB = DISABLE)
bogdanm	86:04dd9b1680ae	852
bogdanm	86:04dd9b1680ae	853	/** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm	86:04dd9b1680ae	854	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	86:04dd9b1680ae	855	* access is denied to this domain after reset, you have to enable write
bogdanm	86:04dd9b1680ae	856	* access using the Power Backup Access macro before to configure
bogdanm	86:04dd9b1680ae	857	* the RTC clock source (to be done once after reset).
bogdanm	86:04dd9b1680ae	858	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	86:04dd9b1680ae	859	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm	86:04dd9b1680ae	860	* a Power On Reset (POR).
bogdanm	86:04dd9b1680ae	861	* @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm	86:04dd9b1680ae	862	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	863	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm	86:04dd9b1680ae	864	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	86:04dd9b1680ae	865	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	86:04dd9b1680ae	866	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm	86:04dd9b1680ae	867	*
bogdanm	86:04dd9b1680ae	868	* @note If the LSE is used as RTC clock source, the RTC continues to
bogdanm	86:04dd9b1680ae	869	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	86:04dd9b1680ae	870	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm	86:04dd9b1680ae	871	* the RTC cannot be used in STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	872	* @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm	86:04dd9b1680ae	873	* equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm	86:04dd9b1680ae	874	*/
bogdanm	86:04dd9b1680ae	875	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
bogdanm	86:04dd9b1680ae	876	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
bogdanm	86:04dd9b1680ae	877
bogdanm	86:04dd9b1680ae	878	/** @brief Macro to get the RTC clock source.
bogdanm	86:04dd9b1680ae	879	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	880	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm	86:04dd9b1680ae	881	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	86:04dd9b1680ae	882	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	86:04dd9b1680ae	883	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
bogdanm	86:04dd9b1680ae	884	*/
bogdanm	86:04dd9b1680ae	885	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
bogdanm	92:4fc01daae5a5	886	/**
bogdanm	92:4fc01daae5a5	887	* @}
bogdanm	92:4fc01daae5a5	888	*/
bogdanm	92:4fc01daae5a5	889
bogdanm	92:4fc01daae5a5	890	/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
bogdanm	92:4fc01daae5a5	891	* @{
bogdanm	92:4fc01daae5a5	892	*/
bogdanm	86:04dd9b1680ae	893
bogdanm	86:04dd9b1680ae	894	/** @brief Macro to force or release the Backup domain reset.
bogdanm	86:04dd9b1680ae	895	* @note These macros reset the RTC peripheral (including the backup registers)
bogdanm	86:04dd9b1680ae	896	* and the RTC clock source selection in RCC_CSR register.
bogdanm	86:04dd9b1680ae	897	* @note The BKPSRAM is not affected by this reset.
bogdanm	86:04dd9b1680ae	898	*/
bogdanm	86:04dd9b1680ae	899	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t )BDCR_BDRST_BB = ENABLE)
bogdanm	86:04dd9b1680ae	900	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t )BDCR_BDRST_BB = DISABLE)
bogdanm	92:4fc01daae5a5	901	/**
bogdanm	92:4fc01daae5a5	902	* @}
bogdanm	92:4fc01daae5a5	903	*/
bogdanm	92:4fc01daae5a5	904
bogdanm	92:4fc01daae5a5	905	/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
bogdanm	92:4fc01daae5a5	906	* @{
bogdanm	92:4fc01daae5a5	907	*/
bogdanm	86:04dd9b1680ae	908
bogdanm	86:04dd9b1680ae	909	/** @brief Macro to enable or disable the PLL.
bogdanm	86:04dd9b1680ae	910	* @note After enabling the PLL, the application software should wait on
bogdanm	86:04dd9b1680ae	911	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	86:04dd9b1680ae	912	* be used as system clock source.
bogdanm	86:04dd9b1680ae	913	* @note The PLL can not be disabled if it is used as system clock source
bogdanm	86:04dd9b1680ae	914	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	86:04dd9b1680ae	915	*/
bogdanm	86:04dd9b1680ae	916	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t )CR_PLLON_BB = ENABLE)
bogdanm	86:04dd9b1680ae	917	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t )CR_PLLON_BB = DISABLE)
bogdanm	92:4fc01daae5a5	918	/**
bogdanm	92:4fc01daae5a5	919	* @}
bogdanm	92:4fc01daae5a5	920	*/
bogdanm	86:04dd9b1680ae	921
bogdanm	92:4fc01daae5a5	922	/** @defgroup RCC_Get_Clock_source RCC Get Clock source
bogdanm	92:4fc01daae5a5	923	* @{
bogdanm	92:4fc01daae5a5	924	*/
bogdanm	86:04dd9b1680ae	925
bogdanm	86:04dd9b1680ae	926	/** @brief Macro to get the clock source used as system clock.
bogdanm	86:04dd9b1680ae	927	* @retval The clock source used as system clock.
bogdanm	86:04dd9b1680ae	928	* The returned value can be one of the following value:
bogdanm	86:04dd9b1680ae	929	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm	86:04dd9b1680ae	930	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm	86:04dd9b1680ae	931	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm	86:04dd9b1680ae	932	*/
bogdanm	86:04dd9b1680ae	933	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
bogdanm	86:04dd9b1680ae	934
bogdanm	86:04dd9b1680ae	935	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	86:04dd9b1680ae	936	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	86:04dd9b1680ae	937	* of the following:
bogdanm	86:04dd9b1680ae	938	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	86:04dd9b1680ae	939	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	86:04dd9b1680ae	940	*/
bogdanm	86:04dd9b1680ae	941	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
bogdanm	92:4fc01daae5a5	942	/**
bogdanm	92:4fc01daae5a5	943	* @}
bogdanm	92:4fc01daae5a5	944	*/
bogdanm	86:04dd9b1680ae	945
bogdanm	92:4fc01daae5a5	946	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
bogdanm	86:04dd9b1680ae	947	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	86:04dd9b1680ae	948	* @{
bogdanm	86:04dd9b1680ae	949	*/
bogdanm	86:04dd9b1680ae	950
bogdanm	86:04dd9b1680ae	951	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
bogdanm	86:04dd9b1680ae	952	* the selected interrupts.).
bogdanm	86:04dd9b1680ae	953	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	86:04dd9b1680ae	954	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	955	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
bogdanm	86:04dd9b1680ae	956	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
bogdanm	86:04dd9b1680ae	957	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
bogdanm	86:04dd9b1680ae	958	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
bogdanm	86:04dd9b1680ae	959	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
bogdanm	86:04dd9b1680ae	960	*/
bogdanm	86:04dd9b1680ae	961	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t )CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	86:04dd9b1680ae	962
bogdanm	86:04dd9b1680ae	963	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
bogdanm	86:04dd9b1680ae	964	* the selected interrupts.).
bogdanm	86:04dd9b1680ae	965	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	86:04dd9b1680ae	966	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	967	* @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
bogdanm	86:04dd9b1680ae	968	* @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
bogdanm	86:04dd9b1680ae	969	* @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
bogdanm	86:04dd9b1680ae	970	* @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
bogdanm	86:04dd9b1680ae	971	* @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
bogdanm	86:04dd9b1680ae	972	*/
bogdanm	86:04dd9b1680ae	973	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t )CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	86:04dd9b1680ae	974
bogdanm	86:04dd9b1680ae	975	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
bogdanm	86:04dd9b1680ae	976	* bits to clear the selected interrupt pending bits.
bogdanm	86:04dd9b1680ae	977	* @param __IT__: specifies the interrupt pending bit to clear.
bogdanm	86:04dd9b1680ae	978	* This parameter can be any combination of the following values:
bogdanm	86:04dd9b1680ae	979	* @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
bogdanm	86:04dd9b1680ae	980	* @arg RCC_IT_LSERDYC: LSE ready interrupt clear
bogdanm	86:04dd9b1680ae	981	* @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
bogdanm	86:04dd9b1680ae	982	* @arg RCC_IT_HSERDYC: HSE ready interrupt clear
bogdanm	86:04dd9b1680ae	983	* @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
bogdanm	86:04dd9b1680ae	984	* @arg RCC_IT_CSSC: Clock Security System interrupt clear
bogdanm	86:04dd9b1680ae	985	*/
bogdanm	86:04dd9b1680ae	986	#define __HAL_RCC_CLEAR_IT(__IT__) ((__IO uint8_t )CIR_BYTE2_ADDRESS = (__IT__))
bogdanm	86:04dd9b1680ae	987
bogdanm	86:04dd9b1680ae	988	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	86:04dd9b1680ae	989	* @param __IT__: specifies the RCC interrupt source to check.
bogdanm	86:04dd9b1680ae	990	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	991	* @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
bogdanm	86:04dd9b1680ae	992	* @arg RCC_IT_LSERDYF: LSE ready interrupt flag
bogdanm	86:04dd9b1680ae	993	* @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
bogdanm	86:04dd9b1680ae	994	* @arg RCC_IT_HSERDYF: HSE ready interrupt flag
bogdanm	86:04dd9b1680ae	995	* @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
bogdanm	86:04dd9b1680ae	996	* @arg RCC_IT_CSSF: Clock Security System interrupt flag
bogdanm	86:04dd9b1680ae	997	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	998	*/
bogdanm	86:04dd9b1680ae	999	#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
bogdanm	86:04dd9b1680ae	1000
bogdanm	86:04dd9b1680ae	1001	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm	86:04dd9b1680ae	1002	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	86:04dd9b1680ae	1003	*/
bogdanm	86:04dd9b1680ae	1004	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )CSR_RMVF_BB = ENABLE)
bogdanm	86:04dd9b1680ae	1005
bogdanm	86:04dd9b1680ae	1006	/** @brief Check RCC flag is set or not.
bogdanm	86:04dd9b1680ae	1007	* @param __FLAG__: specifies the flag to check.
bogdanm	86:04dd9b1680ae	1008	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	1009	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm	86:04dd9b1680ae	1010	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm	86:04dd9b1680ae	1011	* @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm	86:04dd9b1680ae	1012	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm	86:04dd9b1680ae	1013	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm	86:04dd9b1680ae	1014	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
bogdanm	86:04dd9b1680ae	1015	* @arg RCC_FLAG_PINRST: Pin reset
bogdanm	86:04dd9b1680ae	1016	* @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm	86:04dd9b1680ae	1017	* @arg RCC_FLAG_SFTRST: Software reset
bogdanm	86:04dd9b1680ae	1018	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm	86:04dd9b1680ae	1019	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm	86:04dd9b1680ae	1020	* @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm	86:04dd9b1680ae	1021	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	86:04dd9b1680ae	1022	*/
bogdanm	86:04dd9b1680ae	1023	#define RCC_FLAG_MASK ((uint32_t)0x0000001F)
bogdanm	86:04dd9b1680ae	1024	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
bogdanm	86:04dd9b1680ae	1025	((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm	86:04dd9b1680ae	1026	RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	86:04dd9b1680ae	1027
bogdanm	86:04dd9b1680ae	1028
bogdanm	86:04dd9b1680ae	1029	/**
bogdanm	86:04dd9b1680ae	1030	* @}
bogdanm	86:04dd9b1680ae	1031	*/
bogdanm	86:04dd9b1680ae	1032
bogdanm	92:4fc01daae5a5	1033	/**
bogdanm	92:4fc01daae5a5	1034	* @}
bogdanm	92:4fc01daae5a5	1035	*/
bogdanm	92:4fc01daae5a5	1036
bogdanm	92:4fc01daae5a5	1037	/* Include RCC HAL Extended module */
bogdanm	86:04dd9b1680ae	1038	#include "stm32f3xx_hal_rcc_ex.h"
bogdanm	86:04dd9b1680ae	1039
bogdanm	86:04dd9b1680ae	1040	/* Exported functions --------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	1041
bogdanm	92:4fc01daae5a5	1042	/** @addtogroup RCC_Exported_Functions
bogdanm	92:4fc01daae5a5	1043	* @{
bogdanm	92:4fc01daae5a5	1044	*/
bogdanm	92:4fc01daae5a5	1045
bogdanm	92:4fc01daae5a5	1046	/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	92:4fc01daae5a5	1047	* @{
bogdanm	92:4fc01daae5a5	1048	*/
bogdanm	92:4fc01daae5a5	1049
bogdanm	86:04dd9b1680ae	1050	/* Initialization and de-initialization functions ***************************/
bogdanm	86:04dd9b1680ae	1051	void HAL_RCC_DeInit(void);
bogdanm	86:04dd9b1680ae	1052	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	86:04dd9b1680ae	1053	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	86:04dd9b1680ae	1054
bogdanm	92:4fc01daae5a5	1055	/**
bogdanm	92:4fc01daae5a5	1056	* @}
bogdanm	92:4fc01daae5a5	1057	*/
bogdanm	92:4fc01daae5a5	1058
bogdanm	92:4fc01daae5a5	1059	/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm	92:4fc01daae5a5	1060	* @{
bogdanm	92:4fc01daae5a5	1061	*/
bogdanm	92:4fc01daae5a5	1062
bogdanm	86:04dd9b1680ae	1063	/* Peripheral Control functions *********************************************/
bogdanm	86:04dd9b1680ae	1064	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	86:04dd9b1680ae	1065	void HAL_RCC_EnableCSS(void);
bogdanm	86:04dd9b1680ae	1066	void HAL_RCC_DisableCSS(void);
bogdanm	86:04dd9b1680ae	1067	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	86:04dd9b1680ae	1068	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	86:04dd9b1680ae	1069	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	86:04dd9b1680ae	1070	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	86:04dd9b1680ae	1071	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	86:04dd9b1680ae	1072	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	86:04dd9b1680ae	1073
bogdanm	86:04dd9b1680ae	1074	/* CSS NMI IRQ handler */
bogdanm	86:04dd9b1680ae	1075	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	86:04dd9b1680ae	1076
bogdanm	86:04dd9b1680ae	1077	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	86:04dd9b1680ae	1078	void HAL_RCC_CCSCallback(void);
bogdanm	86:04dd9b1680ae	1079
bogdanm	86:04dd9b1680ae	1080	/**
bogdanm	86:04dd9b1680ae	1081	* @}
bogdanm	86:04dd9b1680ae	1082	*/
bogdanm	86:04dd9b1680ae	1083
bogdanm	86:04dd9b1680ae	1084	/**
bogdanm	86:04dd9b1680ae	1085	* @}
bogdanm	86:04dd9b1680ae	1086	*/
bogdanm	86:04dd9b1680ae	1087
bogdanm	92:4fc01daae5a5	1088	/**
bogdanm	92:4fc01daae5a5	1089	* @}
bogdanm	92:4fc01daae5a5	1090	*/
bogdanm	92:4fc01daae5a5	1091
bogdanm	92:4fc01daae5a5	1092	/**
bogdanm	92:4fc01daae5a5	1093	* @}
bogdanm	92:4fc01daae5a5	1094	*/
bogdanm	92:4fc01daae5a5	1095
bogdanm	86:04dd9b1680ae	1096	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	1097	}
bogdanm	86:04dd9b1680ae	1098	#endif
bogdanm	86:04dd9b1680ae	1099
bogdanm	86:04dd9b1680ae	1100	#endif /* __STM32F3xx_HAL_RCC_H */
bogdanm	86:04dd9b1680ae	1101
bogdanm	86:04dd9b1680ae	1102	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	03 May 2015
Imports:	4
Forks:	0
Commits:	100
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TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc.h@92:4fc01daae5a5, 2014-11-27 (annotated)

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