Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

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TARGET_ARCH_MAX/stm32f4xx_ll_fsmc.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
89:552587b429a1 
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_fsmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of FSMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_FSMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 89:552587b429a1 47
bogdanm 89:552587b429a1 48 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 49 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 50
bogdanm 89:552587b429a1 51 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 52 * @{
bogdanm 89:552587b429a1 53 */
bogdanm 89:552587b429a1 54
bogdanm 89:552587b429a1 55 /** @addtogroup FSMC
bogdanm 89:552587b429a1 56 * @{
bogdanm 89:552587b429a1 57 */
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 89:552587b429a1 60 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
bogdanm 89:552587b429a1 61 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
bogdanm 89:552587b429a1 62 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
bogdanm 89:552587b429a1 63 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
bogdanm 89:552587b429a1 64
bogdanm 89:552587b429a1 65 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
bogdanm 89:552587b429a1 66 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
bogdanm 89:552587b429a1 67 #define FSMC_NAND_DEVICE FSMC_Bank2_3
bogdanm 89:552587b429a1 68 #define FSMC_PCCARD_DEVICE FSMC_Bank4
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 /**
bogdanm 89:552587b429a1 71 * @brief FSMC_NORSRAM Configuration Structure definition
bogdanm 89:552587b429a1 72 */
bogdanm 89:552587b429a1 73 typedef struct
bogdanm 89:552587b429a1 74 {
bogdanm 89:552587b429a1 75 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 89:552587b429a1 76 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 89:552587b429a1 77
bogdanm 89:552587b429a1 78 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm 89:552587b429a1 79 multiplexed on the data bus or not.
bogdanm 89:552587b429a1 80 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm 89:552587b429a1 83 the corresponding memory device.
bogdanm 89:552587b429a1 84 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 89:552587b429a1 85
bogdanm 89:552587b429a1 86 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 87 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 89:552587b429a1 88
bogdanm 89:552587b429a1 89 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm 89:552587b429a1 90 valid only with synchronous burst Flash memories.
bogdanm 89:552587b429a1 91 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 89:552587b429a1 92
bogdanm 89:552587b429a1 93 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm 89:552587b429a1 94 the Flash memory in burst mode.
bogdanm 89:552587b429a1 95 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 89:552587b429a1 96
bogdanm 89:552587b429a1 97 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm 89:552587b429a1 98 memory, valid only when accessing Flash memories in burst mode.
bogdanm 89:552587b429a1 99 This parameter can be a value of @ref FSMC_Wrap_Mode */
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm 89:552587b429a1 102 clock cycle before the wait state or during the wait state,
bogdanm 89:552587b429a1 103 valid only when accessing memories in burst mode.
bogdanm 89:552587b429a1 104 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
bogdanm 89:552587b429a1 107 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm 89:552587b429a1 110 signal, valid for Flash memory access in burst mode.
bogdanm 89:552587b429a1 111 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 89:552587b429a1 112
bogdanm 89:552587b429a1 113 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm 89:552587b429a1 114 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 89:552587b429a1 115
bogdanm 89:552587b429a1 116 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm 89:552587b429a1 117 valid only with asynchronous Flash memories.
bogdanm 89:552587b429a1 118 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 89:552587b429a1 119
bogdanm 89:552587b429a1 120 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 89:552587b429a1 121 This parameter can be a value of @ref FSMC_Write_Burst */
bogdanm 89:552587b429a1 122
bogdanm 89:552587b429a1 123 }FSMC_NORSRAM_InitTypeDef;
bogdanm 89:552587b429a1 124
bogdanm 89:552587b429a1 125 /**
bogdanm 89:552587b429a1 126 * @brief FSMC_NORSRAM Timing parameters structure definition
bogdanm 89:552587b429a1 127 */
bogdanm 89:552587b429a1 128 typedef struct
bogdanm 89:552587b429a1 129 {
bogdanm 89:552587b429a1 130 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 131 the duration of the address setup time.
bogdanm 89:552587b429a1 132 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 133 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 134
bogdanm 89:552587b429a1 135 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 136 the duration of the address hold time.
bogdanm 89:552587b429a1 137 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm 89:552587b429a1 138 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 89:552587b429a1 139
bogdanm 89:552587b429a1 140 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 141 the duration of the data setup time.
bogdanm 89:552587b429a1 142 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm 89:552587b429a1 143 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm 89:552587b429a1 144 NOR Flash memories. */
bogdanm 89:552587b429a1 145
bogdanm 89:552587b429a1 146 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm 89:552587b429a1 147 the duration of the bus turnaround.
bogdanm 89:552587b429a1 148 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm 89:552587b429a1 149 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 89:552587b429a1 150
bogdanm 89:552587b429a1 151 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm 89:552587b429a1 152 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm 89:552587b429a1 153 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm 89:552587b429a1 154 accesses. */
bogdanm 89:552587b429a1 155
bogdanm 89:552587b429a1 156 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm 89:552587b429a1 157 to the memory before getting the first data.
bogdanm 89:552587b429a1 158 The parameter value depends on the memory type as shown below:
bogdanm 89:552587b429a1 159 - It must be set to 0 in case of a CRAM
bogdanm 89:552587b429a1 160 - It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm 89:552587b429a1 161 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm 89:552587b429a1 162 with synchronous burst mode enable */
bogdanm 89:552587b429a1 163
bogdanm 89:552587b429a1 164 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm 89:552587b429a1 165 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 89:552587b429a1 166
bogdanm 89:552587b429a1 167 }FSMC_NORSRAM_TimingTypeDef;
bogdanm 89:552587b429a1 168
bogdanm 89:552587b429a1 169 /**
bogdanm 89:552587b429a1 170 * @brief FSMC_NAND Configuration Structure definition
bogdanm 89:552587b429a1 171 */
bogdanm 89:552587b429a1 172 typedef struct
bogdanm 89:552587b429a1 173 {
bogdanm 89:552587b429a1 174 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 89:552587b429a1 175 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 89:552587b429a1 176
bogdanm 89:552587b429a1 177 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm 89:552587b429a1 178 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 179
bogdanm 89:552587b429a1 180 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm 89:552587b429a1 181 This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm 89:552587b429a1 182
bogdanm 89:552587b429a1 183 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm 89:552587b429a1 184 This parameter can be any value of @ref FSMC_ECC */
bogdanm 89:552587b429a1 185
bogdanm 89:552587b429a1 186 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm 89:552587b429a1 187 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 89:552587b429a1 188
bogdanm 89:552587b429a1 189 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 190 delay between CLE low and RE low.
bogdanm 89:552587b429a1 191 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 192
bogdanm 89:552587b429a1 193 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 194 delay between ALE low and RE low.
bogdanm 89:552587b429a1 195 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 196
bogdanm 89:552587b429a1 197 }FSMC_NAND_InitTypeDef;
bogdanm 89:552587b429a1 198
bogdanm 89:552587b429a1 199 /**
bogdanm 89:552587b429a1 200 * @brief FSMC_NAND_PCCARD Timing parameters structure definition
bogdanm 89:552587b429a1 201 */
bogdanm 89:552587b429a1 202 typedef struct
bogdanm 89:552587b429a1 203 {
bogdanm 89:552587b429a1 204 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm 89:552587b429a1 205 the command assertion for NAND-Flash read or write access
bogdanm 89:552587b429a1 206 to common/Attribute or I/O memory space (depending on
bogdanm 89:552587b429a1 207 the memory space timing to be configured).
bogdanm 89:552587b429a1 208 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 209
bogdanm 89:552587b429a1 210 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm 89:552587b429a1 211 command for NAND-Flash read or write access to
bogdanm 89:552587b429a1 212 common/Attribute or I/O memory space (depending on the
bogdanm 89:552587b429a1 213 memory space timing to be configured).
bogdanm 89:552587b429a1 214 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 215
bogdanm 89:552587b429a1 216 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm 89:552587b429a1 217 (and data for write access) after the command de-assertion
bogdanm 89:552587b429a1 218 for NAND-Flash read or write access to common/Attribute
bogdanm 89:552587b429a1 219 or I/O memory space (depending on the memory space timing
bogdanm 89:552587b429a1 220 to be configured).
bogdanm 89:552587b429a1 221 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 222
bogdanm 89:552587b429a1 223 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm 89:552587b429a1 224 data bus is kept in HiZ after the start of a NAND-Flash
bogdanm 89:552587b429a1 225 write access to common/Attribute or I/O memory space (depending
bogdanm 89:552587b429a1 226 on the memory space timing to be configured).
bogdanm 89:552587b429a1 227 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 228
bogdanm 89:552587b429a1 229 }FSMC_NAND_PCC_TimingTypeDef;
bogdanm 89:552587b429a1 230
bogdanm 89:552587b429a1 231 /**
bogdanm 89:552587b429a1 232 * @brief FSMC_NAND Configuration Structure definition
bogdanm 89:552587b429a1 233 */
bogdanm 89:552587b429a1 234 typedef struct
bogdanm 89:552587b429a1 235 {
bogdanm 89:552587b429a1 236 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm 89:552587b429a1 237 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 89:552587b429a1 238
bogdanm 89:552587b429a1 239 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 240 delay between CLE low and RE low.
bogdanm 89:552587b429a1 241 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 242
bogdanm 89:552587b429a1 243 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm 89:552587b429a1 244 delay between ALE low and RE low.
bogdanm 89:552587b429a1 245 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 246
bogdanm 89:552587b429a1 247 }FSMC_PCCARD_InitTypeDef;
bogdanm 89:552587b429a1 248
bogdanm 89:552587b429a1 249 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 250
bogdanm 89:552587b429a1 251 /** @defgroup FSMC_NOR_SRAM_Controller
bogdanm 89:552587b429a1 252 * @{
bogdanm 89:552587b429a1 253 */
bogdanm 89:552587b429a1 254
bogdanm 89:552587b429a1 255 /** @defgroup FSMC_NORSRAM_Bank
bogdanm 89:552587b429a1 256 * @{
bogdanm 89:552587b429a1 257 */
bogdanm 89:552587b429a1 258 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 259 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 260 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 261 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm 89:552587b429a1 262
bogdanm 89:552587b429a1 263 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_NORSRAM_BANK1) || \
bogdanm 89:552587b429a1 264 ((BANK) == FSMC_NORSRAM_BANK2) || \
bogdanm 89:552587b429a1 265 ((BANK) == FSMC_NORSRAM_BANK3) || \
bogdanm 89:552587b429a1 266 ((BANK) == FSMC_NORSRAM_BANK4))
bogdanm 89:552587b429a1 267 /**
bogdanm 89:552587b429a1 268 * @}
bogdanm 89:552587b429a1 269 */
bogdanm 89:552587b429a1 270
bogdanm 89:552587b429a1 271 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
bogdanm 89:552587b429a1 272 * @{
bogdanm 89:552587b429a1 273 */
bogdanm 89:552587b429a1 274
bogdanm 89:552587b429a1 275 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 276 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 277
bogdanm 89:552587b429a1 278 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
bogdanm 89:552587b429a1 279 ((MUX) == FSMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm 89:552587b429a1 280 /**
bogdanm 89:552587b429a1 281 * @}
bogdanm 89:552587b429a1 282 */
bogdanm 89:552587b429a1 283
bogdanm 89:552587b429a1 284 /** @defgroup FSMC_Memory_Type
bogdanm 89:552587b429a1 285 * @{
bogdanm 89:552587b429a1 286 */
bogdanm 89:552587b429a1 287
bogdanm 89:552587b429a1 288 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 289 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 290 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 291
bogdanm 89:552587b429a1 292
bogdanm 89:552587b429a1 293 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MEMORY_TYPE_SRAM) || \
bogdanm 89:552587b429a1 294 ((MEMORY) == FSMC_MEMORY_TYPE_PSRAM)|| \
bogdanm 89:552587b429a1 295 ((MEMORY) == FSMC_MEMORY_TYPE_NOR))
bogdanm 89:552587b429a1 296 /**
bogdanm 89:552587b429a1 297 * @}
bogdanm 89:552587b429a1 298 */
bogdanm 89:552587b429a1 299
bogdanm 89:552587b429a1 300 /** @defgroup FSMC_NORSRAM_Data_Width
bogdanm 89:552587b429a1 301 * @{
bogdanm 89:552587b429a1 302 */
bogdanm 89:552587b429a1 303
bogdanm 89:552587b429a1 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 307
bogdanm 89:552587b429a1 308 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
bogdanm 89:552587b429a1 309 ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
bogdanm 89:552587b429a1 310 ((WIDTH) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm 89:552587b429a1 311 /**
bogdanm 89:552587b429a1 312 * @}
bogdanm 89:552587b429a1 313 */
bogdanm 89:552587b429a1 314
bogdanm 89:552587b429a1 315 /** @defgroup FSMC_NORSRAM_Flash_Access
bogdanm 89:552587b429a1 316 * @{
bogdanm 89:552587b429a1 317 */
bogdanm 89:552587b429a1 318 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 319 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 320 /**
bogdanm 89:552587b429a1 321 * @}
bogdanm 89:552587b429a1 322 */
bogdanm 89:552587b429a1 323
bogdanm 89:552587b429a1 324 /** @defgroup FSMC_Burst_Access_Mode
bogdanm 89:552587b429a1 325 * @{
bogdanm 89:552587b429a1 326 */
bogdanm 89:552587b429a1 327
bogdanm 89:552587b429a1 328 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 329 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 330
bogdanm 89:552587b429a1 331 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
bogdanm 89:552587b429a1 332 ((STATE) == FSMC_BURST_ACCESS_MODE_ENABLE))
bogdanm 89:552587b429a1 333 /**
bogdanm 89:552587b429a1 334 * @}
bogdanm 89:552587b429a1 335 */
bogdanm 89:552587b429a1 336
bogdanm 89:552587b429a1 337
bogdanm 89:552587b429a1 338 /** @defgroup FSMC_Wait_Signal_Polarity
bogdanm 89:552587b429a1 339 * @{
bogdanm 89:552587b429a1 340 */
bogdanm 89:552587b429a1 341 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 342 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 343
bogdanm 89:552587b429a1 344 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
bogdanm 89:552587b429a1 345 ((POLARITY) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm 89:552587b429a1 346 /**
bogdanm 89:552587b429a1 347 * @}
bogdanm 89:552587b429a1 348 */
bogdanm 89:552587b429a1 349
bogdanm 89:552587b429a1 350 /** @defgroup FSMC_Wrap_Mode
bogdanm 89:552587b429a1 351 * @{
bogdanm 89:552587b429a1 352 */
bogdanm 89:552587b429a1 353 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 354 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm 89:552587b429a1 355
bogdanm 89:552587b429a1 356 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WRAP_MODE_DISABLE) || \
bogdanm 89:552587b429a1 357 ((MODE) == FSMC_WRAP_MODE_ENABLE))
bogdanm 89:552587b429a1 358 /**
bogdanm 89:552587b429a1 359 * @}
bogdanm 89:552587b429a1 360 */
bogdanm 89:552587b429a1 361
bogdanm 89:552587b429a1 362 /** @defgroup FSMC_Wait_Timing
bogdanm 89:552587b429a1 363 * @{
bogdanm 89:552587b429a1 364 */
bogdanm 89:552587b429a1 365 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 366 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm 89:552587b429a1 367
bogdanm 89:552587b429a1 368 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WAIT_TIMING_BEFORE_WS) || \
bogdanm 89:552587b429a1 369 ((ACTIVE) == FSMC_WAIT_TIMING_DURING_WS))
bogdanm 89:552587b429a1 370 /**
bogdanm 89:552587b429a1 371 * @}
bogdanm 89:552587b429a1 372 */
bogdanm 89:552587b429a1 373
bogdanm 89:552587b429a1 374 /** @defgroup FSMC_Write_Operation
bogdanm 89:552587b429a1 375 * @{
bogdanm 89:552587b429a1 376 */
bogdanm 89:552587b429a1 377 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 378 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm 89:552587b429a1 379
bogdanm 89:552587b429a1 380 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
bogdanm 89:552587b429a1 381 ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
bogdanm 89:552587b429a1 382 /**
bogdanm 89:552587b429a1 383 * @}
bogdanm 89:552587b429a1 384 */
bogdanm 89:552587b429a1 385
bogdanm 89:552587b429a1 386 /** @defgroup FSMC_Wait_Signal
bogdanm 89:552587b429a1 387 * @{
bogdanm 89:552587b429a1 388 */
bogdanm 89:552587b429a1 389 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 390 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm 89:552587b429a1 391
bogdanm 89:552587b429a1 392 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WAIT_SIGNAL_DISABLE) || \
bogdanm 89:552587b429a1 393 ((SIGNAL) == FSMC_WAIT_SIGNAL_ENABLE))
bogdanm 89:552587b429a1 394
bogdanm 89:552587b429a1 395 /**
bogdanm 89:552587b429a1 396 * @}
bogdanm 89:552587b429a1 397 */
bogdanm 89:552587b429a1 398
bogdanm 89:552587b429a1 399 /** @defgroup FSMC_Extended_Mode
bogdanm 89:552587b429a1 400 * @{
bogdanm 89:552587b429a1 401 */
bogdanm 89:552587b429a1 402 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 403 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 404
bogdanm 89:552587b429a1 405 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_EXTENDED_MODE_DISABLE) || \
bogdanm 89:552587b429a1 406 ((MODE) == FSMC_EXTENDED_MODE_ENABLE))
bogdanm 89:552587b429a1 407 /**
bogdanm 89:552587b429a1 408 * @}
bogdanm 89:552587b429a1 409 */
bogdanm 89:552587b429a1 410
bogdanm 89:552587b429a1 411 /** @defgroup FSMC_AsynchronousWait
bogdanm 89:552587b429a1 412 * @{
bogdanm 89:552587b429a1 413 */
bogdanm 89:552587b429a1 414 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 415 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm 89:552587b429a1 416
bogdanm 89:552587b429a1 417 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
bogdanm 89:552587b429a1 418 ((STATE) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm 89:552587b429a1 419
bogdanm 89:552587b429a1 420 /**
bogdanm 89:552587b429a1 421 * @}
bogdanm 89:552587b429a1 422 */
bogdanm 89:552587b429a1 423
bogdanm 89:552587b429a1 424 /** @defgroup FSMC_Write_Burst
bogdanm 89:552587b429a1 425 * @{
bogdanm 89:552587b429a1 426 */
bogdanm 89:552587b429a1 427
bogdanm 89:552587b429a1 428 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 429 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 430
bogdanm 89:552587b429a1 431 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WRITE_BURST_DISABLE) || \
bogdanm 89:552587b429a1 432 ((BURST) == FSMC_WRITE_BURST_ENABLE))
bogdanm 89:552587b429a1 433
bogdanm 89:552587b429a1 434 /**
bogdanm 89:552587b429a1 435 * @}
bogdanm 89:552587b429a1 436 */
bogdanm 89:552587b429a1 437
bogdanm 89:552587b429a1 438 /** @defgroup FSMC_Continous_Clock
bogdanm 89:552587b429a1 439 * @{
bogdanm 89:552587b429a1 440 */
bogdanm 89:552587b429a1 441
bogdanm 89:552587b429a1 442 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 443 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 444
bogdanm 89:552587b429a1 445 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
bogdanm 89:552587b429a1 446 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm 89:552587b429a1 447
bogdanm 89:552587b429a1 448 /**
bogdanm 89:552587b429a1 449 * @}
bogdanm 89:552587b429a1 450 */
bogdanm 89:552587b429a1 451
bogdanm 89:552587b429a1 452 /** @defgroup FSMC_Address_Setup_Time
bogdanm 89:552587b429a1 453 * @{
bogdanm 89:552587b429a1 454 */
bogdanm 89:552587b429a1 455 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm 89:552587b429a1 456 /**
bogdanm 89:552587b429a1 457 * @}
bogdanm 89:552587b429a1 458 */
bogdanm 89:552587b429a1 459
bogdanm 89:552587b429a1 460 /** @defgroup FSMC_Address_Hold_Time
bogdanm 89:552587b429a1 461 * @{
bogdanm 89:552587b429a1 462 */
bogdanm 89:552587b429a1 463 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm 89:552587b429a1 464 /**
bogdanm 89:552587b429a1 465 * @}
bogdanm 89:552587b429a1 466 */
bogdanm 89:552587b429a1 467
bogdanm 89:552587b429a1 468 /** @defgroup FSMC_Data_Setup_Time
bogdanm 89:552587b429a1 469 * @{
bogdanm 89:552587b429a1 470 */
bogdanm 89:552587b429a1 471 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm 89:552587b429a1 472 /**
bogdanm 89:552587b429a1 473 * @}
bogdanm 89:552587b429a1 474 */
bogdanm 89:552587b429a1 475
bogdanm 89:552587b429a1 476 /** @defgroup FSMC_Bus_Turn_around_Duration
bogdanm 89:552587b429a1 477 * @{
bogdanm 89:552587b429a1 478 */
bogdanm 89:552587b429a1 479 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm 89:552587b429a1 480 /**
bogdanm 89:552587b429a1 481 * @}
bogdanm 89:552587b429a1 482 */
bogdanm 89:552587b429a1 483
bogdanm 89:552587b429a1 484 /** @defgroup FSMC_CLK_Division
bogdanm 89:552587b429a1 485 * @{
bogdanm 89:552587b429a1 486 */
bogdanm 89:552587b429a1 487 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm 89:552587b429a1 488 /**
bogdanm 89:552587b429a1 489 * @}
bogdanm 89:552587b429a1 490 */
bogdanm 89:552587b429a1 491
bogdanm 89:552587b429a1 492 /** @defgroup FSMC_Data_Latency
bogdanm 89:552587b429a1 493 * @{
bogdanm 89:552587b429a1 494 */
bogdanm 89:552587b429a1 495 #define IS_FSMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm 89:552587b429a1 496 /**
bogdanm 89:552587b429a1 497 * @}
bogdanm 89:552587b429a1 498 */
bogdanm 89:552587b429a1 499
bogdanm 89:552587b429a1 500 /** @defgroup FSMC_Access_Mode
bogdanm 89:552587b429a1 501 * @{
bogdanm 89:552587b429a1 502 */
bogdanm 89:552587b429a1 503 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 504 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm 89:552587b429a1 505 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm 89:552587b429a1 506 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm 89:552587b429a1 507
bogdanm 89:552587b429a1 508 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_ACCESS_MODE_A) || \
bogdanm 89:552587b429a1 509 ((MODE) == FSMC_ACCESS_MODE_B) || \
bogdanm 89:552587b429a1 510 ((MODE) == FSMC_ACCESS_MODE_C) || \
bogdanm 89:552587b429a1 511 ((MODE) == FSMC_ACCESS_MODE_D))
bogdanm 89:552587b429a1 512 /**
bogdanm 89:552587b429a1 513 * @}
bogdanm 89:552587b429a1 514 */
bogdanm 89:552587b429a1 515
bogdanm 89:552587b429a1 516 /**
bogdanm 89:552587b429a1 517 * @}
bogdanm 89:552587b429a1 518 */
bogdanm 89:552587b429a1 519
bogdanm 89:552587b429a1 520 /** @defgroup FSMC_NAND_Controller
bogdanm 89:552587b429a1 521 * @{
bogdanm 89:552587b429a1 522 */
bogdanm 89:552587b429a1 523
bogdanm 89:552587b429a1 524 /** @defgroup FSMC_NAND_Bank
bogdanm 89:552587b429a1 525 * @{
bogdanm 89:552587b429a1 526 */
bogdanm 89:552587b429a1 527 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 528 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 529
bogdanm 89:552587b429a1 530 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
bogdanm 89:552587b429a1 531 ((BANK) == FSMC_NAND_BANK3))
bogdanm 89:552587b429a1 532
bogdanm 89:552587b429a1 533 /**
bogdanm 89:552587b429a1 534 * @}
bogdanm 89:552587b429a1 535 */
bogdanm 89:552587b429a1 536
bogdanm 89:552587b429a1 537 /** @defgroup FSMC_Wait_feature
bogdanm 89:552587b429a1 538 * @{
bogdanm 89:552587b429a1 539 */
bogdanm 89:552587b429a1 540 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 541 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 542
bogdanm 89:552587b429a1 543 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
bogdanm 89:552587b429a1 544 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm 89:552587b429a1 545 /**
bogdanm 89:552587b429a1 546 * @}
bogdanm 89:552587b429a1 547 */
bogdanm 89:552587b429a1 548
bogdanm 89:552587b429a1 549 /** @defgroup FSMC_PCR_Memory_Type
bogdanm 89:552587b429a1 550 * @{
bogdanm 89:552587b429a1 551 */
bogdanm 89:552587b429a1 552 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 553 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 554 /**
bogdanm 89:552587b429a1 555 * @}
bogdanm 89:552587b429a1 556 */
bogdanm 89:552587b429a1 557
bogdanm 89:552587b429a1 558 /** @defgroup FSMC_NAND_Data_Width
bogdanm 89:552587b429a1 559 * @{
bogdanm 89:552587b429a1 560 */
bogdanm 89:552587b429a1 561 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 562 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 563
bogdanm 89:552587b429a1 564 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
bogdanm 89:552587b429a1 565 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm 89:552587b429a1 566 /**
bogdanm 89:552587b429a1 567 * @}
bogdanm 89:552587b429a1 568 */
bogdanm 89:552587b429a1 569
bogdanm 89:552587b429a1 570 /** @defgroup FSMC_ECC
bogdanm 89:552587b429a1 571 * @{
bogdanm 89:552587b429a1 572 */
bogdanm 89:552587b429a1 573 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 574 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 575
bogdanm 89:552587b429a1 576 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
bogdanm 89:552587b429a1 577 ((STATE) == FSMC_NAND_ECC_ENABLE))
bogdanm 89:552587b429a1 578 /**
bogdanm 89:552587b429a1 579 * @}
bogdanm 89:552587b429a1 580 */
bogdanm 89:552587b429a1 581
bogdanm 89:552587b429a1 582 /** @defgroup FSMC_ECC_Page_Size
bogdanm 89:552587b429a1 583 * @{
bogdanm 89:552587b429a1 584 */
bogdanm 89:552587b429a1 585 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 586 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 587 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 588 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm 89:552587b429a1 589 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm 89:552587b429a1 590 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm 89:552587b429a1 591
bogdanm 89:552587b429a1 592 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
bogdanm 89:552587b429a1 593 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
bogdanm 89:552587b429a1 594 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
bogdanm 89:552587b429a1 595 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
bogdanm 89:552587b429a1 596 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
bogdanm 89:552587b429a1 597 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm 89:552587b429a1 598 /**
bogdanm 89:552587b429a1 599 * @}
bogdanm 89:552587b429a1 600 */
bogdanm 89:552587b429a1 601
bogdanm 89:552587b429a1 602 /** @defgroup FSMC_TCLR_Setup_Time
bogdanm 89:552587b429a1 603 * @{
bogdanm 89:552587b429a1 604 */
bogdanm 89:552587b429a1 605 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 606 /**
bogdanm 89:552587b429a1 607 * @}
bogdanm 89:552587b429a1 608 */
bogdanm 89:552587b429a1 609
bogdanm 89:552587b429a1 610 /** @defgroup FSMC_TAR_Setup_Time
bogdanm 89:552587b429a1 611 * @{
bogdanm 89:552587b429a1 612 */
bogdanm 89:552587b429a1 613 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 614 /**
bogdanm 89:552587b429a1 615 * @}
bogdanm 89:552587b429a1 616 */
bogdanm 89:552587b429a1 617
bogdanm 89:552587b429a1 618 /** @defgroup FSMC_Setup_Time
bogdanm 89:552587b429a1 619 * @{
bogdanm 89:552587b429a1 620 */
bogdanm 89:552587b429a1 621 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 622 /**
bogdanm 89:552587b429a1 623 * @}
bogdanm 89:552587b429a1 624 */
bogdanm 89:552587b429a1 625
bogdanm 89:552587b429a1 626 /** @defgroup FSMC_Wait_Setup_Time
bogdanm 89:552587b429a1 627 * @{
bogdanm 89:552587b429a1 628 */
bogdanm 89:552587b429a1 629 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 630 /**
bogdanm 89:552587b429a1 631 * @}
bogdanm 89:552587b429a1 632 */
bogdanm 89:552587b429a1 633
bogdanm 89:552587b429a1 634 /** @defgroup FSMC_Hold_Setup_Time
bogdanm 89:552587b429a1 635 * @{
bogdanm 89:552587b429a1 636 */
bogdanm 89:552587b429a1 637 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 638 /**
bogdanm 89:552587b429a1 639 * @}
bogdanm 89:552587b429a1 640 */
bogdanm 89:552587b429a1 641
bogdanm 89:552587b429a1 642 /** @defgroup FSMC_HiZ_Setup_Time
bogdanm 89:552587b429a1 643 * @{
bogdanm 89:552587b429a1 644 */
bogdanm 89:552587b429a1 645 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm 89:552587b429a1 646 /**
bogdanm 89:552587b429a1 647 * @}
bogdanm 89:552587b429a1 648 */
bogdanm 89:552587b429a1 649
bogdanm 89:552587b429a1 650 /**
bogdanm 89:552587b429a1 651 * @}
bogdanm 89:552587b429a1 652 */
bogdanm 89:552587b429a1 653
bogdanm 89:552587b429a1 654
bogdanm 89:552587b429a1 655 /** @defgroup FSMC_NORSRAM_Device_Instance
bogdanm 89:552587b429a1 656 * @{
bogdanm 89:552587b429a1 657 */
bogdanm 89:552587b429a1 658 #define IS_FSMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_DEVICE)
bogdanm 89:552587b429a1 659
bogdanm 89:552587b429a1 660 /**
bogdanm 89:552587b429a1 661 * @}
bogdanm 89:552587b429a1 662 */
bogdanm 89:552587b429a1 663
bogdanm 89:552587b429a1 664 /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance
bogdanm 89:552587b429a1 665 * @{
bogdanm 89:552587b429a1 666 */
bogdanm 89:552587b429a1 667 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NORSRAM_EXTENDED_DEVICE)
bogdanm 89:552587b429a1 668
bogdanm 89:552587b429a1 669 /**
bogdanm 89:552587b429a1 670 * @}
bogdanm 89:552587b429a1 671 */
bogdanm 89:552587b429a1 672
bogdanm 89:552587b429a1 673 /** @defgroup FSMC_NAND_Device_Instance
bogdanm 89:552587b429a1 674 * @{
bogdanm 89:552587b429a1 675 */
bogdanm 89:552587b429a1 676 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
bogdanm 89:552587b429a1 677
bogdanm 89:552587b429a1 678 /**
bogdanm 89:552587b429a1 679 * @}
bogdanm 89:552587b429a1 680 */
bogdanm 89:552587b429a1 681
bogdanm 89:552587b429a1 682 /** @defgroup FSMC_PCCARD_Device_Instance
bogdanm 89:552587b429a1 683 * @{
bogdanm 89:552587b429a1 684 */
bogdanm 89:552587b429a1 685 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
bogdanm 89:552587b429a1 686
bogdanm 89:552587b429a1 687 /**
bogdanm 89:552587b429a1 688 * @}
bogdanm 89:552587b429a1 689 */
bogdanm 89:552587b429a1 690
bogdanm 89:552587b429a1 691 /** @defgroup FSMC_Interrupt_definition
bogdanm 89:552587b429a1 692 * @brief FSMC Interrupt definition
bogdanm 89:552587b429a1 693 * @{
bogdanm 89:552587b429a1 694 */
bogdanm 89:552587b429a1 695 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 696 #define FSMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 697 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 698 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 699
bogdanm 89:552587b429a1 700 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 89:552587b429a1 701 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RISING_EDGE) || \
bogdanm 89:552587b429a1 702 ((IT) == FSMC_IT_LEVEL) || \
bogdanm 89:552587b429a1 703 ((IT) == FSMC_IT_FALLING_EDGE) || \
bogdanm 89:552587b429a1 704 ((IT) == FSMC_IT_REFRESH_ERROR))
bogdanm 89:552587b429a1 705 /**
bogdanm 89:552587b429a1 706 * @}
bogdanm 89:552587b429a1 707 */
bogdanm 89:552587b429a1 708
bogdanm 89:552587b429a1 709 /** @defgroup FSMC_Flag_definition
bogdanm 89:552587b429a1 710 * @brief FSMC Flag definition
bogdanm 89:552587b429a1 711 * @{
bogdanm 89:552587b429a1 712 */
bogdanm 89:552587b429a1 713 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 714 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 715 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 716 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm 89:552587b429a1 717
bogdanm 89:552587b429a1 718 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RISING_EDGE) || \
bogdanm 89:552587b429a1 719 ((FLAG) == FSMC_FLAG_LEVEL) || \
bogdanm 89:552587b429a1 720 ((FLAG) == FSMC_FLAG_FALLING_EDGE) || \
bogdanm 89:552587b429a1 721 ((FLAG) == FSMC_FLAG_FEMPT))
bogdanm 89:552587b429a1 722
bogdanm 89:552587b429a1 723 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm 89:552587b429a1 724
bogdanm 89:552587b429a1 725
bogdanm 89:552587b429a1 726 /**
bogdanm 89:552587b429a1 727 * @}
bogdanm 89:552587b429a1 728 */
bogdanm 89:552587b429a1 729
bogdanm 89:552587b429a1 730
bogdanm 89:552587b429a1 731 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 732
bogdanm 89:552587b429a1 733
bogdanm 89:552587b429a1 734 /** @defgroup FSMC_NOR_Macros
bogdanm 89:552587b429a1 735 * @brief macros to handle NOR device enable/disable and read/write operations
bogdanm 89:552587b429a1 736 * @{
bogdanm 89:552587b429a1 737 */
bogdanm 89:552587b429a1 738
bogdanm 89:552587b429a1 739 /**
bogdanm 89:552587b429a1 740 * @brief Enable the NORSRAM device access.
bogdanm 89:552587b429a1 741 * @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm 89:552587b429a1 742 * @param __BANK__: FSMC_NORSRAM Bank
bogdanm 89:552587b429a1 743 * @retval none
bogdanm 89:552587b429a1 744 */
bogdanm 89:552587b429a1 745 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
bogdanm 89:552587b429a1 746
bogdanm 89:552587b429a1 747 /**
bogdanm 89:552587b429a1 748 * @brief Disable the NORSRAM device access.
bogdanm 89:552587b429a1 749 * @param __INSTANCE__: FSMC_NORSRAM Instance
bogdanm 89:552587b429a1 750 * @param __BANK__: FSMC_NORSRAM Bank
bogdanm 89:552587b429a1 751 * @retval none
bogdanm 89:552587b429a1 752 */
bogdanm 89:552587b429a1 753 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
bogdanm 89:552587b429a1 754
bogdanm 89:552587b429a1 755 /**
bogdanm 89:552587b429a1 756 * @}
bogdanm 89:552587b429a1 757 */
bogdanm 89:552587b429a1 758
bogdanm 89:552587b429a1 759
bogdanm 89:552587b429a1 760 /** @defgroup FSMC_NAND_Macros
bogdanm 89:552587b429a1 761 * @brief macros to handle NAND device enable/disable
bogdanm 89:552587b429a1 762 * @{
bogdanm 89:552587b429a1 763 */
bogdanm 89:552587b429a1 764
bogdanm 89:552587b429a1 765 /**
bogdanm 89:552587b429a1 766 * @brief Enable the NAND device access.
bogdanm 89:552587b429a1 767 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 768 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 769 * @retval none
bogdanm 89:552587b429a1 770 */
bogdanm 89:552587b429a1 771 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
bogdanm 89:552587b429a1 772 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
bogdanm 89:552587b429a1 773
bogdanm 89:552587b429a1 774
bogdanm 89:552587b429a1 775 /**
bogdanm 89:552587b429a1 776 * @brief Disable the NAND device access.
bogdanm 89:552587b429a1 777 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 778 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 779 * @retval none
bogdanm 89:552587b429a1 780 */
bogdanm 89:552587b429a1 781 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
bogdanm 89:552587b429a1 782 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
bogdanm 89:552587b429a1 783
bogdanm 89:552587b429a1 784
bogdanm 89:552587b429a1 785 /**
bogdanm 89:552587b429a1 786 * @}
bogdanm 89:552587b429a1 787 */
bogdanm 89:552587b429a1 788
bogdanm 89:552587b429a1 789 /** @defgroup FSMC_PCCARD_Macros
bogdanm 89:552587b429a1 790 * @brief macros to handle SRAM read/write operations
bogdanm 89:552587b429a1 791 * @{
bogdanm 89:552587b429a1 792 */
bogdanm 89:552587b429a1 793
bogdanm 89:552587b429a1 794 /**
bogdanm 89:552587b429a1 795 * @brief Enable the PCCARD device access.
bogdanm 89:552587b429a1 796 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 797 * @retval none
bogdanm 89:552587b429a1 798 */
bogdanm 89:552587b429a1 799 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
bogdanm 89:552587b429a1 800
bogdanm 89:552587b429a1 801 /**
bogdanm 89:552587b429a1 802 * @brief Disable the PCCARD device access.
bogdanm 89:552587b429a1 803 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 804 * @retval none
bogdanm 89:552587b429a1 805 */
bogdanm 89:552587b429a1 806 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
bogdanm 89:552587b429a1 807
bogdanm 89:552587b429a1 808 /**
bogdanm 89:552587b429a1 809 * @}
bogdanm 89:552587b429a1 810 */
bogdanm 89:552587b429a1 811
bogdanm 89:552587b429a1 812 /** @defgroup FSMC_Interrupt
bogdanm 89:552587b429a1 813 * @brief macros to handle FSMC interrupts
bogdanm 89:552587b429a1 814 * @{
bogdanm 89:552587b429a1 815 */
bogdanm 89:552587b429a1 816
bogdanm 89:552587b429a1 817 /**
bogdanm 89:552587b429a1 818 * @brief Enable the NAND device interrupt.
bogdanm 89:552587b429a1 819 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 820 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 821 * @param __INTERRUPT__: FSMC_NAND interrupt
bogdanm 89:552587b429a1 822 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 823 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 89:552587b429a1 824 * @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm 89:552587b429a1 825 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 89:552587b429a1 826 * @retval None
bogdanm 89:552587b429a1 827 */
bogdanm 89:552587b429a1 828 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
bogdanm 89:552587b429a1 829 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
bogdanm 89:552587b429a1 830
bogdanm 89:552587b429a1 831 /**
bogdanm 89:552587b429a1 832 * @brief Disable the NAND device interrupt.
bogdanm 89:552587b429a1 833 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 834 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 835 * @param __INTERRUPT__: FSMC_NAND interrupt
bogdanm 89:552587b429a1 836 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 837 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 89:552587b429a1 838 * @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm 89:552587b429a1 839 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 89:552587b429a1 840 * @retval None
bogdanm 89:552587b429a1 841 */
bogdanm 89:552587b429a1 842 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm 89:552587b429a1 843 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm 89:552587b429a1 844
bogdanm 89:552587b429a1 845 /**
bogdanm 89:552587b429a1 846 * @brief Get flag status of the NAND device.
bogdanm 89:552587b429a1 847 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 848 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 849 * @param __FLAG__: FSMC_NAND flag
bogdanm 89:552587b429a1 850 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 851 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 89:552587b429a1 852 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 89:552587b429a1 853 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 89:552587b429a1 854 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 89:552587b429a1 855 * @retval The state of FLAG (SET or RESET).
bogdanm 89:552587b429a1 856 */
bogdanm 89:552587b429a1 857 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm 89:552587b429a1 858 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm 89:552587b429a1 859 /**
bogdanm 89:552587b429a1 860 * @brief Clear flag status of the NAND device.
bogdanm 89:552587b429a1 861 * @param __INSTANCE__: FSMC_NAND Instance
bogdanm 89:552587b429a1 862 * @param __BANK__: FSMC_NAND Bank
bogdanm 89:552587b429a1 863 * @param __FLAG__: FSMC_NAND flag
bogdanm 89:552587b429a1 864 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 865 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 89:552587b429a1 866 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 89:552587b429a1 867 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 89:552587b429a1 868 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 89:552587b429a1 869 * @retval None
bogdanm 89:552587b429a1 870 */
bogdanm 89:552587b429a1 871 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm 89:552587b429a1 872 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm 89:552587b429a1 873 /**
bogdanm 89:552587b429a1 874 * @brief Enable the PCCARD device interrupt.
bogdanm 89:552587b429a1 875 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 876 * @param __INTERRUPT__: FSMC_PCCARD interrupt
bogdanm 89:552587b429a1 877 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 878 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 89:552587b429a1 879 * @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm 89:552587b429a1 880 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 89:552587b429a1 881 * @retval None
bogdanm 89:552587b429a1 882 */
bogdanm 89:552587b429a1 883 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
bogdanm 89:552587b429a1 884
bogdanm 89:552587b429a1 885 /**
bogdanm 89:552587b429a1 886 * @brief Disable the PCCARD device interrupt.
bogdanm 89:552587b429a1 887 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 888 * @param __INTERRUPT__: FSMC_PCCARD interrupt
bogdanm 89:552587b429a1 889 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 890 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm 89:552587b429a1 891 * @arg FSMC_IT_LEVEL: Interrupt level.
bogdanm 89:552587b429a1 892 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm 89:552587b429a1 893 * @retval None
bogdanm 89:552587b429a1 894 */
bogdanm 89:552587b429a1 895 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 896
bogdanm 89:552587b429a1 897 /**
bogdanm 89:552587b429a1 898 * @brief Get flag status of the PCCARD device.
bogdanm 89:552587b429a1 899 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 900 * @param __FLAG__: FSMC_PCCARD flag
bogdanm 89:552587b429a1 901 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 902 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 89:552587b429a1 903 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 89:552587b429a1 904 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 89:552587b429a1 905 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 89:552587b429a1 906 * @retval The state of FLAG (SET or RESET).
bogdanm 89:552587b429a1 907 */
bogdanm 89:552587b429a1 908 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm 89:552587b429a1 909
bogdanm 89:552587b429a1 910 /**
bogdanm 89:552587b429a1 911 * @brief Clear flag status of the PCCARD device.
bogdanm 89:552587b429a1 912 * @param __INSTANCE__: FSMC_PCCARD Instance
bogdanm 89:552587b429a1 913 * @param __FLAG__: FSMC_PCCARD flag
bogdanm 89:552587b429a1 914 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 915 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm 89:552587b429a1 916 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm 89:552587b429a1 917 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm 89:552587b429a1 918 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
bogdanm 89:552587b429a1 919 * @retval None
bogdanm 89:552587b429a1 920 */
bogdanm 89:552587b429a1 921 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm 89:552587b429a1 922
bogdanm 89:552587b429a1 923 /**
bogdanm 89:552587b429a1 924 * @}
bogdanm 89:552587b429a1 925 */
bogdanm 89:552587b429a1 926
bogdanm 89:552587b429a1 927 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 928
bogdanm 89:552587b429a1 929 /* FSMC_NORSRAM Controller functions ******************************************/
bogdanm 89:552587b429a1 930 /* Initialization/de-initialization functions */
bogdanm 89:552587b429a1 931 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
bogdanm 89:552587b429a1 932 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 89:552587b429a1 933 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm 89:552587b429a1 934 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
bogdanm 89:552587b429a1 935
bogdanm 89:552587b429a1 936 /* FSMC_NORSRAM Control functions */
bogdanm 89:552587b429a1 937 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 89:552587b429a1 938 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm 89:552587b429a1 939
bogdanm 89:552587b429a1 940 /* FSMC_NAND Controller functions *********************************************/
bogdanm 89:552587b429a1 941 /* Initialization/de-initialization functions */
bogdanm 89:552587b429a1 942 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
bogdanm 89:552587b429a1 943 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 89:552587b429a1 944 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
bogdanm 89:552587b429a1 945 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 89:552587b429a1 946
bogdanm 89:552587b429a1 947 /* FSMC_NAND Control functions */
bogdanm 89:552587b429a1 948 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 89:552587b429a1 949 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm 89:552587b429a1 950 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm 89:552587b429a1 951
bogdanm 89:552587b429a1 952 /* FSMC_PCCARD Controller functions *******************************************/
bogdanm 89:552587b429a1 953 /* Initialization/de-initialization functions */
bogdanm 89:552587b429a1 954 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
bogdanm 89:552587b429a1 955 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 89:552587b429a1 956 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 89:552587b429a1 957 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
bogdanm 89:552587b429a1 958 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
bogdanm 89:552587b429a1 959
bogdanm 89:552587b429a1 960 /* FSMC APIs, macros and typedefs redefinition */
bogdanm 89:552587b429a1 961 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 962 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 963 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
bogdanm 89:552587b429a1 964 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
bogdanm 89:552587b429a1 965
bogdanm 89:552587b429a1 966 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
bogdanm 89:552587b429a1 967 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
bogdanm 89:552587b429a1 968 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
bogdanm 89:552587b429a1 969 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
bogdanm 89:552587b429a1 970 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
bogdanm 89:552587b429a1 971 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
bogdanm 89:552587b429a1 972
bogdanm 89:552587b429a1 973 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
bogdanm 89:552587b429a1 974 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
bogdanm 89:552587b429a1 975
bogdanm 89:552587b429a1 976 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
bogdanm 89:552587b429a1 977 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
bogdanm 89:552587b429a1 978 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
bogdanm 89:552587b429a1 979
bogdanm 89:552587b429a1 980 #define FMC_NAND_Init FSMC_NAND_Init
bogdanm 89:552587b429a1 981 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 982 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 983 #define FMC_NAND_DeInit FSMC_NAND_DeInit
bogdanm 89:552587b429a1 984 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
bogdanm 89:552587b429a1 985 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
bogdanm 89:552587b429a1 986 #define FMC_NAND_GetECC FSMC_NAND_GetECC
bogdanm 89:552587b429a1 987 #define FMC_PCCARD_Init FSMC_PCCARD_Init
bogdanm 89:552587b429a1 988 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
bogdanm 89:552587b429a1 989 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
bogdanm 89:552587b429a1 990 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
bogdanm 89:552587b429a1 991 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
bogdanm 89:552587b429a1 992
bogdanm 89:552587b429a1 993 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
bogdanm 89:552587b429a1 994 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
bogdanm 89:552587b429a1 995 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
bogdanm 89:552587b429a1 996 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
bogdanm 89:552587b429a1 997 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
bogdanm 89:552587b429a1 998 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
bogdanm 89:552587b429a1 999 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
bogdanm 89:552587b429a1 1000 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
bogdanm 89:552587b429a1 1001 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
bogdanm 89:552587b429a1 1002 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
bogdanm 89:552587b429a1 1003 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
bogdanm 89:552587b429a1 1004 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
bogdanm 89:552587b429a1 1005
bogdanm 89:552587b429a1 1006 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
bogdanm 89:552587b429a1 1007 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
bogdanm 89:552587b429a1 1008 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
bogdanm 89:552587b429a1 1009 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
bogdanm 89:552587b429a1 1010
bogdanm 89:552587b429a1 1011 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
bogdanm 89:552587b429a1 1012 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
bogdanm 89:552587b429a1 1013 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
bogdanm 89:552587b429a1 1014 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
bogdanm 89:552587b429a1 1015
bogdanm 89:552587b429a1 1016 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
bogdanm 89:552587b429a1 1017
bogdanm 92:4fc01daae5a5 1018 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
bogdanm 92:4fc01daae5a5 1019 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
bogdanm 92:4fc01daae5a5 1020 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
bogdanm 92:4fc01daae5a5 1021
bogdanm 89:552587b429a1 1022 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
bogdanm 89:552587b429a1 1023 #define FMC_IT_LEVEL FSMC_IT_LEVEL
bogdanm 89:552587b429a1 1024 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
bogdanm 89:552587b429a1 1025 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
bogdanm 89:552587b429a1 1026
bogdanm 89:552587b429a1 1027 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
bogdanm 89:552587b429a1 1028 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
bogdanm 89:552587b429a1 1029 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
bogdanm 89:552587b429a1 1030 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
bogdanm 89:552587b429a1 1031
bogdanm 89:552587b429a1 1032 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 1033
bogdanm 89:552587b429a1 1034 /**
bogdanm 89:552587b429a1 1035 * @}
bogdanm 89:552587b429a1 1036 */
bogdanm 89:552587b429a1 1037
bogdanm 89:552587b429a1 1038 /**
bogdanm 89:552587b429a1 1039 * @}
bogdanm 89:552587b429a1 1040 */
bogdanm 89:552587b429a1 1041
bogdanm 89:552587b429a1 1042 #ifdef __cplusplus
bogdanm 89:552587b429a1 1043 }
bogdanm 89:552587b429a1 1044 #endif
bogdanm 89:552587b429a1 1045
bogdanm 89:552587b429a1 1046 #endif /* __STM32F4xx_LL_FSMC_H */
bogdanm 89:552587b429a1 1047
bogdanm 89:552587b429a1 1048 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/