Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_RBLAB_NRF51822/nrf51.h@97:433970e64889, 2015-04-14 (annotated)

Committer:
Kojto
Date:
Tue Apr 14 10:58:58 2015 +0200
Revision:
97:433970e64889
Parent:
93:e188a91d3eaa 
Release 97 of the mbed library



Changes:

- NRF51 - Update Softdevice, fix us ticker

- MTS Dragonfly - bugfixes, IAR support

- MTS mdot - bootloader support

- RZ_A1 - nvic wrapper

- STM F3xx, F4xx - hal reorganization

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 97:433970e64889 1
Kojto 97:433970e64889 2 /****************************************************************************************************//**
Kojto 97:433970e64889 3 * @file nRF51.h
Kojto 97:433970e64889 4 *
Kojto 97:433970e64889 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
Kojto 97:433970e64889 6 * nRF51 from Nordic Semiconductor.
Kojto 97:433970e64889 7 *
Kojto 97:433970e64889 8 * @version V522
Kojto 97:433970e64889 9 * @date 31. October 2014
bogdanm 87:6213f644d804 10 *
Kojto 97:433970e64889 11 * @note Generated with SVDConv V2.81d
Kojto 97:433970e64889 12 * from CMSIS SVD File 'nRF51.xml' Version 522,
Kojto 97:433970e64889 13 *
Kojto 97:433970e64889 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
Kojto 97:433970e64889 15 * All rights reserved.
Kojto 97:433970e64889 16 *
Kojto 97:433970e64889 17 * Redistribution and use in source and binary forms, with or without
Kojto 97:433970e64889 18 * modification, are permitted provided that the following conditions are met:
Kojto 97:433970e64889 19 *
Kojto 97:433970e64889 20 * * Redistributions of source code must retain the above copyright notice, this
Kojto 97:433970e64889 21 * list of conditions and the following disclaimer.
bogdanm 87:6213f644d804 22 *
Kojto 97:433970e64889 23 * * Redistributions in binary form must reproduce the above copyright notice,
Kojto 97:433970e64889 24 * this list of conditions and the following disclaimer in the documentation
Kojto 97:433970e64889 25 * and/or other materials provided with the distribution.
Kojto 97:433970e64889 26 *
Kojto 97:433970e64889 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto 97:433970e64889 28 * contributors may be used to endorse or promote products derived from
Kojto 97:433970e64889 29 * this software without specific prior written permission.
bogdanm 87:6213f644d804 30 *
Kojto 97:433970e64889 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 97:433970e64889 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 97:433970e64889 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 97:433970e64889 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 97:433970e64889 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 97:433970e64889 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 97:433970e64889 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 97:433970e64889 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 97:433970e64889 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 97:433970e64889 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 97:433970e64889 41 *
Kojto 97:433970e64889 42 *
Kojto 97:433970e64889 43 *******************************************************************************************************/
bogdanm 87:6213f644d804 44
bogdanm 87:6213f644d804 45
bogdanm 87:6213f644d804 46
bogdanm 87:6213f644d804 47 /** @addtogroup Nordic Semiconductor
bogdanm 87:6213f644d804 48 * @{
bogdanm 87:6213f644d804 49 */
bogdanm 87:6213f644d804 50
bogdanm 87:6213f644d804 51 /** @addtogroup nRF51
bogdanm 87:6213f644d804 52 * @{
bogdanm 87:6213f644d804 53 */
bogdanm 87:6213f644d804 54
bogdanm 87:6213f644d804 55 #ifndef NRF51_H
bogdanm 87:6213f644d804 56 #define NRF51_H
bogdanm 87:6213f644d804 57
bogdanm 87:6213f644d804 58 #ifdef __cplusplus
bogdanm 87:6213f644d804 59 extern "C" {
bogdanm 87:6213f644d804 60 #endif
bogdanm 87:6213f644d804 61
bogdanm 87:6213f644d804 62
bogdanm 87:6213f644d804 63 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 87:6213f644d804 64
bogdanm 87:6213f644d804 65 typedef enum {
bogdanm 87:6213f644d804 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm 87:6213f644d804 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 87:6213f644d804 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 87:6213f644d804 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 87:6213f644d804 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 87:6213f644d804 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 87:6213f644d804 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 87:6213f644d804 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 87:6213f644d804 74 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
bogdanm 87:6213f644d804 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
bogdanm 87:6213f644d804 76 RADIO_IRQn = 1, /*!< 1 RADIO */
bogdanm 87:6213f644d804 77 UART0_IRQn = 2, /*!< 2 UART0 */
bogdanm 87:6213f644d804 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
bogdanm 87:6213f644d804 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
bogdanm 87:6213f644d804 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
bogdanm 87:6213f644d804 81 ADC_IRQn = 7, /*!< 7 ADC */
bogdanm 87:6213f644d804 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
bogdanm 87:6213f644d804 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
bogdanm 87:6213f644d804 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
bogdanm 87:6213f644d804 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
bogdanm 87:6213f644d804 86 TEMP_IRQn = 12, /*!< 12 TEMP */
bogdanm 87:6213f644d804 87 RNG_IRQn = 13, /*!< 13 RNG */
bogdanm 87:6213f644d804 88 ECB_IRQn = 14, /*!< 14 ECB */
bogdanm 87:6213f644d804 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
bogdanm 87:6213f644d804 90 WDT_IRQn = 16, /*!< 16 WDT */
bogdanm 87:6213f644d804 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
bogdanm 87:6213f644d804 92 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 97:433970e64889 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
bogdanm 87:6213f644d804 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
bogdanm 87:6213f644d804 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
bogdanm 87:6213f644d804 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
bogdanm 87:6213f644d804 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
bogdanm 87:6213f644d804 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
bogdanm 87:6213f644d804 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
bogdanm 87:6213f644d804 100 } IRQn_Type;
bogdanm 87:6213f644d804 101
bogdanm 87:6213f644d804 102
bogdanm 87:6213f644d804 103 /** @addtogroup Configuration_of_CMSIS
bogdanm 87:6213f644d804 104 * @{
bogdanm 87:6213f644d804 105 */
bogdanm 87:6213f644d804 106
bogdanm 87:6213f644d804 107
bogdanm 87:6213f644d804 108 /* ================================================================================ */
bogdanm 87:6213f644d804 109 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 87:6213f644d804 110 /* ================================================================================ */
bogdanm 87:6213f644d804 111
Kojto 97:433970e64889 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
bogdanm 87:6213f644d804 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
bogdanm 87:6213f644d804 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 87:6213f644d804 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 87:6213f644d804 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 87:6213f644d804 117 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 87:6213f644d804 118
Kojto 97:433970e64889 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Kojto 97:433970e64889 120 #include "system_nrf51.h" /*!< nRF51 System */
bogdanm 87:6213f644d804 121
bogdanm 87:6213f644d804 122 /* ================================================================================ */
bogdanm 87:6213f644d804 123 /* ================ Device Specific Peripheral Section ================ */
bogdanm 87:6213f644d804 124 /* ================================================================================ */
bogdanm 87:6213f644d804 125
bogdanm 87:6213f644d804 126
bogdanm 87:6213f644d804 127 /** @addtogroup Device_Peripheral_Registers
bogdanm 87:6213f644d804 128 * @{
bogdanm 87:6213f644d804 129 */
bogdanm 87:6213f644d804 130
bogdanm 87:6213f644d804 131
bogdanm 87:6213f644d804 132 /* ------------------- Start of section using anonymous unions ------------------ */
bogdanm 87:6213f644d804 133 #if defined(__CC_ARM)
bogdanm 87:6213f644d804 134 #pragma push
bogdanm 87:6213f644d804 135 #pragma anon_unions
bogdanm 87:6213f644d804 136 #elif defined(__ICCARM__)
bogdanm 87:6213f644d804 137 #pragma language=extended
bogdanm 87:6213f644d804 138 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 139 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 140 #elif defined(__TMS470__)
bogdanm 87:6213f644d804 141 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 142 #elif defined(__TASKING__)
bogdanm 87:6213f644d804 143 #pragma warning 586
bogdanm 87:6213f644d804 144 #else
bogdanm 87:6213f644d804 145 #warning Not supported compiler type
bogdanm 87:6213f644d804 146 #endif
bogdanm 87:6213f644d804 147
bogdanm 87:6213f644d804 148
bogdanm 87:6213f644d804 149 typedef struct {
bogdanm 87:6213f644d804 150 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
bogdanm 87:6213f644d804 151 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
bogdanm 87:6213f644d804 152 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
bogdanm 87:6213f644d804 153 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
bogdanm 87:6213f644d804 154 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
bogdanm 87:6213f644d804 155 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
bogdanm 87:6213f644d804 156 } AMLI_RAMPRI_Type;
bogdanm 87:6213f644d804 157
bogdanm 87:6213f644d804 158 typedef struct {
Kojto 97:433970e64889 159 __IO uint32_t SCK; /*!< Pin select for SCK. */
Kojto 97:433970e64889 160 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Kojto 97:433970e64889 161 __IO uint32_t MISO; /*!< Pin select for MISO. */
Kojto 97:433970e64889 162 } SPIM_PSEL_Type;
Kojto 97:433970e64889 163
Kojto 97:433970e64889 164 typedef struct {
Kojto 97:433970e64889 165 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 166 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Kojto 97:433970e64889 167 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Kojto 97:433970e64889 168 } SPIM_RXD_Type;
Kojto 97:433970e64889 169
Kojto 97:433970e64889 170 typedef struct {
Kojto 97:433970e64889 171 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 172 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Kojto 97:433970e64889 173 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Kojto 97:433970e64889 174 } SPIM_TXD_Type;
Kojto 97:433970e64889 175
Kojto 97:433970e64889 176 typedef struct {
bogdanm 87:6213f644d804 177 __O uint32_t EN; /*!< Enable channel group. */
bogdanm 87:6213f644d804 178 __O uint32_t DIS; /*!< Disable channel group. */
bogdanm 87:6213f644d804 179 } PPI_TASKS_CHG_Type;
bogdanm 87:6213f644d804 180
bogdanm 87:6213f644d804 181 typedef struct {
bogdanm 87:6213f644d804 182 __IO uint32_t EEP; /*!< Channel event end-point. */
bogdanm 87:6213f644d804 183 __IO uint32_t TEP; /*!< Channel task end-point. */
bogdanm 87:6213f644d804 184 } PPI_CH_Type;
bogdanm 87:6213f644d804 185
Kojto 97:433970e64889 186 typedef struct {
Kojto 97:433970e64889 187 __I uint32_t PART; /*!< Part code */
Kojto 97:433970e64889 188 __I uint32_t VARIANT; /*!< Part variant */
Kojto 97:433970e64889 189 __I uint32_t PACKAGE; /*!< Package option */
Kojto 97:433970e64889 190 __I uint32_t RAM; /*!< RAM variant */
Kojto 97:433970e64889 191 __I uint32_t FLASH; /*!< Flash variant */
Kojto 97:433970e64889 192 __I uint32_t RESERVED[3]; /*!< Reserved */
Kojto 97:433970e64889 193 } FICR_INFO_Type;
Kojto 97:433970e64889 194
bogdanm 87:6213f644d804 195
bogdanm 87:6213f644d804 196 /* ================================================================================ */
bogdanm 87:6213f644d804 197 /* ================ POWER ================ */
bogdanm 87:6213f644d804 198 /* ================================================================================ */
bogdanm 87:6213f644d804 199
bogdanm 87:6213f644d804 200
bogdanm 87:6213f644d804 201 /**
bogdanm 87:6213f644d804 202 * @brief Power Control. (POWER)
bogdanm 87:6213f644d804 203 */
bogdanm 87:6213f644d804 204
bogdanm 87:6213f644d804 205 typedef struct { /*!< POWER Structure */
bogdanm 87:6213f644d804 206 __I uint32_t RESERVED0[30];
bogdanm 87:6213f644d804 207 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
bogdanm 87:6213f644d804 208 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
bogdanm 87:6213f644d804 209 __I uint32_t RESERVED1[34];
bogdanm 87:6213f644d804 210 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
bogdanm 87:6213f644d804 211 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 212 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 213 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 214 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 215 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 97:433970e64889 216 __I uint32_t RESERVED4[9];
Kojto 97:433970e64889 217 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Kojto 97:433970e64889 218 __I uint32_t RESERVED5[53];
bogdanm 87:6213f644d804 219 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 97:433970e64889 220 __I uint32_t RESERVED6[3];
bogdanm 87:6213f644d804 221 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 97:433970e64889 222 __I uint32_t RESERVED7[2];
bogdanm 87:6213f644d804 223 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
bogdanm 87:6213f644d804 224 register. */
Kojto 97:433970e64889 225 __I uint32_t RESERVED8;
bogdanm 87:6213f644d804 226 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 97:433970e64889 227 __I uint32_t RESERVED9[7];
bogdanm 87:6213f644d804 228 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
bogdanm 87:6213f644d804 229 is a retained register. */
Kojto 97:433970e64889 230 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 231 __IO uint32_t RAMONB; /*!< Ram on/off. */
Kojto 97:433970e64889 232 __I uint32_t RESERVED11[8];
bogdanm 87:6213f644d804 233 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 97:433970e64889 234 __I uint32_t RESERVED12[291];
Kojto 97:433970e64889 235 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
bogdanm 87:6213f644d804 236 } NRF_POWER_Type;
bogdanm 87:6213f644d804 237
bogdanm 87:6213f644d804 238
bogdanm 87:6213f644d804 239 /* ================================================================================ */
bogdanm 87:6213f644d804 240 /* ================ CLOCK ================ */
bogdanm 87:6213f644d804 241 /* ================================================================================ */
bogdanm 87:6213f644d804 242
bogdanm 87:6213f644d804 243
bogdanm 87:6213f644d804 244 /**
bogdanm 87:6213f644d804 245 * @brief Clock control. (CLOCK)
bogdanm 87:6213f644d804 246 */
bogdanm 87:6213f644d804 247
bogdanm 87:6213f644d804 248 typedef struct { /*!< CLOCK Structure */
bogdanm 87:6213f644d804 249 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
bogdanm 87:6213f644d804 250 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
bogdanm 87:6213f644d804 251 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
bogdanm 87:6213f644d804 252 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
bogdanm 87:6213f644d804 253 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
bogdanm 87:6213f644d804 254 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
bogdanm 87:6213f644d804 255 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
bogdanm 87:6213f644d804 256 __I uint32_t RESERVED0[57];
bogdanm 87:6213f644d804 257 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
bogdanm 87:6213f644d804 258 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
bogdanm 87:6213f644d804 259 __I uint32_t RESERVED1;
Kojto 97:433970e64889 260 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Kojto 97:433970e64889 261 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
bogdanm 87:6213f644d804 262 __I uint32_t RESERVED2[124];
bogdanm 87:6213f644d804 263 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 264 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 265 __I uint32_t RESERVED3[63];
Kojto 97:433970e64889 266 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
bogdanm 87:6213f644d804 267 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 97:433970e64889 268 __I uint32_t RESERVED4;
Kojto 97:433970e64889 269 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
bogdanm 87:6213f644d804 270 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 97:433970e64889 271 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto 97:433970e64889 272 triggered. */
Kojto 97:433970e64889 273 __I uint32_t RESERVED5[62];
bogdanm 87:6213f644d804 274 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
bogdanm 87:6213f644d804 275 __I uint32_t RESERVED6[7];
bogdanm 87:6213f644d804 276 __IO uint32_t CTIV; /*!< Calibration timer interval. */
bogdanm 87:6213f644d804 277 __I uint32_t RESERVED7[5];
bogdanm 87:6213f644d804 278 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
bogdanm 87:6213f644d804 279 } NRF_CLOCK_Type;
bogdanm 87:6213f644d804 280
bogdanm 87:6213f644d804 281
bogdanm 87:6213f644d804 282 /* ================================================================================ */
bogdanm 87:6213f644d804 283 /* ================ MPU ================ */
bogdanm 87:6213f644d804 284 /* ================================================================================ */
bogdanm 87:6213f644d804 285
bogdanm 87:6213f644d804 286
bogdanm 87:6213f644d804 287 /**
bogdanm 87:6213f644d804 288 * @brief Memory Protection Unit. (MPU)
bogdanm 87:6213f644d804 289 */
bogdanm 87:6213f644d804 290
bogdanm 87:6213f644d804 291 typedef struct { /*!< MPU Structure */
bogdanm 87:6213f644d804 292 __I uint32_t RESERVED0[330];
bogdanm 87:6213f644d804 293 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
bogdanm 87:6213f644d804 294 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
bogdanm 87:6213f644d804 295 __I uint32_t RESERVED1[52];
Kojto 97:433970e64889 296 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 297 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 298 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Kojto 97:433970e64889 299 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
bogdanm 87:6213f644d804 300 } NRF_MPU_Type;
bogdanm 87:6213f644d804 301
bogdanm 87:6213f644d804 302
bogdanm 87:6213f644d804 303 /* ================================================================================ */
bogdanm 87:6213f644d804 304 /* ================ PU ================ */
bogdanm 87:6213f644d804 305 /* ================================================================================ */
bogdanm 87:6213f644d804 306
bogdanm 87:6213f644d804 307
bogdanm 87:6213f644d804 308 /**
bogdanm 87:6213f644d804 309 * @brief Patch unit. (PU)
bogdanm 87:6213f644d804 310 */
bogdanm 87:6213f644d804 311
bogdanm 87:6213f644d804 312 typedef struct { /*!< PU Structure */
bogdanm 87:6213f644d804 313 __I uint32_t RESERVED0[448];
bogdanm 87:6213f644d804 314 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
bogdanm 87:6213f644d804 315 __I uint32_t RESERVED1[24];
bogdanm 87:6213f644d804 316 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
bogdanm 87:6213f644d804 317 __I uint32_t RESERVED2[24];
bogdanm 87:6213f644d804 318 __IO uint32_t PATCHEN; /*!< Patch enable register. */
bogdanm 87:6213f644d804 319 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
bogdanm 87:6213f644d804 320 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
bogdanm 87:6213f644d804 321 } NRF_PU_Type;
bogdanm 87:6213f644d804 322
bogdanm 87:6213f644d804 323
bogdanm 87:6213f644d804 324 /* ================================================================================ */
bogdanm 87:6213f644d804 325 /* ================ AMLI ================ */
bogdanm 87:6213f644d804 326 /* ================================================================================ */
bogdanm 87:6213f644d804 327
bogdanm 87:6213f644d804 328
bogdanm 87:6213f644d804 329 /**
bogdanm 87:6213f644d804 330 * @brief AHB Multi-Layer Interface. (AMLI)
bogdanm 87:6213f644d804 331 */
bogdanm 87:6213f644d804 332
bogdanm 87:6213f644d804 333 typedef struct { /*!< AMLI Structure */
bogdanm 87:6213f644d804 334 __I uint32_t RESERVED0[896];
bogdanm 87:6213f644d804 335 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
bogdanm 87:6213f644d804 336 } NRF_AMLI_Type;
bogdanm 87:6213f644d804 337
bogdanm 87:6213f644d804 338
bogdanm 87:6213f644d804 339 /* ================================================================================ */
bogdanm 87:6213f644d804 340 /* ================ RADIO ================ */
bogdanm 87:6213f644d804 341 /* ================================================================================ */
bogdanm 87:6213f644d804 342
bogdanm 87:6213f644d804 343
bogdanm 87:6213f644d804 344 /**
bogdanm 87:6213f644d804 345 * @brief The radio. (RADIO)
bogdanm 87:6213f644d804 346 */
bogdanm 87:6213f644d804 347
bogdanm 87:6213f644d804 348 typedef struct { /*!< RADIO Structure */
bogdanm 87:6213f644d804 349 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
bogdanm 87:6213f644d804 350 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
bogdanm 87:6213f644d804 351 __O uint32_t TASKS_START; /*!< Start radio. */
bogdanm 87:6213f644d804 352 __O uint32_t TASKS_STOP; /*!< Stop radio. */
bogdanm 87:6213f644d804 353 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
bogdanm 87:6213f644d804 354 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
bogdanm 87:6213f644d804 355 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
bogdanm 87:6213f644d804 356 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
bogdanm 87:6213f644d804 357 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
bogdanm 87:6213f644d804 358 __I uint32_t RESERVED0[55];
bogdanm 87:6213f644d804 359 __IO uint32_t EVENTS_READY; /*!< Ready event. */
bogdanm 87:6213f644d804 360 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
bogdanm 87:6213f644d804 361 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
bogdanm 87:6213f644d804 362 __IO uint32_t EVENTS_END; /*!< End event. */
bogdanm 87:6213f644d804 363 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
bogdanm 87:6213f644d804 364 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
bogdanm 87:6213f644d804 365 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
bogdanm 87:6213f644d804 366 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
bogdanm 87:6213f644d804 367 sample is ready for readout at the RSSISAMPLE register. */
bogdanm 87:6213f644d804 368 __I uint32_t RESERVED1[2];
bogdanm 87:6213f644d804 369 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
bogdanm 87:6213f644d804 370 __I uint32_t RESERVED2[53];
Kojto 97:433970e64889 371 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
bogdanm 87:6213f644d804 372 __I uint32_t RESERVED3[64];
bogdanm 87:6213f644d804 373 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 374 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 375 __I uint32_t RESERVED4[61];
bogdanm 87:6213f644d804 376 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 97:433970e64889 377 __I uint32_t CD; /*!< Carrier detect. */
bogdanm 87:6213f644d804 378 __I uint32_t RXMATCH; /*!< Received address. */
bogdanm 87:6213f644d804 379 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 97:433970e64889 380 __I uint32_t DAI; /*!< Device address match index. */
Kojto 97:433970e64889 381 __I uint32_t RESERVED5[60];
bogdanm 87:6213f644d804 382 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
bogdanm 87:6213f644d804 383 __IO uint32_t FREQUENCY; /*!< Frequency. */
bogdanm 87:6213f644d804 384 __IO uint32_t TXPOWER; /*!< Output power. */
bogdanm 87:6213f644d804 385 __IO uint32_t MODE; /*!< Data rate and modulation. */
bogdanm 87:6213f644d804 386 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
bogdanm 87:6213f644d804 387 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
bogdanm 87:6213f644d804 388 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
bogdanm 87:6213f644d804 389 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
bogdanm 87:6213f644d804 390 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
bogdanm 87:6213f644d804 391 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
bogdanm 87:6213f644d804 392 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
bogdanm 87:6213f644d804 393 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
bogdanm 87:6213f644d804 394 __IO uint32_t CRCCNF; /*!< CRC configuration. */
bogdanm 87:6213f644d804 395 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
bogdanm 87:6213f644d804 396 __IO uint32_t CRCINIT; /*!< CRC initial value. */
bogdanm 87:6213f644d804 397 __IO uint32_t TEST; /*!< Test features enable register. */
bogdanm 87:6213f644d804 398 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 97:433970e64889 399 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 97:433970e64889 400 __I uint32_t RESERVED6;
bogdanm 87:6213f644d804 401 __I uint32_t STATE; /*!< Current radio state. */
bogdanm 87:6213f644d804 402 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 97:433970e64889 403 __I uint32_t RESERVED7[2];
bogdanm 87:6213f644d804 404 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 97:433970e64889 405 __I uint32_t RESERVED8[39];
bogdanm 87:6213f644d804 406 __IO uint32_t DAB[8]; /*!< Device address base segment. */
bogdanm 87:6213f644d804 407 __IO uint32_t DAP[8]; /*!< Device address prefix. */
bogdanm 87:6213f644d804 408 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 97:433970e64889 409 __I uint32_t RESERVED9[56];
bogdanm 87:6213f644d804 410 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
bogdanm 87:6213f644d804 411 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
bogdanm 87:6213f644d804 412 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
bogdanm 87:6213f644d804 413 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
bogdanm 87:6213f644d804 414 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 97:433970e64889 415 __I uint32_t RESERVED10[561];
bogdanm 87:6213f644d804 416 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 417 } NRF_RADIO_Type;
bogdanm 87:6213f644d804 418
bogdanm 87:6213f644d804 419
bogdanm 87:6213f644d804 420 /* ================================================================================ */
bogdanm 87:6213f644d804 421 /* ================ UART ================ */
bogdanm 87:6213f644d804 422 /* ================================================================================ */
bogdanm 87:6213f644d804 423
bogdanm 87:6213f644d804 424
bogdanm 87:6213f644d804 425 /**
bogdanm 87:6213f644d804 426 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
bogdanm 87:6213f644d804 427 */
bogdanm 87:6213f644d804 428
bogdanm 87:6213f644d804 429 typedef struct { /*!< UART Structure */
bogdanm 87:6213f644d804 430 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
bogdanm 87:6213f644d804 431 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
bogdanm 87:6213f644d804 432 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
bogdanm 87:6213f644d804 433 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
bogdanm 87:6213f644d804 434 __I uint32_t RESERVED0[3];
bogdanm 87:6213f644d804 435 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
bogdanm 87:6213f644d804 436 __I uint32_t RESERVED1[56];
bogdanm 87:6213f644d804 437 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
bogdanm 87:6213f644d804 438 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
bogdanm 87:6213f644d804 439 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
bogdanm 87:6213f644d804 440 __I uint32_t RESERVED2[4];
bogdanm 87:6213f644d804 441 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
bogdanm 87:6213f644d804 442 __I uint32_t RESERVED3;
bogdanm 87:6213f644d804 443 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
bogdanm 87:6213f644d804 444 __I uint32_t RESERVED4[7];
bogdanm 87:6213f644d804 445 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
bogdanm 87:6213f644d804 446 __I uint32_t RESERVED5[46];
Kojto 97:433970e64889 447 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Kojto 97:433970e64889 448 __I uint32_t RESERVED6[64];
bogdanm 87:6213f644d804 449 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 450 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 451 __I uint32_t RESERVED7[93];
bogdanm 87:6213f644d804 452 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
bogdanm 87:6213f644d804 453 __I uint32_t RESERVED8[31];
bogdanm 87:6213f644d804 454 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
bogdanm 87:6213f644d804 455 __I uint32_t RESERVED9;
bogdanm 87:6213f644d804 456 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
bogdanm 87:6213f644d804 457 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
bogdanm 87:6213f644d804 458 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
bogdanm 87:6213f644d804 459 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
bogdanm 87:6213f644d804 460 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 97:433970e64889 461 Once read the character is consumed. If read when no character
bogdanm 87:6213f644d804 462 available, the UART will stop working. */
bogdanm 87:6213f644d804 463 __O uint32_t TXD; /*!< TXD register. */
bogdanm 87:6213f644d804 464 __I uint32_t RESERVED10;
bogdanm 87:6213f644d804 465 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
bogdanm 87:6213f644d804 466 __I uint32_t RESERVED11[17];
bogdanm 87:6213f644d804 467 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
bogdanm 87:6213f644d804 468 __I uint32_t RESERVED12[675];
bogdanm 87:6213f644d804 469 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 470 } NRF_UART_Type;
bogdanm 87:6213f644d804 471
bogdanm 87:6213f644d804 472
bogdanm 87:6213f644d804 473 /* ================================================================================ */
bogdanm 87:6213f644d804 474 /* ================ SPI ================ */
bogdanm 87:6213f644d804 475 /* ================================================================================ */
bogdanm 87:6213f644d804 476
bogdanm 87:6213f644d804 477
bogdanm 87:6213f644d804 478 /**
bogdanm 87:6213f644d804 479 * @brief SPI master 0. (SPI)
bogdanm 87:6213f644d804 480 */
bogdanm 87:6213f644d804 481
bogdanm 87:6213f644d804 482 typedef struct { /*!< SPI Structure */
bogdanm 87:6213f644d804 483 __I uint32_t RESERVED0[66];
bogdanm 87:6213f644d804 484 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
bogdanm 87:6213f644d804 485 __I uint32_t RESERVED1[126];
bogdanm 87:6213f644d804 486 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 487 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 488 __I uint32_t RESERVED2[125];
bogdanm 87:6213f644d804 489 __IO uint32_t ENABLE; /*!< Enable SPI. */
bogdanm 87:6213f644d804 490 __I uint32_t RESERVED3;
bogdanm 87:6213f644d804 491 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 87:6213f644d804 492 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 87:6213f644d804 493 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 87:6213f644d804 494 __I uint32_t RESERVED4;
Kojto 97:433970e64889 495 __I uint32_t RXD; /*!< RX data. */
bogdanm 87:6213f644d804 496 __IO uint32_t TXD; /*!< TX data. */
bogdanm 87:6213f644d804 497 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 498 __IO uint32_t FREQUENCY; /*!< SPI frequency */
bogdanm 87:6213f644d804 499 __I uint32_t RESERVED6[11];
bogdanm 87:6213f644d804 500 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 501 __I uint32_t RESERVED7[681];
bogdanm 87:6213f644d804 502 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 503 } NRF_SPI_Type;
bogdanm 87:6213f644d804 504
bogdanm 87:6213f644d804 505
bogdanm 87:6213f644d804 506 /* ================================================================================ */
bogdanm 87:6213f644d804 507 /* ================ TWI ================ */
bogdanm 87:6213f644d804 508 /* ================================================================================ */
bogdanm 87:6213f644d804 509
bogdanm 87:6213f644d804 510
bogdanm 87:6213f644d804 511 /**
bogdanm 87:6213f644d804 512 * @brief Two-wire interface master 0. (TWI)
bogdanm 87:6213f644d804 513 */
bogdanm 87:6213f644d804 514
bogdanm 87:6213f644d804 515 typedef struct { /*!< TWI Structure */
bogdanm 87:6213f644d804 516 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
bogdanm 87:6213f644d804 517 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 518 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
bogdanm 87:6213f644d804 519 __I uint32_t RESERVED1[2];
bogdanm 87:6213f644d804 520 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
bogdanm 87:6213f644d804 521 __I uint32_t RESERVED2;
bogdanm 87:6213f644d804 522 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
bogdanm 87:6213f644d804 523 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
bogdanm 87:6213f644d804 524 __I uint32_t RESERVED3[56];
bogdanm 87:6213f644d804 525 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
bogdanm 87:6213f644d804 526 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
bogdanm 87:6213f644d804 527 __I uint32_t RESERVED4[4];
bogdanm 87:6213f644d804 528 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
bogdanm 87:6213f644d804 529 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 530 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
bogdanm 87:6213f644d804 531 __I uint32_t RESERVED6[4];
bogdanm 87:6213f644d804 532 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 97:433970e64889 533 __I uint32_t RESERVED7[3];
Kojto 97:433970e64889 534 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Kojto 97:433970e64889 535 __I uint32_t RESERVED8[45];
bogdanm 87:6213f644d804 536 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 97:433970e64889 537 __I uint32_t RESERVED9[64];
bogdanm 87:6213f644d804 538 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 539 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 540 __I uint32_t RESERVED10[110];
bogdanm 87:6213f644d804 541 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 97:433970e64889 542 __I uint32_t RESERVED11[14];
bogdanm 87:6213f644d804 543 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 97:433970e64889 544 __I uint32_t RESERVED12;
bogdanm 87:6213f644d804 545 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
bogdanm 87:6213f644d804 546 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 97:433970e64889 547 __I uint32_t RESERVED13[2];
Kojto 97:433970e64889 548 __I uint32_t RXD; /*!< RX data register. */
bogdanm 87:6213f644d804 549 __IO uint32_t TXD; /*!< TX data register. */
Kojto 97:433970e64889 550 __I uint32_t RESERVED14;
bogdanm 87:6213f644d804 551 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 97:433970e64889 552 __I uint32_t RESERVED15[24];
bogdanm 87:6213f644d804 553 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 97:433970e64889 554 __I uint32_t RESERVED16[668];
bogdanm 87:6213f644d804 555 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 556 } NRF_TWI_Type;
bogdanm 87:6213f644d804 557
bogdanm 87:6213f644d804 558
bogdanm 87:6213f644d804 559 /* ================================================================================ */
bogdanm 87:6213f644d804 560 /* ================ SPIS ================ */
bogdanm 87:6213f644d804 561 /* ================================================================================ */
bogdanm 87:6213f644d804 562
bogdanm 87:6213f644d804 563
bogdanm 87:6213f644d804 564 /**
bogdanm 87:6213f644d804 565 * @brief SPI slave 1. (SPIS)
bogdanm 87:6213f644d804 566 */
bogdanm 87:6213f644d804 567
bogdanm 87:6213f644d804 568 typedef struct { /*!< SPIS Structure */
bogdanm 87:6213f644d804 569 __I uint32_t RESERVED0[9];
bogdanm 87:6213f644d804 570 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
bogdanm 87:6213f644d804 571 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
bogdanm 87:6213f644d804 572 __I uint32_t RESERVED1[54];
bogdanm 87:6213f644d804 573 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
bogdanm 87:6213f644d804 574 __I uint32_t RESERVED2[8];
bogdanm 87:6213f644d804 575 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
bogdanm 87:6213f644d804 576 __I uint32_t RESERVED3[53];
bogdanm 87:6213f644d804 577 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
bogdanm 87:6213f644d804 578 __I uint32_t RESERVED4[64];
bogdanm 87:6213f644d804 579 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 580 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 581 __I uint32_t RESERVED5[61];
bogdanm 87:6213f644d804 582 __I uint32_t SEMSTAT; /*!< Semaphore status. */
bogdanm 87:6213f644d804 583 __I uint32_t RESERVED6[15];
bogdanm 87:6213f644d804 584 __IO uint32_t STATUS; /*!< Status from last transaction. */
bogdanm 87:6213f644d804 585 __I uint32_t RESERVED7[47];
bogdanm 87:6213f644d804 586 __IO uint32_t ENABLE; /*!< Enable SPIS. */
bogdanm 87:6213f644d804 587 __I uint32_t RESERVED8;
bogdanm 87:6213f644d804 588 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
bogdanm 87:6213f644d804 589 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
bogdanm 87:6213f644d804 590 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
bogdanm 87:6213f644d804 591 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
bogdanm 87:6213f644d804 592 __I uint32_t RESERVED9[7];
bogdanm 87:6213f644d804 593 __IO uint32_t RXDPTR; /*!< RX data pointer. */
bogdanm 87:6213f644d804 594 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 97:433970e64889 595 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
bogdanm 87:6213f644d804 596 __I uint32_t RESERVED10;
bogdanm 87:6213f644d804 597 __IO uint32_t TXDPTR; /*!< TX data pointer. */
bogdanm 87:6213f644d804 598 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 97:433970e64889 599 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
bogdanm 87:6213f644d804 600 __I uint32_t RESERVED11;
bogdanm 87:6213f644d804 601 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 602 __I uint32_t RESERVED12;
bogdanm 87:6213f644d804 603 __IO uint32_t DEF; /*!< Default character. */
bogdanm 87:6213f644d804 604 __I uint32_t RESERVED13[24];
bogdanm 87:6213f644d804 605 __IO uint32_t ORC; /*!< Over-read character. */
bogdanm 87:6213f644d804 606 __I uint32_t RESERVED14[654];
bogdanm 87:6213f644d804 607 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 608 } NRF_SPIS_Type;
bogdanm 87:6213f644d804 609
bogdanm 87:6213f644d804 610
bogdanm 87:6213f644d804 611 /* ================================================================================ */
Kojto 97:433970e64889 612 /* ================ SPIM ================ */
Kojto 97:433970e64889 613 /* ================================================================================ */
Kojto 97:433970e64889 614
Kojto 97:433970e64889 615
Kojto 97:433970e64889 616 /**
Kojto 97:433970e64889 617 * @brief SPI master with easyDMA 1. (SPIM)
Kojto 97:433970e64889 618 */
Kojto 97:433970e64889 619
Kojto 97:433970e64889 620 typedef struct { /*!< SPIM Structure */
Kojto 97:433970e64889 621 __I uint32_t RESERVED0[4];
Kojto 97:433970e64889 622 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Kojto 97:433970e64889 623 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Kojto 97:433970e64889 624 __I uint32_t RESERVED1;
Kojto 97:433970e64889 625 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Kojto 97:433970e64889 626 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Kojto 97:433970e64889 627 __I uint32_t RESERVED2[56];
Kojto 97:433970e64889 628 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Kojto 97:433970e64889 629 __I uint32_t RESERVED3[2];
Kojto 97:433970e64889 630 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Kojto 97:433970e64889 631 __I uint32_t RESERVED4;
Kojto 97:433970e64889 632 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
Kojto 97:433970e64889 633 __I uint32_t RESERVED5;
Kojto 97:433970e64889 634 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Kojto 97:433970e64889 635 __I uint32_t RESERVED6[10];
Kojto 97:433970e64889 636 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Kojto 97:433970e64889 637 __I uint32_t RESERVED7[44];
Kojto 97:433970e64889 638 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
Kojto 97:433970e64889 639 __I uint32_t RESERVED8[64];
Kojto 97:433970e64889 640 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 97:433970e64889 641 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 642 __I uint32_t RESERVED9[125];
Kojto 97:433970e64889 643 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Kojto 97:433970e64889 644 __I uint32_t RESERVED10;
Kojto 97:433970e64889 645 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Kojto 97:433970e64889 646 __I uint32_t RESERVED11;
Kojto 97:433970e64889 647 __I uint32_t RXDDATA; /*!< RXD register. */
Kojto 97:433970e64889 648 __IO uint32_t TXDDATA; /*!< TXD register. */
Kojto 97:433970e64889 649 __I uint32_t RESERVED12;
Kojto 97:433970e64889 650 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Kojto 97:433970e64889 651 __I uint32_t RESERVED13[3];
Kojto 97:433970e64889 652 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Kojto 97:433970e64889 653 __I uint32_t RESERVED14;
Kojto 97:433970e64889 654 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Kojto 97:433970e64889 655 __I uint32_t RESERVED15;
Kojto 97:433970e64889 656 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 97:433970e64889 657 __I uint32_t RESERVED16[26];
Kojto 97:433970e64889 658 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 97:433970e64889 659 __I uint32_t RESERVED17[654];
Kojto 97:433970e64889 660 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 97:433970e64889 661 } NRF_SPIM_Type;
Kojto 97:433970e64889 662
Kojto 97:433970e64889 663
Kojto 97:433970e64889 664 /* ================================================================================ */
bogdanm 87:6213f644d804 665 /* ================ GPIOTE ================ */
bogdanm 87:6213f644d804 666 /* ================================================================================ */
bogdanm 87:6213f644d804 667
bogdanm 87:6213f644d804 668
bogdanm 87:6213f644d804 669 /**
bogdanm 87:6213f644d804 670 * @brief GPIO tasks and events. (GPIOTE)
bogdanm 87:6213f644d804 671 */
bogdanm 87:6213f644d804 672
bogdanm 87:6213f644d804 673 typedef struct { /*!< GPIOTE Structure */
bogdanm 87:6213f644d804 674 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 87:6213f644d804 675 __I uint32_t RESERVED0[60];
bogdanm 87:6213f644d804 676 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
bogdanm 87:6213f644d804 677 __I uint32_t RESERVED1[27];
bogdanm 87:6213f644d804 678 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
bogdanm 87:6213f644d804 679 __I uint32_t RESERVED2[97];
bogdanm 87:6213f644d804 680 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 681 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 682 __I uint32_t RESERVED3[129];
bogdanm 87:6213f644d804 683 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
bogdanm 87:6213f644d804 684 __I uint32_t RESERVED4[695];
bogdanm 87:6213f644d804 685 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 686 } NRF_GPIOTE_Type;
bogdanm 87:6213f644d804 687
bogdanm 87:6213f644d804 688
bogdanm 87:6213f644d804 689 /* ================================================================================ */
bogdanm 87:6213f644d804 690 /* ================ ADC ================ */
bogdanm 87:6213f644d804 691 /* ================================================================================ */
bogdanm 87:6213f644d804 692
bogdanm 87:6213f644d804 693
bogdanm 87:6213f644d804 694 /**
bogdanm 87:6213f644d804 695 * @brief Analog to digital converter. (ADC)
bogdanm 87:6213f644d804 696 */
bogdanm 87:6213f644d804 697
bogdanm 87:6213f644d804 698 typedef struct { /*!< ADC Structure */
bogdanm 87:6213f644d804 699 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
bogdanm 87:6213f644d804 700 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
bogdanm 87:6213f644d804 701 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 702 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
bogdanm 87:6213f644d804 703 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 704 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 705 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 706 __I uint32_t RESERVED2[61];
bogdanm 87:6213f644d804 707 __I uint32_t BUSY; /*!< ADC busy register. */
bogdanm 87:6213f644d804 708 __I uint32_t RESERVED3[63];
bogdanm 87:6213f644d804 709 __IO uint32_t ENABLE; /*!< ADC enable. */
bogdanm 87:6213f644d804 710 __IO uint32_t CONFIG; /*!< ADC configuration register. */
bogdanm 87:6213f644d804 711 __I uint32_t RESULT; /*!< Result of ADC conversion. */
bogdanm 87:6213f644d804 712 __I uint32_t RESERVED4[700];
bogdanm 87:6213f644d804 713 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 714 } NRF_ADC_Type;
bogdanm 87:6213f644d804 715
bogdanm 87:6213f644d804 716
bogdanm 87:6213f644d804 717 /* ================================================================================ */
bogdanm 87:6213f644d804 718 /* ================ TIMER ================ */
bogdanm 87:6213f644d804 719 /* ================================================================================ */
bogdanm 87:6213f644d804 720
bogdanm 87:6213f644d804 721
bogdanm 87:6213f644d804 722 /**
bogdanm 87:6213f644d804 723 * @brief Timer 0. (TIMER)
bogdanm 87:6213f644d804 724 */
bogdanm 87:6213f644d804 725
bogdanm 87:6213f644d804 726 typedef struct { /*!< TIMER Structure */
bogdanm 87:6213f644d804 727 __O uint32_t TASKS_START; /*!< Start Timer. */
bogdanm 87:6213f644d804 728 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
bogdanm 87:6213f644d804 729 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
bogdanm 87:6213f644d804 730 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 97:433970e64889 731 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Kojto 97:433970e64889 732 __I uint32_t RESERVED0[11];
bogdanm 87:6213f644d804 733 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
bogdanm 87:6213f644d804 734 __I uint32_t RESERVED1[60];
bogdanm 87:6213f644d804 735 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 87:6213f644d804 736 __I uint32_t RESERVED2[44];
bogdanm 87:6213f644d804 737 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
bogdanm 87:6213f644d804 738 __I uint32_t RESERVED3[64];
bogdanm 87:6213f644d804 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 741 __I uint32_t RESERVED4[126];
bogdanm 87:6213f644d804 742 __IO uint32_t MODE; /*!< Timer Mode selection. */
bogdanm 87:6213f644d804 743 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
bogdanm 87:6213f644d804 744 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 745 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
bogdanm 87:6213f644d804 746 clock frequency is divided by 2^SCALE. */
bogdanm 87:6213f644d804 747 __I uint32_t RESERVED6[11];
bogdanm 87:6213f644d804 748 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 87:6213f644d804 749 __I uint32_t RESERVED7[683];
bogdanm 87:6213f644d804 750 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 751 } NRF_TIMER_Type;
bogdanm 87:6213f644d804 752
bogdanm 87:6213f644d804 753
bogdanm 87:6213f644d804 754 /* ================================================================================ */
bogdanm 87:6213f644d804 755 /* ================ RTC ================ */
bogdanm 87:6213f644d804 756 /* ================================================================================ */
bogdanm 87:6213f644d804 757
bogdanm 87:6213f644d804 758
bogdanm 87:6213f644d804 759 /**
bogdanm 87:6213f644d804 760 * @brief Real time counter 0. (RTC)
bogdanm 87:6213f644d804 761 */
bogdanm 87:6213f644d804 762
bogdanm 87:6213f644d804 763 typedef struct { /*!< RTC Structure */
bogdanm 87:6213f644d804 764 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
bogdanm 87:6213f644d804 765 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
bogdanm 87:6213f644d804 766 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
bogdanm 87:6213f644d804 767 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
bogdanm 87:6213f644d804 768 __I uint32_t RESERVED0[60];
bogdanm 87:6213f644d804 769 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
bogdanm 87:6213f644d804 770 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
bogdanm 87:6213f644d804 771 __I uint32_t RESERVED1[14];
bogdanm 87:6213f644d804 772 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
bogdanm 87:6213f644d804 773 __I uint32_t RESERVED2[109];
bogdanm 87:6213f644d804 774 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 775 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 776 __I uint32_t RESERVED3[13];
bogdanm 87:6213f644d804 777 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
bogdanm 87:6213f644d804 778 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
bogdanm 87:6213f644d804 779 the value of EVTEN. */
bogdanm 87:6213f644d804 780 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
bogdanm 87:6213f644d804 781 gives the value of EVTEN. */
bogdanm 87:6213f644d804 782 __I uint32_t RESERVED4[110];
Kojto 97:433970e64889 783 __I uint32_t COUNTER; /*!< Current COUNTER value. */
bogdanm 87:6213f644d804 784 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
bogdanm 87:6213f644d804 785 Must be written when RTC is STOPed. */
bogdanm 87:6213f644d804 786 __I uint32_t RESERVED5[13];
bogdanm 87:6213f644d804 787 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
bogdanm 87:6213f644d804 788 __I uint32_t RESERVED6[683];
bogdanm 87:6213f644d804 789 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 790 } NRF_RTC_Type;
bogdanm 87:6213f644d804 791
bogdanm 87:6213f644d804 792
bogdanm 87:6213f644d804 793 /* ================================================================================ */
bogdanm 87:6213f644d804 794 /* ================ TEMP ================ */
bogdanm 87:6213f644d804 795 /* ================================================================================ */
bogdanm 87:6213f644d804 796
bogdanm 87:6213f644d804 797
bogdanm 87:6213f644d804 798 /**
bogdanm 87:6213f644d804 799 * @brief Temperature Sensor. (TEMP)
bogdanm 87:6213f644d804 800 */
bogdanm 87:6213f644d804 801
bogdanm 87:6213f644d804 802 typedef struct { /*!< TEMP Structure */
bogdanm 87:6213f644d804 803 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
bogdanm 87:6213f644d804 804 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
bogdanm 87:6213f644d804 805 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 806 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
bogdanm 87:6213f644d804 807 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 810 __I uint32_t RESERVED2[127];
bogdanm 87:6213f644d804 811 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
bogdanm 87:6213f644d804 812 __I uint32_t RESERVED3[700];
bogdanm 87:6213f644d804 813 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 814 } NRF_TEMP_Type;
bogdanm 87:6213f644d804 815
bogdanm 87:6213f644d804 816
bogdanm 87:6213f644d804 817 /* ================================================================================ */
bogdanm 87:6213f644d804 818 /* ================ RNG ================ */
bogdanm 87:6213f644d804 819 /* ================================================================================ */
bogdanm 87:6213f644d804 820
bogdanm 87:6213f644d804 821
bogdanm 87:6213f644d804 822 /**
bogdanm 87:6213f644d804 823 * @brief Random Number Generator. (RNG)
bogdanm 87:6213f644d804 824 */
bogdanm 87:6213f644d804 825
bogdanm 87:6213f644d804 826 typedef struct { /*!< RNG Structure */
bogdanm 87:6213f644d804 827 __O uint32_t TASKS_START; /*!< Start the random number generator. */
bogdanm 87:6213f644d804 828 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
bogdanm 87:6213f644d804 829 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 830 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
bogdanm 87:6213f644d804 831 __I uint32_t RESERVED1[63];
Kojto 97:433970e64889 832 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
bogdanm 87:6213f644d804 833 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 834 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
bogdanm 87:6213f644d804 835 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
bogdanm 87:6213f644d804 836 __I uint32_t RESERVED3[126];
bogdanm 87:6213f644d804 837 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 838 __I uint32_t VALUE; /*!< RNG random number. */
bogdanm 87:6213f644d804 839 __I uint32_t RESERVED4[700];
bogdanm 87:6213f644d804 840 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 841 } NRF_RNG_Type;
bogdanm 87:6213f644d804 842
bogdanm 87:6213f644d804 843
bogdanm 87:6213f644d804 844 /* ================================================================================ */
bogdanm 87:6213f644d804 845 /* ================ ECB ================ */
bogdanm 87:6213f644d804 846 /* ================================================================================ */
bogdanm 87:6213f644d804 847
bogdanm 87:6213f644d804 848
bogdanm 87:6213f644d804 849 /**
bogdanm 87:6213f644d804 850 * @brief AES ECB Mode Encryption. (ECB)
bogdanm 87:6213f644d804 851 */
bogdanm 87:6213f644d804 852
bogdanm 87:6213f644d804 853 typedef struct { /*!< ECB Structure */
bogdanm 87:6213f644d804 854 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
bogdanm 87:6213f644d804 855 will not initiate a new encryption and the ERRORECB event will
bogdanm 87:6213f644d804 856 be triggered. */
bogdanm 87:6213f644d804 857 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
bogdanm 87:6213f644d804 858 this will will trigger the ERRORECB event. */
bogdanm 87:6213f644d804 859 __I uint32_t RESERVED0[62];
bogdanm 87:6213f644d804 860 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
bogdanm 87:6213f644d804 861 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
bogdanm 87:6213f644d804 862 error. */
bogdanm 87:6213f644d804 863 __I uint32_t RESERVED1[127];
bogdanm 87:6213f644d804 864 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 865 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 866 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 867 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
bogdanm 87:6213f644d804 868 __I uint32_t RESERVED3[701];
bogdanm 87:6213f644d804 869 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 870 } NRF_ECB_Type;
bogdanm 87:6213f644d804 871
bogdanm 87:6213f644d804 872
bogdanm 87:6213f644d804 873 /* ================================================================================ */
bogdanm 87:6213f644d804 874 /* ================ AAR ================ */
bogdanm 87:6213f644d804 875 /* ================================================================================ */
bogdanm 87:6213f644d804 876
bogdanm 87:6213f644d804 877
bogdanm 87:6213f644d804 878 /**
bogdanm 87:6213f644d804 879 * @brief Accelerated Address Resolver. (AAR)
bogdanm 87:6213f644d804 880 */
bogdanm 87:6213f644d804 881
bogdanm 87:6213f644d804 882 typedef struct { /*!< AAR Structure */
bogdanm 87:6213f644d804 883 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
bogdanm 87:6213f644d804 884 data structure. */
bogdanm 87:6213f644d804 885 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 886 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
bogdanm 87:6213f644d804 887 __I uint32_t RESERVED1[61];
bogdanm 87:6213f644d804 888 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
bogdanm 87:6213f644d804 889 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
bogdanm 87:6213f644d804 890 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
bogdanm 87:6213f644d804 891 __I uint32_t RESERVED2[126];
bogdanm 87:6213f644d804 892 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 893 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 894 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 895 __I uint32_t STATUS; /*!< Resolution status. */
bogdanm 87:6213f644d804 896 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 897 __IO uint32_t ENABLE; /*!< Enable AAR. */
bogdanm 87:6213f644d804 898 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
bogdanm 87:6213f644d804 899 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
bogdanm 87:6213f644d804 900 __I uint32_t RESERVED5;
bogdanm 87:6213f644d804 901 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 97:433970e64889 902 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 903 during resolution. A minimum of 3 bytes must be reserved. */
bogdanm 87:6213f644d804 904 __I uint32_t RESERVED6[697];
bogdanm 87:6213f644d804 905 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 906 } NRF_AAR_Type;
bogdanm 87:6213f644d804 907
bogdanm 87:6213f644d804 908
bogdanm 87:6213f644d804 909 /* ================================================================================ */
bogdanm 87:6213f644d804 910 /* ================ CCM ================ */
bogdanm 87:6213f644d804 911 /* ================================================================================ */
bogdanm 87:6213f644d804 912
bogdanm 87:6213f644d804 913
bogdanm 87:6213f644d804 914 /**
bogdanm 87:6213f644d804 915 * @brief AES CCM Mode Encryption. (CCM)
bogdanm 87:6213f644d804 916 */
bogdanm 87:6213f644d804 917
bogdanm 87:6213f644d804 918 typedef struct { /*!< CCM Structure */
bogdanm 87:6213f644d804 919 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
bogdanm 87:6213f644d804 920 itself when completed. */
bogdanm 87:6213f644d804 921 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
bogdanm 87:6213f644d804 922 completed. */
bogdanm 87:6213f644d804 923 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
bogdanm 87:6213f644d804 924 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 925 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
bogdanm 87:6213f644d804 926 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
bogdanm 87:6213f644d804 927 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
bogdanm 87:6213f644d804 928 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 929 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
bogdanm 87:6213f644d804 930 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 931 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 932 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 933 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 934 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
bogdanm 87:6213f644d804 935 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 936 __IO uint32_t ENABLE; /*!< CCM enable. */
bogdanm 87:6213f644d804 937 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 97:433970e64889 938 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Kojto 97:433970e64889 939 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Kojto 97:433970e64889 940 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Kojto 97:433970e64889 941 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 942 during resolution. A minimum of 43 bytes must be reserved. */
bogdanm 87:6213f644d804 943 __I uint32_t RESERVED5[697];
bogdanm 87:6213f644d804 944 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 945 } NRF_CCM_Type;
bogdanm 87:6213f644d804 946
bogdanm 87:6213f644d804 947
bogdanm 87:6213f644d804 948 /* ================================================================================ */
bogdanm 87:6213f644d804 949 /* ================ WDT ================ */
bogdanm 87:6213f644d804 950 /* ================================================================================ */
bogdanm 87:6213f644d804 951
bogdanm 87:6213f644d804 952
bogdanm 87:6213f644d804 953 /**
bogdanm 87:6213f644d804 954 * @brief Watchdog Timer. (WDT)
bogdanm 87:6213f644d804 955 */
bogdanm 87:6213f644d804 956
bogdanm 87:6213f644d804 957 typedef struct { /*!< WDT Structure */
bogdanm 87:6213f644d804 958 __O uint32_t TASKS_START; /*!< Start the watchdog. */
bogdanm 87:6213f644d804 959 __I uint32_t RESERVED0[63];
bogdanm 87:6213f644d804 960 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
bogdanm 87:6213f644d804 961 __I uint32_t RESERVED1[128];
bogdanm 87:6213f644d804 962 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 963 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 964 __I uint32_t RESERVED2[61];
bogdanm 87:6213f644d804 965 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
bogdanm 87:6213f644d804 966 __I uint32_t REQSTATUS; /*!< Request status. */
bogdanm 87:6213f644d804 967 __I uint32_t RESERVED3[63];
bogdanm 87:6213f644d804 968 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
bogdanm 87:6213f644d804 969 __IO uint32_t RREN; /*!< Reload request enable. */
bogdanm 87:6213f644d804 970 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 971 __I uint32_t RESERVED4[60];
bogdanm 87:6213f644d804 972 __O uint32_t RR[8]; /*!< Reload requests registers. */
bogdanm 87:6213f644d804 973 __I uint32_t RESERVED5[631];
bogdanm 87:6213f644d804 974 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 975 } NRF_WDT_Type;
bogdanm 87:6213f644d804 976
bogdanm 87:6213f644d804 977
bogdanm 87:6213f644d804 978 /* ================================================================================ */
bogdanm 87:6213f644d804 979 /* ================ QDEC ================ */
bogdanm 87:6213f644d804 980 /* ================================================================================ */
bogdanm 87:6213f644d804 981
bogdanm 87:6213f644d804 982
bogdanm 87:6213f644d804 983 /**
bogdanm 87:6213f644d804 984 * @brief Rotary decoder. (QDEC)
bogdanm 87:6213f644d804 985 */
bogdanm 87:6213f644d804 986
bogdanm 87:6213f644d804 987 typedef struct { /*!< QDEC Structure */
bogdanm 87:6213f644d804 988 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
bogdanm 87:6213f644d804 989 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
bogdanm 87:6213f644d804 990 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
bogdanm 87:6213f644d804 991 and clears the ACC registers. */
bogdanm 87:6213f644d804 992 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 993 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
bogdanm 87:6213f644d804 994 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
bogdanm 87:6213f644d804 995 ACC register different than zero. */
bogdanm 87:6213f644d804 996 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
bogdanm 87:6213f644d804 997 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 998 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
bogdanm 87:6213f644d804 999 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 1000 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 1001 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 1002 __I uint32_t RESERVED3[125];
bogdanm 87:6213f644d804 1003 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
bogdanm 87:6213f644d804 1004 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
bogdanm 87:6213f644d804 1005 __IO uint32_t SAMPLEPER; /*!< Sample period. */
bogdanm 87:6213f644d804 1006 __I int32_t SAMPLE; /*!< Motion sample value. */
bogdanm 87:6213f644d804 1007 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
bogdanm 87:6213f644d804 1008 __I int32_t ACC; /*!< Accumulated valid transitions register. */
bogdanm 87:6213f644d804 1009 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
bogdanm 87:6213f644d804 1010 task. */
bogdanm 87:6213f644d804 1011 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
bogdanm 87:6213f644d804 1012 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
bogdanm 87:6213f644d804 1013 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
bogdanm 87:6213f644d804 1014 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
bogdanm 87:6213f644d804 1015 __I uint32_t RESERVED4[5];
bogdanm 87:6213f644d804 1016 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
bogdanm 87:6213f644d804 1017 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
bogdanm 87:6213f644d804 1018 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
bogdanm 87:6213f644d804 1019 task. */
bogdanm 87:6213f644d804 1020 __I uint32_t RESERVED5[684];
bogdanm 87:6213f644d804 1021 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 1022 } NRF_QDEC_Type;
bogdanm 87:6213f644d804 1023
bogdanm 87:6213f644d804 1024
bogdanm 87:6213f644d804 1025 /* ================================================================================ */
bogdanm 87:6213f644d804 1026 /* ================ LPCOMP ================ */
bogdanm 87:6213f644d804 1027 /* ================================================================================ */
bogdanm 87:6213f644d804 1028
bogdanm 87:6213f644d804 1029
bogdanm 87:6213f644d804 1030 /**
Kojto 97:433970e64889 1031 * @brief Low power comparator. (LPCOMP)
bogdanm 87:6213f644d804 1032 */
bogdanm 87:6213f644d804 1033
bogdanm 87:6213f644d804 1034 typedef struct { /*!< LPCOMP Structure */
bogdanm 87:6213f644d804 1035 __O uint32_t TASKS_START; /*!< Start the comparator. */
bogdanm 87:6213f644d804 1036 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
bogdanm 87:6213f644d804 1037 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
bogdanm 87:6213f644d804 1038 __I uint32_t RESERVED0[61];
bogdanm 87:6213f644d804 1039 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
bogdanm 87:6213f644d804 1040 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
bogdanm 87:6213f644d804 1041 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
bogdanm 87:6213f644d804 1042 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
bogdanm 87:6213f644d804 1043 __I uint32_t RESERVED1[60];
Kojto 97:433970e64889 1044 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
bogdanm 87:6213f644d804 1045 __I uint32_t RESERVED2[64];
bogdanm 87:6213f644d804 1046 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
bogdanm 87:6213f644d804 1047 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
bogdanm 87:6213f644d804 1048 __I uint32_t RESERVED3[61];
bogdanm 87:6213f644d804 1049 __I uint32_t RESULT; /*!< Result of last compare. */
bogdanm 87:6213f644d804 1050 __I uint32_t RESERVED4[63];
bogdanm 87:6213f644d804 1051 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
bogdanm 87:6213f644d804 1052 __IO uint32_t PSEL; /*!< Input pin select. */
bogdanm 87:6213f644d804 1053 __IO uint32_t REFSEL; /*!< Reference select. */
bogdanm 87:6213f644d804 1054 __IO uint32_t EXTREFSEL; /*!< External reference select. */
bogdanm 87:6213f644d804 1055 __I uint32_t RESERVED5[4];
bogdanm 87:6213f644d804 1056 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
bogdanm 87:6213f644d804 1057 __I uint32_t RESERVED6[694];
bogdanm 87:6213f644d804 1058 __IO uint32_t POWER; /*!< Peripheral power control. */
bogdanm 87:6213f644d804 1059 } NRF_LPCOMP_Type;
bogdanm 87:6213f644d804 1060
bogdanm 87:6213f644d804 1061
bogdanm 87:6213f644d804 1062 /* ================================================================================ */
bogdanm 87:6213f644d804 1063 /* ================ SWI ================ */
bogdanm 87:6213f644d804 1064 /* ================================================================================ */
bogdanm 87:6213f644d804 1065
bogdanm 87:6213f644d804 1066
bogdanm 87:6213f644d804 1067 /**
bogdanm 87:6213f644d804 1068 * @brief SW Interrupts. (SWI)
bogdanm 87:6213f644d804 1069 */
bogdanm 87:6213f644d804 1070
bogdanm 87:6213f644d804 1071 typedef struct { /*!< SWI Structure */
bogdanm 87:6213f644d804 1072 __I uint32_t UNUSED; /*!< Unused. */
bogdanm 87:6213f644d804 1073 } NRF_SWI_Type;
bogdanm 87:6213f644d804 1074
bogdanm 87:6213f644d804 1075
bogdanm 87:6213f644d804 1076 /* ================================================================================ */
bogdanm 87:6213f644d804 1077 /* ================ NVMC ================ */
bogdanm 87:6213f644d804 1078 /* ================================================================================ */
bogdanm 87:6213f644d804 1079
bogdanm 87:6213f644d804 1080
bogdanm 87:6213f644d804 1081 /**
bogdanm 87:6213f644d804 1082 * @brief Non Volatile Memory Controller. (NVMC)
bogdanm 87:6213f644d804 1083 */
bogdanm 87:6213f644d804 1084
bogdanm 87:6213f644d804 1085 typedef struct { /*!< NVMC Structure */
bogdanm 87:6213f644d804 1086 __I uint32_t RESERVED0[256];
bogdanm 87:6213f644d804 1087 __I uint32_t READY; /*!< Ready flag. */
bogdanm 87:6213f644d804 1088 __I uint32_t RESERVED1[64];
bogdanm 87:6213f644d804 1089 __IO uint32_t CONFIG; /*!< Configuration register. */
bogdanm 87:6213f644d804 1090 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
bogdanm 87:6213f644d804 1091 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
bogdanm 87:6213f644d804 1092 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
bogdanm 87:6213f644d804 1093 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
bogdanm 87:6213f644d804 1094 } NRF_NVMC_Type;
bogdanm 87:6213f644d804 1095
bogdanm 87:6213f644d804 1096
bogdanm 87:6213f644d804 1097 /* ================================================================================ */
bogdanm 87:6213f644d804 1098 /* ================ PPI ================ */
bogdanm 87:6213f644d804 1099 /* ================================================================================ */
bogdanm 87:6213f644d804 1100
bogdanm 87:6213f644d804 1101
bogdanm 87:6213f644d804 1102 /**
bogdanm 87:6213f644d804 1103 * @brief PPI controller. (PPI)
bogdanm 87:6213f644d804 1104 */
bogdanm 87:6213f644d804 1105
bogdanm 87:6213f644d804 1106 typedef struct { /*!< PPI Structure */
bogdanm 87:6213f644d804 1107 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
bogdanm 87:6213f644d804 1108 __I uint32_t RESERVED0[312];
bogdanm 87:6213f644d804 1109 __IO uint32_t CHEN; /*!< Channel enable. */
bogdanm 87:6213f644d804 1110 __IO uint32_t CHENSET; /*!< Channel enable set. */
bogdanm 87:6213f644d804 1111 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
bogdanm 87:6213f644d804 1112 __I uint32_t RESERVED1;
bogdanm 87:6213f644d804 1113 PPI_CH_Type CH[16]; /*!< PPI Channel. */
bogdanm 87:6213f644d804 1114 __I uint32_t RESERVED2[156];
bogdanm 87:6213f644d804 1115 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
bogdanm 87:6213f644d804 1116 } NRF_PPI_Type;
bogdanm 87:6213f644d804 1117
bogdanm 87:6213f644d804 1118
bogdanm 87:6213f644d804 1119 /* ================================================================================ */
bogdanm 87:6213f644d804 1120 /* ================ FICR ================ */
bogdanm 87:6213f644d804 1121 /* ================================================================================ */
bogdanm 87:6213f644d804 1122
bogdanm 87:6213f644d804 1123
bogdanm 87:6213f644d804 1124 /**
bogdanm 87:6213f644d804 1125 * @brief Factory Information Configuration. (FICR)
bogdanm 87:6213f644d804 1126 */
bogdanm 87:6213f644d804 1127
bogdanm 87:6213f644d804 1128 typedef struct { /*!< FICR Structure */
bogdanm 87:6213f644d804 1129 __I uint32_t RESERVED0[4];
bogdanm 87:6213f644d804 1130 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
bogdanm 87:6213f644d804 1131 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
bogdanm 87:6213f644d804 1132 __I uint32_t RESERVED1[4];
bogdanm 87:6213f644d804 1133 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
bogdanm 87:6213f644d804 1134 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
bogdanm 87:6213f644d804 1135 __I uint32_t RESERVED2;
bogdanm 87:6213f644d804 1136 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 97:433970e64889 1137
Kojto 97:433970e64889 1138 union {
Kojto 97:433970e64889 1139 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto 97:433970e64889 1140 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto 97:433970e64889 1141 instead. */
Kojto 97:433970e64889 1142 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Kojto 97:433970e64889 1143 };
bogdanm 87:6213f644d804 1144 __I uint32_t RESERVED3[5];
bogdanm 87:6213f644d804 1145 __I uint32_t CONFIGID; /*!< Configuration identifier. */
bogdanm 87:6213f644d804 1146 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
bogdanm 87:6213f644d804 1147 __I uint32_t RESERVED4[6];
bogdanm 87:6213f644d804 1148 __I uint32_t ER[4]; /*!< Encryption root. */
bogdanm 87:6213f644d804 1149 __I uint32_t IR[4]; /*!< Identity root. */
bogdanm 87:6213f644d804 1150 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
bogdanm 87:6213f644d804 1151 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
bogdanm 87:6213f644d804 1152 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 97:433970e64889 1153 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto 97:433970e64889 1154 mode. */
Kojto 97:433970e64889 1155 __I uint32_t RESERVED5[10];
bogdanm 87:6213f644d804 1156 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
bogdanm 87:6213f644d804 1157 mode. */
Kojto 97:433970e64889 1158 FICR_INFO_Type INFO; /*!< Device info */
bogdanm 87:6213f644d804 1159 } NRF_FICR_Type;
bogdanm 87:6213f644d804 1160
bogdanm 87:6213f644d804 1161
bogdanm 87:6213f644d804 1162 /* ================================================================================ */
bogdanm 87:6213f644d804 1163 /* ================ UICR ================ */
bogdanm 87:6213f644d804 1164 /* ================================================================================ */
bogdanm 87:6213f644d804 1165
bogdanm 87:6213f644d804 1166
bogdanm 87:6213f644d804 1167 /**
bogdanm 87:6213f644d804 1168 * @brief User Information Configuration. (UICR)
bogdanm 87:6213f644d804 1169 */
bogdanm 87:6213f644d804 1170
bogdanm 87:6213f644d804 1171 typedef struct { /*!< UICR Structure */
bogdanm 87:6213f644d804 1172 __IO uint32_t CLENR0; /*!< Length of code region 0. */
bogdanm 87:6213f644d804 1173 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
bogdanm 87:6213f644d804 1174 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
bogdanm 87:6213f644d804 1175 __I uint32_t RESERVED0;
bogdanm 87:6213f644d804 1176 __I uint32_t FWID; /*!< Firmware ID. */
bogdanm 87:6213f644d804 1177 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
bogdanm 87:6213f644d804 1178 } NRF_UICR_Type;
bogdanm 87:6213f644d804 1179
bogdanm 87:6213f644d804 1180
bogdanm 87:6213f644d804 1181 /* ================================================================================ */
bogdanm 87:6213f644d804 1182 /* ================ GPIO ================ */
bogdanm 87:6213f644d804 1183 /* ================================================================================ */
bogdanm 87:6213f644d804 1184
bogdanm 87:6213f644d804 1185
bogdanm 87:6213f644d804 1186 /**
bogdanm 87:6213f644d804 1187 * @brief General purpose input and output. (GPIO)
bogdanm 87:6213f644d804 1188 */
bogdanm 87:6213f644d804 1189
bogdanm 87:6213f644d804 1190 typedef struct { /*!< GPIO Structure */
bogdanm 87:6213f644d804 1191 __I uint32_t RESERVED0[321];
bogdanm 87:6213f644d804 1192 __IO uint32_t OUT; /*!< Write GPIO port. */
bogdanm 87:6213f644d804 1193 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
bogdanm 87:6213f644d804 1194 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
bogdanm 87:6213f644d804 1195 __I uint32_t IN; /*!< Read GPIO port. */
bogdanm 87:6213f644d804 1196 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
bogdanm 87:6213f644d804 1197 __IO uint32_t DIRSET; /*!< DIR set register. */
bogdanm 87:6213f644d804 1198 __IO uint32_t DIRCLR; /*!< DIR clear register. */
bogdanm 87:6213f644d804 1199 __I uint32_t RESERVED1[120];
bogdanm 87:6213f644d804 1200 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
bogdanm 87:6213f644d804 1201 } NRF_GPIO_Type;
bogdanm 87:6213f644d804 1202
bogdanm 87:6213f644d804 1203
bogdanm 87:6213f644d804 1204 /* -------------------- End of section using anonymous unions ------------------- */
bogdanm 87:6213f644d804 1205 #if defined(__CC_ARM)
bogdanm 87:6213f644d804 1206 #pragma pop
bogdanm 87:6213f644d804 1207 #elif defined(__ICCARM__)
bogdanm 87:6213f644d804 1208 /* leave anonymous unions enabled */
bogdanm 87:6213f644d804 1209 #elif defined(__GNUC__)
bogdanm 87:6213f644d804 1210 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 1211 #elif defined(__TMS470__)
bogdanm 87:6213f644d804 1212 /* anonymous unions are enabled by default */
bogdanm 87:6213f644d804 1213 #elif defined(__TASKING__)
bogdanm 87:6213f644d804 1214 #pragma warning restore
bogdanm 87:6213f644d804 1215 #else
bogdanm 87:6213f644d804 1216 #warning Not supported compiler type
bogdanm 87:6213f644d804 1217 #endif
bogdanm 87:6213f644d804 1218
bogdanm 87:6213f644d804 1219
bogdanm 87:6213f644d804 1220
bogdanm 87:6213f644d804 1221
bogdanm 87:6213f644d804 1222 /* ================================================================================ */
bogdanm 87:6213f644d804 1223 /* ================ Peripheral memory map ================ */
bogdanm 87:6213f644d804 1224 /* ================================================================================ */
bogdanm 87:6213f644d804 1225
bogdanm 87:6213f644d804 1226 #define NRF_POWER_BASE 0x40000000UL
bogdanm 87:6213f644d804 1227 #define NRF_CLOCK_BASE 0x40000000UL
bogdanm 87:6213f644d804 1228 #define NRF_MPU_BASE 0x40000000UL
bogdanm 87:6213f644d804 1229 #define NRF_PU_BASE 0x40000000UL
bogdanm 87:6213f644d804 1230 #define NRF_AMLI_BASE 0x40000000UL
bogdanm 87:6213f644d804 1231 #define NRF_RADIO_BASE 0x40001000UL
bogdanm 87:6213f644d804 1232 #define NRF_UART0_BASE 0x40002000UL
bogdanm 87:6213f644d804 1233 #define NRF_SPI0_BASE 0x40003000UL
bogdanm 87:6213f644d804 1234 #define NRF_TWI0_BASE 0x40003000UL
bogdanm 87:6213f644d804 1235 #define NRF_SPI1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1236 #define NRF_TWI1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1237 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 97:433970e64889 1238 #define NRF_SPIM1_BASE 0x40004000UL
bogdanm 87:6213f644d804 1239 #define NRF_GPIOTE_BASE 0x40006000UL
bogdanm 87:6213f644d804 1240 #define NRF_ADC_BASE 0x40007000UL
bogdanm 87:6213f644d804 1241 #define NRF_TIMER0_BASE 0x40008000UL
bogdanm 87:6213f644d804 1242 #define NRF_TIMER1_BASE 0x40009000UL
bogdanm 87:6213f644d804 1243 #define NRF_TIMER2_BASE 0x4000A000UL
bogdanm 87:6213f644d804 1244 #define NRF_RTC0_BASE 0x4000B000UL
bogdanm 87:6213f644d804 1245 #define NRF_TEMP_BASE 0x4000C000UL
bogdanm 87:6213f644d804 1246 #define NRF_RNG_BASE 0x4000D000UL
bogdanm 87:6213f644d804 1247 #define NRF_ECB_BASE 0x4000E000UL
bogdanm 87:6213f644d804 1248 #define NRF_AAR_BASE 0x4000F000UL
bogdanm 87:6213f644d804 1249 #define NRF_CCM_BASE 0x4000F000UL
bogdanm 87:6213f644d804 1250 #define NRF_WDT_BASE 0x40010000UL
bogdanm 87:6213f644d804 1251 #define NRF_RTC1_BASE 0x40011000UL
bogdanm 87:6213f644d804 1252 #define NRF_QDEC_BASE 0x40012000UL
bogdanm 87:6213f644d804 1253 #define NRF_LPCOMP_BASE 0x40013000UL
bogdanm 87:6213f644d804 1254 #define NRF_SWI_BASE 0x40014000UL
bogdanm 87:6213f644d804 1255 #define NRF_NVMC_BASE 0x4001E000UL
bogdanm 87:6213f644d804 1256 #define NRF_PPI_BASE 0x4001F000UL
bogdanm 87:6213f644d804 1257 #define NRF_FICR_BASE 0x10000000UL
bogdanm 87:6213f644d804 1258 #define NRF_UICR_BASE 0x10001000UL
bogdanm 87:6213f644d804 1259 #define NRF_GPIO_BASE 0x50000000UL
bogdanm 87:6213f644d804 1260
bogdanm 87:6213f644d804 1261
bogdanm 87:6213f644d804 1262 /* ================================================================================ */
bogdanm 87:6213f644d804 1263 /* ================ Peripheral declaration ================ */
bogdanm 87:6213f644d804 1264 /* ================================================================================ */
bogdanm 87:6213f644d804 1265
bogdanm 87:6213f644d804 1266 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
bogdanm 87:6213f644d804 1267 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
bogdanm 87:6213f644d804 1268 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
bogdanm 87:6213f644d804 1269 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
bogdanm 87:6213f644d804 1270 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
bogdanm 87:6213f644d804 1271 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
bogdanm 87:6213f644d804 1272 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
bogdanm 87:6213f644d804 1273 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
bogdanm 87:6213f644d804 1274 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
bogdanm 87:6213f644d804 1275 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
bogdanm 87:6213f644d804 1276 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
bogdanm 87:6213f644d804 1277 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 97:433970e64889 1278 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
bogdanm 87:6213f644d804 1279 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
bogdanm 87:6213f644d804 1280 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
bogdanm 87:6213f644d804 1281 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
bogdanm 87:6213f644d804 1282 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
bogdanm 87:6213f644d804 1283 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
bogdanm 87:6213f644d804 1284 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
bogdanm 87:6213f644d804 1285 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
bogdanm 87:6213f644d804 1286 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
bogdanm 87:6213f644d804 1287 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
bogdanm 87:6213f644d804 1288 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
bogdanm 87:6213f644d804 1289 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
bogdanm 87:6213f644d804 1290 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
bogdanm 87:6213f644d804 1291 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
bogdanm 87:6213f644d804 1292 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
bogdanm 87:6213f644d804 1293 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
bogdanm 87:6213f644d804 1294 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
bogdanm 87:6213f644d804 1295 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
bogdanm 87:6213f644d804 1296 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
bogdanm 87:6213f644d804 1297 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
bogdanm 87:6213f644d804 1298 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
bogdanm 87:6213f644d804 1299 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
bogdanm 87:6213f644d804 1300
bogdanm 87:6213f644d804 1301
bogdanm 87:6213f644d804 1302 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 87:6213f644d804 1303 /** @} */ /* End of group nRF51 */
bogdanm 87:6213f644d804 1304 /** @} */ /* End of group Nordic Semiconductor */
bogdanm 87:6213f644d804 1305
bogdanm 87:6213f644d804 1306 #ifdef __cplusplus
bogdanm 87:6213f644d804 1307 }
bogdanm 87:6213f644d804 1308 #endif
bogdanm 87:6213f644d804 1309
bogdanm 87:6213f644d804 1310
bogdanm 87:6213f644d804 1311 #endif /* nRF51_H */
Kojto 97:433970e64889 1312