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LPC1768/LPC17xx.h@11:1c1ebd0324fa, 2009-08-28 (annotated)

Committer:
rolf.meyer@arm.com
Date:
Fri Aug 28 12:10:11 2009 +0000
Revision:
11:1c1ebd0324fa
Child:
14:20a79241b4a0
A shiny new version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rolf.meyer@arm.com 11:1c1ebd0324fa 1 /******************************************************************************
rolf.meyer@arm.com 11:1c1ebd0324fa 2 * @file: LPC17xx.h
rolf.meyer@arm.com 11:1c1ebd0324fa 3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
rolf.meyer@arm.com 11:1c1ebd0324fa 4 * NXP LPC17xx Device Series
rolf.meyer@arm.com 11:1c1ebd0324fa 5 * @version: V1.04
rolf.meyer@arm.com 11:1c1ebd0324fa 6 * @date: 2. July 2009
rolf.meyer@arm.com 11:1c1ebd0324fa 7 *----------------------------------------------------------------------------
rolf.meyer@arm.com 11:1c1ebd0324fa 8 *
rolf.meyer@arm.com 11:1c1ebd0324fa 9 * Copyright (C) 2008 ARM Limited. All rights reserved.
rolf.meyer@arm.com 11:1c1ebd0324fa 10 *
rolf.meyer@arm.com 11:1c1ebd0324fa 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
rolf.meyer@arm.com 11:1c1ebd0324fa 12 * processor based microcontrollers. This file can be freely distributed
rolf.meyer@arm.com 11:1c1ebd0324fa 13 * within development tools that are supporting such ARM based processors.
rolf.meyer@arm.com 11:1c1ebd0324fa 14 *
rolf.meyer@arm.com 11:1c1ebd0324fa 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
rolf.meyer@arm.com 11:1c1ebd0324fa 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
rolf.meyer@arm.com 11:1c1ebd0324fa 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
rolf.meyer@arm.com 11:1c1ebd0324fa 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
rolf.meyer@arm.com 11:1c1ebd0324fa 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
rolf.meyer@arm.com 11:1c1ebd0324fa 20 *
rolf.meyer@arm.com 11:1c1ebd0324fa 21 ******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 22
rolf.meyer@arm.com 11:1c1ebd0324fa 23
rolf.meyer@arm.com 11:1c1ebd0324fa 24 #ifndef __LPC17xx_H__
rolf.meyer@arm.com 11:1c1ebd0324fa 25 #define __LPC17xx_H__
rolf.meyer@arm.com 11:1c1ebd0324fa 26
rolf.meyer@arm.com 11:1c1ebd0324fa 27 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 28 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 29 * ---------- Interrupt Number Definition -----------------------------------
rolf.meyer@arm.com 11:1c1ebd0324fa 30 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 31 */
rolf.meyer@arm.com 11:1c1ebd0324fa 32
rolf.meyer@arm.com 11:1c1ebd0324fa 33 typedef enum IRQn
rolf.meyer@arm.com 11:1c1ebd0324fa 34 {
rolf.meyer@arm.com 11:1c1ebd0324fa 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 36 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 37 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 38 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 39 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 40 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 41 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 42 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 43 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 44
rolf.meyer@arm.com 11:1c1ebd0324fa 45 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 46 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 47 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 48 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 49 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 50 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 51 UART0_IRQn = 5, /*!< UART0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 52 UART1_IRQn = 6, /*!< UART1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 53 UART2_IRQn = 7, /*!< UART2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 54 UART3_IRQn = 8, /*!< UART3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 55 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 56 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 57 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 58 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 59 SPI_IRQn = 13, /*!< SPI Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 60 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 61 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 62 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 63 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 64 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 65 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 66 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 67 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 68 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 69 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 70 USB_IRQn = 24, /*!< USB Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 71 CAN_IRQn = 25, /*!< CAN Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 72 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 73 I2S_IRQn = 27, /*!< I2S Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 74 ENET_IRQn = 28, /*!< Ethernet Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 75 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 76 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 77 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 78 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 79 } IRQn_Type;
rolf.meyer@arm.com 11:1c1ebd0324fa 80
rolf.meyer@arm.com 11:1c1ebd0324fa 81
rolf.meyer@arm.com 11:1c1ebd0324fa 82 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 83 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 84 * ----------- Processor and Core Peripheral Section ------------------------
rolf.meyer@arm.com 11:1c1ebd0324fa 85 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 86 */
rolf.meyer@arm.com 11:1c1ebd0324fa 87
rolf.meyer@arm.com 11:1c1ebd0324fa 88 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 89 #define __MPU_PRESENT 1 /*!< MPU present or not */
rolf.meyer@arm.com 11:1c1ebd0324fa 90 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
rolf.meyer@arm.com 11:1c1ebd0324fa 91 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rolf.meyer@arm.com 11:1c1ebd0324fa 92
rolf.meyer@arm.com 11:1c1ebd0324fa 93
rolf.meyer@arm.com 11:1c1ebd0324fa 94 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 95 #include "system_LPC17xx.h" /* System Header */
rolf.meyer@arm.com 11:1c1ebd0324fa 96
rolf.meyer@arm.com 11:1c1ebd0324fa 97
rolf.meyer@arm.com 11:1c1ebd0324fa 98 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 99 /* Device Specific Peripheral registers structures */
rolf.meyer@arm.com 11:1c1ebd0324fa 100 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 101
rolf.meyer@arm.com 11:1c1ebd0324fa 102 #if defined ( __CC_ARM )
rolf.meyer@arm.com 11:1c1ebd0324fa 103 #pragma anon_unions
rolf.meyer@arm.com 11:1c1ebd0324fa 104 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 105
rolf.meyer@arm.com 11:1c1ebd0324fa 106 /*------------- System Control (SC) ------------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 107 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 108 {
rolf.meyer@arm.com 11:1c1ebd0324fa 109 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
rolf.meyer@arm.com 11:1c1ebd0324fa 110 uint32_t RESERVED0[31];
rolf.meyer@arm.com 11:1c1ebd0324fa 111 __IO uint32_t PLL0CON; /* Clocking and Power Control */
rolf.meyer@arm.com 11:1c1ebd0324fa 112 __IO uint32_t PLL0CFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 113 __I uint32_t PLL0STAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 114 __O uint32_t PLL0FEED;
rolf.meyer@arm.com 11:1c1ebd0324fa 115 uint32_t RESERVED1[4];
rolf.meyer@arm.com 11:1c1ebd0324fa 116 __IO uint32_t PLL1CON;
rolf.meyer@arm.com 11:1c1ebd0324fa 117 __IO uint32_t PLL1CFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 118 __I uint32_t PLL1STAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 119 __O uint32_t PLL1FEED;
rolf.meyer@arm.com 11:1c1ebd0324fa 120 uint32_t RESERVED2[4];
rolf.meyer@arm.com 11:1c1ebd0324fa 121 __IO uint32_t PCON;
rolf.meyer@arm.com 11:1c1ebd0324fa 122 __IO uint32_t PCONP;
rolf.meyer@arm.com 11:1c1ebd0324fa 123 uint32_t RESERVED3[15];
rolf.meyer@arm.com 11:1c1ebd0324fa 124 __IO uint32_t CCLKCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 125 __IO uint32_t USBCLKCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 126 __IO uint32_t CLKSRCSEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 127 uint32_t RESERVED4[12];
rolf.meyer@arm.com 11:1c1ebd0324fa 128 __IO uint32_t EXTINT; /* External Interrupts */
rolf.meyer@arm.com 11:1c1ebd0324fa 129 uint32_t RESERVED5;
rolf.meyer@arm.com 11:1c1ebd0324fa 130 __IO uint32_t EXTMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 131 __IO uint32_t EXTPOLAR;
rolf.meyer@arm.com 11:1c1ebd0324fa 132 uint32_t RESERVED6[12];
rolf.meyer@arm.com 11:1c1ebd0324fa 133 __IO uint32_t RSID; /* Reset */
rolf.meyer@arm.com 11:1c1ebd0324fa 134 uint32_t RESERVED7[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 135 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 136 __IO uint32_t IRCTRIM; /* Clock Dividers */
rolf.meyer@arm.com 11:1c1ebd0324fa 137 __IO uint32_t PCLKSEL0;
rolf.meyer@arm.com 11:1c1ebd0324fa 138 __IO uint32_t PCLKSEL1;
rolf.meyer@arm.com 11:1c1ebd0324fa 139 uint32_t RESERVED8[4];
rolf.meyer@arm.com 11:1c1ebd0324fa 140 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
rolf.meyer@arm.com 11:1c1ebd0324fa 141 uint32_t RESERVED9;
rolf.meyer@arm.com 11:1c1ebd0324fa 142 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
rolf.meyer@arm.com 11:1c1ebd0324fa 143 } LPC_SC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 144
rolf.meyer@arm.com 11:1c1ebd0324fa 145 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 146 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 147 {
rolf.meyer@arm.com 11:1c1ebd0324fa 148 __IO uint32_t PINSEL0;
rolf.meyer@arm.com 11:1c1ebd0324fa 149 __IO uint32_t PINSEL1;
rolf.meyer@arm.com 11:1c1ebd0324fa 150 __IO uint32_t PINSEL2;
rolf.meyer@arm.com 11:1c1ebd0324fa 151 __IO uint32_t PINSEL3;
rolf.meyer@arm.com 11:1c1ebd0324fa 152 __IO uint32_t PINSEL4;
rolf.meyer@arm.com 11:1c1ebd0324fa 153 __IO uint32_t PINSEL5;
rolf.meyer@arm.com 11:1c1ebd0324fa 154 __IO uint32_t PINSEL6;
rolf.meyer@arm.com 11:1c1ebd0324fa 155 __IO uint32_t PINSEL7;
rolf.meyer@arm.com 11:1c1ebd0324fa 156 __IO uint32_t PINSEL8;
rolf.meyer@arm.com 11:1c1ebd0324fa 157 __IO uint32_t PINSEL9;
rolf.meyer@arm.com 11:1c1ebd0324fa 158 __IO uint32_t PINSEL10;
rolf.meyer@arm.com 11:1c1ebd0324fa 159 uint32_t RESERVED0[5];
rolf.meyer@arm.com 11:1c1ebd0324fa 160 __IO uint32_t PINMODE0;
rolf.meyer@arm.com 11:1c1ebd0324fa 161 __IO uint32_t PINMODE1;
rolf.meyer@arm.com 11:1c1ebd0324fa 162 __IO uint32_t PINMODE2;
rolf.meyer@arm.com 11:1c1ebd0324fa 163 __IO uint32_t PINMODE3;
rolf.meyer@arm.com 11:1c1ebd0324fa 164 __IO uint32_t PINMODE4;
rolf.meyer@arm.com 11:1c1ebd0324fa 165 __IO uint32_t PINMODE5;
rolf.meyer@arm.com 11:1c1ebd0324fa 166 __IO uint32_t PINMODE6;
rolf.meyer@arm.com 11:1c1ebd0324fa 167 __IO uint32_t PINMODE7;
rolf.meyer@arm.com 11:1c1ebd0324fa 168 __IO uint32_t PINMODE8;
rolf.meyer@arm.com 11:1c1ebd0324fa 169 __IO uint32_t PINMODE9;
rolf.meyer@arm.com 11:1c1ebd0324fa 170 __IO uint32_t PINMODE_OD0;
rolf.meyer@arm.com 11:1c1ebd0324fa 171 __IO uint32_t PINMODE_OD1;
rolf.meyer@arm.com 11:1c1ebd0324fa 172 __IO uint32_t PINMODE_OD2;
rolf.meyer@arm.com 11:1c1ebd0324fa 173 __IO uint32_t PINMODE_OD3;
rolf.meyer@arm.com 11:1c1ebd0324fa 174 __IO uint32_t PINMODE_OD4;
rolf.meyer@arm.com 11:1c1ebd0324fa 175 __IO uint32_t I2CPADCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 176 } LPC_PINCON_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 177
rolf.meyer@arm.com 11:1c1ebd0324fa 178 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 179 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 180 {
rolf.meyer@arm.com 11:1c1ebd0324fa 181 __IO uint32_t FIODIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 182 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 183 __IO uint32_t FIOMASK;
rolf.meyer@arm.com 11:1c1ebd0324fa 184 __IO uint32_t FIOPIN;
rolf.meyer@arm.com 11:1c1ebd0324fa 185 __IO uint32_t FIOSET;
rolf.meyer@arm.com 11:1c1ebd0324fa 186 __O uint32_t FIOCLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 187 } LPC_GPIO_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 188
rolf.meyer@arm.com 11:1c1ebd0324fa 189 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 190 {
rolf.meyer@arm.com 11:1c1ebd0324fa 191 __I uint32_t IntStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 192 __I uint32_t IO0IntStatR;
rolf.meyer@arm.com 11:1c1ebd0324fa 193 __I uint32_t IO0IntStatF;
rolf.meyer@arm.com 11:1c1ebd0324fa 194 __O uint32_t IO0IntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 195 __IO uint32_t IO0IntEnR;
rolf.meyer@arm.com 11:1c1ebd0324fa 196 __IO uint32_t IO0IntEnF;
rolf.meyer@arm.com 11:1c1ebd0324fa 197 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 198 __I uint32_t IO2IntStatR;
rolf.meyer@arm.com 11:1c1ebd0324fa 199 __I uint32_t IO2IntStatF;
rolf.meyer@arm.com 11:1c1ebd0324fa 200 __O uint32_t IO2IntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 201 __IO uint32_t IO2IntEnR;
rolf.meyer@arm.com 11:1c1ebd0324fa 202 __IO uint32_t IO2IntEnF;
rolf.meyer@arm.com 11:1c1ebd0324fa 203 } LPC_GPIOINT_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 204
rolf.meyer@arm.com 11:1c1ebd0324fa 205 /*------------- Timer (TIM) --------------------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 206 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 207 {
rolf.meyer@arm.com 11:1c1ebd0324fa 208 __IO uint32_t IR;
rolf.meyer@arm.com 11:1c1ebd0324fa 209 __IO uint32_t TCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 210 __IO uint32_t TC;
rolf.meyer@arm.com 11:1c1ebd0324fa 211 __IO uint32_t PR;
rolf.meyer@arm.com 11:1c1ebd0324fa 212 __IO uint32_t PC;
rolf.meyer@arm.com 11:1c1ebd0324fa 213 __IO uint32_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 214 __IO uint32_t MR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 215 __IO uint32_t MR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 216 __IO uint32_t MR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 217 __IO uint32_t MR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 218 __IO uint32_t CCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 219 __I uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 220 __I uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 221 uint32_t RESERVED0[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 222 __IO uint32_t EMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 223 uint32_t RESERVED1[24];
rolf.meyer@arm.com 11:1c1ebd0324fa 224 __IO uint32_t CTCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 225 } LPC_TIM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 226
rolf.meyer@arm.com 11:1c1ebd0324fa 227 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 228 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 229 {
rolf.meyer@arm.com 11:1c1ebd0324fa 230 __IO uint32_t IR;
rolf.meyer@arm.com 11:1c1ebd0324fa 231 __IO uint32_t TCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 232 __IO uint32_t TC;
rolf.meyer@arm.com 11:1c1ebd0324fa 233 __IO uint32_t PR;
rolf.meyer@arm.com 11:1c1ebd0324fa 234 __IO uint32_t PC;
rolf.meyer@arm.com 11:1c1ebd0324fa 235 __IO uint32_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 236 __IO uint32_t MR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 237 __IO uint32_t MR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 238 __IO uint32_t MR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 239 __IO uint32_t MR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 240 __IO uint32_t CCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 241 __I uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 242 __I uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 243 __I uint32_t CR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 244 __I uint32_t CR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 245 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 246 __IO uint32_t MR4;
rolf.meyer@arm.com 11:1c1ebd0324fa 247 __IO uint32_t MR5;
rolf.meyer@arm.com 11:1c1ebd0324fa 248 __IO uint32_t MR6;
rolf.meyer@arm.com 11:1c1ebd0324fa 249 __IO uint32_t PCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 250 __IO uint32_t LER;
rolf.meyer@arm.com 11:1c1ebd0324fa 251 uint32_t RESERVED1[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 252 __IO uint32_t CTCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 253 } LPC_PWM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 254
rolf.meyer@arm.com 11:1c1ebd0324fa 255 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 256 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 257 {
rolf.meyer@arm.com 11:1c1ebd0324fa 258 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 259 __I uint8_t RBR;
rolf.meyer@arm.com 11:1c1ebd0324fa 260 __O uint8_t THR;
rolf.meyer@arm.com 11:1c1ebd0324fa 261 __IO uint8_t DLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 262 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 263 };
rolf.meyer@arm.com 11:1c1ebd0324fa 264 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 265 __IO uint8_t DLM;
rolf.meyer@arm.com 11:1c1ebd0324fa 266 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 267 };
rolf.meyer@arm.com 11:1c1ebd0324fa 268 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 269 __I uint32_t IIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 270 __O uint8_t FCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 271 };
rolf.meyer@arm.com 11:1c1ebd0324fa 272 __IO uint8_t LCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 273 uint8_t RESERVED1[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 274 __I uint8_t LSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 275 uint8_t RESERVED2[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 276 __IO uint8_t SCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 277 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 278 __IO uint32_t ACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 279 __IO uint8_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 280 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 281 __IO uint8_t FDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 282 uint8_t RESERVED5[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 283 __IO uint8_t TER;
rolf.meyer@arm.com 11:1c1ebd0324fa 284 uint8_t RESERVED6[39];
rolf.meyer@arm.com 11:1c1ebd0324fa 285 __I uint8_t FIFOLVL;
rolf.meyer@arm.com 11:1c1ebd0324fa 286 } LPC_UART_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 287
rolf.meyer@arm.com 11:1c1ebd0324fa 288 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 289 {
rolf.meyer@arm.com 11:1c1ebd0324fa 290 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 291 __I uint8_t RBR;
rolf.meyer@arm.com 11:1c1ebd0324fa 292 __O uint8_t THR;
rolf.meyer@arm.com 11:1c1ebd0324fa 293 __IO uint8_t DLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 294 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 295 };
rolf.meyer@arm.com 11:1c1ebd0324fa 296 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 297 __IO uint8_t DLM;
rolf.meyer@arm.com 11:1c1ebd0324fa 298 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 299 };
rolf.meyer@arm.com 11:1c1ebd0324fa 300 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 301 __I uint32_t IIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 302 __O uint8_t FCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 303 };
rolf.meyer@arm.com 11:1c1ebd0324fa 304 __IO uint8_t LCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 305 uint8_t RESERVED1[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 306 __I uint8_t LSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 307 uint8_t RESERVED2[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 308 __IO uint8_t SCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 309 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 310 __IO uint32_t ACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 311 __IO uint8_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 312 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 313 __IO uint8_t FDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 314 uint8_t RESERVED5[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 315 __IO uint8_t TER;
rolf.meyer@arm.com 11:1c1ebd0324fa 316 uint8_t RESERVED6[39];
rolf.meyer@arm.com 11:1c1ebd0324fa 317 __I uint8_t FIFOLVL;
rolf.meyer@arm.com 11:1c1ebd0324fa 318 uint8_t RESERVED7[363];
rolf.meyer@arm.com 11:1c1ebd0324fa 319 __IO uint32_t DMAREQSEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 320 } LPC_UART0_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 321
rolf.meyer@arm.com 11:1c1ebd0324fa 322 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 323 {
rolf.meyer@arm.com 11:1c1ebd0324fa 324 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 325 __I uint8_t RBR;
rolf.meyer@arm.com 11:1c1ebd0324fa 326 __O uint8_t THR;
rolf.meyer@arm.com 11:1c1ebd0324fa 327 __IO uint8_t DLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 328 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 329 };
rolf.meyer@arm.com 11:1c1ebd0324fa 330 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 331 __IO uint8_t DLM;
rolf.meyer@arm.com 11:1c1ebd0324fa 332 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 333 };
rolf.meyer@arm.com 11:1c1ebd0324fa 334 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 335 __I uint32_t IIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 336 __O uint8_t FCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 337 };
rolf.meyer@arm.com 11:1c1ebd0324fa 338 __IO uint8_t LCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 339 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 340 __IO uint8_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 341 uint8_t RESERVED2[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 342 __I uint8_t LSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 343 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 344 __I uint8_t MSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 345 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 346 __IO uint8_t SCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 347 uint8_t RESERVED5[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 348 __IO uint32_t ACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 349 uint32_t RESERVED6;
rolf.meyer@arm.com 11:1c1ebd0324fa 350 __IO uint32_t FDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 351 uint32_t RESERVED7;
rolf.meyer@arm.com 11:1c1ebd0324fa 352 __IO uint8_t TER;
rolf.meyer@arm.com 11:1c1ebd0324fa 353 uint8_t RESERVED8[27];
rolf.meyer@arm.com 11:1c1ebd0324fa 354 __IO uint8_t RS485CTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 355 uint8_t RESERVED9[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 356 __IO uint8_t ADRMATCH;
rolf.meyer@arm.com 11:1c1ebd0324fa 357 uint8_t RESERVED10[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 358 __IO uint8_t RS485DLY;
rolf.meyer@arm.com 11:1c1ebd0324fa 359 uint8_t RESERVED11[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 360 __I uint8_t FIFOLVL;
rolf.meyer@arm.com 11:1c1ebd0324fa 361 } LPC_UART1_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 362
rolf.meyer@arm.com 11:1c1ebd0324fa 363 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 364 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 365 {
rolf.meyer@arm.com 11:1c1ebd0324fa 366 __IO uint32_t SPCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 367 __I uint32_t SPSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 368 __IO uint32_t SPDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 369 __IO uint32_t SPCCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 370 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 371 __IO uint32_t SPINT;
rolf.meyer@arm.com 11:1c1ebd0324fa 372 } LPC_SPI_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 373
rolf.meyer@arm.com 11:1c1ebd0324fa 374 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 375 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 376 {
rolf.meyer@arm.com 11:1c1ebd0324fa 377 __IO uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 378 __IO uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 379 __IO uint32_t DR;
rolf.meyer@arm.com 11:1c1ebd0324fa 380 __I uint32_t SR;
rolf.meyer@arm.com 11:1c1ebd0324fa 381 __IO uint32_t CPSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 382 __IO uint32_t IMSC;
rolf.meyer@arm.com 11:1c1ebd0324fa 383 __IO uint32_t RIS;
rolf.meyer@arm.com 11:1c1ebd0324fa 384 __IO uint32_t MIS;
rolf.meyer@arm.com 11:1c1ebd0324fa 385 __IO uint32_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 386 __IO uint32_t DMACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 387 } LPC_SSP_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 388
rolf.meyer@arm.com 11:1c1ebd0324fa 389 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 390 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 391 {
rolf.meyer@arm.com 11:1c1ebd0324fa 392 __IO uint32_t I2CONSET;
rolf.meyer@arm.com 11:1c1ebd0324fa 393 __I uint32_t I2STAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 394 __IO uint32_t I2DAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 395 __IO uint32_t I2ADR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 396 __IO uint32_t I2SCLH;
rolf.meyer@arm.com 11:1c1ebd0324fa 397 __IO uint32_t I2SCLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 398 __O uint32_t I2CONCLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 399 __IO uint32_t MMCTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 400 __IO uint32_t I2ADR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 401 __IO uint32_t I2ADR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 402 __IO uint32_t I2ADR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 403 __I uint32_t I2DATA_BUFFER;
rolf.meyer@arm.com 11:1c1ebd0324fa 404 __IO uint32_t I2MASK0;
rolf.meyer@arm.com 11:1c1ebd0324fa 405 __IO uint32_t I2MASK1;
rolf.meyer@arm.com 11:1c1ebd0324fa 406 __IO uint32_t I2MASK2;
rolf.meyer@arm.com 11:1c1ebd0324fa 407 __IO uint32_t I2MASK3;
rolf.meyer@arm.com 11:1c1ebd0324fa 408 } LPC_I2C_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 409
rolf.meyer@arm.com 11:1c1ebd0324fa 410 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 411 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 412 {
rolf.meyer@arm.com 11:1c1ebd0324fa 413 __IO uint32_t I2SDAO;
rolf.meyer@arm.com 11:1c1ebd0324fa 414 __IO uint32_t I2SDAI;
rolf.meyer@arm.com 11:1c1ebd0324fa 415 __O uint32_t I2STXFIFO;
rolf.meyer@arm.com 11:1c1ebd0324fa 416 __I uint32_t I2SRXFIFO;
rolf.meyer@arm.com 11:1c1ebd0324fa 417 __I uint32_t I2SSTATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 418 __IO uint32_t I2SDMA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 419 __IO uint32_t I2SDMA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 420 __IO uint32_t I2SIRQ;
rolf.meyer@arm.com 11:1c1ebd0324fa 421 __IO uint32_t I2STXRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 422 __IO uint32_t I2SRXRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 423 __IO uint32_t I2STXBITRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 424 __IO uint32_t I2SRXBITRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 425 __IO uint32_t I2STXMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 426 __IO uint32_t I2SRXMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 427 } LPC_I2S_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 428
rolf.meyer@arm.com 11:1c1ebd0324fa 429 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 430 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 431 {
rolf.meyer@arm.com 11:1c1ebd0324fa 432 __IO uint32_t RICOMPVAL;
rolf.meyer@arm.com 11:1c1ebd0324fa 433 __IO uint32_t RIMASK;
rolf.meyer@arm.com 11:1c1ebd0324fa 434 __IO uint8_t RICTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 435 uint8_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 436 __IO uint32_t RICOUNTER;
rolf.meyer@arm.com 11:1c1ebd0324fa 437 } LPC_RIT_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 438
rolf.meyer@arm.com 11:1c1ebd0324fa 439 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 440 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 441 {
rolf.meyer@arm.com 11:1c1ebd0324fa 442 __IO uint8_t ILR;
rolf.meyer@arm.com 11:1c1ebd0324fa 443 uint8_t RESERVED0[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 444 __IO uint8_t CCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 445 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 446 __IO uint8_t CIIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 447 uint8_t RESERVED2[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 448 __IO uint8_t AMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 449 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 450 __I uint32_t CTIME0;
rolf.meyer@arm.com 11:1c1ebd0324fa 451 __I uint32_t CTIME1;
rolf.meyer@arm.com 11:1c1ebd0324fa 452 __I uint32_t CTIME2;
rolf.meyer@arm.com 11:1c1ebd0324fa 453 __IO uint8_t SEC;
rolf.meyer@arm.com 11:1c1ebd0324fa 454 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 455 __IO uint8_t MIN;
rolf.meyer@arm.com 11:1c1ebd0324fa 456 uint8_t RESERVED5[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 457 __IO uint8_t HOUR;
rolf.meyer@arm.com 11:1c1ebd0324fa 458 uint8_t RESERVED6[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 459 __IO uint8_t DOM;
rolf.meyer@arm.com 11:1c1ebd0324fa 460 uint8_t RESERVED7[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 461 __IO uint8_t DOW;
rolf.meyer@arm.com 11:1c1ebd0324fa 462 uint8_t RESERVED8[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 463 __IO uint16_t DOY;
rolf.meyer@arm.com 11:1c1ebd0324fa 464 uint16_t RESERVED9;
rolf.meyer@arm.com 11:1c1ebd0324fa 465 __IO uint8_t MONTH;
rolf.meyer@arm.com 11:1c1ebd0324fa 466 uint8_t RESERVED10[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 467 __IO uint16_t YEAR;
rolf.meyer@arm.com 11:1c1ebd0324fa 468 uint16_t RESERVED11;
rolf.meyer@arm.com 11:1c1ebd0324fa 469 __IO uint32_t CALIBRATION;
rolf.meyer@arm.com 11:1c1ebd0324fa 470 __IO uint32_t GPREG0;
rolf.meyer@arm.com 11:1c1ebd0324fa 471 __IO uint32_t GPREG1;
rolf.meyer@arm.com 11:1c1ebd0324fa 472 __IO uint32_t GPREG2;
rolf.meyer@arm.com 11:1c1ebd0324fa 473 __IO uint32_t GPREG3;
rolf.meyer@arm.com 11:1c1ebd0324fa 474 __IO uint32_t GPREG4;
rolf.meyer@arm.com 11:1c1ebd0324fa 475 __IO uint8_t RTC_AUXEN;
rolf.meyer@arm.com 11:1c1ebd0324fa 476 uint8_t RESERVED12[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 477 __IO uint8_t RTC_AUX;
rolf.meyer@arm.com 11:1c1ebd0324fa 478 uint8_t RESERVED13[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 479 __IO uint8_t ALSEC;
rolf.meyer@arm.com 11:1c1ebd0324fa 480 uint8_t RESERVED14[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 481 __IO uint8_t ALMIN;
rolf.meyer@arm.com 11:1c1ebd0324fa 482 uint8_t RESERVED15[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 483 __IO uint8_t ALHOUR;
rolf.meyer@arm.com 11:1c1ebd0324fa 484 uint8_t RESERVED16[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 485 __IO uint8_t ALDOM;
rolf.meyer@arm.com 11:1c1ebd0324fa 486 uint8_t RESERVED17[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 487 __IO uint8_t ALDOW;
rolf.meyer@arm.com 11:1c1ebd0324fa 488 uint8_t RESERVED18[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 489 __IO uint16_t ALDOY;
rolf.meyer@arm.com 11:1c1ebd0324fa 490 uint16_t RESERVED19;
rolf.meyer@arm.com 11:1c1ebd0324fa 491 __IO uint8_t ALMON;
rolf.meyer@arm.com 11:1c1ebd0324fa 492 uint8_t RESERVED20[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 493 __IO uint16_t ALYEAR;
rolf.meyer@arm.com 11:1c1ebd0324fa 494 uint16_t RESERVED21;
rolf.meyer@arm.com 11:1c1ebd0324fa 495 } LPC_RTC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 496
rolf.meyer@arm.com 11:1c1ebd0324fa 497 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 498 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 499 {
rolf.meyer@arm.com 11:1c1ebd0324fa 500 __IO uint8_t WDMOD;
rolf.meyer@arm.com 11:1c1ebd0324fa 501 uint8_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 502 __IO uint32_t WDTC;
rolf.meyer@arm.com 11:1c1ebd0324fa 503 __O uint8_t WDFEED;
rolf.meyer@arm.com 11:1c1ebd0324fa 504 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 505 __I uint32_t WDTV;
rolf.meyer@arm.com 11:1c1ebd0324fa 506 __IO uint32_t WDCLKSEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 507 } LPC_WDT_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 508
rolf.meyer@arm.com 11:1c1ebd0324fa 509 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 510 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 511 {
rolf.meyer@arm.com 11:1c1ebd0324fa 512 __IO uint32_t ADCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 513 __IO uint32_t ADGDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 514 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 515 __IO uint32_t ADINTEN;
rolf.meyer@arm.com 11:1c1ebd0324fa 516 __I uint32_t ADDR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 517 __I uint32_t ADDR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 518 __I uint32_t ADDR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 519 __I uint32_t ADDR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 520 __I uint32_t ADDR4;
rolf.meyer@arm.com 11:1c1ebd0324fa 521 __I uint32_t ADDR5;
rolf.meyer@arm.com 11:1c1ebd0324fa 522 __I uint32_t ADDR6;
rolf.meyer@arm.com 11:1c1ebd0324fa 523 __I uint32_t ADDR7;
rolf.meyer@arm.com 11:1c1ebd0324fa 524 __I uint32_t ADSTAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 525 __IO uint32_t ADTRM;
rolf.meyer@arm.com 11:1c1ebd0324fa 526 } LPC_ADC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 527
rolf.meyer@arm.com 11:1c1ebd0324fa 528 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 529 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 530 {
rolf.meyer@arm.com 11:1c1ebd0324fa 531 __IO uint32_t DACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 532 __IO uint32_t DACCTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 533 __IO uint16_t DACCNTVAL;
rolf.meyer@arm.com 11:1c1ebd0324fa 534 } LPC_DAC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 535
rolf.meyer@arm.com 11:1c1ebd0324fa 536 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 537 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 538 {
rolf.meyer@arm.com 11:1c1ebd0324fa 539 __I uint32_t MCCON;
rolf.meyer@arm.com 11:1c1ebd0324fa 540 __O uint32_t MCCON_SET;
rolf.meyer@arm.com 11:1c1ebd0324fa 541 __O uint32_t MCCON_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 542 __I uint32_t MCCAPCON;
rolf.meyer@arm.com 11:1c1ebd0324fa 543 __O uint32_t MCCAPCON_SET;
rolf.meyer@arm.com 11:1c1ebd0324fa 544 __O uint32_t MCCAPCON_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 545 __IO uint32_t MCTIM0;
rolf.meyer@arm.com 11:1c1ebd0324fa 546 __IO uint32_t MCTIM1;
rolf.meyer@arm.com 11:1c1ebd0324fa 547 __IO uint32_t MCTIM2;
rolf.meyer@arm.com 11:1c1ebd0324fa 548 __IO uint32_t MCPER0;
rolf.meyer@arm.com 11:1c1ebd0324fa 549 __IO uint32_t MCPER1;
rolf.meyer@arm.com 11:1c1ebd0324fa 550 __IO uint32_t MCPER2;
rolf.meyer@arm.com 11:1c1ebd0324fa 551 __IO uint32_t MCPW0;
rolf.meyer@arm.com 11:1c1ebd0324fa 552 __IO uint32_t MCPW1;
rolf.meyer@arm.com 11:1c1ebd0324fa 553 __IO uint32_t MCPW2;
rolf.meyer@arm.com 11:1c1ebd0324fa 554 __IO uint32_t MCDEADTIME;
rolf.meyer@arm.com 11:1c1ebd0324fa 555 __IO uint32_t MCCCP;
rolf.meyer@arm.com 11:1c1ebd0324fa 556 __IO uint32_t MCCR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 557 __IO uint32_t MCCR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 558 __IO uint32_t MCCR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 559 __I uint32_t MCINTEN;
rolf.meyer@arm.com 11:1c1ebd0324fa 560 __O uint32_t MCINTEN_SET;
rolf.meyer@arm.com 11:1c1ebd0324fa 561 __O uint32_t MCINTEN_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 562 __I uint32_t MCCNTCON;
rolf.meyer@arm.com 11:1c1ebd0324fa 563 __O uint32_t MCCNTCON_SET;
rolf.meyer@arm.com 11:1c1ebd0324fa 564 __O uint32_t MCCNTCON_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 565 __I uint32_t MCINTFLAG;
rolf.meyer@arm.com 11:1c1ebd0324fa 566 __O uint32_t MCINTFLAG_SET;
rolf.meyer@arm.com 11:1c1ebd0324fa 567 __O uint32_t MCINTFLAG_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 568 __O uint32_t MCCAP_CLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 569 } LPC_MCPWM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 570
rolf.meyer@arm.com 11:1c1ebd0324fa 571 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 572 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 573 {
rolf.meyer@arm.com 11:1c1ebd0324fa 574 __O uint32_t QEICON;
rolf.meyer@arm.com 11:1c1ebd0324fa 575 __I uint32_t QEISTAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 576 __IO uint32_t QEICONF;
rolf.meyer@arm.com 11:1c1ebd0324fa 577 __I uint32_t QEIPOS;
rolf.meyer@arm.com 11:1c1ebd0324fa 578 __IO uint32_t QEIMAXPOS;
rolf.meyer@arm.com 11:1c1ebd0324fa 579 __IO uint32_t CMPOS0;
rolf.meyer@arm.com 11:1c1ebd0324fa 580 __IO uint32_t CMPOS1;
rolf.meyer@arm.com 11:1c1ebd0324fa 581 __IO uint32_t CMPOS2;
rolf.meyer@arm.com 11:1c1ebd0324fa 582 __I uint32_t INXCNT;
rolf.meyer@arm.com 11:1c1ebd0324fa 583 __IO uint32_t INXCMP;
rolf.meyer@arm.com 11:1c1ebd0324fa 584 __IO uint32_t QEILOAD;
rolf.meyer@arm.com 11:1c1ebd0324fa 585 __I uint32_t QEITIME;
rolf.meyer@arm.com 11:1c1ebd0324fa 586 __I uint32_t QEIVEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 587 __I uint32_t QEICAP;
rolf.meyer@arm.com 11:1c1ebd0324fa 588 __IO uint32_t VELCOMP;
rolf.meyer@arm.com 11:1c1ebd0324fa 589 __IO uint32_t FILTER;
rolf.meyer@arm.com 11:1c1ebd0324fa 590 uint32_t RESERVED0[998];
rolf.meyer@arm.com 11:1c1ebd0324fa 591 __O uint32_t QEIIEC;
rolf.meyer@arm.com 11:1c1ebd0324fa 592 __O uint32_t QEIIES;
rolf.meyer@arm.com 11:1c1ebd0324fa 593 __I uint32_t QEIINTSTAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 594 __I uint32_t QEIIE;
rolf.meyer@arm.com 11:1c1ebd0324fa 595 __O uint32_t QEICLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 596 __O uint32_t QEISET;
rolf.meyer@arm.com 11:1c1ebd0324fa 597 } LPC_QEI_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 598
rolf.meyer@arm.com 11:1c1ebd0324fa 599 /*------------- Controller Area Network (CAN) --------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 600 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 601 {
rolf.meyer@arm.com 11:1c1ebd0324fa 602 __IO uint32_t mask[512]; /* ID Masks */
rolf.meyer@arm.com 11:1c1ebd0324fa 603 } LPC_CANAF_RAM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 604
rolf.meyer@arm.com 11:1c1ebd0324fa 605 typedef struct /* Acceptance Filter Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 606 {
rolf.meyer@arm.com 11:1c1ebd0324fa 607 __IO uint32_t AFMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 608 __IO uint32_t SFF_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 609 __IO uint32_t SFF_GRP_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 610 __IO uint32_t EFF_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 611 __IO uint32_t EFF_GRP_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 612 __IO uint32_t ENDofTable;
rolf.meyer@arm.com 11:1c1ebd0324fa 613 __I uint32_t LUTerrAd;
rolf.meyer@arm.com 11:1c1ebd0324fa 614 __I uint32_t LUTerr;
rolf.meyer@arm.com 11:1c1ebd0324fa 615 __IO uint32_t FCANIE;
rolf.meyer@arm.com 11:1c1ebd0324fa 616 __IO uint32_t FCANIC0;
rolf.meyer@arm.com 11:1c1ebd0324fa 617 __IO uint32_t FCANIC1;
rolf.meyer@arm.com 11:1c1ebd0324fa 618 } LPC_CANAF_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 619
rolf.meyer@arm.com 11:1c1ebd0324fa 620 typedef struct /* Central Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 621 {
rolf.meyer@arm.com 11:1c1ebd0324fa 622 __I uint32_t CANTxSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 623 __I uint32_t CANRxSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 624 __I uint32_t CANMSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 625 } LPC_CANCR_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 626
rolf.meyer@arm.com 11:1c1ebd0324fa 627 typedef struct /* Controller Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 628 {
rolf.meyer@arm.com 11:1c1ebd0324fa 629 __IO uint32_t MOD;
rolf.meyer@arm.com 11:1c1ebd0324fa 630 __O uint32_t CMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 631 __IO uint32_t GSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 632 __I uint32_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 633 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 634 __IO uint32_t BTR;
rolf.meyer@arm.com 11:1c1ebd0324fa 635 __IO uint32_t EWL;
rolf.meyer@arm.com 11:1c1ebd0324fa 636 __I uint32_t SR;
rolf.meyer@arm.com 11:1c1ebd0324fa 637 __IO uint32_t RFS;
rolf.meyer@arm.com 11:1c1ebd0324fa 638 __IO uint32_t RID;
rolf.meyer@arm.com 11:1c1ebd0324fa 639 __IO uint32_t RDA;
rolf.meyer@arm.com 11:1c1ebd0324fa 640 __IO uint32_t RDB;
rolf.meyer@arm.com 11:1c1ebd0324fa 641 __IO uint32_t TFI1;
rolf.meyer@arm.com 11:1c1ebd0324fa 642 __IO uint32_t TID1;
rolf.meyer@arm.com 11:1c1ebd0324fa 643 __IO uint32_t TDA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 644 __IO uint32_t TDB1;
rolf.meyer@arm.com 11:1c1ebd0324fa 645 __IO uint32_t TFI2;
rolf.meyer@arm.com 11:1c1ebd0324fa 646 __IO uint32_t TID2;
rolf.meyer@arm.com 11:1c1ebd0324fa 647 __IO uint32_t TDA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 648 __IO uint32_t TDB2;
rolf.meyer@arm.com 11:1c1ebd0324fa 649 __IO uint32_t TFI3;
rolf.meyer@arm.com 11:1c1ebd0324fa 650 __IO uint32_t TID3;
rolf.meyer@arm.com 11:1c1ebd0324fa 651 __IO uint32_t TDA3;
rolf.meyer@arm.com 11:1c1ebd0324fa 652 __IO uint32_t TDB3;
rolf.meyer@arm.com 11:1c1ebd0324fa 653 } LPC_CAN_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 654
rolf.meyer@arm.com 11:1c1ebd0324fa 655 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 656 typedef struct /* Common Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 657 {
rolf.meyer@arm.com 11:1c1ebd0324fa 658 __I uint32_t DMACIntStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 659 __I uint32_t DMACIntTCStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 660 __O uint32_t DMACIntTCClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 661 __I uint32_t DMACIntErrStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 662 __O uint32_t DMACIntErrClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 663 __I uint32_t DMACRawIntTCStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 664 __I uint32_t DMACRawIntErrStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 665 __I uint32_t DMACEnbldChns;
rolf.meyer@arm.com 11:1c1ebd0324fa 666 __IO uint32_t DMACSoftBReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 667 __IO uint32_t DMACSoftSReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 668 __IO uint32_t DMACSoftLBReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 669 __IO uint32_t DMACSoftLSReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 670 __IO uint32_t DMACConfig;
rolf.meyer@arm.com 11:1c1ebd0324fa 671 __IO uint32_t DMACSync;
rolf.meyer@arm.com 11:1c1ebd0324fa 672 } LPC_GPDMA_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 673
rolf.meyer@arm.com 11:1c1ebd0324fa 674 typedef struct /* Channel Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 675 {
rolf.meyer@arm.com 11:1c1ebd0324fa 676 __IO uint32_t DMACCSrcAddr;
rolf.meyer@arm.com 11:1c1ebd0324fa 677 __IO uint32_t DMACCDestAddr;
rolf.meyer@arm.com 11:1c1ebd0324fa 678 __IO uint32_t DMACCLLI;
rolf.meyer@arm.com 11:1c1ebd0324fa 679 __IO uint32_t DMACCControl;
rolf.meyer@arm.com 11:1c1ebd0324fa 680 __IO uint32_t DMACCConfig;
rolf.meyer@arm.com 11:1c1ebd0324fa 681 } LPC_GPDMACH_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 682
rolf.meyer@arm.com 11:1c1ebd0324fa 683 /*------------- Universal Serial Bus (USB) -----------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 684 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 685 {
rolf.meyer@arm.com 11:1c1ebd0324fa 686 __I uint32_t HcRevision; /* USB Host Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 687 __IO uint32_t HcControl;
rolf.meyer@arm.com 11:1c1ebd0324fa 688 __IO uint32_t HcCommandStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 689 __IO uint32_t HcInterruptStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 690 __IO uint32_t HcInterruptEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 691 __IO uint32_t HcInterruptDisable;
rolf.meyer@arm.com 11:1c1ebd0324fa 692 __IO uint32_t HcHCCA;
rolf.meyer@arm.com 11:1c1ebd0324fa 693 __I uint32_t HcPeriodCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 694 __IO uint32_t HcControlHeadED;
rolf.meyer@arm.com 11:1c1ebd0324fa 695 __IO uint32_t HcControlCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 696 __IO uint32_t HcBulkHeadED;
rolf.meyer@arm.com 11:1c1ebd0324fa 697 __IO uint32_t HcBulkCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 698 __I uint32_t HcDoneHead;
rolf.meyer@arm.com 11:1c1ebd0324fa 699 __IO uint32_t HcFmInterval;
rolf.meyer@arm.com 11:1c1ebd0324fa 700 __I uint32_t HcFmRemaining;
rolf.meyer@arm.com 11:1c1ebd0324fa 701 __I uint32_t HcFmNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 702 __IO uint32_t HcPeriodicStart;
rolf.meyer@arm.com 11:1c1ebd0324fa 703 __IO uint32_t HcLSTreshold;
rolf.meyer@arm.com 11:1c1ebd0324fa 704 __IO uint32_t HcRhDescriptorA;
rolf.meyer@arm.com 11:1c1ebd0324fa 705 __IO uint32_t HcRhDescriptorB;
rolf.meyer@arm.com 11:1c1ebd0324fa 706 __IO uint32_t HcRhStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 707 __IO uint32_t HcRhPortStatus1;
rolf.meyer@arm.com 11:1c1ebd0324fa 708 __IO uint32_t HcRhPortStatus2;
rolf.meyer@arm.com 11:1c1ebd0324fa 709 uint32_t RESERVED0[40];
rolf.meyer@arm.com 11:1c1ebd0324fa 710 __I uint32_t Module_ID;
rolf.meyer@arm.com 11:1c1ebd0324fa 711
rolf.meyer@arm.com 11:1c1ebd0324fa 712 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 713 __IO uint32_t OTGIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 714 __O uint32_t OTGIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 715 __O uint32_t OTGIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 716 __IO uint32_t OTGStCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 717 __IO uint32_t OTGTmr;
rolf.meyer@arm.com 11:1c1ebd0324fa 718 uint32_t RESERVED1[58];
rolf.meyer@arm.com 11:1c1ebd0324fa 719
rolf.meyer@arm.com 11:1c1ebd0324fa 720 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 721 __IO uint32_t USBDevIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 722 __O uint32_t USBDevIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 723 __O uint32_t USBDevIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 724
rolf.meyer@arm.com 11:1c1ebd0324fa 725 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 726 __I uint32_t USBCmdData;
rolf.meyer@arm.com 11:1c1ebd0324fa 727
rolf.meyer@arm.com 11:1c1ebd0324fa 728 __I uint32_t USBRxData; /* USB Device Transfer Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 729 __O uint32_t USBTxData;
rolf.meyer@arm.com 11:1c1ebd0324fa 730 __I uint32_t USBRxPLen;
rolf.meyer@arm.com 11:1c1ebd0324fa 731 __O uint32_t USBTxPLen;
rolf.meyer@arm.com 11:1c1ebd0324fa 732 __IO uint32_t USBCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 733 __O uint32_t USBDevIntPri;
rolf.meyer@arm.com 11:1c1ebd0324fa 734
rolf.meyer@arm.com 11:1c1ebd0324fa 735 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
rolf.meyer@arm.com 11:1c1ebd0324fa 736 __IO uint32_t USBEpIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 737 __O uint32_t USBEpIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 738 __O uint32_t USBEpIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 739 __O uint32_t USBEpIntPri;
rolf.meyer@arm.com 11:1c1ebd0324fa 740
rolf.meyer@arm.com 11:1c1ebd0324fa 741 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
rolf.meyer@arm.com 11:1c1ebd0324fa 742 __O uint32_t USBEpInd;
rolf.meyer@arm.com 11:1c1ebd0324fa 743 __IO uint32_t USBMaxPSize;
rolf.meyer@arm.com 11:1c1ebd0324fa 744
rolf.meyer@arm.com 11:1c1ebd0324fa 745 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 746 __O uint32_t USBDMARClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 747 __O uint32_t USBDMARSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 748 uint32_t RESERVED2[9];
rolf.meyer@arm.com 11:1c1ebd0324fa 749 __IO uint32_t USBUDCAH;
rolf.meyer@arm.com 11:1c1ebd0324fa 750 __I uint32_t USBEpDMASt;
rolf.meyer@arm.com 11:1c1ebd0324fa 751 __O uint32_t USBEpDMAEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 752 __O uint32_t USBEpDMADis;
rolf.meyer@arm.com 11:1c1ebd0324fa 753 __I uint32_t USBDMAIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 754 __IO uint32_t USBDMAIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 755 uint32_t RESERVED3[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 756 __I uint32_t USBEoTIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 757 __O uint32_t USBEoTIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 758 __O uint32_t USBEoTIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 759 __I uint32_t USBNDDRIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 760 __O uint32_t USBNDDRIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 761 __O uint32_t USBNDDRIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 762 __I uint32_t USBSysErrIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 763 __O uint32_t USBSysErrIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 764 __O uint32_t USBSysErrIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 765 uint32_t RESERVED4[15];
rolf.meyer@arm.com 11:1c1ebd0324fa 766
rolf.meyer@arm.com 11:1c1ebd0324fa 767 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 768 __O uint32_t I2C_WO;
rolf.meyer@arm.com 11:1c1ebd0324fa 769 __I uint32_t I2C_STS;
rolf.meyer@arm.com 11:1c1ebd0324fa 770 __IO uint32_t I2C_CTL;
rolf.meyer@arm.com 11:1c1ebd0324fa 771 __IO uint32_t I2C_CLKHI;
rolf.meyer@arm.com 11:1c1ebd0324fa 772 __O uint32_t I2C_CLKLO;
rolf.meyer@arm.com 11:1c1ebd0324fa 773 uint32_t RESERVED5[823];
rolf.meyer@arm.com 11:1c1ebd0324fa 774
rolf.meyer@arm.com 11:1c1ebd0324fa 775 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 776 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 777 __IO uint32_t OTGClkCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 778 };
rolf.meyer@arm.com 11:1c1ebd0324fa 779 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 780 __I uint32_t USBClkSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 781 __I uint32_t OTGClkSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 782 };
rolf.meyer@arm.com 11:1c1ebd0324fa 783 } LPC_USB_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 784
rolf.meyer@arm.com 11:1c1ebd0324fa 785 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 786 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 787 {
rolf.meyer@arm.com 11:1c1ebd0324fa 788 __IO uint32_t MAC1; /* MAC Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 789 __IO uint32_t MAC2;
rolf.meyer@arm.com 11:1c1ebd0324fa 790 __IO uint32_t IPGT;
rolf.meyer@arm.com 11:1c1ebd0324fa 791 __IO uint32_t IPGR;
rolf.meyer@arm.com 11:1c1ebd0324fa 792 __IO uint32_t CLRT;
rolf.meyer@arm.com 11:1c1ebd0324fa 793 __IO uint32_t MAXF;
rolf.meyer@arm.com 11:1c1ebd0324fa 794 __IO uint32_t SUPP;
rolf.meyer@arm.com 11:1c1ebd0324fa 795 __IO uint32_t TEST;
rolf.meyer@arm.com 11:1c1ebd0324fa 796 __IO uint32_t MCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 797 __IO uint32_t MCMD;
rolf.meyer@arm.com 11:1c1ebd0324fa 798 __IO uint32_t MADR;
rolf.meyer@arm.com 11:1c1ebd0324fa 799 __O uint32_t MWTD;
rolf.meyer@arm.com 11:1c1ebd0324fa 800 __I uint32_t MRDD;
rolf.meyer@arm.com 11:1c1ebd0324fa 801 __I uint32_t MIND;
rolf.meyer@arm.com 11:1c1ebd0324fa 802 uint32_t RESERVED0[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 803 __IO uint32_t SA0;
rolf.meyer@arm.com 11:1c1ebd0324fa 804 __IO uint32_t SA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 805 __IO uint32_t SA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 806 uint32_t RESERVED1[45];
rolf.meyer@arm.com 11:1c1ebd0324fa 807 __IO uint32_t Command; /* Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 808 __I uint32_t Status;
rolf.meyer@arm.com 11:1c1ebd0324fa 809 __IO uint32_t RxDescriptor;
rolf.meyer@arm.com 11:1c1ebd0324fa 810 __IO uint32_t RxStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 811 __IO uint32_t RxDescriptorNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 812 __I uint32_t RxProduceIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 813 __IO uint32_t RxConsumeIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 814 __IO uint32_t TxDescriptor;
rolf.meyer@arm.com 11:1c1ebd0324fa 815 __IO uint32_t TxStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 816 __IO uint32_t TxDescriptorNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 817 __IO uint32_t TxProduceIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 818 __I uint32_t TxConsumeIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 819 uint32_t RESERVED2[10];
rolf.meyer@arm.com 11:1c1ebd0324fa 820 __I uint32_t TSV0;
rolf.meyer@arm.com 11:1c1ebd0324fa 821 __I uint32_t TSV1;
rolf.meyer@arm.com 11:1c1ebd0324fa 822 __I uint32_t RSV;
rolf.meyer@arm.com 11:1c1ebd0324fa 823 uint32_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 824 __IO uint32_t FlowControlCounter;
rolf.meyer@arm.com 11:1c1ebd0324fa 825 __I uint32_t FlowControlStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 826 uint32_t RESERVED4[34];
rolf.meyer@arm.com 11:1c1ebd0324fa 827 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 828 __IO uint32_t RxFilterWoLStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 829 __IO uint32_t RxFilterWoLClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 830 uint32_t RESERVED5;
rolf.meyer@arm.com 11:1c1ebd0324fa 831 __IO uint32_t HashFilterL;
rolf.meyer@arm.com 11:1c1ebd0324fa 832 __IO uint32_t HashFilterH;
rolf.meyer@arm.com 11:1c1ebd0324fa 833 uint32_t RESERVED6[882];
rolf.meyer@arm.com 11:1c1ebd0324fa 834 __I uint32_t IntStatus; /* Module Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 835 __IO uint32_t IntEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 836 __O uint32_t IntClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 837 __O uint32_t IntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 838 uint32_t RESERVED7;
rolf.meyer@arm.com 11:1c1ebd0324fa 839 __IO uint32_t PowerDown;
rolf.meyer@arm.com 11:1c1ebd0324fa 840 uint32_t RESERVED8;
rolf.meyer@arm.com 11:1c1ebd0324fa 841 __IO uint32_t Module_ID;
rolf.meyer@arm.com 11:1c1ebd0324fa 842 } LPC_EMAC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 843
rolf.meyer@arm.com 11:1c1ebd0324fa 844 #if defined ( __CC_ARM )
rolf.meyer@arm.com 11:1c1ebd0324fa 845 #pragma anon_unions
rolf.meyer@arm.com 11:1c1ebd0324fa 846 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 847
rolf.meyer@arm.com 11:1c1ebd0324fa 848
rolf.meyer@arm.com 11:1c1ebd0324fa 849 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 850 /* Peripheral memory map */
rolf.meyer@arm.com 11:1c1ebd0324fa 851 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 852 /* Base addresses */
rolf.meyer@arm.com 11:1c1ebd0324fa 853 #define LPC_FLASH_BASE (0x00000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 854 #define LPC_RAM_BASE (0x10000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 855 #define LPC_GPIO_BASE (0x2009C000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 856 #define LPC_APB0_BASE (0x40000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 857 #define LPC_APB1_BASE (0x40080000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 858 #define LPC_AHB_BASE (0x50000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 859 #define LPC_CM3_BASE (0xE0000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 860
rolf.meyer@arm.com 11:1c1ebd0324fa 861 /* APB0 peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 862 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
rolf.meyer@arm.com 11:1c1ebd0324fa 863 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
rolf.meyer@arm.com 11:1c1ebd0324fa 864 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
rolf.meyer@arm.com 11:1c1ebd0324fa 865 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 866 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
rolf.meyer@arm.com 11:1c1ebd0324fa 867 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
rolf.meyer@arm.com 11:1c1ebd0324fa 868 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 869 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
rolf.meyer@arm.com 11:1c1ebd0324fa 870 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
rolf.meyer@arm.com 11:1c1ebd0324fa 871 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
rolf.meyer@arm.com 11:1c1ebd0324fa 872 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 873 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
rolf.meyer@arm.com 11:1c1ebd0324fa 874 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
rolf.meyer@arm.com 11:1c1ebd0324fa 875 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
rolf.meyer@arm.com 11:1c1ebd0324fa 876 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 877 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
rolf.meyer@arm.com 11:1c1ebd0324fa 878 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
rolf.meyer@arm.com 11:1c1ebd0324fa 879 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
rolf.meyer@arm.com 11:1c1ebd0324fa 880 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 881
rolf.meyer@arm.com 11:1c1ebd0324fa 882 /* APB1 peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 883 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
rolf.meyer@arm.com 11:1c1ebd0324fa 884 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 885 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
rolf.meyer@arm.com 11:1c1ebd0324fa 886 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
rolf.meyer@arm.com 11:1c1ebd0324fa 887 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
rolf.meyer@arm.com 11:1c1ebd0324fa 888 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 889 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
rolf.meyer@arm.com 11:1c1ebd0324fa 890 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
rolf.meyer@arm.com 11:1c1ebd0324fa 891 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
rolf.meyer@arm.com 11:1c1ebd0324fa 892 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
rolf.meyer@arm.com 11:1c1ebd0324fa 893 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 894 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 895
rolf.meyer@arm.com 11:1c1ebd0324fa 896 /* AHB peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 897 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
rolf.meyer@arm.com 11:1c1ebd0324fa 898 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
rolf.meyer@arm.com 11:1c1ebd0324fa 899 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
rolf.meyer@arm.com 11:1c1ebd0324fa 900 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
rolf.meyer@arm.com 11:1c1ebd0324fa 901 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
rolf.meyer@arm.com 11:1c1ebd0324fa 902 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
rolf.meyer@arm.com 11:1c1ebd0324fa 903 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
rolf.meyer@arm.com 11:1c1ebd0324fa 904 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
rolf.meyer@arm.com 11:1c1ebd0324fa 905 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
rolf.meyer@arm.com 11:1c1ebd0324fa 906 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
rolf.meyer@arm.com 11:1c1ebd0324fa 907 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 908
rolf.meyer@arm.com 11:1c1ebd0324fa 909 /* GPIOs */
rolf.meyer@arm.com 11:1c1ebd0324fa 910 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
rolf.meyer@arm.com 11:1c1ebd0324fa 911 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
rolf.meyer@arm.com 11:1c1ebd0324fa 912 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
rolf.meyer@arm.com 11:1c1ebd0324fa 913 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
rolf.meyer@arm.com 11:1c1ebd0324fa 914 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
rolf.meyer@arm.com 11:1c1ebd0324fa 915
rolf.meyer@arm.com 11:1c1ebd0324fa 916
rolf.meyer@arm.com 11:1c1ebd0324fa 917 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 918 /* Peripheral declaration */
rolf.meyer@arm.com 11:1c1ebd0324fa 919 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 920 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 921 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 922 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 923 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 924 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 925 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 926 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 927 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 928 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 929 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 930 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 931 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 932 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 933 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 934 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 935 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 936 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 937 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 938 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 939 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 940 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 941 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 942 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 943 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 944 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 945 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 946 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 947 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 948 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 949 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 950 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 951 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 952 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 953 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 954 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 955 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 956 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 957 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 958 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 959 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 960 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 961 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 962 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 963 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 964 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 965 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 966 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
rolf.meyer@arm.com 11:1c1ebd0324fa 967
rolf.meyer@arm.com 11:1c1ebd0324fa 968 #endif // __LPC17xx_H__