Egor Rumjantsev / mbed

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim_ex.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:
bogdanm
Date:
Wed Jun 11 15:14:05 2014 +0100
Revision:
85:024bf7f99721
Parent:
81:7d30d6019079
Child:
90:cb3d968589d8
Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_tim_ex.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
bogdanm 85:024bf7f99721 5 * @version V1.1.0RC2
bogdanm 85:024bf7f99721 6 * @date 14-May-2014
emilmont 77:869cf507173a 7 * @brief Header file of TIM HAL Extension module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_TIM_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_TIM_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup TIMEx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59 /**
emilmont 77:869cf507173a 60 * @brief TIM Hall sensor Configuration Structure definition
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 typedef struct
emilmont 77:869cf507173a 64 {
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
emilmont 77:869cf507173a 67 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
emilmont 77:869cf507173a 68
emilmont 77:869cf507173a 69 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
emilmont 77:869cf507173a 70 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 uint32_t IC1Filter; /*!< Specifies the input capture filter.
emilmont 77:869cf507173a 73 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
emilmont 77:869cf507173a 74 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
emilmont 77:869cf507173a 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
emilmont 77:869cf507173a 76 } TIM_HallSensor_InitTypeDef;
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78 /**
emilmont 77:869cf507173a 79 * @brief TIM Master configuration Structure definition
emilmont 77:869cf507173a 80 */
emilmont 77:869cf507173a 81 typedef struct {
bogdanm 85:024bf7f99721 82 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
bogdanm 85:024bf7f99721 83 This parameter can be a value of @ref TIMEx_Master_Mode_Selection */
bogdanm 85:024bf7f99721 84 uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
bogdanm 85:024bf7f99721 85 This parameter can be a value of @ref TIMEx_Master_Slave_Mode */
emilmont 77:869cf507173a 86 }TIM_MasterConfigTypeDef;
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 /**
emilmont 77:869cf507173a 89 * @brief TIM Break and Dead time configuration Structure definition
emilmont 77:869cf507173a 90 */
emilmont 77:869cf507173a 91 typedef struct
emilmont 77:869cf507173a 92 {
bogdanm 85:024bf7f99721 93 uint32_t OffStateRunMode; /*!< TIM off state in run mode.
bogdanm 85:024bf7f99721 94 This parameter can be a value of @ref TIMEx_OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm 85:024bf7f99721 95 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
bogdanm 85:024bf7f99721 96 This parameter can be a value of @ref TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm 85:024bf7f99721 97 uint32_t LockLevel; /*!< TIM Lock level.
bogdanm 85:024bf7f99721 98 This parameter can be a value of @ref TIMEx_Lock_level */
bogdanm 85:024bf7f99721 99 uint32_t DeadTime; /*!< TIM dead Time.
emilmont 77:869cf507173a 100 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 85:024bf7f99721 101 uint32_t BreakState; /*!< TIM Break State.
bogdanm 85:024bf7f99721 102 This parameter can be a value of @ref TIMEx_Break_Input_enable_disable */
bogdanm 85:024bf7f99721 103 uint32_t BreakPolarity; /*!< TIM Break input polarity.
bogdanm 85:024bf7f99721 104 This parameter can be a value of @ref TIMEx_Break_Polarity */
bogdanm 85:024bf7f99721 105 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
bogdanm 85:024bf7f99721 106 This parameter can be a value of @ref TIMEx_AOE_Bit_Set_Reset */
emilmont 77:869cf507173a 107 }TIM_BreakDeadTimeConfigTypeDef;
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 110 /** @defgroup TIMEx_Exported_Constants
emilmont 77:869cf507173a 111 * @{
emilmont 77:869cf507173a 112 */
bogdanm 85:024bf7f99721 113 /** @defgroup TIMEx_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm 85:024bf7f99721 114 * @{
bogdanm 85:024bf7f99721 115 */
bogdanm 85:024bf7f99721 116 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm 85:024bf7f99721 117 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
emilmont 77:869cf507173a 118
bogdanm 85:024bf7f99721 119 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
bogdanm 85:024bf7f99721 120 ((STATE) == TIM_OSSR_DISABLE))
bogdanm 85:024bf7f99721 121 /**
bogdanm 85:024bf7f99721 122 * @}
bogdanm 85:024bf7f99721 123 */
bogdanm 85:024bf7f99721 124
bogdanm 85:024bf7f99721 125 /** @defgroup TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm 85:024bf7f99721 126 * @{
bogdanm 85:024bf7f99721 127 */
bogdanm 85:024bf7f99721 128 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 85:024bf7f99721 129 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 130
bogdanm 85:024bf7f99721 131 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
bogdanm 85:024bf7f99721 132 ((STATE) == TIM_OSSI_DISABLE))
bogdanm 85:024bf7f99721 133 /**
bogdanm 85:024bf7f99721 134 * @}
bogdanm 85:024bf7f99721 135 */
bogdanm 85:024bf7f99721 136 /** @defgroup TIMEx_Lock_level
bogdanm 85:024bf7f99721 137 * @{
bogdanm 85:024bf7f99721 138 */
bogdanm 85:024bf7f99721 139 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 140 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 85:024bf7f99721 141 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 85:024bf7f99721 142 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 85:024bf7f99721 143
bogdanm 85:024bf7f99721 144 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
bogdanm 85:024bf7f99721 145 ((LEVEL) == TIM_LOCKLEVEL_1) || \
bogdanm 85:024bf7f99721 146 ((LEVEL) == TIM_LOCKLEVEL_2) || \
bogdanm 85:024bf7f99721 147 ((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm 85:024bf7f99721 148 /**
bogdanm 85:024bf7f99721 149 * @}
bogdanm 85:024bf7f99721 150 */
bogdanm 85:024bf7f99721 151 /** @defgroup TIMEx_Break_Input_enable_disable
bogdanm 85:024bf7f99721 152 * @{
bogdanm 85:024bf7f99721 153 */
bogdanm 85:024bf7f99721 154 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 85:024bf7f99721 155 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 156
bogdanm 85:024bf7f99721 157 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
bogdanm 85:024bf7f99721 158 ((STATE) == TIM_BREAK_DISABLE))
bogdanm 85:024bf7f99721 159 /**
bogdanm 85:024bf7f99721 160 * @}
bogdanm 85:024bf7f99721 161 */
bogdanm 85:024bf7f99721 162 /** @defgroup TIMEx_Break_Polarity
bogdanm 85:024bf7f99721 163 * @{
bogdanm 85:024bf7f99721 164 */
bogdanm 85:024bf7f99721 165 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 166 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 85:024bf7f99721 167
bogdanm 85:024bf7f99721 168 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
bogdanm 85:024bf7f99721 169 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm 85:024bf7f99721 170 /**
bogdanm 85:024bf7f99721 171 * @}
bogdanm 85:024bf7f99721 172 */
bogdanm 85:024bf7f99721 173 /** @defgroup TIMEx_AOE_Bit_Set_Reset
bogdanm 85:024bf7f99721 174 * @{
bogdanm 85:024bf7f99721 175 */
bogdanm 85:024bf7f99721 176 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 85:024bf7f99721 177 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 178
bogdanm 85:024bf7f99721 179 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
bogdanm 85:024bf7f99721 180 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm 85:024bf7f99721 181 /**
bogdanm 85:024bf7f99721 182 * @}
bogdanm 85:024bf7f99721 183 */
bogdanm 85:024bf7f99721 184
bogdanm 85:024bf7f99721 185 /** @defgroup TIMEx_Master_Mode_Selection
bogdanm 85:024bf7f99721 186 * @{
bogdanm 85:024bf7f99721 187 */
bogdanm 85:024bf7f99721 188 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 189 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 85:024bf7f99721 190 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 85:024bf7f99721 191 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 192 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 85:024bf7f99721 193 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 194 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 85:024bf7f99721 195 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 85:024bf7f99721 196
bogdanm 85:024bf7f99721 197 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 85:024bf7f99721 198 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 85:024bf7f99721 199 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 85:024bf7f99721 200 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 85:024bf7f99721 201 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 85:024bf7f99721 202 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 85:024bf7f99721 203 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 85:024bf7f99721 204 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 85:024bf7f99721 205
bogdanm 85:024bf7f99721 206
bogdanm 85:024bf7f99721 207 /**
bogdanm 85:024bf7f99721 208 * @}
bogdanm 85:024bf7f99721 209 */
bogdanm 85:024bf7f99721 210
bogdanm 85:024bf7f99721 211 /** @defgroup TIMEx_Master_Slave_Mode
bogdanm 85:024bf7f99721 212 * @{
bogdanm 85:024bf7f99721 213 */
bogdanm 85:024bf7f99721 214
bogdanm 85:024bf7f99721 215 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 85:024bf7f99721 216 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 217 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
bogdanm 85:024bf7f99721 218 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm 85:024bf7f99721 219 /**
bogdanm 85:024bf7f99721 220 * @}
bogdanm 85:024bf7f99721 221 */
bogdanm 85:024bf7f99721 222
bogdanm 85:024bf7f99721 223 /** @defgroup TIMEx_Commutation_Mode
bogdanm 85:024bf7f99721 224 * @{
bogdanm 85:024bf7f99721 225 */
bogdanm 85:024bf7f99721 226 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 85:024bf7f99721 227 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm 85:024bf7f99721 228 /**
bogdanm 85:024bf7f99721 229 * @}
bogdanm 85:024bf7f99721 230 */
bogdanm 85:024bf7f99721 231
emilmont 77:869cf507173a 232 /** @defgroup TIMEx_Remap
emilmont 77:869cf507173a 233 * @{
emilmont 77:869cf507173a 234 */
emilmont 77:869cf507173a 235
emilmont 77:869cf507173a 236 #define TIM_TIM2_TIM8_TRGO (0x00000000)
emilmont 77:869cf507173a 237 #define TIM_TIM2_ETH_PTP (0x00000400)
emilmont 77:869cf507173a 238 #define TIM_TIM2_USBFS_SOF (0x00000800)
emilmont 77:869cf507173a 239 #define TIM_TIM2_USBHS_SOF (0x00000C00)
emilmont 77:869cf507173a 240 #define TIM_TIM5_GPIO (0x00000000)
emilmont 77:869cf507173a 241 #define TIM_TIM5_LSI (0x00000040)
emilmont 77:869cf507173a 242 #define TIM_TIM5_LSE (0x00000080)
emilmont 77:869cf507173a 243 #define TIM_TIM5_RTC (0x000000C0)
emilmont 77:869cf507173a 244 #define TIM_TIM11_GPIO (0x00000000)
emilmont 77:869cf507173a 245 #define TIM_TIM11_HSE (0x00000002)
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
emilmont 77:869cf507173a 248 ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
emilmont 77:869cf507173a 249 ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
emilmont 77:869cf507173a 250 ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
emilmont 77:869cf507173a 251 ((TIM_REMAP) == TIM_TIM5_GPIO)||\
emilmont 77:869cf507173a 252 ((TIM_REMAP) == TIM_TIM5_LSI)||\
emilmont 77:869cf507173a 253 ((TIM_REMAP) == TIM_TIM5_LSE)||\
emilmont 77:869cf507173a 254 ((TIM_REMAP) == TIM_TIM5_RTC)||\
emilmont 77:869cf507173a 255 ((TIM_REMAP) == TIM_TIM11_GPIO)||\
emilmont 77:869cf507173a 256 ((TIM_REMAP) == TIM_TIM11_HSE))
emilmont 77:869cf507173a 257
emilmont 77:869cf507173a 258 /**
emilmont 77:869cf507173a 259 * @}
emilmont 77:869cf507173a 260 */
emilmont 77:869cf507173a 261
emilmont 77:869cf507173a 262 /**
emilmont 77:869cf507173a 263 * @}
emilmont 77:869cf507173a 264 */
emilmont 77:869cf507173a 265
emilmont 77:869cf507173a 266 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 267
emilmont 77:869cf507173a 268 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 269
emilmont 77:869cf507173a 270 /* Timer Hall Sensor functions **********************************************/
emilmont 77:869cf507173a 271 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
emilmont 77:869cf507173a 272 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 273
emilmont 77:869cf507173a 274 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 275 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 276
emilmont 77:869cf507173a 277 /* Blocking mode: Polling */
emilmont 77:869cf507173a 278 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 279 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 280 /* Non-Blocking mode: Interrupt */
emilmont 77:869cf507173a 281 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 282 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 283 /* Non-Blocking mode: DMA */
emilmont 77:869cf507173a 284 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
emilmont 77:869cf507173a 285 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 286
emilmont 77:869cf507173a 287 /* Timer Complementary Output Compare functions *****************************/
emilmont 77:869cf507173a 288 /* Blocking mode: Polling */
emilmont 77:869cf507173a 289 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 290 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 291
emilmont 77:869cf507173a 292 /* Non-Blocking mode: Interrupt */
emilmont 77:869cf507173a 293 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 294 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 /* Non-Blocking mode: DMA */
emilmont 77:869cf507173a 297 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
emilmont 77:869cf507173a 298 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 299
emilmont 77:869cf507173a 300 /* Timer Complementary PWM functions ****************************************/
emilmont 77:869cf507173a 301 /* Blocking mode: Polling */
emilmont 77:869cf507173a 302 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 303 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 304
emilmont 77:869cf507173a 305 /* Non-Blocking mode: Interrupt */
emilmont 77:869cf507173a 306 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 307 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 308 /* Non-Blocking mode: DMA */
emilmont 77:869cf507173a 309 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
emilmont 77:869cf507173a 310 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
emilmont 77:869cf507173a 311
emilmont 77:869cf507173a 312 /* Timer Complementary One Pulse functions **********************************/
emilmont 77:869cf507173a 313 /* Blocking mode: Polling */
emilmont 77:869cf507173a 314 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
emilmont 77:869cf507173a 315 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
emilmont 77:869cf507173a 316
emilmont 77:869cf507173a 317 /* Non-Blocking mode: Interrupt */
emilmont 77:869cf507173a 318 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
emilmont 77:869cf507173a 319 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
emilmont 77:869cf507173a 320
emilmont 77:869cf507173a 321 /* Extnsion Control functions ************************************************/
emilmont 77:869cf507173a 322 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
emilmont 77:869cf507173a 323 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
emilmont 77:869cf507173a 324 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
emilmont 77:869cf507173a 325 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
emilmont 77:869cf507173a 326 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
emilmont 77:869cf507173a 327 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
emilmont 77:869cf507173a 328
emilmont 77:869cf507173a 329 /* Extension Callback *********************************************************/
bogdanm 81:7d30d6019079 330 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
bogdanm 81:7d30d6019079 331 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 332 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334 /* Extension Peripheral State functions **************************************/
emilmont 77:869cf507173a 335 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
emilmont 77:869cf507173a 336
emilmont 77:869cf507173a 337 /**
emilmont 77:869cf507173a 338 * @}
emilmont 77:869cf507173a 339 */
emilmont 77:869cf507173a 340
emilmont 77:869cf507173a 341 /**
emilmont 77:869cf507173a 342 * @}
emilmont 77:869cf507173a 343 */
emilmont 77:869cf507173a 344
emilmont 77:869cf507173a 345 #ifdef __cplusplus
emilmont 77:869cf507173a 346 }
emilmont 77:869cf507173a 347 #endif
emilmont 77:869cf507173a 348
emilmont 77:869cf507173a 349 #endif /* __STM32F4xx_HAL_TIM_EX_H */
emilmont 77:869cf507173a 350
emilmont 77:869cf507173a 351 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/