不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cm0.h@4:c1beacfc42c7, 2016-10-02 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Oct 02 10:51:10 2016 +0000
Revision:
4:c1beacfc42c7
5

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_cm0.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V4.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 18. March 2015
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #if defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 4:c1beacfc42c7 40 #endif
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 #ifndef __CORE_CM0_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 43 #define __CORE_CM0_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 44
MikamiUitOpen 4:c1beacfc42c7 45 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 46 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 47 #endif
MikamiUitOpen 4:c1beacfc42c7 48
MikamiUitOpen 4:c1beacfc42c7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 4:c1beacfc42c7 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 4:c1beacfc42c7 51
MikamiUitOpen 4:c1beacfc42c7 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 4:c1beacfc42c7 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 4:c1beacfc42c7 56 Unions are used for effective representation of core registers.
MikamiUitOpen 4:c1beacfc42c7 57
MikamiUitOpen 4:c1beacfc42c7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 4:c1beacfc42c7 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 4:c1beacfc42c7 60 */
MikamiUitOpen 4:c1beacfc42c7 61
MikamiUitOpen 4:c1beacfc42c7 62
MikamiUitOpen 4:c1beacfc42c7 63 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 64 * CMSIS definitions
MikamiUitOpen 4:c1beacfc42c7 65 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 66 /** \ingroup Cortex_M0
MikamiUitOpen 4:c1beacfc42c7 67 @{
MikamiUitOpen 4:c1beacfc42c7 68 */
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70 /* CMSIS CM0 definitions */
MikamiUitOpen 4:c1beacfc42c7 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 4:c1beacfc42c7 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 4:c1beacfc42c7 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 4:c1beacfc42c7 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 4:c1beacfc42c7 75
MikamiUitOpen 4:c1beacfc42c7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
MikamiUitOpen 4:c1beacfc42c7 77
MikamiUitOpen 4:c1beacfc42c7 78
MikamiUitOpen 4:c1beacfc42c7 79 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 4:c1beacfc42c7 83
MikamiUitOpen 4:c1beacfc42c7 84 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 87 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 88
MikamiUitOpen 4:c1beacfc42c7 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 4:c1beacfc42c7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 4:c1beacfc42c7 92 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 93
MikamiUitOpen 4:c1beacfc42c7 94 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 4:c1beacfc42c7 96 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 97
MikamiUitOpen 4:c1beacfc42c7 98 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 101 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 102
MikamiUitOpen 4:c1beacfc42c7 103 #elif defined ( __CSMC__ )
MikamiUitOpen 4:c1beacfc42c7 104 #define __packed
MikamiUitOpen 4:c1beacfc42c7 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 4:c1beacfc42c7 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 4:c1beacfc42c7 107 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 108
MikamiUitOpen 4:c1beacfc42c7 109 #endif
MikamiUitOpen 4:c1beacfc42c7 110
MikamiUitOpen 4:c1beacfc42c7 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 4:c1beacfc42c7 112 This core does not support an FPU at all
MikamiUitOpen 4:c1beacfc42c7 113 */
MikamiUitOpen 4:c1beacfc42c7 114 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 115
MikamiUitOpen 4:c1beacfc42c7 116 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 4:c1beacfc42c7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 119 #endif
MikamiUitOpen 4:c1beacfc42c7 120
MikamiUitOpen 4:c1beacfc42c7 121 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 4:c1beacfc42c7 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 124 #endif
MikamiUitOpen 4:c1beacfc42c7 125
MikamiUitOpen 4:c1beacfc42c7 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 127 #if defined __ARMVFP__
MikamiUitOpen 4:c1beacfc42c7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 129 #endif
MikamiUitOpen 4:c1beacfc42c7 130
MikamiUitOpen 4:c1beacfc42c7 131 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 4:c1beacfc42c7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 134 #endif
MikamiUitOpen 4:c1beacfc42c7 135
MikamiUitOpen 4:c1beacfc42c7 136 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 137 #if defined __FPU_VFP__
MikamiUitOpen 4:c1beacfc42c7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 139 #endif
MikamiUitOpen 4:c1beacfc42c7 140
MikamiUitOpen 4:c1beacfc42c7 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 4:c1beacfc42c7 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 4:c1beacfc42c7 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 144 #endif
MikamiUitOpen 4:c1beacfc42c7 145 #endif
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 4:c1beacfc42c7 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 4:c1beacfc42c7 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 4:c1beacfc42c7 150
MikamiUitOpen 4:c1beacfc42c7 151 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 152 }
MikamiUitOpen 4:c1beacfc42c7 153 #endif
MikamiUitOpen 4:c1beacfc42c7 154
MikamiUitOpen 4:c1beacfc42c7 155 #endif /* __CORE_CM0_H_GENERIC */
MikamiUitOpen 4:c1beacfc42c7 156
MikamiUitOpen 4:c1beacfc42c7 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 4:c1beacfc42c7 158
MikamiUitOpen 4:c1beacfc42c7 159 #ifndef __CORE_CM0_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 160 #define __CORE_CM0_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 163 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 164 #endif
MikamiUitOpen 4:c1beacfc42c7 165
MikamiUitOpen 4:c1beacfc42c7 166 /* check device defines and use defaults */
MikamiUitOpen 4:c1beacfc42c7 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 4:c1beacfc42c7 168 #ifndef __CM0_REV
MikamiUitOpen 4:c1beacfc42c7 169 #define __CM0_REV 0x0000
MikamiUitOpen 4:c1beacfc42c7 170 #warning "__CM0_REV not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 171 #endif
MikamiUitOpen 4:c1beacfc42c7 172
MikamiUitOpen 4:c1beacfc42c7 173 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 4:c1beacfc42c7 174 #define __NVIC_PRIO_BITS 2
MikamiUitOpen 4:c1beacfc42c7 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 176 #endif
MikamiUitOpen 4:c1beacfc42c7 177
MikamiUitOpen 4:c1beacfc42c7 178 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 4:c1beacfc42c7 179 #define __Vendor_SysTickConfig 0
MikamiUitOpen 4:c1beacfc42c7 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 181 #endif
MikamiUitOpen 4:c1beacfc42c7 182 #endif
MikamiUitOpen 4:c1beacfc42c7 183
MikamiUitOpen 4:c1beacfc42c7 184 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 4:c1beacfc42c7 185 /**
MikamiUitOpen 4:c1beacfc42c7 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 4:c1beacfc42c7 187
MikamiUitOpen 4:c1beacfc42c7 188 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 4:c1beacfc42c7 189 \li to specify the access to peripheral variables.
MikamiUitOpen 4:c1beacfc42c7 190 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 4:c1beacfc42c7 191 */
MikamiUitOpen 4:c1beacfc42c7 192 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 193 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 194 #else
MikamiUitOpen 4:c1beacfc42c7 195 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 196 #endif
MikamiUitOpen 4:c1beacfc42c7 197 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 4:c1beacfc42c7 198 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 4:c1beacfc42c7 199
MikamiUitOpen 4:c1beacfc42c7 200 /*@} end of group Cortex_M0 */
MikamiUitOpen 4:c1beacfc42c7 201
MikamiUitOpen 4:c1beacfc42c7 202
MikamiUitOpen 4:c1beacfc42c7 203
MikamiUitOpen 4:c1beacfc42c7 204 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 205 * Register Abstraction
MikamiUitOpen 4:c1beacfc42c7 206 Core Register contain:
MikamiUitOpen 4:c1beacfc42c7 207 - Core Register
MikamiUitOpen 4:c1beacfc42c7 208 - Core NVIC Register
MikamiUitOpen 4:c1beacfc42c7 209 - Core SCB Register
MikamiUitOpen 4:c1beacfc42c7 210 - Core SysTick Register
MikamiUitOpen 4:c1beacfc42c7 211 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 4:c1beacfc42c7 213 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 4:c1beacfc42c7 214 */
MikamiUitOpen 4:c1beacfc42c7 215
MikamiUitOpen 4:c1beacfc42c7 216 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 217 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 4:c1beacfc42c7 218 \brief Core Register type definitions.
MikamiUitOpen 4:c1beacfc42c7 219 @{
MikamiUitOpen 4:c1beacfc42c7 220 */
MikamiUitOpen 4:c1beacfc42c7 221
MikamiUitOpen 4:c1beacfc42c7 222 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 4:c1beacfc42c7 223 */
MikamiUitOpen 4:c1beacfc42c7 224 typedef union
MikamiUitOpen 4:c1beacfc42c7 225 {
MikamiUitOpen 4:c1beacfc42c7 226 struct
MikamiUitOpen 4:c1beacfc42c7 227 {
MikamiUitOpen 4:c1beacfc42c7 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
MikamiUitOpen 4:c1beacfc42c7 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 4:c1beacfc42c7 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 4:c1beacfc42c7 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 4:c1beacfc42c7 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 4:c1beacfc42c7 233 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 234 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 235 } APSR_Type;
MikamiUitOpen 4:c1beacfc42c7 236
MikamiUitOpen 4:c1beacfc42c7 237 /* APSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 4:c1beacfc42c7 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 4:c1beacfc42c7 240
MikamiUitOpen 4:c1beacfc42c7 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 4:c1beacfc42c7 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 4:c1beacfc42c7 243
MikamiUitOpen 4:c1beacfc42c7 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 4:c1beacfc42c7 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 4:c1beacfc42c7 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 4:c1beacfc42c7 249
MikamiUitOpen 4:c1beacfc42c7 250
MikamiUitOpen 4:c1beacfc42c7 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 4:c1beacfc42c7 252 */
MikamiUitOpen 4:c1beacfc42c7 253 typedef union
MikamiUitOpen 4:c1beacfc42c7 254 {
MikamiUitOpen 4:c1beacfc42c7 255 struct
MikamiUitOpen 4:c1beacfc42c7 256 {
MikamiUitOpen 4:c1beacfc42c7 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 4:c1beacfc42c7 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 4:c1beacfc42c7 259 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 260 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 261 } IPSR_Type;
MikamiUitOpen 4:c1beacfc42c7 262
MikamiUitOpen 4:c1beacfc42c7 263 /* IPSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 4:c1beacfc42c7 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 4:c1beacfc42c7 266
MikamiUitOpen 4:c1beacfc42c7 267
MikamiUitOpen 4:c1beacfc42c7 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 4:c1beacfc42c7 269 */
MikamiUitOpen 4:c1beacfc42c7 270 typedef union
MikamiUitOpen 4:c1beacfc42c7 271 {
MikamiUitOpen 4:c1beacfc42c7 272 struct
MikamiUitOpen 4:c1beacfc42c7 273 {
MikamiUitOpen 4:c1beacfc42c7 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 4:c1beacfc42c7 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 4:c1beacfc42c7 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 4:c1beacfc42c7 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
MikamiUitOpen 4:c1beacfc42c7 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 4:c1beacfc42c7 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 4:c1beacfc42c7 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 4:c1beacfc42c7 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 4:c1beacfc42c7 282 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 283 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 284 } xPSR_Type;
MikamiUitOpen 4:c1beacfc42c7 285
MikamiUitOpen 4:c1beacfc42c7 286 /* xPSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 4:c1beacfc42c7 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 4:c1beacfc42c7 289
MikamiUitOpen 4:c1beacfc42c7 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 4:c1beacfc42c7 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 4:c1beacfc42c7 292
MikamiUitOpen 4:c1beacfc42c7 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 4:c1beacfc42c7 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 4:c1beacfc42c7 295
MikamiUitOpen 4:c1beacfc42c7 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 4:c1beacfc42c7 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 4:c1beacfc42c7 298
MikamiUitOpen 4:c1beacfc42c7 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 4:c1beacfc42c7 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 4:c1beacfc42c7 301
MikamiUitOpen 4:c1beacfc42c7 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 4:c1beacfc42c7 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 4:c1beacfc42c7 304
MikamiUitOpen 4:c1beacfc42c7 305
MikamiUitOpen 4:c1beacfc42c7 306 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 4:c1beacfc42c7 307 */
MikamiUitOpen 4:c1beacfc42c7 308 typedef union
MikamiUitOpen 4:c1beacfc42c7 309 {
MikamiUitOpen 4:c1beacfc42c7 310 struct
MikamiUitOpen 4:c1beacfc42c7 311 {
MikamiUitOpen 4:c1beacfc42c7 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
MikamiUitOpen 4:c1beacfc42c7 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 4:c1beacfc42c7 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 4:c1beacfc42c7 315 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 316 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 317 } CONTROL_Type;
MikamiUitOpen 4:c1beacfc42c7 318
MikamiUitOpen 4:c1beacfc42c7 319 /* CONTROL Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 4:c1beacfc42c7 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 4:c1beacfc42c7 322
MikamiUitOpen 4:c1beacfc42c7 323 /*@} end of group CMSIS_CORE */
MikamiUitOpen 4:c1beacfc42c7 324
MikamiUitOpen 4:c1beacfc42c7 325
MikamiUitOpen 4:c1beacfc42c7 326 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 4:c1beacfc42c7 328 \brief Type definitions for the NVIC Registers
MikamiUitOpen 4:c1beacfc42c7 329 @{
MikamiUitOpen 4:c1beacfc42c7 330 */
MikamiUitOpen 4:c1beacfc42c7 331
MikamiUitOpen 4:c1beacfc42c7 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 4:c1beacfc42c7 333 */
MikamiUitOpen 4:c1beacfc42c7 334 typedef struct
MikamiUitOpen 4:c1beacfc42c7 335 {
MikamiUitOpen 4:c1beacfc42c7 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 4:c1beacfc42c7 337 uint32_t RESERVED0[31];
MikamiUitOpen 4:c1beacfc42c7 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 4:c1beacfc42c7 339 uint32_t RSERVED1[31];
MikamiUitOpen 4:c1beacfc42c7 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 4:c1beacfc42c7 341 uint32_t RESERVED2[31];
MikamiUitOpen 4:c1beacfc42c7 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 4:c1beacfc42c7 343 uint32_t RESERVED3[31];
MikamiUitOpen 4:c1beacfc42c7 344 uint32_t RESERVED4[64];
MikamiUitOpen 4:c1beacfc42c7 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
MikamiUitOpen 4:c1beacfc42c7 346 } NVIC_Type;
MikamiUitOpen 4:c1beacfc42c7 347
MikamiUitOpen 4:c1beacfc42c7 348 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 4:c1beacfc42c7 349
MikamiUitOpen 4:c1beacfc42c7 350
MikamiUitOpen 4:c1beacfc42c7 351 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 352 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 4:c1beacfc42c7 353 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 4:c1beacfc42c7 354 @{
MikamiUitOpen 4:c1beacfc42c7 355 */
MikamiUitOpen 4:c1beacfc42c7 356
MikamiUitOpen 4:c1beacfc42c7 357 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 4:c1beacfc42c7 358 */
MikamiUitOpen 4:c1beacfc42c7 359 typedef struct
MikamiUitOpen 4:c1beacfc42c7 360 {
MikamiUitOpen 4:c1beacfc42c7 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 4:c1beacfc42c7 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 4:c1beacfc42c7 363 uint32_t RESERVED0;
MikamiUitOpen 4:c1beacfc42c7 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 4:c1beacfc42c7 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 4:c1beacfc42c7 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 4:c1beacfc42c7 367 uint32_t RESERVED1;
MikamiUitOpen 4:c1beacfc42c7 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
MikamiUitOpen 4:c1beacfc42c7 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 4:c1beacfc42c7 370 } SCB_Type;
MikamiUitOpen 4:c1beacfc42c7 371
MikamiUitOpen 4:c1beacfc42c7 372 /* SCB CPUID Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 4:c1beacfc42c7 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 4:c1beacfc42c7 375
MikamiUitOpen 4:c1beacfc42c7 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 4:c1beacfc42c7 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 4:c1beacfc42c7 378
MikamiUitOpen 4:c1beacfc42c7 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 4:c1beacfc42c7 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 4:c1beacfc42c7 381
MikamiUitOpen 4:c1beacfc42c7 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 4:c1beacfc42c7 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 4:c1beacfc42c7 384
MikamiUitOpen 4:c1beacfc42c7 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 4:c1beacfc42c7 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 4:c1beacfc42c7 387
MikamiUitOpen 4:c1beacfc42c7 388 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 4:c1beacfc42c7 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 4:c1beacfc42c7 391
MikamiUitOpen 4:c1beacfc42c7 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 4:c1beacfc42c7 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 4:c1beacfc42c7 394
MikamiUitOpen 4:c1beacfc42c7 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 4:c1beacfc42c7 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 4:c1beacfc42c7 397
MikamiUitOpen 4:c1beacfc42c7 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 4:c1beacfc42c7 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 4:c1beacfc42c7 400
MikamiUitOpen 4:c1beacfc42c7 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 4:c1beacfc42c7 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 4:c1beacfc42c7 403
MikamiUitOpen 4:c1beacfc42c7 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 4:c1beacfc42c7 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 4:c1beacfc42c7 406
MikamiUitOpen 4:c1beacfc42c7 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 4:c1beacfc42c7 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 4:c1beacfc42c7 409
MikamiUitOpen 4:c1beacfc42c7 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 4:c1beacfc42c7 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 4:c1beacfc42c7 412
MikamiUitOpen 4:c1beacfc42c7 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 4:c1beacfc42c7 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 4:c1beacfc42c7 415
MikamiUitOpen 4:c1beacfc42c7 416 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 4:c1beacfc42c7 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 4:c1beacfc42c7 419
MikamiUitOpen 4:c1beacfc42c7 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 4:c1beacfc42c7 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 4:c1beacfc42c7 422
MikamiUitOpen 4:c1beacfc42c7 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 4:c1beacfc42c7 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 4:c1beacfc42c7 425
MikamiUitOpen 4:c1beacfc42c7 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 4:c1beacfc42c7 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 4:c1beacfc42c7 428
MikamiUitOpen 4:c1beacfc42c7 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 4:c1beacfc42c7 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 4:c1beacfc42c7 431
MikamiUitOpen 4:c1beacfc42c7 432 /* SCB System Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 4:c1beacfc42c7 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 4:c1beacfc42c7 435
MikamiUitOpen 4:c1beacfc42c7 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 4:c1beacfc42c7 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 4:c1beacfc42c7 438
MikamiUitOpen 4:c1beacfc42c7 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 4:c1beacfc42c7 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 4:c1beacfc42c7 441
MikamiUitOpen 4:c1beacfc42c7 442 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 4:c1beacfc42c7 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 4:c1beacfc42c7 445
MikamiUitOpen 4:c1beacfc42c7 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 4:c1beacfc42c7 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 4:c1beacfc42c7 448
MikamiUitOpen 4:c1beacfc42c7 449 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 4:c1beacfc42c7 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 4:c1beacfc42c7 452
MikamiUitOpen 4:c1beacfc42c7 453 /*@} end of group CMSIS_SCB */
MikamiUitOpen 4:c1beacfc42c7 454
MikamiUitOpen 4:c1beacfc42c7 455
MikamiUitOpen 4:c1beacfc42c7 456 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 4:c1beacfc42c7 458 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 4:c1beacfc42c7 459 @{
MikamiUitOpen 4:c1beacfc42c7 460 */
MikamiUitOpen 4:c1beacfc42c7 461
MikamiUitOpen 4:c1beacfc42c7 462 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 4:c1beacfc42c7 463 */
MikamiUitOpen 4:c1beacfc42c7 464 typedef struct
MikamiUitOpen 4:c1beacfc42c7 465 {
MikamiUitOpen 4:c1beacfc42c7 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 4:c1beacfc42c7 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 4:c1beacfc42c7 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 4:c1beacfc42c7 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 4:c1beacfc42c7 470 } SysTick_Type;
MikamiUitOpen 4:c1beacfc42c7 471
MikamiUitOpen 4:c1beacfc42c7 472 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 4:c1beacfc42c7 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 4:c1beacfc42c7 475
MikamiUitOpen 4:c1beacfc42c7 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 4:c1beacfc42c7 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 4:c1beacfc42c7 478
MikamiUitOpen 4:c1beacfc42c7 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 4:c1beacfc42c7 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 4:c1beacfc42c7 481
MikamiUitOpen 4:c1beacfc42c7 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 4:c1beacfc42c7 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 4:c1beacfc42c7 484
MikamiUitOpen 4:c1beacfc42c7 485 /* SysTick Reload Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 4:c1beacfc42c7 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 4:c1beacfc42c7 488
MikamiUitOpen 4:c1beacfc42c7 489 /* SysTick Current Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 4:c1beacfc42c7 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 4:c1beacfc42c7 492
MikamiUitOpen 4:c1beacfc42c7 493 /* SysTick Calibration Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 4:c1beacfc42c7 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 4:c1beacfc42c7 496
MikamiUitOpen 4:c1beacfc42c7 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 4:c1beacfc42c7 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 4:c1beacfc42c7 499
MikamiUitOpen 4:c1beacfc42c7 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 4:c1beacfc42c7 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 4:c1beacfc42c7 502
MikamiUitOpen 4:c1beacfc42c7 503 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 4:c1beacfc42c7 504
MikamiUitOpen 4:c1beacfc42c7 505
MikamiUitOpen 4:c1beacfc42c7 506 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 4:c1beacfc42c7 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
MikamiUitOpen 4:c1beacfc42c7 509 are only accessible over DAP and not via processor. Therefore
MikamiUitOpen 4:c1beacfc42c7 510 they are not covered by the Cortex-M0 header file.
MikamiUitOpen 4:c1beacfc42c7 511 @{
MikamiUitOpen 4:c1beacfc42c7 512 */
MikamiUitOpen 4:c1beacfc42c7 513 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 4:c1beacfc42c7 514
MikamiUitOpen 4:c1beacfc42c7 515
MikamiUitOpen 4:c1beacfc42c7 516 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 517 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 4:c1beacfc42c7 518 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 4:c1beacfc42c7 519 @{
MikamiUitOpen 4:c1beacfc42c7 520 */
MikamiUitOpen 4:c1beacfc42c7 521
MikamiUitOpen 4:c1beacfc42c7 522 /* Memory mapping of Cortex-M0 Hardware */
MikamiUitOpen 4:c1beacfc42c7 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 4:c1beacfc42c7 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 4:c1beacfc42c7 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 4:c1beacfc42c7 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 4:c1beacfc42c7 527
MikamiUitOpen 4:c1beacfc42c7 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 4:c1beacfc42c7 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 4:c1beacfc42c7 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 4:c1beacfc42c7 531
MikamiUitOpen 4:c1beacfc42c7 532
MikamiUitOpen 4:c1beacfc42c7 533 /*@} */
MikamiUitOpen 4:c1beacfc42c7 534
MikamiUitOpen 4:c1beacfc42c7 535
MikamiUitOpen 4:c1beacfc42c7 536
MikamiUitOpen 4:c1beacfc42c7 537 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 538 * Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 539 Core Function Interface contains:
MikamiUitOpen 4:c1beacfc42c7 540 - Core NVIC Functions
MikamiUitOpen 4:c1beacfc42c7 541 - Core SysTick Functions
MikamiUitOpen 4:c1beacfc42c7 542 - Core Register Access Functions
MikamiUitOpen 4:c1beacfc42c7 543 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 4:c1beacfc42c7 545 */
MikamiUitOpen 4:c1beacfc42c7 546
MikamiUitOpen 4:c1beacfc42c7 547
MikamiUitOpen 4:c1beacfc42c7 548
MikamiUitOpen 4:c1beacfc42c7 549 /* ########################## NVIC functions #################################### */
MikamiUitOpen 4:c1beacfc42c7 550 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 4:c1beacfc42c7 552 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 4:c1beacfc42c7 553 @{
MikamiUitOpen 4:c1beacfc42c7 554 */
MikamiUitOpen 4:c1beacfc42c7 555
MikamiUitOpen 4:c1beacfc42c7 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
MikamiUitOpen 4:c1beacfc42c7 557 /* The following MACROS handle generation of the register offset and byte masks */
MikamiUitOpen 4:c1beacfc42c7 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
MikamiUitOpen 4:c1beacfc42c7 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
MikamiUitOpen 4:c1beacfc42c7 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
MikamiUitOpen 4:c1beacfc42c7 561
MikamiUitOpen 4:c1beacfc42c7 562
MikamiUitOpen 4:c1beacfc42c7 563 /** \brief Enable External Interrupt
MikamiUitOpen 4:c1beacfc42c7 564
MikamiUitOpen 4:c1beacfc42c7 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 4:c1beacfc42c7 566
MikamiUitOpen 4:c1beacfc42c7 567 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 568 */
MikamiUitOpen 4:c1beacfc42c7 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 570 {
MikamiUitOpen 4:c1beacfc42c7 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 572 }
MikamiUitOpen 4:c1beacfc42c7 573
MikamiUitOpen 4:c1beacfc42c7 574
MikamiUitOpen 4:c1beacfc42c7 575 /** \brief Disable External Interrupt
MikamiUitOpen 4:c1beacfc42c7 576
MikamiUitOpen 4:c1beacfc42c7 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 4:c1beacfc42c7 578
MikamiUitOpen 4:c1beacfc42c7 579 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 580 */
MikamiUitOpen 4:c1beacfc42c7 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 582 {
MikamiUitOpen 4:c1beacfc42c7 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 584 }
MikamiUitOpen 4:c1beacfc42c7 585
MikamiUitOpen 4:c1beacfc42c7 586
MikamiUitOpen 4:c1beacfc42c7 587 /** \brief Get Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 588
MikamiUitOpen 4:c1beacfc42c7 589 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 4:c1beacfc42c7 590 for the specified interrupt.
MikamiUitOpen 4:c1beacfc42c7 591
MikamiUitOpen 4:c1beacfc42c7 592 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 593
MikamiUitOpen 4:c1beacfc42c7 594 \return 0 Interrupt status is not pending.
MikamiUitOpen 4:c1beacfc42c7 595 \return 1 Interrupt status is pending.
MikamiUitOpen 4:c1beacfc42c7 596 */
MikamiUitOpen 4:c1beacfc42c7 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 598 {
MikamiUitOpen 4:c1beacfc42c7 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 4:c1beacfc42c7 600 }
MikamiUitOpen 4:c1beacfc42c7 601
MikamiUitOpen 4:c1beacfc42c7 602
MikamiUitOpen 4:c1beacfc42c7 603 /** \brief Set Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 604
MikamiUitOpen 4:c1beacfc42c7 605 The function sets the pending bit of an external interrupt.
MikamiUitOpen 4:c1beacfc42c7 606
MikamiUitOpen 4:c1beacfc42c7 607 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 608 */
MikamiUitOpen 4:c1beacfc42c7 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 610 {
MikamiUitOpen 4:c1beacfc42c7 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 612 }
MikamiUitOpen 4:c1beacfc42c7 613
MikamiUitOpen 4:c1beacfc42c7 614
MikamiUitOpen 4:c1beacfc42c7 615 /** \brief Clear Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 616
MikamiUitOpen 4:c1beacfc42c7 617 The function clears the pending bit of an external interrupt.
MikamiUitOpen 4:c1beacfc42c7 618
MikamiUitOpen 4:c1beacfc42c7 619 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 620 */
MikamiUitOpen 4:c1beacfc42c7 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 622 {
MikamiUitOpen 4:c1beacfc42c7 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 624 }
MikamiUitOpen 4:c1beacfc42c7 625
MikamiUitOpen 4:c1beacfc42c7 626
MikamiUitOpen 4:c1beacfc42c7 627 /** \brief Set Interrupt Priority
MikamiUitOpen 4:c1beacfc42c7 628
MikamiUitOpen 4:c1beacfc42c7 629 The function sets the priority of an interrupt.
MikamiUitOpen 4:c1beacfc42c7 630
MikamiUitOpen 4:c1beacfc42c7 631 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 4:c1beacfc42c7 632
MikamiUitOpen 4:c1beacfc42c7 633 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 634 \param [in] priority Priority to set.
MikamiUitOpen 4:c1beacfc42c7 635 */
MikamiUitOpen 4:c1beacfc42c7 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 4:c1beacfc42c7 637 {
MikamiUitOpen 4:c1beacfc42c7 638 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 4:c1beacfc42c7 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 4:c1beacfc42c7 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 4:c1beacfc42c7 641 }
MikamiUitOpen 4:c1beacfc42c7 642 else {
MikamiUitOpen 4:c1beacfc42c7 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 4:c1beacfc42c7 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 4:c1beacfc42c7 645 }
MikamiUitOpen 4:c1beacfc42c7 646 }
MikamiUitOpen 4:c1beacfc42c7 647
MikamiUitOpen 4:c1beacfc42c7 648
MikamiUitOpen 4:c1beacfc42c7 649 /** \brief Get Interrupt Priority
MikamiUitOpen 4:c1beacfc42c7 650
MikamiUitOpen 4:c1beacfc42c7 651 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 4:c1beacfc42c7 652 number can be positive to specify an external (device specific)
MikamiUitOpen 4:c1beacfc42c7 653 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 4:c1beacfc42c7 654
MikamiUitOpen 4:c1beacfc42c7 655
MikamiUitOpen 4:c1beacfc42c7 656 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 657 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 4:c1beacfc42c7 658 priority bits of the microcontroller.
MikamiUitOpen 4:c1beacfc42c7 659 */
MikamiUitOpen 4:c1beacfc42c7 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 661 {
MikamiUitOpen 4:c1beacfc42c7 662
MikamiUitOpen 4:c1beacfc42c7 663 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 4:c1beacfc42c7 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 4:c1beacfc42c7 665 }
MikamiUitOpen 4:c1beacfc42c7 666 else {
MikamiUitOpen 4:c1beacfc42c7 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 4:c1beacfc42c7 668 }
MikamiUitOpen 4:c1beacfc42c7 669 }
MikamiUitOpen 4:c1beacfc42c7 670
MikamiUitOpen 4:c1beacfc42c7 671
MikamiUitOpen 4:c1beacfc42c7 672 /** \brief System Reset
MikamiUitOpen 4:c1beacfc42c7 673
MikamiUitOpen 4:c1beacfc42c7 674 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 4:c1beacfc42c7 675 */
MikamiUitOpen 4:c1beacfc42c7 676 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 4:c1beacfc42c7 677 {
MikamiUitOpen 4:c1beacfc42c7 678 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 4:c1beacfc42c7 679 buffered write are completed before reset */
MikamiUitOpen 4:c1beacfc42c7 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 4:c1beacfc42c7 681 SCB_AIRCR_SYSRESETREQ_Msk);
MikamiUitOpen 4:c1beacfc42c7 682 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 4:c1beacfc42c7 683 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 4:c1beacfc42c7 684 }
MikamiUitOpen 4:c1beacfc42c7 685
MikamiUitOpen 4:c1beacfc42c7 686 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 4:c1beacfc42c7 687
MikamiUitOpen 4:c1beacfc42c7 688
MikamiUitOpen 4:c1beacfc42c7 689
MikamiUitOpen 4:c1beacfc42c7 690 /* ################################## SysTick function ############################################ */
MikamiUitOpen 4:c1beacfc42c7 691 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 4:c1beacfc42c7 693 \brief Functions that configure the System.
MikamiUitOpen 4:c1beacfc42c7 694 @{
MikamiUitOpen 4:c1beacfc42c7 695 */
MikamiUitOpen 4:c1beacfc42c7 696
MikamiUitOpen 4:c1beacfc42c7 697 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 4:c1beacfc42c7 698
MikamiUitOpen 4:c1beacfc42c7 699 /** \brief System Tick Configuration
MikamiUitOpen 4:c1beacfc42c7 700
MikamiUitOpen 4:c1beacfc42c7 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 4:c1beacfc42c7 702 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 4:c1beacfc42c7 703
MikamiUitOpen 4:c1beacfc42c7 704 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 4:c1beacfc42c7 705
MikamiUitOpen 4:c1beacfc42c7 706 \return 0 Function succeeded.
MikamiUitOpen 4:c1beacfc42c7 707 \return 1 Function failed.
MikamiUitOpen 4:c1beacfc42c7 708
MikamiUitOpen 4:c1beacfc42c7 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 4:c1beacfc42c7 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 4:c1beacfc42c7 711 must contain a vendor-specific implementation of this function.
MikamiUitOpen 4:c1beacfc42c7 712
MikamiUitOpen 4:c1beacfc42c7 713 */
MikamiUitOpen 4:c1beacfc42c7 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 4:c1beacfc42c7 715 {
MikamiUitOpen 4:c1beacfc42c7 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
MikamiUitOpen 4:c1beacfc42c7 717
MikamiUitOpen 4:c1beacfc42c7 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 4:c1beacfc42c7 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 4:c1beacfc42c7 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 4:c1beacfc42c7 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 4:c1beacfc42c7 722 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 4:c1beacfc42c7 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 4:c1beacfc42c7 724 return (0UL); /* Function successful */
MikamiUitOpen 4:c1beacfc42c7 725 }
MikamiUitOpen 4:c1beacfc42c7 726
MikamiUitOpen 4:c1beacfc42c7 727 #endif
MikamiUitOpen 4:c1beacfc42c7 728
MikamiUitOpen 4:c1beacfc42c7 729 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 4:c1beacfc42c7 730
MikamiUitOpen 4:c1beacfc42c7 731
MikamiUitOpen 4:c1beacfc42c7 732
MikamiUitOpen 4:c1beacfc42c7 733
MikamiUitOpen 4:c1beacfc42c7 734 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 735 }
MikamiUitOpen 4:c1beacfc42c7 736 #endif
MikamiUitOpen 4:c1beacfc42c7 737
MikamiUitOpen 4:c1beacfc42c7 738 #endif /* __CORE_CM0_H_DEPENDANT */
MikamiUitOpen 4:c1beacfc42c7 739
MikamiUitOpen 4:c1beacfc42c7 740 #endif /* __CMSIS_GENERIC */