不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_ca_mmu.h@4:c1beacfc42c7, 2016-10-02 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Oct 02 10:51:10 2016 +0000
Revision:
4:c1beacfc42c7
5

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 ;/**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 ; * @file core_ca_mmu.h
MikamiUitOpen 4:c1beacfc42c7 3 ; * @brief MMU Startup File for A9_MP Device Series
MikamiUitOpen 4:c1beacfc42c7 4 ; * @version V1.01
MikamiUitOpen 4:c1beacfc42c7 5 ; * @date 10 Sept 2014
MikamiUitOpen 4:c1beacfc42c7 6 ; *
MikamiUitOpen 4:c1beacfc42c7 7 ; * @note
MikamiUitOpen 4:c1beacfc42c7 8 ; *
MikamiUitOpen 4:c1beacfc42c7 9 ; ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11 ;
MikamiUitOpen 4:c1beacfc42c7 12 ; All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 ; Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 ; modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 ; - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 ; notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 ; - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 ; notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 ; documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 ; - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 ; to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 ; specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 ; *
MikamiUitOpen 4:c1beacfc42c7 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 ; POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ; ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 38 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 39 #endif
MikamiUitOpen 4:c1beacfc42c7 40
MikamiUitOpen 4:c1beacfc42c7 41 #ifndef _MMU_FUNC_H
MikamiUitOpen 4:c1beacfc42c7 42 #define _MMU_FUNC_H
MikamiUitOpen 4:c1beacfc42c7 43
MikamiUitOpen 4:c1beacfc42c7 44 #define SECTION_DESCRIPTOR (0x2)
MikamiUitOpen 4:c1beacfc42c7 45 #define SECTION_MASK (0xFFFFFFFC)
MikamiUitOpen 4:c1beacfc42c7 46
MikamiUitOpen 4:c1beacfc42c7 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 4:c1beacfc42c7 48 #define SECTION_B_SHIFT (2)
MikamiUitOpen 4:c1beacfc42c7 49 #define SECTION_C_SHIFT (3)
MikamiUitOpen 4:c1beacfc42c7 50 #define SECTION_TEX0_SHIFT (12)
MikamiUitOpen 4:c1beacfc42c7 51 #define SECTION_TEX1_SHIFT (13)
MikamiUitOpen 4:c1beacfc42c7 52 #define SECTION_TEX2_SHIFT (14)
MikamiUitOpen 4:c1beacfc42c7 53
MikamiUitOpen 4:c1beacfc42c7 54 #define SECTION_XN_MASK (0xFFFFFFEF)
MikamiUitOpen 4:c1beacfc42c7 55 #define SECTION_XN_SHIFT (4)
MikamiUitOpen 4:c1beacfc42c7 56
MikamiUitOpen 4:c1beacfc42c7 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
MikamiUitOpen 4:c1beacfc42c7 58 #define SECTION_DOMAIN_SHIFT (5)
MikamiUitOpen 4:c1beacfc42c7 59
MikamiUitOpen 4:c1beacfc42c7 60 #define SECTION_P_MASK (0xFFFFFDFF)
MikamiUitOpen 4:c1beacfc42c7 61 #define SECTION_P_SHIFT (9)
MikamiUitOpen 4:c1beacfc42c7 62
MikamiUitOpen 4:c1beacfc42c7 63 #define SECTION_AP_MASK (0xFFFF73FF)
MikamiUitOpen 4:c1beacfc42c7 64 #define SECTION_AP_SHIFT (10)
MikamiUitOpen 4:c1beacfc42c7 65 #define SECTION_AP2_SHIFT (15)
MikamiUitOpen 4:c1beacfc42c7 66
MikamiUitOpen 4:c1beacfc42c7 67 #define SECTION_S_MASK (0xFFFEFFFF)
MikamiUitOpen 4:c1beacfc42c7 68 #define SECTION_S_SHIFT (16)
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70 #define SECTION_NG_MASK (0xFFFDFFFF)
MikamiUitOpen 4:c1beacfc42c7 71 #define SECTION_NG_SHIFT (17)
MikamiUitOpen 4:c1beacfc42c7 72
MikamiUitOpen 4:c1beacfc42c7 73 #define SECTION_NS_MASK (0xFFF7FFFF)
MikamiUitOpen 4:c1beacfc42c7 74 #define SECTION_NS_SHIFT (19)
MikamiUitOpen 4:c1beacfc42c7 75
MikamiUitOpen 4:c1beacfc42c7 76
MikamiUitOpen 4:c1beacfc42c7 77 #define PAGE_L1_DESCRIPTOR (0x1)
MikamiUitOpen 4:c1beacfc42c7 78 #define PAGE_L1_MASK (0xFFFFFFFC)
MikamiUitOpen 4:c1beacfc42c7 79
MikamiUitOpen 4:c1beacfc42c7 80 #define PAGE_L2_4K_DESC (0x2)
MikamiUitOpen 4:c1beacfc42c7 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
MikamiUitOpen 4:c1beacfc42c7 82
MikamiUitOpen 4:c1beacfc42c7 83 #define PAGE_L2_64K_DESC (0x1)
MikamiUitOpen 4:c1beacfc42c7 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
MikamiUitOpen 4:c1beacfc42c7 85
MikamiUitOpen 4:c1beacfc42c7 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
MikamiUitOpen 4:c1beacfc42c7 87 #define PAGE_4K_B_SHIFT (2)
MikamiUitOpen 4:c1beacfc42c7 88 #define PAGE_4K_C_SHIFT (3)
MikamiUitOpen 4:c1beacfc42c7 89 #define PAGE_4K_TEX0_SHIFT (6)
MikamiUitOpen 4:c1beacfc42c7 90 #define PAGE_4K_TEX1_SHIFT (7)
MikamiUitOpen 4:c1beacfc42c7 91 #define PAGE_4K_TEX2_SHIFT (8)
MikamiUitOpen 4:c1beacfc42c7 92
MikamiUitOpen 4:c1beacfc42c7 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 4:c1beacfc42c7 94 #define PAGE_64K_B_SHIFT (2)
MikamiUitOpen 4:c1beacfc42c7 95 #define PAGE_64K_C_SHIFT (3)
MikamiUitOpen 4:c1beacfc42c7 96 #define PAGE_64K_TEX0_SHIFT (12)
MikamiUitOpen 4:c1beacfc42c7 97 #define PAGE_64K_TEX1_SHIFT (13)
MikamiUitOpen 4:c1beacfc42c7 98 #define PAGE_64K_TEX2_SHIFT (14)
MikamiUitOpen 4:c1beacfc42c7 99
MikamiUitOpen 4:c1beacfc42c7 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 4:c1beacfc42c7 101 #define PAGE_B_SHIFT (2)
MikamiUitOpen 4:c1beacfc42c7 102 #define PAGE_C_SHIFT (3)
MikamiUitOpen 4:c1beacfc42c7 103 #define PAGE_TEX_SHIFT (12)
MikamiUitOpen 4:c1beacfc42c7 104
MikamiUitOpen 4:c1beacfc42c7 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
MikamiUitOpen 4:c1beacfc42c7 106 #define PAGE_XN_4K_SHIFT (0)
MikamiUitOpen 4:c1beacfc42c7 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
MikamiUitOpen 4:c1beacfc42c7 108 #define PAGE_XN_64K_SHIFT (15)
MikamiUitOpen 4:c1beacfc42c7 109
MikamiUitOpen 4:c1beacfc42c7 110
MikamiUitOpen 4:c1beacfc42c7 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
MikamiUitOpen 4:c1beacfc42c7 112 #define PAGE_DOMAIN_SHIFT (5)
MikamiUitOpen 4:c1beacfc42c7 113
MikamiUitOpen 4:c1beacfc42c7 114 #define PAGE_P_MASK (0xFFFFFDFF)
MikamiUitOpen 4:c1beacfc42c7 115 #define PAGE_P_SHIFT (9)
MikamiUitOpen 4:c1beacfc42c7 116
MikamiUitOpen 4:c1beacfc42c7 117 #define PAGE_AP_MASK (0xFFFFFDCF)
MikamiUitOpen 4:c1beacfc42c7 118 #define PAGE_AP_SHIFT (4)
MikamiUitOpen 4:c1beacfc42c7 119 #define PAGE_AP2_SHIFT (9)
MikamiUitOpen 4:c1beacfc42c7 120
MikamiUitOpen 4:c1beacfc42c7 121 #define PAGE_S_MASK (0xFFFFFBFF)
MikamiUitOpen 4:c1beacfc42c7 122 #define PAGE_S_SHIFT (10)
MikamiUitOpen 4:c1beacfc42c7 123
MikamiUitOpen 4:c1beacfc42c7 124 #define PAGE_NG_MASK (0xFFFFF7FF)
MikamiUitOpen 4:c1beacfc42c7 125 #define PAGE_NG_SHIFT (11)
MikamiUitOpen 4:c1beacfc42c7 126
MikamiUitOpen 4:c1beacfc42c7 127 #define PAGE_NS_MASK (0xFFFFFFF7)
MikamiUitOpen 4:c1beacfc42c7 128 #define PAGE_NS_SHIFT (3)
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 #define OFFSET_1M (0x00100000)
MikamiUitOpen 4:c1beacfc42c7 131 #define OFFSET_64K (0x00010000)
MikamiUitOpen 4:c1beacfc42c7 132 #define OFFSET_4K (0x00001000)
MikamiUitOpen 4:c1beacfc42c7 133
MikamiUitOpen 4:c1beacfc42c7 134 #define DESCRIPTOR_FAULT (0x00000000)
MikamiUitOpen 4:c1beacfc42c7 135
MikamiUitOpen 4:c1beacfc42c7 136 /* ########################### MMU Function Access ########################### */
MikamiUitOpen 4:c1beacfc42c7 137 /** \ingroup MMU_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 138 \defgroup MMU_Functions MMU Functions Interface
MikamiUitOpen 4:c1beacfc42c7 139 @{
MikamiUitOpen 4:c1beacfc42c7 140 */
MikamiUitOpen 4:c1beacfc42c7 141
MikamiUitOpen 4:c1beacfc42c7 142 /* Attributes enumerations */
MikamiUitOpen 4:c1beacfc42c7 143
MikamiUitOpen 4:c1beacfc42c7 144 /* Region size attributes */
MikamiUitOpen 4:c1beacfc42c7 145 typedef enum
MikamiUitOpen 4:c1beacfc42c7 146 {
MikamiUitOpen 4:c1beacfc42c7 147 SECTION,
MikamiUitOpen 4:c1beacfc42c7 148 PAGE_4k,
MikamiUitOpen 4:c1beacfc42c7 149 PAGE_64k,
MikamiUitOpen 4:c1beacfc42c7 150 } mmu_region_size_Type;
MikamiUitOpen 4:c1beacfc42c7 151
MikamiUitOpen 4:c1beacfc42c7 152 /* Region type attributes */
MikamiUitOpen 4:c1beacfc42c7 153 typedef enum
MikamiUitOpen 4:c1beacfc42c7 154 {
MikamiUitOpen 4:c1beacfc42c7 155 NORMAL,
MikamiUitOpen 4:c1beacfc42c7 156 DEVICE,
MikamiUitOpen 4:c1beacfc42c7 157 SHARED_DEVICE,
MikamiUitOpen 4:c1beacfc42c7 158 NON_SHARED_DEVICE,
MikamiUitOpen 4:c1beacfc42c7 159 STRONGLY_ORDERED
MikamiUitOpen 4:c1beacfc42c7 160 } mmu_memory_Type;
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 /* Region cacheability attributes */
MikamiUitOpen 4:c1beacfc42c7 163 typedef enum
MikamiUitOpen 4:c1beacfc42c7 164 {
MikamiUitOpen 4:c1beacfc42c7 165 NON_CACHEABLE,
MikamiUitOpen 4:c1beacfc42c7 166 WB_WA,
MikamiUitOpen 4:c1beacfc42c7 167 WT,
MikamiUitOpen 4:c1beacfc42c7 168 WB_NO_WA,
MikamiUitOpen 4:c1beacfc42c7 169 } mmu_cacheability_Type;
MikamiUitOpen 4:c1beacfc42c7 170
MikamiUitOpen 4:c1beacfc42c7 171 /* Region parity check attributes */
MikamiUitOpen 4:c1beacfc42c7 172 typedef enum
MikamiUitOpen 4:c1beacfc42c7 173 {
MikamiUitOpen 4:c1beacfc42c7 174 ECC_DISABLED,
MikamiUitOpen 4:c1beacfc42c7 175 ECC_ENABLED,
MikamiUitOpen 4:c1beacfc42c7 176 } mmu_ecc_check_Type;
MikamiUitOpen 4:c1beacfc42c7 177
MikamiUitOpen 4:c1beacfc42c7 178 /* Region execution attributes */
MikamiUitOpen 4:c1beacfc42c7 179 typedef enum
MikamiUitOpen 4:c1beacfc42c7 180 {
MikamiUitOpen 4:c1beacfc42c7 181 EXECUTE,
MikamiUitOpen 4:c1beacfc42c7 182 NON_EXECUTE,
MikamiUitOpen 4:c1beacfc42c7 183 } mmu_execute_Type;
MikamiUitOpen 4:c1beacfc42c7 184
MikamiUitOpen 4:c1beacfc42c7 185 /* Region global attributes */
MikamiUitOpen 4:c1beacfc42c7 186 typedef enum
MikamiUitOpen 4:c1beacfc42c7 187 {
MikamiUitOpen 4:c1beacfc42c7 188 GLOBAL,
MikamiUitOpen 4:c1beacfc42c7 189 NON_GLOBAL,
MikamiUitOpen 4:c1beacfc42c7 190 } mmu_global_Type;
MikamiUitOpen 4:c1beacfc42c7 191
MikamiUitOpen 4:c1beacfc42c7 192 /* Region shareability attributes */
MikamiUitOpen 4:c1beacfc42c7 193 typedef enum
MikamiUitOpen 4:c1beacfc42c7 194 {
MikamiUitOpen 4:c1beacfc42c7 195 NON_SHARED,
MikamiUitOpen 4:c1beacfc42c7 196 SHARED,
MikamiUitOpen 4:c1beacfc42c7 197 } mmu_shared_Type;
MikamiUitOpen 4:c1beacfc42c7 198
MikamiUitOpen 4:c1beacfc42c7 199 /* Region security attributes */
MikamiUitOpen 4:c1beacfc42c7 200 typedef enum
MikamiUitOpen 4:c1beacfc42c7 201 {
MikamiUitOpen 4:c1beacfc42c7 202 SECURE,
MikamiUitOpen 4:c1beacfc42c7 203 NON_SECURE,
MikamiUitOpen 4:c1beacfc42c7 204 } mmu_secure_Type;
MikamiUitOpen 4:c1beacfc42c7 205
MikamiUitOpen 4:c1beacfc42c7 206 /* Region access attributes */
MikamiUitOpen 4:c1beacfc42c7 207 typedef enum
MikamiUitOpen 4:c1beacfc42c7 208 {
MikamiUitOpen 4:c1beacfc42c7 209 NO_ACCESS,
MikamiUitOpen 4:c1beacfc42c7 210 RW,
MikamiUitOpen 4:c1beacfc42c7 211 READ,
MikamiUitOpen 4:c1beacfc42c7 212 } mmu_access_Type;
MikamiUitOpen 4:c1beacfc42c7 213
MikamiUitOpen 4:c1beacfc42c7 214 /* Memory Region definition */
MikamiUitOpen 4:c1beacfc42c7 215 typedef struct RegionStruct {
MikamiUitOpen 4:c1beacfc42c7 216 mmu_region_size_Type rg_t;
MikamiUitOpen 4:c1beacfc42c7 217 mmu_memory_Type mem_t;
MikamiUitOpen 4:c1beacfc42c7 218 uint8_t domain;
MikamiUitOpen 4:c1beacfc42c7 219 mmu_cacheability_Type inner_norm_t;
MikamiUitOpen 4:c1beacfc42c7 220 mmu_cacheability_Type outer_norm_t;
MikamiUitOpen 4:c1beacfc42c7 221 mmu_ecc_check_Type e_t;
MikamiUitOpen 4:c1beacfc42c7 222 mmu_execute_Type xn_t;
MikamiUitOpen 4:c1beacfc42c7 223 mmu_global_Type g_t;
MikamiUitOpen 4:c1beacfc42c7 224 mmu_secure_Type sec_t;
MikamiUitOpen 4:c1beacfc42c7 225 mmu_access_Type priv_t;
MikamiUitOpen 4:c1beacfc42c7 226 mmu_access_Type user_t;
MikamiUitOpen 4:c1beacfc42c7 227 mmu_shared_Type sh_t;
MikamiUitOpen 4:c1beacfc42c7 228
MikamiUitOpen 4:c1beacfc42c7 229 } mmu_region_attributes_Type;
MikamiUitOpen 4:c1beacfc42c7 230
MikamiUitOpen 4:c1beacfc42c7 231 /** \brief Set section execution-never attribute
MikamiUitOpen 4:c1beacfc42c7 232
MikamiUitOpen 4:c1beacfc42c7 233 The function sets section execution-never attribute
MikamiUitOpen 4:c1beacfc42c7 234
MikamiUitOpen 4:c1beacfc42c7 235 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
MikamiUitOpen 4:c1beacfc42c7 237
MikamiUitOpen 4:c1beacfc42c7 238 \return 0
MikamiUitOpen 4:c1beacfc42c7 239 */
MikamiUitOpen 4:c1beacfc42c7 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
MikamiUitOpen 4:c1beacfc42c7 241 {
MikamiUitOpen 4:c1beacfc42c7 242 *descriptor_l1 &= SECTION_XN_MASK;
MikamiUitOpen 4:c1beacfc42c7 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 244 return 0;
MikamiUitOpen 4:c1beacfc42c7 245 }
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 /** \brief Set section domain
MikamiUitOpen 4:c1beacfc42c7 248
MikamiUitOpen 4:c1beacfc42c7 249 The function sets section domain
MikamiUitOpen 4:c1beacfc42c7 250
MikamiUitOpen 4:c1beacfc42c7 251 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 252 \param [in] domain Section domain
MikamiUitOpen 4:c1beacfc42c7 253
MikamiUitOpen 4:c1beacfc42c7 254 \return 0
MikamiUitOpen 4:c1beacfc42c7 255 */
MikamiUitOpen 4:c1beacfc42c7 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
MikamiUitOpen 4:c1beacfc42c7 257 {
MikamiUitOpen 4:c1beacfc42c7 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
MikamiUitOpen 4:c1beacfc42c7 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 260 return 0;
MikamiUitOpen 4:c1beacfc42c7 261 }
MikamiUitOpen 4:c1beacfc42c7 262
MikamiUitOpen 4:c1beacfc42c7 263 /** \brief Set section parity check
MikamiUitOpen 4:c1beacfc42c7 264
MikamiUitOpen 4:c1beacfc42c7 265 The function sets section parity check
MikamiUitOpen 4:c1beacfc42c7 266
MikamiUitOpen 4:c1beacfc42c7 267 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
MikamiUitOpen 4:c1beacfc42c7 269
MikamiUitOpen 4:c1beacfc42c7 270 \return 0
MikamiUitOpen 4:c1beacfc42c7 271 */
MikamiUitOpen 4:c1beacfc42c7 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
MikamiUitOpen 4:c1beacfc42c7 273 {
MikamiUitOpen 4:c1beacfc42c7 274 *descriptor_l1 &= SECTION_P_MASK;
MikamiUitOpen 4:c1beacfc42c7 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 276 return 0;
MikamiUitOpen 4:c1beacfc42c7 277 }
MikamiUitOpen 4:c1beacfc42c7 278
MikamiUitOpen 4:c1beacfc42c7 279 /** \brief Set section access privileges
MikamiUitOpen 4:c1beacfc42c7 280
MikamiUitOpen 4:c1beacfc42c7 281 The function sets section access privileges
MikamiUitOpen 4:c1beacfc42c7 282
MikamiUitOpen 4:c1beacfc42c7 283 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 4:c1beacfc42c7 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 4:c1beacfc42c7 286 \param [in] afe Access flag enable
MikamiUitOpen 4:c1beacfc42c7 287
MikamiUitOpen 4:c1beacfc42c7 288 \return 0
MikamiUitOpen 4:c1beacfc42c7 289 */
MikamiUitOpen 4:c1beacfc42c7 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
MikamiUitOpen 4:c1beacfc42c7 291 {
MikamiUitOpen 4:c1beacfc42c7 292 uint32_t ap = 0;
MikamiUitOpen 4:c1beacfc42c7 293
MikamiUitOpen 4:c1beacfc42c7 294 if (afe == 0) { //full access
MikamiUitOpen 4:c1beacfc42c7 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
MikamiUitOpen 4:c1beacfc42c7 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 4:c1beacfc42c7 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
MikamiUitOpen 4:c1beacfc42c7 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 4:c1beacfc42c7 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 4:c1beacfc42c7 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 4:c1beacfc42c7 301 }
MikamiUitOpen 4:c1beacfc42c7 302
MikamiUitOpen 4:c1beacfc42c7 303 else { //Simplified access
MikamiUitOpen 4:c1beacfc42c7 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 4:c1beacfc42c7 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 4:c1beacfc42c7 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 4:c1beacfc42c7 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 4:c1beacfc42c7 308 }
MikamiUitOpen 4:c1beacfc42c7 309
MikamiUitOpen 4:c1beacfc42c7 310 *descriptor_l1 &= SECTION_AP_MASK;
MikamiUitOpen 4:c1beacfc42c7 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 313
MikamiUitOpen 4:c1beacfc42c7 314 return 0;
MikamiUitOpen 4:c1beacfc42c7 315 }
MikamiUitOpen 4:c1beacfc42c7 316
MikamiUitOpen 4:c1beacfc42c7 317 /** \brief Set section shareability
MikamiUitOpen 4:c1beacfc42c7 318
MikamiUitOpen 4:c1beacfc42c7 319 The function sets section shareability
MikamiUitOpen 4:c1beacfc42c7 320
MikamiUitOpen 4:c1beacfc42c7 321 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
MikamiUitOpen 4:c1beacfc42c7 323
MikamiUitOpen 4:c1beacfc42c7 324 \return 0
MikamiUitOpen 4:c1beacfc42c7 325 */
MikamiUitOpen 4:c1beacfc42c7 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
MikamiUitOpen 4:c1beacfc42c7 327 {
MikamiUitOpen 4:c1beacfc42c7 328 *descriptor_l1 &= SECTION_S_MASK;
MikamiUitOpen 4:c1beacfc42c7 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 330 return 0;
MikamiUitOpen 4:c1beacfc42c7 331 }
MikamiUitOpen 4:c1beacfc42c7 332
MikamiUitOpen 4:c1beacfc42c7 333 /** \brief Set section Global attribute
MikamiUitOpen 4:c1beacfc42c7 334
MikamiUitOpen 4:c1beacfc42c7 335 The function sets section Global attribute
MikamiUitOpen 4:c1beacfc42c7 336
MikamiUitOpen 4:c1beacfc42c7 337 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
MikamiUitOpen 4:c1beacfc42c7 339
MikamiUitOpen 4:c1beacfc42c7 340 \return 0
MikamiUitOpen 4:c1beacfc42c7 341 */
MikamiUitOpen 4:c1beacfc42c7 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
MikamiUitOpen 4:c1beacfc42c7 343 {
MikamiUitOpen 4:c1beacfc42c7 344 *descriptor_l1 &= SECTION_NG_MASK;
MikamiUitOpen 4:c1beacfc42c7 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 346 return 0;
MikamiUitOpen 4:c1beacfc42c7 347 }
MikamiUitOpen 4:c1beacfc42c7 348
MikamiUitOpen 4:c1beacfc42c7 349 /** \brief Set section Security attribute
MikamiUitOpen 4:c1beacfc42c7 350
MikamiUitOpen 4:c1beacfc42c7 351 The function sets section Global attribute
MikamiUitOpen 4:c1beacfc42c7 352
MikamiUitOpen 4:c1beacfc42c7 353 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
MikamiUitOpen 4:c1beacfc42c7 355
MikamiUitOpen 4:c1beacfc42c7 356 \return 0
MikamiUitOpen 4:c1beacfc42c7 357 */
MikamiUitOpen 4:c1beacfc42c7 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
MikamiUitOpen 4:c1beacfc42c7 359 {
MikamiUitOpen 4:c1beacfc42c7 360 *descriptor_l1 &= SECTION_NS_MASK;
MikamiUitOpen 4:c1beacfc42c7 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 362 return 0;
MikamiUitOpen 4:c1beacfc42c7 363 }
MikamiUitOpen 4:c1beacfc42c7 364
MikamiUitOpen 4:c1beacfc42c7 365 /* Page 4k or 64k */
MikamiUitOpen 4:c1beacfc42c7 366 /** \brief Set 4k/64k page execution-never attribute
MikamiUitOpen 4:c1beacfc42c7 367
MikamiUitOpen 4:c1beacfc42c7 368 The function sets 4k/64k page execution-never attribute
MikamiUitOpen 4:c1beacfc42c7 369
MikamiUitOpen 4:c1beacfc42c7 370 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 4:c1beacfc42c7 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
MikamiUitOpen 4:c1beacfc42c7 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
MikamiUitOpen 4:c1beacfc42c7 373
MikamiUitOpen 4:c1beacfc42c7 374 \return 0
MikamiUitOpen 4:c1beacfc42c7 375 */
MikamiUitOpen 4:c1beacfc42c7 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
MikamiUitOpen 4:c1beacfc42c7 377 {
MikamiUitOpen 4:c1beacfc42c7 378 if (page == PAGE_4k)
MikamiUitOpen 4:c1beacfc42c7 379 {
MikamiUitOpen 4:c1beacfc42c7 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
MikamiUitOpen 4:c1beacfc42c7 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 382 }
MikamiUitOpen 4:c1beacfc42c7 383 else
MikamiUitOpen 4:c1beacfc42c7 384 {
MikamiUitOpen 4:c1beacfc42c7 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
MikamiUitOpen 4:c1beacfc42c7 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 387 }
MikamiUitOpen 4:c1beacfc42c7 388 return 0;
MikamiUitOpen 4:c1beacfc42c7 389 }
MikamiUitOpen 4:c1beacfc42c7 390
MikamiUitOpen 4:c1beacfc42c7 391 /** \brief Set 4k/64k page domain
MikamiUitOpen 4:c1beacfc42c7 392
MikamiUitOpen 4:c1beacfc42c7 393 The function sets 4k/64k page domain
MikamiUitOpen 4:c1beacfc42c7 394
MikamiUitOpen 4:c1beacfc42c7 395 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 396 \param [in] domain Page domain
MikamiUitOpen 4:c1beacfc42c7 397
MikamiUitOpen 4:c1beacfc42c7 398 \return 0
MikamiUitOpen 4:c1beacfc42c7 399 */
MikamiUitOpen 4:c1beacfc42c7 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
MikamiUitOpen 4:c1beacfc42c7 401 {
MikamiUitOpen 4:c1beacfc42c7 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
MikamiUitOpen 4:c1beacfc42c7 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 404 return 0;
MikamiUitOpen 4:c1beacfc42c7 405 }
MikamiUitOpen 4:c1beacfc42c7 406
MikamiUitOpen 4:c1beacfc42c7 407 /** \brief Set 4k/64k page parity check
MikamiUitOpen 4:c1beacfc42c7 408
MikamiUitOpen 4:c1beacfc42c7 409 The function sets 4k/64k page parity check
MikamiUitOpen 4:c1beacfc42c7 410
MikamiUitOpen 4:c1beacfc42c7 411 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
MikamiUitOpen 4:c1beacfc42c7 413
MikamiUitOpen 4:c1beacfc42c7 414 \return 0
MikamiUitOpen 4:c1beacfc42c7 415 */
MikamiUitOpen 4:c1beacfc42c7 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
MikamiUitOpen 4:c1beacfc42c7 417 {
MikamiUitOpen 4:c1beacfc42c7 418 *descriptor_l1 &= SECTION_P_MASK;
MikamiUitOpen 4:c1beacfc42c7 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 420 return 0;
MikamiUitOpen 4:c1beacfc42c7 421 }
MikamiUitOpen 4:c1beacfc42c7 422
MikamiUitOpen 4:c1beacfc42c7 423 /** \brief Set 4k/64k page access privileges
MikamiUitOpen 4:c1beacfc42c7 424
MikamiUitOpen 4:c1beacfc42c7 425 The function sets 4k/64k page access privileges
MikamiUitOpen 4:c1beacfc42c7 426
MikamiUitOpen 4:c1beacfc42c7 427 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 4:c1beacfc42c7 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 4:c1beacfc42c7 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 4:c1beacfc42c7 430 \param [in] afe Access flag enable
MikamiUitOpen 4:c1beacfc42c7 431
MikamiUitOpen 4:c1beacfc42c7 432 \return 0
MikamiUitOpen 4:c1beacfc42c7 433 */
MikamiUitOpen 4:c1beacfc42c7 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
MikamiUitOpen 4:c1beacfc42c7 435 {
MikamiUitOpen 4:c1beacfc42c7 436 uint32_t ap = 0;
MikamiUitOpen 4:c1beacfc42c7 437
MikamiUitOpen 4:c1beacfc42c7 438 if (afe == 0) { //full access
MikamiUitOpen 4:c1beacfc42c7 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
MikamiUitOpen 4:c1beacfc42c7 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 4:c1beacfc42c7 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
MikamiUitOpen 4:c1beacfc42c7 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 4:c1beacfc42c7 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 4:c1beacfc42c7 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
MikamiUitOpen 4:c1beacfc42c7 445 }
MikamiUitOpen 4:c1beacfc42c7 446
MikamiUitOpen 4:c1beacfc42c7 447 else { //Simplified access
MikamiUitOpen 4:c1beacfc42c7 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 4:c1beacfc42c7 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 4:c1beacfc42c7 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 4:c1beacfc42c7 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 4:c1beacfc42c7 452 }
MikamiUitOpen 4:c1beacfc42c7 453
MikamiUitOpen 4:c1beacfc42c7 454 *descriptor_l2 &= PAGE_AP_MASK;
MikamiUitOpen 4:c1beacfc42c7 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 457
MikamiUitOpen 4:c1beacfc42c7 458 return 0;
MikamiUitOpen 4:c1beacfc42c7 459 }
MikamiUitOpen 4:c1beacfc42c7 460
MikamiUitOpen 4:c1beacfc42c7 461 /** \brief Set 4k/64k page shareability
MikamiUitOpen 4:c1beacfc42c7 462
MikamiUitOpen 4:c1beacfc42c7 463 The function sets 4k/64k page shareability
MikamiUitOpen 4:c1beacfc42c7 464
MikamiUitOpen 4:c1beacfc42c7 465 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 4:c1beacfc42c7 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
MikamiUitOpen 4:c1beacfc42c7 467
MikamiUitOpen 4:c1beacfc42c7 468 \return 0
MikamiUitOpen 4:c1beacfc42c7 469 */
MikamiUitOpen 4:c1beacfc42c7 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
MikamiUitOpen 4:c1beacfc42c7 471 {
MikamiUitOpen 4:c1beacfc42c7 472 *descriptor_l2 &= PAGE_S_MASK;
MikamiUitOpen 4:c1beacfc42c7 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 474 return 0;
MikamiUitOpen 4:c1beacfc42c7 475 }
MikamiUitOpen 4:c1beacfc42c7 476
MikamiUitOpen 4:c1beacfc42c7 477 /** \brief Set 4k/64k page Global attribute
MikamiUitOpen 4:c1beacfc42c7 478
MikamiUitOpen 4:c1beacfc42c7 479 The function sets 4k/64k page Global attribute
MikamiUitOpen 4:c1beacfc42c7 480
MikamiUitOpen 4:c1beacfc42c7 481 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 4:c1beacfc42c7 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
MikamiUitOpen 4:c1beacfc42c7 483
MikamiUitOpen 4:c1beacfc42c7 484 \return 0
MikamiUitOpen 4:c1beacfc42c7 485 */
MikamiUitOpen 4:c1beacfc42c7 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
MikamiUitOpen 4:c1beacfc42c7 487 {
MikamiUitOpen 4:c1beacfc42c7 488 *descriptor_l2 &= PAGE_NG_MASK;
MikamiUitOpen 4:c1beacfc42c7 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 490 return 0;
MikamiUitOpen 4:c1beacfc42c7 491 }
MikamiUitOpen 4:c1beacfc42c7 492
MikamiUitOpen 4:c1beacfc42c7 493 /** \brief Set 4k/64k page Security attribute
MikamiUitOpen 4:c1beacfc42c7 494
MikamiUitOpen 4:c1beacfc42c7 495 The function sets 4k/64k page Global attribute
MikamiUitOpen 4:c1beacfc42c7 496
MikamiUitOpen 4:c1beacfc42c7 497 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
MikamiUitOpen 4:c1beacfc42c7 499
MikamiUitOpen 4:c1beacfc42c7 500 \return 0
MikamiUitOpen 4:c1beacfc42c7 501 */
MikamiUitOpen 4:c1beacfc42c7 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
MikamiUitOpen 4:c1beacfc42c7 503 {
MikamiUitOpen 4:c1beacfc42c7 504 *descriptor_l1 &= PAGE_NS_MASK;
MikamiUitOpen 4:c1beacfc42c7 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 506 return 0;
MikamiUitOpen 4:c1beacfc42c7 507 }
MikamiUitOpen 4:c1beacfc42c7 508
MikamiUitOpen 4:c1beacfc42c7 509
MikamiUitOpen 4:c1beacfc42c7 510 /** \brief Set Section memory attributes
MikamiUitOpen 4:c1beacfc42c7 511
MikamiUitOpen 4:c1beacfc42c7 512 The function sets section memory attributes
MikamiUitOpen 4:c1beacfc42c7 513
MikamiUitOpen 4:c1beacfc42c7 514 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 4:c1beacfc42c7 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
MikamiUitOpen 4:c1beacfc42c7 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 4:c1beacfc42c7 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 4:c1beacfc42c7 518
MikamiUitOpen 4:c1beacfc42c7 519 \return 0
MikamiUitOpen 4:c1beacfc42c7 520 */
MikamiUitOpen 4:c1beacfc42c7 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
MikamiUitOpen 4:c1beacfc42c7 522 {
MikamiUitOpen 4:c1beacfc42c7 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
MikamiUitOpen 4:c1beacfc42c7 524
MikamiUitOpen 4:c1beacfc42c7 525 if (STRONGLY_ORDERED == mem)
MikamiUitOpen 4:c1beacfc42c7 526 {
MikamiUitOpen 4:c1beacfc42c7 527 return 0;
MikamiUitOpen 4:c1beacfc42c7 528 }
MikamiUitOpen 4:c1beacfc42c7 529 else if (SHARED_DEVICE == mem)
MikamiUitOpen 4:c1beacfc42c7 530 {
MikamiUitOpen 4:c1beacfc42c7 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 532 }
MikamiUitOpen 4:c1beacfc42c7 533 else if (NON_SHARED_DEVICE == mem)
MikamiUitOpen 4:c1beacfc42c7 534 {
MikamiUitOpen 4:c1beacfc42c7 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 536 }
MikamiUitOpen 4:c1beacfc42c7 537 else if (NORMAL == mem)
MikamiUitOpen 4:c1beacfc42c7 538 {
MikamiUitOpen 4:c1beacfc42c7 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 540 switch(inner)
MikamiUitOpen 4:c1beacfc42c7 541 {
MikamiUitOpen 4:c1beacfc42c7 542 case NON_CACHEABLE:
MikamiUitOpen 4:c1beacfc42c7 543 break;
MikamiUitOpen 4:c1beacfc42c7 544 case WB_WA:
MikamiUitOpen 4:c1beacfc42c7 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 546 break;
MikamiUitOpen 4:c1beacfc42c7 547 case WT:
MikamiUitOpen 4:c1beacfc42c7 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 549 break;
MikamiUitOpen 4:c1beacfc42c7 550 case WB_NO_WA:
MikamiUitOpen 4:c1beacfc42c7 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 552 break;
MikamiUitOpen 4:c1beacfc42c7 553 }
MikamiUitOpen 4:c1beacfc42c7 554 switch(outer)
MikamiUitOpen 4:c1beacfc42c7 555 {
MikamiUitOpen 4:c1beacfc42c7 556 case NON_CACHEABLE:
MikamiUitOpen 4:c1beacfc42c7 557 break;
MikamiUitOpen 4:c1beacfc42c7 558 case WB_WA:
MikamiUitOpen 4:c1beacfc42c7 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 560 break;
MikamiUitOpen 4:c1beacfc42c7 561 case WT:
MikamiUitOpen 4:c1beacfc42c7 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 563 break;
MikamiUitOpen 4:c1beacfc42c7 564 case WB_NO_WA:
MikamiUitOpen 4:c1beacfc42c7 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 566 break;
MikamiUitOpen 4:c1beacfc42c7 567 }
MikamiUitOpen 4:c1beacfc42c7 568 }
MikamiUitOpen 4:c1beacfc42c7 569
MikamiUitOpen 4:c1beacfc42c7 570 return 0;
MikamiUitOpen 4:c1beacfc42c7 571 }
MikamiUitOpen 4:c1beacfc42c7 572
MikamiUitOpen 4:c1beacfc42c7 573 /** \brief Set 4k/64k page memory attributes
MikamiUitOpen 4:c1beacfc42c7 574
MikamiUitOpen 4:c1beacfc42c7 575 The function sets 4k/64k page memory attributes
MikamiUitOpen 4:c1beacfc42c7 576
MikamiUitOpen 4:c1beacfc42c7 577 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 4:c1beacfc42c7 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
MikamiUitOpen 4:c1beacfc42c7 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 4:c1beacfc42c7 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 4:c1beacfc42c7 581
MikamiUitOpen 4:c1beacfc42c7 582 \return 0
MikamiUitOpen 4:c1beacfc42c7 583 */
MikamiUitOpen 4:c1beacfc42c7 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
MikamiUitOpen 4:c1beacfc42c7 585 {
MikamiUitOpen 4:c1beacfc42c7 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
MikamiUitOpen 4:c1beacfc42c7 587
MikamiUitOpen 4:c1beacfc42c7 588 if (page == PAGE_64k)
MikamiUitOpen 4:c1beacfc42c7 589 {
MikamiUitOpen 4:c1beacfc42c7 590 //same as section
MikamiUitOpen 4:c1beacfc42c7 591 __memory_section(descriptor_l2, mem, outer, inner);
MikamiUitOpen 4:c1beacfc42c7 592 }
MikamiUitOpen 4:c1beacfc42c7 593 else
MikamiUitOpen 4:c1beacfc42c7 594 {
MikamiUitOpen 4:c1beacfc42c7 595 if (STRONGLY_ORDERED == mem)
MikamiUitOpen 4:c1beacfc42c7 596 {
MikamiUitOpen 4:c1beacfc42c7 597 return 0;
MikamiUitOpen 4:c1beacfc42c7 598 }
MikamiUitOpen 4:c1beacfc42c7 599 else if (SHARED_DEVICE == mem)
MikamiUitOpen 4:c1beacfc42c7 600 {
MikamiUitOpen 4:c1beacfc42c7 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 602 }
MikamiUitOpen 4:c1beacfc42c7 603 else if (NON_SHARED_DEVICE == mem)
MikamiUitOpen 4:c1beacfc42c7 604 {
MikamiUitOpen 4:c1beacfc42c7 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 606 }
MikamiUitOpen 4:c1beacfc42c7 607 else if (NORMAL == mem)
MikamiUitOpen 4:c1beacfc42c7 608 {
MikamiUitOpen 4:c1beacfc42c7 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 610 switch(inner)
MikamiUitOpen 4:c1beacfc42c7 611 {
MikamiUitOpen 4:c1beacfc42c7 612 case NON_CACHEABLE:
MikamiUitOpen 4:c1beacfc42c7 613 break;
MikamiUitOpen 4:c1beacfc42c7 614 case WB_WA:
MikamiUitOpen 4:c1beacfc42c7 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 616 break;
MikamiUitOpen 4:c1beacfc42c7 617 case WT:
MikamiUitOpen 4:c1beacfc42c7 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 619 break;
MikamiUitOpen 4:c1beacfc42c7 620 case WB_NO_WA:
MikamiUitOpen 4:c1beacfc42c7 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 622 break;
MikamiUitOpen 4:c1beacfc42c7 623 }
MikamiUitOpen 4:c1beacfc42c7 624 switch(outer)
MikamiUitOpen 4:c1beacfc42c7 625 {
MikamiUitOpen 4:c1beacfc42c7 626 case NON_CACHEABLE:
MikamiUitOpen 4:c1beacfc42c7 627 break;
MikamiUitOpen 4:c1beacfc42c7 628 case WB_WA:
MikamiUitOpen 4:c1beacfc42c7 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 630 break;
MikamiUitOpen 4:c1beacfc42c7 631 case WT:
MikamiUitOpen 4:c1beacfc42c7 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
MikamiUitOpen 4:c1beacfc42c7 633 break;
MikamiUitOpen 4:c1beacfc42c7 634 case WB_NO_WA:
MikamiUitOpen 4:c1beacfc42c7 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
MikamiUitOpen 4:c1beacfc42c7 636 break;
MikamiUitOpen 4:c1beacfc42c7 637 }
MikamiUitOpen 4:c1beacfc42c7 638 }
MikamiUitOpen 4:c1beacfc42c7 639 }
MikamiUitOpen 4:c1beacfc42c7 640
MikamiUitOpen 4:c1beacfc42c7 641 return 0;
MikamiUitOpen 4:c1beacfc42c7 642 }
MikamiUitOpen 4:c1beacfc42c7 643
MikamiUitOpen 4:c1beacfc42c7 644 /** \brief Create a L1 section descriptor
MikamiUitOpen 4:c1beacfc42c7 645
MikamiUitOpen 4:c1beacfc42c7 646 The function creates a section descriptor.
MikamiUitOpen 4:c1beacfc42c7 647
MikamiUitOpen 4:c1beacfc42c7 648 Assumptions:
MikamiUitOpen 4:c1beacfc42c7 649 - 16MB super sections not supported
MikamiUitOpen 4:c1beacfc42c7 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
MikamiUitOpen 4:c1beacfc42c7 651 - Functions always return 0
MikamiUitOpen 4:c1beacfc42c7 652
MikamiUitOpen 4:c1beacfc42c7 653 \param [out] descriptor L1 descriptor
MikamiUitOpen 4:c1beacfc42c7 654 \param [out] descriptor2 L2 descriptor
MikamiUitOpen 4:c1beacfc42c7 655 \param [in] reg Section attributes
MikamiUitOpen 4:c1beacfc42c7 656
MikamiUitOpen 4:c1beacfc42c7 657 \return 0
MikamiUitOpen 4:c1beacfc42c7 658 */
MikamiUitOpen 4:c1beacfc42c7 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
MikamiUitOpen 4:c1beacfc42c7 660 {
MikamiUitOpen 4:c1beacfc42c7 661 *descriptor = 0;
MikamiUitOpen 4:c1beacfc42c7 662
MikamiUitOpen 4:c1beacfc42c7 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
MikamiUitOpen 4:c1beacfc42c7 664 __xn_section(descriptor,reg.xn_t);
MikamiUitOpen 4:c1beacfc42c7 665 __domain_section(descriptor, reg.domain);
MikamiUitOpen 4:c1beacfc42c7 666 __p_section(descriptor, reg.e_t);
MikamiUitOpen 4:c1beacfc42c7 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 4:c1beacfc42c7 668 __shared_section(descriptor,reg.sh_t);
MikamiUitOpen 4:c1beacfc42c7 669 __global_section(descriptor,reg.g_t);
MikamiUitOpen 4:c1beacfc42c7 670 __secure_section(descriptor,reg.sec_t);
MikamiUitOpen 4:c1beacfc42c7 671 *descriptor &= SECTION_MASK;
MikamiUitOpen 4:c1beacfc42c7 672 *descriptor |= SECTION_DESCRIPTOR;
MikamiUitOpen 4:c1beacfc42c7 673
MikamiUitOpen 4:c1beacfc42c7 674 return 0;
MikamiUitOpen 4:c1beacfc42c7 675
MikamiUitOpen 4:c1beacfc42c7 676 }
MikamiUitOpen 4:c1beacfc42c7 677
MikamiUitOpen 4:c1beacfc42c7 678
MikamiUitOpen 4:c1beacfc42c7 679 /** \brief Create a L1 and L2 4k/64k page descriptor
MikamiUitOpen 4:c1beacfc42c7 680
MikamiUitOpen 4:c1beacfc42c7 681 The function creates a 4k/64k page descriptor.
MikamiUitOpen 4:c1beacfc42c7 682 Assumptions:
MikamiUitOpen 4:c1beacfc42c7 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
MikamiUitOpen 4:c1beacfc42c7 684 - Functions always return 0
MikamiUitOpen 4:c1beacfc42c7 685
MikamiUitOpen 4:c1beacfc42c7 686 \param [out] descriptor L1 descriptor
MikamiUitOpen 4:c1beacfc42c7 687 \param [out] descriptor2 L2 descriptor
MikamiUitOpen 4:c1beacfc42c7 688 \param [in] reg 4k/64k page attributes
MikamiUitOpen 4:c1beacfc42c7 689
MikamiUitOpen 4:c1beacfc42c7 690 \return 0
MikamiUitOpen 4:c1beacfc42c7 691 */
MikamiUitOpen 4:c1beacfc42c7 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
MikamiUitOpen 4:c1beacfc42c7 693 {
MikamiUitOpen 4:c1beacfc42c7 694 *descriptor = 0;
MikamiUitOpen 4:c1beacfc42c7 695 *descriptor2 = 0;
MikamiUitOpen 4:c1beacfc42c7 696
MikamiUitOpen 4:c1beacfc42c7 697 switch (reg.rg_t)
MikamiUitOpen 4:c1beacfc42c7 698 {
MikamiUitOpen 4:c1beacfc42c7 699 case PAGE_4k:
MikamiUitOpen 4:c1beacfc42c7 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
MikamiUitOpen 4:c1beacfc42c7 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
MikamiUitOpen 4:c1beacfc42c7 702 __domain_page(descriptor, reg.domain);
MikamiUitOpen 4:c1beacfc42c7 703 __p_page(descriptor, reg.e_t);
MikamiUitOpen 4:c1beacfc42c7 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 4:c1beacfc42c7 705 __shared_page(descriptor2,reg.sh_t);
MikamiUitOpen 4:c1beacfc42c7 706 __global_page(descriptor2,reg.g_t);
MikamiUitOpen 4:c1beacfc42c7 707 __secure_page(descriptor,reg.sec_t);
MikamiUitOpen 4:c1beacfc42c7 708 *descriptor &= PAGE_L1_MASK;
MikamiUitOpen 4:c1beacfc42c7 709 *descriptor |= PAGE_L1_DESCRIPTOR;
MikamiUitOpen 4:c1beacfc42c7 710 *descriptor2 &= PAGE_L2_4K_MASK;
MikamiUitOpen 4:c1beacfc42c7 711 *descriptor2 |= PAGE_L2_4K_DESC;
MikamiUitOpen 4:c1beacfc42c7 712 break;
MikamiUitOpen 4:c1beacfc42c7 713
MikamiUitOpen 4:c1beacfc42c7 714 case PAGE_64k:
MikamiUitOpen 4:c1beacfc42c7 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
MikamiUitOpen 4:c1beacfc42c7 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
MikamiUitOpen 4:c1beacfc42c7 717 __domain_page(descriptor, reg.domain);
MikamiUitOpen 4:c1beacfc42c7 718 __p_page(descriptor, reg.e_t);
MikamiUitOpen 4:c1beacfc42c7 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 4:c1beacfc42c7 720 __shared_page(descriptor2,reg.sh_t);
MikamiUitOpen 4:c1beacfc42c7 721 __global_page(descriptor2,reg.g_t);
MikamiUitOpen 4:c1beacfc42c7 722 __secure_page(descriptor,reg.sec_t);
MikamiUitOpen 4:c1beacfc42c7 723 *descriptor &= PAGE_L1_MASK;
MikamiUitOpen 4:c1beacfc42c7 724 *descriptor |= PAGE_L1_DESCRIPTOR;
MikamiUitOpen 4:c1beacfc42c7 725 *descriptor2 &= PAGE_L2_64K_MASK;
MikamiUitOpen 4:c1beacfc42c7 726 *descriptor2 |= PAGE_L2_64K_DESC;
MikamiUitOpen 4:c1beacfc42c7 727 break;
MikamiUitOpen 4:c1beacfc42c7 728
MikamiUitOpen 4:c1beacfc42c7 729 case SECTION:
MikamiUitOpen 4:c1beacfc42c7 730 //error
MikamiUitOpen 4:c1beacfc42c7 731 break;
MikamiUitOpen 4:c1beacfc42c7 732
MikamiUitOpen 4:c1beacfc42c7 733 }
MikamiUitOpen 4:c1beacfc42c7 734
MikamiUitOpen 4:c1beacfc42c7 735 return 0;
MikamiUitOpen 4:c1beacfc42c7 736
MikamiUitOpen 4:c1beacfc42c7 737 }
MikamiUitOpen 4:c1beacfc42c7 738
MikamiUitOpen 4:c1beacfc42c7 739 /** \brief Create a 1MB Section
MikamiUitOpen 4:c1beacfc42c7 740
MikamiUitOpen 4:c1beacfc42c7 741 \param [in] ttb Translation table base address
MikamiUitOpen 4:c1beacfc42c7 742 \param [in] base_address Section base address
MikamiUitOpen 4:c1beacfc42c7 743 \param [in] count Number of sections to create
MikamiUitOpen 4:c1beacfc42c7 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 4:c1beacfc42c7 745
MikamiUitOpen 4:c1beacfc42c7 746 */
MikamiUitOpen 4:c1beacfc42c7 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
MikamiUitOpen 4:c1beacfc42c7 748 {
MikamiUitOpen 4:c1beacfc42c7 749 uint32_t offset;
MikamiUitOpen 4:c1beacfc42c7 750 uint32_t entry;
MikamiUitOpen 4:c1beacfc42c7 751 uint32_t i;
MikamiUitOpen 4:c1beacfc42c7 752
MikamiUitOpen 4:c1beacfc42c7 753 offset = base_address >> 20;
MikamiUitOpen 4:c1beacfc42c7 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
MikamiUitOpen 4:c1beacfc42c7 755
MikamiUitOpen 4:c1beacfc42c7 756 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 757 ttb = ttb + offset;
MikamiUitOpen 4:c1beacfc42c7 758
MikamiUitOpen 4:c1beacfc42c7 759 for (i = 0; i < count; i++ )
MikamiUitOpen 4:c1beacfc42c7 760 {
MikamiUitOpen 4:c1beacfc42c7 761 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 762 *ttb++ = entry;
MikamiUitOpen 4:c1beacfc42c7 763 entry += OFFSET_1M;
MikamiUitOpen 4:c1beacfc42c7 764 }
MikamiUitOpen 4:c1beacfc42c7 765 }
MikamiUitOpen 4:c1beacfc42c7 766
MikamiUitOpen 4:c1beacfc42c7 767 /** \brief Create a 4k page entry
MikamiUitOpen 4:c1beacfc42c7 768
MikamiUitOpen 4:c1beacfc42c7 769 \param [in] ttb L1 table base address
MikamiUitOpen 4:c1beacfc42c7 770 \param [in] base_address 4k base address
MikamiUitOpen 4:c1beacfc42c7 771 \param [in] count Number of 4k pages to create
MikamiUitOpen 4:c1beacfc42c7 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 4:c1beacfc42c7 773 \param [in] ttb_l2 L2 table base address
MikamiUitOpen 4:c1beacfc42c7 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
MikamiUitOpen 4:c1beacfc42c7 775
MikamiUitOpen 4:c1beacfc42c7 776 */
MikamiUitOpen 4:c1beacfc42c7 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
MikamiUitOpen 4:c1beacfc42c7 778 {
MikamiUitOpen 4:c1beacfc42c7 779
MikamiUitOpen 4:c1beacfc42c7 780 uint32_t offset, offset2;
MikamiUitOpen 4:c1beacfc42c7 781 uint32_t entry, entry2;
MikamiUitOpen 4:c1beacfc42c7 782 uint32_t i;
MikamiUitOpen 4:c1beacfc42c7 783
MikamiUitOpen 4:c1beacfc42c7 784
MikamiUitOpen 4:c1beacfc42c7 785 offset = base_address >> 20;
MikamiUitOpen 4:c1beacfc42c7 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
MikamiUitOpen 4:c1beacfc42c7 787
MikamiUitOpen 4:c1beacfc42c7 788 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 789 ttb += offset;
MikamiUitOpen 4:c1beacfc42c7 790 //create l1_entry
MikamiUitOpen 4:c1beacfc42c7 791 *ttb = entry;
MikamiUitOpen 4:c1beacfc42c7 792
MikamiUitOpen 4:c1beacfc42c7 793 offset2 = (base_address & 0xff000) >> 12;
MikamiUitOpen 4:c1beacfc42c7 794 ttb_l2 += offset2;
MikamiUitOpen 4:c1beacfc42c7 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
MikamiUitOpen 4:c1beacfc42c7 796 for (i = 0; i < count; i++ )
MikamiUitOpen 4:c1beacfc42c7 797 {
MikamiUitOpen 4:c1beacfc42c7 798 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 799 *ttb_l2++ = entry2;
MikamiUitOpen 4:c1beacfc42c7 800 entry2 += OFFSET_4K;
MikamiUitOpen 4:c1beacfc42c7 801 }
MikamiUitOpen 4:c1beacfc42c7 802 }
MikamiUitOpen 4:c1beacfc42c7 803
MikamiUitOpen 4:c1beacfc42c7 804 /** \brief Create a 64k page entry
MikamiUitOpen 4:c1beacfc42c7 805
MikamiUitOpen 4:c1beacfc42c7 806 \param [in] ttb L1 table base address
MikamiUitOpen 4:c1beacfc42c7 807 \param [in] base_address 64k base address
MikamiUitOpen 4:c1beacfc42c7 808 \param [in] count Number of 64k pages to create
MikamiUitOpen 4:c1beacfc42c7 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 4:c1beacfc42c7 810 \param [in] ttb_l2 L2 table base address
MikamiUitOpen 4:c1beacfc42c7 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
MikamiUitOpen 4:c1beacfc42c7 812
MikamiUitOpen 4:c1beacfc42c7 813 */
MikamiUitOpen 4:c1beacfc42c7 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
MikamiUitOpen 4:c1beacfc42c7 815 {
MikamiUitOpen 4:c1beacfc42c7 816 uint32_t offset, offset2;
MikamiUitOpen 4:c1beacfc42c7 817 uint32_t entry, entry2;
MikamiUitOpen 4:c1beacfc42c7 818 uint32_t i,j;
MikamiUitOpen 4:c1beacfc42c7 819
MikamiUitOpen 4:c1beacfc42c7 820
MikamiUitOpen 4:c1beacfc42c7 821 offset = base_address >> 20;
MikamiUitOpen 4:c1beacfc42c7 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
MikamiUitOpen 4:c1beacfc42c7 823
MikamiUitOpen 4:c1beacfc42c7 824 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 825 ttb += offset;
MikamiUitOpen 4:c1beacfc42c7 826 //create l1_entry
MikamiUitOpen 4:c1beacfc42c7 827 *ttb = entry;
MikamiUitOpen 4:c1beacfc42c7 828
MikamiUitOpen 4:c1beacfc42c7 829 offset2 = (base_address & 0xff000) >> 12;
MikamiUitOpen 4:c1beacfc42c7 830 ttb_l2 += offset2;
MikamiUitOpen 4:c1beacfc42c7 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
MikamiUitOpen 4:c1beacfc42c7 832 for (i = 0; i < count; i++ )
MikamiUitOpen 4:c1beacfc42c7 833 {
MikamiUitOpen 4:c1beacfc42c7 834 //create 16 entries
MikamiUitOpen 4:c1beacfc42c7 835 for (j = 0; j < 16; j++)
MikamiUitOpen 4:c1beacfc42c7 836 //4 bytes aligned
MikamiUitOpen 4:c1beacfc42c7 837 *ttb_l2++ = entry2;
MikamiUitOpen 4:c1beacfc42c7 838 entry2 += OFFSET_64K;
MikamiUitOpen 4:c1beacfc42c7 839 }
MikamiUitOpen 4:c1beacfc42c7 840 }
MikamiUitOpen 4:c1beacfc42c7 841
MikamiUitOpen 4:c1beacfc42c7 842 /*@} end of MMU_Functions */
MikamiUitOpen 4:c1beacfc42c7 843 #endif
MikamiUitOpen 4:c1beacfc42c7 844
MikamiUitOpen 4:c1beacfc42c7 845 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 846 }
MikamiUitOpen 4:c1beacfc42c7 847 #endif