不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_caFunc.h@4:c1beacfc42c7, 2016-10-02 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Oct 02 10:51:10 2016 +0000
Revision:
4:c1beacfc42c7
5

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_caFunc.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-A Core Function Access Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V3.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 30 Oct 2013
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #ifndef __CORE_CAFUNC_H__
MikamiUitOpen 4:c1beacfc42c7 39 #define __CORE_CAFUNC_H__
MikamiUitOpen 4:c1beacfc42c7 40
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 /* ########################### Core Function Access ########################### */
MikamiUitOpen 4:c1beacfc42c7 43 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
MikamiUitOpen 4:c1beacfc42c7 45 @{
MikamiUitOpen 4:c1beacfc42c7 46 */
MikamiUitOpen 4:c1beacfc42c7 47
MikamiUitOpen 4:c1beacfc42c7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 49 /* ARM armcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 50
MikamiUitOpen 4:c1beacfc42c7 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 4:c1beacfc42c7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 4:c1beacfc42c7 53 #endif
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 #define MODE_USR 0x10
MikamiUitOpen 4:c1beacfc42c7 56 #define MODE_FIQ 0x11
MikamiUitOpen 4:c1beacfc42c7 57 #define MODE_IRQ 0x12
MikamiUitOpen 4:c1beacfc42c7 58 #define MODE_SVC 0x13
MikamiUitOpen 4:c1beacfc42c7 59 #define MODE_MON 0x16
MikamiUitOpen 4:c1beacfc42c7 60 #define MODE_ABT 0x17
MikamiUitOpen 4:c1beacfc42c7 61 #define MODE_HYP 0x1A
MikamiUitOpen 4:c1beacfc42c7 62 #define MODE_UND 0x1B
MikamiUitOpen 4:c1beacfc42c7 63 #define MODE_SYS 0x1F
MikamiUitOpen 4:c1beacfc42c7 64
MikamiUitOpen 4:c1beacfc42c7 65 /** \brief Get APSR Register
MikamiUitOpen 4:c1beacfc42c7 66
MikamiUitOpen 4:c1beacfc42c7 67 This function returns the content of the APSR Register.
MikamiUitOpen 4:c1beacfc42c7 68
MikamiUitOpen 4:c1beacfc42c7 69 \return APSR Register value
MikamiUitOpen 4:c1beacfc42c7 70 */
MikamiUitOpen 4:c1beacfc42c7 71 __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 4:c1beacfc42c7 72 {
MikamiUitOpen 4:c1beacfc42c7 73 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 4:c1beacfc42c7 74 return(__regAPSR);
MikamiUitOpen 4:c1beacfc42c7 75 }
MikamiUitOpen 4:c1beacfc42c7 76
MikamiUitOpen 4:c1beacfc42c7 77
MikamiUitOpen 4:c1beacfc42c7 78 /** \brief Get CPSR Register
MikamiUitOpen 4:c1beacfc42c7 79
MikamiUitOpen 4:c1beacfc42c7 80 This function returns the content of the CPSR Register.
MikamiUitOpen 4:c1beacfc42c7 81
MikamiUitOpen 4:c1beacfc42c7 82 \return CPSR Register value
MikamiUitOpen 4:c1beacfc42c7 83 */
MikamiUitOpen 4:c1beacfc42c7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
MikamiUitOpen 4:c1beacfc42c7 85 {
MikamiUitOpen 4:c1beacfc42c7 86 register uint32_t __regCPSR __ASM("cpsr");
MikamiUitOpen 4:c1beacfc42c7 87 return(__regCPSR);
MikamiUitOpen 4:c1beacfc42c7 88 }
MikamiUitOpen 4:c1beacfc42c7 89
MikamiUitOpen 4:c1beacfc42c7 90 /** \brief Set Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 91
MikamiUitOpen 4:c1beacfc42c7 92 This function assigns the given value to the current stack pointer.
MikamiUitOpen 4:c1beacfc42c7 93
MikamiUitOpen 4:c1beacfc42c7 94 \param [in] topOfStack Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 95 */
MikamiUitOpen 4:c1beacfc42c7 96 register uint32_t __regSP __ASM("sp");
MikamiUitOpen 4:c1beacfc42c7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MikamiUitOpen 4:c1beacfc42c7 98 {
MikamiUitOpen 4:c1beacfc42c7 99 __regSP = topOfStack;
MikamiUitOpen 4:c1beacfc42c7 100 }
MikamiUitOpen 4:c1beacfc42c7 101
MikamiUitOpen 4:c1beacfc42c7 102
MikamiUitOpen 4:c1beacfc42c7 103 /** \brief Get link register
MikamiUitOpen 4:c1beacfc42c7 104
MikamiUitOpen 4:c1beacfc42c7 105 This function returns the value of the link register
MikamiUitOpen 4:c1beacfc42c7 106
MikamiUitOpen 4:c1beacfc42c7 107 \return Value of link register
MikamiUitOpen 4:c1beacfc42c7 108 */
MikamiUitOpen 4:c1beacfc42c7 109 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 4:c1beacfc42c7 110 __STATIC_INLINE uint32_t __get_LR(void)
MikamiUitOpen 4:c1beacfc42c7 111 {
MikamiUitOpen 4:c1beacfc42c7 112 return(__reglr);
MikamiUitOpen 4:c1beacfc42c7 113 }
MikamiUitOpen 4:c1beacfc42c7 114
MikamiUitOpen 4:c1beacfc42c7 115 /** \brief Set link register
MikamiUitOpen 4:c1beacfc42c7 116
MikamiUitOpen 4:c1beacfc42c7 117 This function sets the value of the link register
MikamiUitOpen 4:c1beacfc42c7 118
MikamiUitOpen 4:c1beacfc42c7 119 \param [in] lr LR value to set
MikamiUitOpen 4:c1beacfc42c7 120 */
MikamiUitOpen 4:c1beacfc42c7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
MikamiUitOpen 4:c1beacfc42c7 122 {
MikamiUitOpen 4:c1beacfc42c7 123 __reglr = lr;
MikamiUitOpen 4:c1beacfc42c7 124 }
MikamiUitOpen 4:c1beacfc42c7 125
MikamiUitOpen 4:c1beacfc42c7 126 /** \brief Set Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 127
MikamiUitOpen 4:c1beacfc42c7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 131 */
MikamiUitOpen 4:c1beacfc42c7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 4:c1beacfc42c7 133 {
MikamiUitOpen 4:c1beacfc42c7 134 ARM
MikamiUitOpen 4:c1beacfc42c7 135 PRESERVE8
MikamiUitOpen 4:c1beacfc42c7 136
MikamiUitOpen 4:c1beacfc42c7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
MikamiUitOpen 4:c1beacfc42c7 138 MRS R1, CPSR
MikamiUitOpen 4:c1beacfc42c7 139 CPS #MODE_SYS ;no effect in USR mode
MikamiUitOpen 4:c1beacfc42c7 140 MOV SP, R0
MikamiUitOpen 4:c1beacfc42c7 141 MSR CPSR_c, R1 ;no effect in USR mode
MikamiUitOpen 4:c1beacfc42c7 142 ISB
MikamiUitOpen 4:c1beacfc42c7 143 BX LR
MikamiUitOpen 4:c1beacfc42c7 144
MikamiUitOpen 4:c1beacfc42c7 145 }
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 /** \brief Set User Mode
MikamiUitOpen 4:c1beacfc42c7 148
MikamiUitOpen 4:c1beacfc42c7 149 This function changes the processor state to User Mode
MikamiUitOpen 4:c1beacfc42c7 150 */
MikamiUitOpen 4:c1beacfc42c7 151 __STATIC_ASM void __set_CPS_USR(void)
MikamiUitOpen 4:c1beacfc42c7 152 {
MikamiUitOpen 4:c1beacfc42c7 153 ARM
MikamiUitOpen 4:c1beacfc42c7 154
MikamiUitOpen 4:c1beacfc42c7 155 CPS #MODE_USR
MikamiUitOpen 4:c1beacfc42c7 156 BX LR
MikamiUitOpen 4:c1beacfc42c7 157 }
MikamiUitOpen 4:c1beacfc42c7 158
MikamiUitOpen 4:c1beacfc42c7 159
MikamiUitOpen 4:c1beacfc42c7 160 /** \brief Enable FIQ
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 163 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 164 */
MikamiUitOpen 4:c1beacfc42c7 165 #define __enable_fault_irq __enable_fiq
MikamiUitOpen 4:c1beacfc42c7 166
MikamiUitOpen 4:c1beacfc42c7 167
MikamiUitOpen 4:c1beacfc42c7 168 /** \brief Disable FIQ
MikamiUitOpen 4:c1beacfc42c7 169
MikamiUitOpen 4:c1beacfc42c7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 171 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 172 */
MikamiUitOpen 4:c1beacfc42c7 173 #define __disable_fault_irq __disable_fiq
MikamiUitOpen 4:c1beacfc42c7 174
MikamiUitOpen 4:c1beacfc42c7 175
MikamiUitOpen 4:c1beacfc42c7 176 /** \brief Get FPSCR
MikamiUitOpen 4:c1beacfc42c7 177
MikamiUitOpen 4:c1beacfc42c7 178 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 179
MikamiUitOpen 4:c1beacfc42c7 180 \return Floating Point Status/Control register value
MikamiUitOpen 4:c1beacfc42c7 181 */
MikamiUitOpen 4:c1beacfc42c7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 4:c1beacfc42c7 183 {
MikamiUitOpen 4:c1beacfc42c7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 185 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 186 return(__regfpscr);
MikamiUitOpen 4:c1beacfc42c7 187 #else
MikamiUitOpen 4:c1beacfc42c7 188 return(0);
MikamiUitOpen 4:c1beacfc42c7 189 #endif
MikamiUitOpen 4:c1beacfc42c7 190 }
MikamiUitOpen 4:c1beacfc42c7 191
MikamiUitOpen 4:c1beacfc42c7 192
MikamiUitOpen 4:c1beacfc42c7 193 /** \brief Set FPSCR
MikamiUitOpen 4:c1beacfc42c7 194
MikamiUitOpen 4:c1beacfc42c7 195 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 196
MikamiUitOpen 4:c1beacfc42c7 197 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 4:c1beacfc42c7 198 */
MikamiUitOpen 4:c1beacfc42c7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 4:c1beacfc42c7 200 {
MikamiUitOpen 4:c1beacfc42c7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 202 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 203 __regfpscr = (fpscr);
MikamiUitOpen 4:c1beacfc42c7 204 #endif
MikamiUitOpen 4:c1beacfc42c7 205 }
MikamiUitOpen 4:c1beacfc42c7 206
MikamiUitOpen 4:c1beacfc42c7 207 /** \brief Get FPEXC
MikamiUitOpen 4:c1beacfc42c7 208
MikamiUitOpen 4:c1beacfc42c7 209 This function returns the current value of the Floating Point Exception Control register.
MikamiUitOpen 4:c1beacfc42c7 210
MikamiUitOpen 4:c1beacfc42c7 211 \return Floating Point Exception Control register value
MikamiUitOpen 4:c1beacfc42c7 212 */
MikamiUitOpen 4:c1beacfc42c7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
MikamiUitOpen 4:c1beacfc42c7 214 {
MikamiUitOpen 4:c1beacfc42c7 215 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 216 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 4:c1beacfc42c7 217 return(__regfpexc);
MikamiUitOpen 4:c1beacfc42c7 218 #else
MikamiUitOpen 4:c1beacfc42c7 219 return(0);
MikamiUitOpen 4:c1beacfc42c7 220 #endif
MikamiUitOpen 4:c1beacfc42c7 221 }
MikamiUitOpen 4:c1beacfc42c7 222
MikamiUitOpen 4:c1beacfc42c7 223
MikamiUitOpen 4:c1beacfc42c7 224 /** \brief Set FPEXC
MikamiUitOpen 4:c1beacfc42c7 225
MikamiUitOpen 4:c1beacfc42c7 226 This function assigns the given value to the Floating Point Exception Control register.
MikamiUitOpen 4:c1beacfc42c7 227
MikamiUitOpen 4:c1beacfc42c7 228 \param [in] fpscr Floating Point Exception Control value to set
MikamiUitOpen 4:c1beacfc42c7 229 */
MikamiUitOpen 4:c1beacfc42c7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MikamiUitOpen 4:c1beacfc42c7 231 {
MikamiUitOpen 4:c1beacfc42c7 232 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 233 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 4:c1beacfc42c7 234 __regfpexc = (fpexc);
MikamiUitOpen 4:c1beacfc42c7 235 #endif
MikamiUitOpen 4:c1beacfc42c7 236 }
MikamiUitOpen 4:c1beacfc42c7 237
MikamiUitOpen 4:c1beacfc42c7 238 /** \brief Get CPACR
MikamiUitOpen 4:c1beacfc42c7 239
MikamiUitOpen 4:c1beacfc42c7 240 This function returns the current value of the Coprocessor Access Control register.
MikamiUitOpen 4:c1beacfc42c7 241
MikamiUitOpen 4:c1beacfc42c7 242 \return Coprocessor Access Control register value
MikamiUitOpen 4:c1beacfc42c7 243 */
MikamiUitOpen 4:c1beacfc42c7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
MikamiUitOpen 4:c1beacfc42c7 245 {
MikamiUitOpen 4:c1beacfc42c7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 4:c1beacfc42c7 247 return __regCPACR;
MikamiUitOpen 4:c1beacfc42c7 248 }
MikamiUitOpen 4:c1beacfc42c7 249
MikamiUitOpen 4:c1beacfc42c7 250 /** \brief Set CPACR
MikamiUitOpen 4:c1beacfc42c7 251
MikamiUitOpen 4:c1beacfc42c7 252 This function assigns the given value to the Coprocessor Access Control register.
MikamiUitOpen 4:c1beacfc42c7 253
MikamiUitOpen 4:c1beacfc42c7 254 \param [in] cpacr Coprocessor Acccess Control value to set
MikamiUitOpen 4:c1beacfc42c7 255 */
MikamiUitOpen 4:c1beacfc42c7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MikamiUitOpen 4:c1beacfc42c7 257 {
MikamiUitOpen 4:c1beacfc42c7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 4:c1beacfc42c7 259 __regCPACR = cpacr;
MikamiUitOpen 4:c1beacfc42c7 260 __ISB();
MikamiUitOpen 4:c1beacfc42c7 261 }
MikamiUitOpen 4:c1beacfc42c7 262
MikamiUitOpen 4:c1beacfc42c7 263 /** \brief Get CBAR
MikamiUitOpen 4:c1beacfc42c7 264
MikamiUitOpen 4:c1beacfc42c7 265 This function returns the value of the Configuration Base Address register.
MikamiUitOpen 4:c1beacfc42c7 266
MikamiUitOpen 4:c1beacfc42c7 267 \return Configuration Base Address register value
MikamiUitOpen 4:c1beacfc42c7 268 */
MikamiUitOpen 4:c1beacfc42c7 269 __STATIC_INLINE uint32_t __get_CBAR() {
MikamiUitOpen 4:c1beacfc42c7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MikamiUitOpen 4:c1beacfc42c7 271 return(__regCBAR);
MikamiUitOpen 4:c1beacfc42c7 272 }
MikamiUitOpen 4:c1beacfc42c7 273
MikamiUitOpen 4:c1beacfc42c7 274 /** \brief Get TTBR0
MikamiUitOpen 4:c1beacfc42c7 275
MikamiUitOpen 4:c1beacfc42c7 276 This function returns the value of the Translation Table Base Register 0.
MikamiUitOpen 4:c1beacfc42c7 277
MikamiUitOpen 4:c1beacfc42c7 278 \return Translation Table Base Register 0 value
MikamiUitOpen 4:c1beacfc42c7 279 */
MikamiUitOpen 4:c1beacfc42c7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
MikamiUitOpen 4:c1beacfc42c7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 4:c1beacfc42c7 282 return(__regTTBR0);
MikamiUitOpen 4:c1beacfc42c7 283 }
MikamiUitOpen 4:c1beacfc42c7 284
MikamiUitOpen 4:c1beacfc42c7 285 /** \brief Set TTBR0
MikamiUitOpen 4:c1beacfc42c7 286
MikamiUitOpen 4:c1beacfc42c7 287 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 4:c1beacfc42c7 288
MikamiUitOpen 4:c1beacfc42c7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 4:c1beacfc42c7 290 */
MikamiUitOpen 4:c1beacfc42c7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 4:c1beacfc42c7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 4:c1beacfc42c7 293 __regTTBR0 = ttbr0;
MikamiUitOpen 4:c1beacfc42c7 294 __ISB();
MikamiUitOpen 4:c1beacfc42c7 295 }
MikamiUitOpen 4:c1beacfc42c7 296
MikamiUitOpen 4:c1beacfc42c7 297 /** \brief Get DACR
MikamiUitOpen 4:c1beacfc42c7 298
MikamiUitOpen 4:c1beacfc42c7 299 This function returns the value of the Domain Access Control Register.
MikamiUitOpen 4:c1beacfc42c7 300
MikamiUitOpen 4:c1beacfc42c7 301 \return Domain Access Control Register value
MikamiUitOpen 4:c1beacfc42c7 302 */
MikamiUitOpen 4:c1beacfc42c7 303 __STATIC_INLINE uint32_t __get_DACR() {
MikamiUitOpen 4:c1beacfc42c7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 4:c1beacfc42c7 305 return(__regDACR);
MikamiUitOpen 4:c1beacfc42c7 306 }
MikamiUitOpen 4:c1beacfc42c7 307
MikamiUitOpen 4:c1beacfc42c7 308 /** \brief Set DACR
MikamiUitOpen 4:c1beacfc42c7 309
MikamiUitOpen 4:c1beacfc42c7 310 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 4:c1beacfc42c7 311
MikamiUitOpen 4:c1beacfc42c7 312 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 313 */
MikamiUitOpen 4:c1beacfc42c7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 4:c1beacfc42c7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 4:c1beacfc42c7 316 __regDACR = dacr;
MikamiUitOpen 4:c1beacfc42c7 317 __ISB();
MikamiUitOpen 4:c1beacfc42c7 318 }
MikamiUitOpen 4:c1beacfc42c7 319
MikamiUitOpen 4:c1beacfc42c7 320 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 4:c1beacfc42c7 321
MikamiUitOpen 4:c1beacfc42c7 322 /** \brief Set SCTLR
MikamiUitOpen 4:c1beacfc42c7 323
MikamiUitOpen 4:c1beacfc42c7 324 This function assigns the given value to the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 325
MikamiUitOpen 4:c1beacfc42c7 326 \param [in] sctlr System Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 327 */
MikamiUitOpen 4:c1beacfc42c7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MikamiUitOpen 4:c1beacfc42c7 329 {
MikamiUitOpen 4:c1beacfc42c7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 4:c1beacfc42c7 331 __regSCTLR = sctlr;
MikamiUitOpen 4:c1beacfc42c7 332 }
MikamiUitOpen 4:c1beacfc42c7 333
MikamiUitOpen 4:c1beacfc42c7 334 /** \brief Get SCTLR
MikamiUitOpen 4:c1beacfc42c7 335
MikamiUitOpen 4:c1beacfc42c7 336 This function returns the value of the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 337
MikamiUitOpen 4:c1beacfc42c7 338 \return System Control Register value
MikamiUitOpen 4:c1beacfc42c7 339 */
MikamiUitOpen 4:c1beacfc42c7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 4:c1beacfc42c7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 4:c1beacfc42c7 342 return(__regSCTLR);
MikamiUitOpen 4:c1beacfc42c7 343 }
MikamiUitOpen 4:c1beacfc42c7 344
MikamiUitOpen 4:c1beacfc42c7 345 /** \brief Enable Caches
MikamiUitOpen 4:c1beacfc42c7 346
MikamiUitOpen 4:c1beacfc42c7 347 Enable Caches
MikamiUitOpen 4:c1beacfc42c7 348 */
MikamiUitOpen 4:c1beacfc42c7 349 __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 4:c1beacfc42c7 350 // Set I bit 12 to enable I Cache
MikamiUitOpen 4:c1beacfc42c7 351 // Set C bit 2 to enable D Cache
MikamiUitOpen 4:c1beacfc42c7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 4:c1beacfc42c7 353 }
MikamiUitOpen 4:c1beacfc42c7 354
MikamiUitOpen 4:c1beacfc42c7 355 /** \brief Disable Caches
MikamiUitOpen 4:c1beacfc42c7 356
MikamiUitOpen 4:c1beacfc42c7 357 Disable Caches
MikamiUitOpen 4:c1beacfc42c7 358 */
MikamiUitOpen 4:c1beacfc42c7 359 __STATIC_INLINE void __disable_caches(void) {
MikamiUitOpen 4:c1beacfc42c7 360 // Clear I bit 12 to disable I Cache
MikamiUitOpen 4:c1beacfc42c7 361 // Clear C bit 2 to disable D Cache
MikamiUitOpen 4:c1beacfc42c7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MikamiUitOpen 4:c1beacfc42c7 363 __ISB();
MikamiUitOpen 4:c1beacfc42c7 364 }
MikamiUitOpen 4:c1beacfc42c7 365
MikamiUitOpen 4:c1beacfc42c7 366 /** \brief Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 367
MikamiUitOpen 4:c1beacfc42c7 368 Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 369 */
MikamiUitOpen 4:c1beacfc42c7 370 __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 371 // Set Z bit 11 to enable branch prediction
MikamiUitOpen 4:c1beacfc42c7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 4:c1beacfc42c7 373 __ISB();
MikamiUitOpen 4:c1beacfc42c7 374 }
MikamiUitOpen 4:c1beacfc42c7 375
MikamiUitOpen 4:c1beacfc42c7 376 /** \brief Disable BTAC
MikamiUitOpen 4:c1beacfc42c7 377
MikamiUitOpen 4:c1beacfc42c7 378 Disable BTAC
MikamiUitOpen 4:c1beacfc42c7 379 */
MikamiUitOpen 4:c1beacfc42c7 380 __STATIC_INLINE void __disable_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 381 // Clear Z bit 11 to disable branch prediction
MikamiUitOpen 4:c1beacfc42c7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MikamiUitOpen 4:c1beacfc42c7 383 }
MikamiUitOpen 4:c1beacfc42c7 384
MikamiUitOpen 4:c1beacfc42c7 385
MikamiUitOpen 4:c1beacfc42c7 386 /** \brief Enable MMU
MikamiUitOpen 4:c1beacfc42c7 387
MikamiUitOpen 4:c1beacfc42c7 388 Enable MMU
MikamiUitOpen 4:c1beacfc42c7 389 */
MikamiUitOpen 4:c1beacfc42c7 390 __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 4:c1beacfc42c7 391 // Set M bit 0 to enable the MMU
MikamiUitOpen 4:c1beacfc42c7 392 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 4:c1beacfc42c7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 4:c1beacfc42c7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 4:c1beacfc42c7 395 __ISB();
MikamiUitOpen 4:c1beacfc42c7 396 }
MikamiUitOpen 4:c1beacfc42c7 397
MikamiUitOpen 4:c1beacfc42c7 398 /** \brief Disable MMU
MikamiUitOpen 4:c1beacfc42c7 399
MikamiUitOpen 4:c1beacfc42c7 400 Disable MMU
MikamiUitOpen 4:c1beacfc42c7 401 */
MikamiUitOpen 4:c1beacfc42c7 402 __STATIC_INLINE void __disable_mmu(void) {
MikamiUitOpen 4:c1beacfc42c7 403 // Clear M bit 0 to disable the MMU
MikamiUitOpen 4:c1beacfc42c7 404 __set_SCTLR( __get_SCTLR() & ~1);
MikamiUitOpen 4:c1beacfc42c7 405 __ISB();
MikamiUitOpen 4:c1beacfc42c7 406 }
MikamiUitOpen 4:c1beacfc42c7 407
MikamiUitOpen 4:c1beacfc42c7 408 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 409 /** \brief Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 410
MikamiUitOpen 4:c1beacfc42c7 411 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 412 */
MikamiUitOpen 4:c1beacfc42c7 413
MikamiUitOpen 4:c1beacfc42c7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 4:c1beacfc42c7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MikamiUitOpen 4:c1beacfc42c7 416 __TLBIALL = 0;
MikamiUitOpen 4:c1beacfc42c7 417 __DSB();
MikamiUitOpen 4:c1beacfc42c7 418 __ISB();
MikamiUitOpen 4:c1beacfc42c7 419 }
MikamiUitOpen 4:c1beacfc42c7 420
MikamiUitOpen 4:c1beacfc42c7 421 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 422 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 4:c1beacfc42c7 423
MikamiUitOpen 4:c1beacfc42c7 424 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 4:c1beacfc42c7 425 */
MikamiUitOpen 4:c1beacfc42c7 426
MikamiUitOpen 4:c1beacfc42c7 427 __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MikamiUitOpen 4:c1beacfc42c7 429 __BPIALL = 0;
MikamiUitOpen 4:c1beacfc42c7 430 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 431 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 4:c1beacfc42c7 432 }
MikamiUitOpen 4:c1beacfc42c7 433
MikamiUitOpen 4:c1beacfc42c7 434
MikamiUitOpen 4:c1beacfc42c7 435 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 4:c1beacfc42c7 436
MikamiUitOpen 4:c1beacfc42c7 437 /** \brief Invalidate the whole I$
MikamiUitOpen 4:c1beacfc42c7 438
MikamiUitOpen 4:c1beacfc42c7 439 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 4:c1beacfc42c7 440 */
MikamiUitOpen 4:c1beacfc42c7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MikamiUitOpen 4:c1beacfc42c7 443 __ICIALLU = 0;
MikamiUitOpen 4:c1beacfc42c7 444 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 445 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 4:c1beacfc42c7 446 }
MikamiUitOpen 4:c1beacfc42c7 447
MikamiUitOpen 4:c1beacfc42c7 448 /** \brief Clean D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 449
MikamiUitOpen 4:c1beacfc42c7 450 DCCMVAC. Data cache clean by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 451 */
MikamiUitOpen 4:c1beacfc42c7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MikamiUitOpen 4:c1beacfc42c7 454 __DCCMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 456 }
MikamiUitOpen 4:c1beacfc42c7 457
MikamiUitOpen 4:c1beacfc42c7 458 /** \brief Invalidate D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 459
MikamiUitOpen 4:c1beacfc42c7 460 DCIMVAC. Data cache invalidate by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 461 */
MikamiUitOpen 4:c1beacfc42c7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MikamiUitOpen 4:c1beacfc42c7 464 __DCIMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 466 }
MikamiUitOpen 4:c1beacfc42c7 467
MikamiUitOpen 4:c1beacfc42c7 468 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 469
MikamiUitOpen 4:c1beacfc42c7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 471 */
MikamiUitOpen 4:c1beacfc42c7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MikamiUitOpen 4:c1beacfc42c7 474 __DCCIMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 476 }
MikamiUitOpen 4:c1beacfc42c7 477
MikamiUitOpen 4:c1beacfc42c7 478 /** \brief Clean and Invalidate the entire data or unified cache
MikamiUitOpen 4:c1beacfc42c7 479
MikamiUitOpen 4:c1beacfc42c7 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MikamiUitOpen 4:c1beacfc42c7 481 */
MikamiUitOpen 4:c1beacfc42c7 482 #pragma push
MikamiUitOpen 4:c1beacfc42c7 483 #pragma arm
MikamiUitOpen 4:c1beacfc42c7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
MikamiUitOpen 4:c1beacfc42c7 485 ARM
MikamiUitOpen 4:c1beacfc42c7 486
MikamiUitOpen 4:c1beacfc42c7 487 PUSH {R4-R11}
MikamiUitOpen 4:c1beacfc42c7 488
MikamiUitOpen 4:c1beacfc42c7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
MikamiUitOpen 4:c1beacfc42c7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
MikamiUitOpen 4:c1beacfc42c7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
MikamiUitOpen 4:c1beacfc42c7 492 BEQ Finished // If 0, no need to clean
MikamiUitOpen 4:c1beacfc42c7 493
MikamiUitOpen 4:c1beacfc42c7 494 MOV R10, #0 // R10 holds current cache level << 1
MikamiUitOpen 4:c1beacfc42c7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
MikamiUitOpen 4:c1beacfc42c7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
MikamiUitOpen 4:c1beacfc42c7 497 AND R1, R1, #7 // Isolate those lower 3 bits
MikamiUitOpen 4:c1beacfc42c7 498 CMP R1, #2
MikamiUitOpen 4:c1beacfc42c7 499 BLT Skip // No cache or only instruction cache at this level
MikamiUitOpen 4:c1beacfc42c7 500
MikamiUitOpen 4:c1beacfc42c7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
MikamiUitOpen 4:c1beacfc42c7 502 ISB // ISB to sync the change to the CacheSizeID reg
MikamiUitOpen 4:c1beacfc42c7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
MikamiUitOpen 4:c1beacfc42c7 504 AND R2, R1, #7 // Extract the line length field
MikamiUitOpen 4:c1beacfc42c7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
MikamiUitOpen 4:c1beacfc42c7 506 LDR R4, =0x3FF
MikamiUitOpen 4:c1beacfc42c7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
MikamiUitOpen 4:c1beacfc42c7 509 LDR R7, =0x7FFF
MikamiUitOpen 4:c1beacfc42c7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 511
MikamiUitOpen 4:c1beacfc42c7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 513
MikamiUitOpen 4:c1beacfc42c7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
MikamiUitOpen 4:c1beacfc42c7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
MikamiUitOpen 4:c1beacfc42c7 516 CMP R0, #0
MikamiUitOpen 4:c1beacfc42c7 517 BNE Dccsw
MikamiUitOpen 4:c1beacfc42c7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 519 B cont
MikamiUitOpen 4:c1beacfc42c7 520 Dccsw CMP R0, #1
MikamiUitOpen 4:c1beacfc42c7 521 BNE Dccisw
MikamiUitOpen 4:c1beacfc42c7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
MikamiUitOpen 4:c1beacfc42c7 523 B cont
MikamiUitOpen 4:c1beacfc42c7 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 525 cont SUBS R9, R9, #1 // Decrement the Way number
MikamiUitOpen 4:c1beacfc42c7 526 BGE Loop3
MikamiUitOpen 4:c1beacfc42c7 527 SUBS R7, R7, #1 // Decrement the Set number
MikamiUitOpen 4:c1beacfc42c7 528 BGE Loop2
MikamiUitOpen 4:c1beacfc42c7 529 Skip ADD R10, R10, #2 // Increment the cache number
MikamiUitOpen 4:c1beacfc42c7 530 CMP R3, R10
MikamiUitOpen 4:c1beacfc42c7 531 BGT Loop1
MikamiUitOpen 4:c1beacfc42c7 532
MikamiUitOpen 4:c1beacfc42c7 533 Finished
MikamiUitOpen 4:c1beacfc42c7 534 DSB
MikamiUitOpen 4:c1beacfc42c7 535 POP {R4-R11}
MikamiUitOpen 4:c1beacfc42c7 536 BX lr
MikamiUitOpen 4:c1beacfc42c7 537
MikamiUitOpen 4:c1beacfc42c7 538 }
MikamiUitOpen 4:c1beacfc42c7 539 #pragma pop
MikamiUitOpen 4:c1beacfc42c7 540
MikamiUitOpen 4:c1beacfc42c7 541
MikamiUitOpen 4:c1beacfc42c7 542 /** \brief Invalidate the whole D$
MikamiUitOpen 4:c1beacfc42c7 543
MikamiUitOpen 4:c1beacfc42c7 544 DCISW. Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 545 */
MikamiUitOpen 4:c1beacfc42c7 546
MikamiUitOpen 4:c1beacfc42c7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 548 __v7_all_cache(0);
MikamiUitOpen 4:c1beacfc42c7 549 }
MikamiUitOpen 4:c1beacfc42c7 550
MikamiUitOpen 4:c1beacfc42c7 551 /** \brief Clean the whole D$
MikamiUitOpen 4:c1beacfc42c7 552
MikamiUitOpen 4:c1beacfc42c7 553 DCCSW. Clean by Set/Way
MikamiUitOpen 4:c1beacfc42c7 554 */
MikamiUitOpen 4:c1beacfc42c7 555
MikamiUitOpen 4:c1beacfc42c7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 557 __v7_all_cache(1);
MikamiUitOpen 4:c1beacfc42c7 558 }
MikamiUitOpen 4:c1beacfc42c7 559
MikamiUitOpen 4:c1beacfc42c7 560 /** \brief Clean and invalidate the whole D$
MikamiUitOpen 4:c1beacfc42c7 561
MikamiUitOpen 4:c1beacfc42c7 562 DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 563 */
MikamiUitOpen 4:c1beacfc42c7 564
MikamiUitOpen 4:c1beacfc42c7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 566 __v7_all_cache(2);
MikamiUitOpen 4:c1beacfc42c7 567 }
MikamiUitOpen 4:c1beacfc42c7 568
MikamiUitOpen 4:c1beacfc42c7 569 #include "core_ca_mmu.h"
MikamiUitOpen 4:c1beacfc42c7 570
MikamiUitOpen 4:c1beacfc42c7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 572
MikamiUitOpen 4:c1beacfc42c7 573 #define __inline inline
MikamiUitOpen 4:c1beacfc42c7 574
MikamiUitOpen 4:c1beacfc42c7 575 inline static uint32_t __disable_irq_iar() {
MikamiUitOpen 4:c1beacfc42c7 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
MikamiUitOpen 4:c1beacfc42c7 577 __disable_irq();
MikamiUitOpen 4:c1beacfc42c7 578 return irq_dis;
MikamiUitOpen 4:c1beacfc42c7 579 }
MikamiUitOpen 4:c1beacfc42c7 580
MikamiUitOpen 4:c1beacfc42c7 581 #define MODE_USR 0x10
MikamiUitOpen 4:c1beacfc42c7 582 #define MODE_FIQ 0x11
MikamiUitOpen 4:c1beacfc42c7 583 #define MODE_IRQ 0x12
MikamiUitOpen 4:c1beacfc42c7 584 #define MODE_SVC 0x13
MikamiUitOpen 4:c1beacfc42c7 585 #define MODE_MON 0x16
MikamiUitOpen 4:c1beacfc42c7 586 #define MODE_ABT 0x17
MikamiUitOpen 4:c1beacfc42c7 587 #define MODE_HYP 0x1A
MikamiUitOpen 4:c1beacfc42c7 588 #define MODE_UND 0x1B
MikamiUitOpen 4:c1beacfc42c7 589 #define MODE_SYS 0x1F
MikamiUitOpen 4:c1beacfc42c7 590
MikamiUitOpen 4:c1beacfc42c7 591 /** \brief Set Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 592
MikamiUitOpen 4:c1beacfc42c7 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 594
MikamiUitOpen 4:c1beacfc42c7 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 596 */
MikamiUitOpen 4:c1beacfc42c7 597 // from rt_CMSIS.c
MikamiUitOpen 4:c1beacfc42c7 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
MikamiUitOpen 4:c1beacfc42c7 599 __asm(
MikamiUitOpen 4:c1beacfc42c7 600 " ARM\n"
MikamiUitOpen 4:c1beacfc42c7 601 // " PRESERVE8\n"
MikamiUitOpen 4:c1beacfc42c7 602
MikamiUitOpen 4:c1beacfc42c7 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
MikamiUitOpen 4:c1beacfc42c7 604 " MRS R1, CPSR \n"
MikamiUitOpen 4:c1beacfc42c7 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
MikamiUitOpen 4:c1beacfc42c7 606 " MOV SP, R0 \n"
MikamiUitOpen 4:c1beacfc42c7 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
MikamiUitOpen 4:c1beacfc42c7 608 " ISB \n"
MikamiUitOpen 4:c1beacfc42c7 609 " BX LR \n");
MikamiUitOpen 4:c1beacfc42c7 610 }
MikamiUitOpen 4:c1beacfc42c7 611
MikamiUitOpen 4:c1beacfc42c7 612 /** \brief Set User Mode
MikamiUitOpen 4:c1beacfc42c7 613
MikamiUitOpen 4:c1beacfc42c7 614 This function changes the processor state to User Mode
MikamiUitOpen 4:c1beacfc42c7 615 */
MikamiUitOpen 4:c1beacfc42c7 616 // from rt_CMSIS.c
MikamiUitOpen 4:c1beacfc42c7 617 __arm static inline void __set_CPS_USR(void) {
MikamiUitOpen 4:c1beacfc42c7 618 __asm(
MikamiUitOpen 4:c1beacfc42c7 619 " ARM \n"
MikamiUitOpen 4:c1beacfc42c7 620
MikamiUitOpen 4:c1beacfc42c7 621 " CPS #0x10 \n" // MODE_USR
MikamiUitOpen 4:c1beacfc42c7 622 " BX LR\n");
MikamiUitOpen 4:c1beacfc42c7 623 }
MikamiUitOpen 4:c1beacfc42c7 624
MikamiUitOpen 4:c1beacfc42c7 625 /** \brief Set TTBR0
MikamiUitOpen 4:c1beacfc42c7 626
MikamiUitOpen 4:c1beacfc42c7 627 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 4:c1beacfc42c7 628
MikamiUitOpen 4:c1beacfc42c7 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 4:c1beacfc42c7 630 */
MikamiUitOpen 4:c1beacfc42c7 631 // from mmu_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 4:c1beacfc42c7 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 634 __ISB();
MikamiUitOpen 4:c1beacfc42c7 635 }
MikamiUitOpen 4:c1beacfc42c7 636
MikamiUitOpen 4:c1beacfc42c7 637 /** \brief Set DACR
MikamiUitOpen 4:c1beacfc42c7 638
MikamiUitOpen 4:c1beacfc42c7 639 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 4:c1beacfc42c7 640
MikamiUitOpen 4:c1beacfc42c7 641 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 642 */
MikamiUitOpen 4:c1beacfc42c7 643 // from mmu_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 4:c1beacfc42c7 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 646 __ISB();
MikamiUitOpen 4:c1beacfc42c7 647 }
MikamiUitOpen 4:c1beacfc42c7 648
MikamiUitOpen 4:c1beacfc42c7 649
MikamiUitOpen 4:c1beacfc42c7 650 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 4:c1beacfc42c7 651 /** \brief Set SCTLR
MikamiUitOpen 4:c1beacfc42c7 652
MikamiUitOpen 4:c1beacfc42c7 653 This function assigns the given value to the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 654
MikamiUitOpen 4:c1beacfc42c7 655 \param [in] sctlr System Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 656 */
MikamiUitOpen 4:c1beacfc42c7 657 // from __enable_mmu()
MikamiUitOpen 4:c1beacfc42c7 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
MikamiUitOpen 4:c1beacfc42c7 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 660 }
MikamiUitOpen 4:c1beacfc42c7 661
MikamiUitOpen 4:c1beacfc42c7 662 /** \brief Get SCTLR
MikamiUitOpen 4:c1beacfc42c7 663
MikamiUitOpen 4:c1beacfc42c7 664 This function returns the value of the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 665
MikamiUitOpen 4:c1beacfc42c7 666 \return System Control Register value
MikamiUitOpen 4:c1beacfc42c7 667 */
MikamiUitOpen 4:c1beacfc42c7 668 // from __enable_mmu()
MikamiUitOpen 4:c1beacfc42c7 669 __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 4:c1beacfc42c7 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
MikamiUitOpen 4:c1beacfc42c7 671 return __regSCTLR;
MikamiUitOpen 4:c1beacfc42c7 672 }
MikamiUitOpen 4:c1beacfc42c7 673
MikamiUitOpen 4:c1beacfc42c7 674 /** \brief Enable Caches
MikamiUitOpen 4:c1beacfc42c7 675
MikamiUitOpen 4:c1beacfc42c7 676 Enable Caches
MikamiUitOpen 4:c1beacfc42c7 677 */
MikamiUitOpen 4:c1beacfc42c7 678 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 679 __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 4:c1beacfc42c7 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 4:c1beacfc42c7 681 }
MikamiUitOpen 4:c1beacfc42c7 682
MikamiUitOpen 4:c1beacfc42c7 683 /** \brief Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 684
MikamiUitOpen 4:c1beacfc42c7 685 Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 686 */
MikamiUitOpen 4:c1beacfc42c7 687 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 688 __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 4:c1beacfc42c7 690 __ISB();
MikamiUitOpen 4:c1beacfc42c7 691 }
MikamiUitOpen 4:c1beacfc42c7 692
MikamiUitOpen 4:c1beacfc42c7 693 /** \brief Enable MMU
MikamiUitOpen 4:c1beacfc42c7 694
MikamiUitOpen 4:c1beacfc42c7 695 Enable MMU
MikamiUitOpen 4:c1beacfc42c7 696 */
MikamiUitOpen 4:c1beacfc42c7 697 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 698 __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 4:c1beacfc42c7 699 // Set M bit 0 to enable the MMU
MikamiUitOpen 4:c1beacfc42c7 700 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 4:c1beacfc42c7 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 4:c1beacfc42c7 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 4:c1beacfc42c7 703 __ISB();
MikamiUitOpen 4:c1beacfc42c7 704 }
MikamiUitOpen 4:c1beacfc42c7 705
MikamiUitOpen 4:c1beacfc42c7 706 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 707 /** \brief Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 708
MikamiUitOpen 4:c1beacfc42c7 709 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 710 */
MikamiUitOpen 4:c1beacfc42c7 711 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 4:c1beacfc42c7 713 uint32_t val = 0;
MikamiUitOpen 4:c1beacfc42c7 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 717 __DSB();
MikamiUitOpen 4:c1beacfc42c7 718 __ISB();
MikamiUitOpen 4:c1beacfc42c7 719 }
MikamiUitOpen 4:c1beacfc42c7 720
MikamiUitOpen 4:c1beacfc42c7 721 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 722 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 4:c1beacfc42c7 723
MikamiUitOpen 4:c1beacfc42c7 724 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 4:c1beacfc42c7 725 */
MikamiUitOpen 4:c1beacfc42c7 726 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 727 __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 728 uint32_t val = 0;
MikamiUitOpen 4:c1beacfc42c7 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 730 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 731 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 4:c1beacfc42c7 732 }
MikamiUitOpen 4:c1beacfc42c7 733
MikamiUitOpen 4:c1beacfc42c7 734
MikamiUitOpen 4:c1beacfc42c7 735 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 4:c1beacfc42c7 736
MikamiUitOpen 4:c1beacfc42c7 737 /** \brief Invalidate the whole I$
MikamiUitOpen 4:c1beacfc42c7 738
MikamiUitOpen 4:c1beacfc42c7 739 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 4:c1beacfc42c7 740 */
MikamiUitOpen 4:c1beacfc42c7 741 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 743 uint32_t val = 0;
MikamiUitOpen 4:c1beacfc42c7 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
MikamiUitOpen 4:c1beacfc42c7 745 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 746 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 4:c1beacfc42c7 747 }
MikamiUitOpen 4:c1beacfc42c7 748
MikamiUitOpen 4:c1beacfc42c7 749 // from __v7_inv_dcache_all()
MikamiUitOpen 4:c1beacfc42c7 750 __arm static inline void __v7_all_cache(uint32_t op) {
MikamiUitOpen 4:c1beacfc42c7 751 __asm(
MikamiUitOpen 4:c1beacfc42c7 752 " ARM \n"
MikamiUitOpen 4:c1beacfc42c7 753
MikamiUitOpen 4:c1beacfc42c7 754 " PUSH {R4-R11} \n"
MikamiUitOpen 4:c1beacfc42c7 755
MikamiUitOpen 4:c1beacfc42c7 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
MikamiUitOpen 4:c1beacfc42c7 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
MikamiUitOpen 4:c1beacfc42c7 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
MikamiUitOpen 4:c1beacfc42c7 759 " BEQ Finished\n" // If 0, no need to clean
MikamiUitOpen 4:c1beacfc42c7 760
MikamiUitOpen 4:c1beacfc42c7 761 " MOV R10, #0\n" // R10 holds current cache level << 1
MikamiUitOpen 4:c1beacfc42c7 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
MikamiUitOpen 4:c1beacfc42c7 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
MikamiUitOpen 4:c1beacfc42c7 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
MikamiUitOpen 4:c1beacfc42c7 765 " CMP R1, #2 \n"
MikamiUitOpen 4:c1beacfc42c7 766 " BLT Skip \n" // No cache or only instruction cache at this level
MikamiUitOpen 4:c1beacfc42c7 767
MikamiUitOpen 4:c1beacfc42c7 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
MikamiUitOpen 4:c1beacfc42c7 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
MikamiUitOpen 4:c1beacfc42c7 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
MikamiUitOpen 4:c1beacfc42c7 771 " AND R2, R1, #7 \n" // Extract the line length field
MikamiUitOpen 4:c1beacfc42c7 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
MikamiUitOpen 4:c1beacfc42c7 773 " movw R4, #0x3FF \n"
MikamiUitOpen 4:c1beacfc42c7 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
MikamiUitOpen 4:c1beacfc42c7 776 " movw R7, #0x7FFF \n"
MikamiUitOpen 4:c1beacfc42c7 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 778
MikamiUitOpen 4:c1beacfc42c7 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
MikamiUitOpen 4:c1beacfc42c7 780
MikamiUitOpen 4:c1beacfc42c7 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
MikamiUitOpen 4:c1beacfc42c7 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
MikamiUitOpen 4:c1beacfc42c7 783 " CMP R0, #0 \n"
MikamiUitOpen 4:c1beacfc42c7 784 " BNE Dccsw \n"
MikamiUitOpen 4:c1beacfc42c7 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 786 " B cont \n"
MikamiUitOpen 4:c1beacfc42c7 787 "Dccsw: CMP R0, #1 \n"
MikamiUitOpen 4:c1beacfc42c7 788 " BNE Dccisw \n"
MikamiUitOpen 4:c1beacfc42c7 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
MikamiUitOpen 4:c1beacfc42c7 790 " B cont \n"
MikamiUitOpen 4:c1beacfc42c7 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
MikamiUitOpen 4:c1beacfc42c7 793 " BGE Loop3 \n"
MikamiUitOpen 4:c1beacfc42c7 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
MikamiUitOpen 4:c1beacfc42c7 795 " BGE Loop2 \n"
MikamiUitOpen 4:c1beacfc42c7 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
MikamiUitOpen 4:c1beacfc42c7 797 " CMP R3, R10 \n"
MikamiUitOpen 4:c1beacfc42c7 798 " BGT Loop1 \n"
MikamiUitOpen 4:c1beacfc42c7 799
MikamiUitOpen 4:c1beacfc42c7 800 "Finished: \n"
MikamiUitOpen 4:c1beacfc42c7 801 " DSB \n"
MikamiUitOpen 4:c1beacfc42c7 802 " POP {R4-R11} \n"
MikamiUitOpen 4:c1beacfc42c7 803 " BX lr \n" );
MikamiUitOpen 4:c1beacfc42c7 804 }
MikamiUitOpen 4:c1beacfc42c7 805
MikamiUitOpen 4:c1beacfc42c7 806 /** \brief Invalidate the whole D$
MikamiUitOpen 4:c1beacfc42c7 807
MikamiUitOpen 4:c1beacfc42c7 808 DCISW. Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 809 */
MikamiUitOpen 4:c1beacfc42c7 810 // from system_Renesas_RZ_A1.c
MikamiUitOpen 4:c1beacfc42c7 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 812 __v7_all_cache(0);
MikamiUitOpen 4:c1beacfc42c7 813 }
MikamiUitOpen 4:c1beacfc42c7 814 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 815
MikamiUitOpen 4:c1beacfc42c7 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 817 */
MikamiUitOpen 4:c1beacfc42c7 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
MikamiUitOpen 4:c1beacfc42c7 820 __DMB();
MikamiUitOpen 4:c1beacfc42c7 821 }
MikamiUitOpen 4:c1beacfc42c7 822
MikamiUitOpen 4:c1beacfc42c7 823 #include "core_ca_mmu.h"
MikamiUitOpen 4:c1beacfc42c7 824
MikamiUitOpen 4:c1beacfc42c7 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 826 /* GNU gcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 827
MikamiUitOpen 4:c1beacfc42c7 828 #define MODE_USR 0x10
MikamiUitOpen 4:c1beacfc42c7 829 #define MODE_FIQ 0x11
MikamiUitOpen 4:c1beacfc42c7 830 #define MODE_IRQ 0x12
MikamiUitOpen 4:c1beacfc42c7 831 #define MODE_SVC 0x13
MikamiUitOpen 4:c1beacfc42c7 832 #define MODE_MON 0x16
MikamiUitOpen 4:c1beacfc42c7 833 #define MODE_ABT 0x17
MikamiUitOpen 4:c1beacfc42c7 834 #define MODE_HYP 0x1A
MikamiUitOpen 4:c1beacfc42c7 835 #define MODE_UND 0x1B
MikamiUitOpen 4:c1beacfc42c7 836 #define MODE_SYS 0x1F
MikamiUitOpen 4:c1beacfc42c7 837
MikamiUitOpen 4:c1beacfc42c7 838
MikamiUitOpen 4:c1beacfc42c7 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
MikamiUitOpen 4:c1beacfc42c7 840 {
MikamiUitOpen 4:c1beacfc42c7 841 __ASM volatile ("cpsie i");
MikamiUitOpen 4:c1beacfc42c7 842 }
MikamiUitOpen 4:c1beacfc42c7 843
MikamiUitOpen 4:c1beacfc42c7 844 /** \brief Disable IRQ Interrupts
MikamiUitOpen 4:c1beacfc42c7 845
MikamiUitOpen 4:c1beacfc42c7 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 847 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 848 */
MikamiUitOpen 4:c1beacfc42c7 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
MikamiUitOpen 4:c1beacfc42c7 850 {
MikamiUitOpen 4:c1beacfc42c7 851 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 852
MikamiUitOpen 4:c1beacfc42c7 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
MikamiUitOpen 4:c1beacfc42c7 854 __ASM volatile ("cpsid i");
MikamiUitOpen 4:c1beacfc42c7 855 return(result & 0x80);
MikamiUitOpen 4:c1beacfc42c7 856 }
MikamiUitOpen 4:c1beacfc42c7 857
MikamiUitOpen 4:c1beacfc42c7 858
MikamiUitOpen 4:c1beacfc42c7 859 /** \brief Get APSR Register
MikamiUitOpen 4:c1beacfc42c7 860
MikamiUitOpen 4:c1beacfc42c7 861 This function returns the content of the APSR Register.
MikamiUitOpen 4:c1beacfc42c7 862
MikamiUitOpen 4:c1beacfc42c7 863 \return APSR Register value
MikamiUitOpen 4:c1beacfc42c7 864 */
MikamiUitOpen 4:c1beacfc42c7 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
MikamiUitOpen 4:c1beacfc42c7 866 {
MikamiUitOpen 4:c1beacfc42c7 867 #if 1
MikamiUitOpen 4:c1beacfc42c7 868 register uint32_t __regAPSR;
MikamiUitOpen 4:c1beacfc42c7 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
MikamiUitOpen 4:c1beacfc42c7 870 #else
MikamiUitOpen 4:c1beacfc42c7 871 register uint32_t __regAPSR __ASM("apsr");
MikamiUitOpen 4:c1beacfc42c7 872 #endif
MikamiUitOpen 4:c1beacfc42c7 873 return(__regAPSR);
MikamiUitOpen 4:c1beacfc42c7 874 }
MikamiUitOpen 4:c1beacfc42c7 875
MikamiUitOpen 4:c1beacfc42c7 876
MikamiUitOpen 4:c1beacfc42c7 877 /** \brief Get CPSR Register
MikamiUitOpen 4:c1beacfc42c7 878
MikamiUitOpen 4:c1beacfc42c7 879 This function returns the content of the CPSR Register.
MikamiUitOpen 4:c1beacfc42c7 880
MikamiUitOpen 4:c1beacfc42c7 881 \return CPSR Register value
MikamiUitOpen 4:c1beacfc42c7 882 */
MikamiUitOpen 4:c1beacfc42c7 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
MikamiUitOpen 4:c1beacfc42c7 884 {
MikamiUitOpen 4:c1beacfc42c7 885 #if 1
MikamiUitOpen 4:c1beacfc42c7 886 register uint32_t __regCPSR;
MikamiUitOpen 4:c1beacfc42c7 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
MikamiUitOpen 4:c1beacfc42c7 888 #else
MikamiUitOpen 4:c1beacfc42c7 889 register uint32_t __regCPSR __ASM("cpsr");
MikamiUitOpen 4:c1beacfc42c7 890 #endif
MikamiUitOpen 4:c1beacfc42c7 891 return(__regCPSR);
MikamiUitOpen 4:c1beacfc42c7 892 }
MikamiUitOpen 4:c1beacfc42c7 893
MikamiUitOpen 4:c1beacfc42c7 894 #if 0
MikamiUitOpen 4:c1beacfc42c7 895 /** \brief Set Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 896
MikamiUitOpen 4:c1beacfc42c7 897 This function assigns the given value to the current stack pointer.
MikamiUitOpen 4:c1beacfc42c7 898
MikamiUitOpen 4:c1beacfc42c7 899 \param [in] topOfStack Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 900 */
MikamiUitOpen 4:c1beacfc42c7 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
MikamiUitOpen 4:c1beacfc42c7 902 {
MikamiUitOpen 4:c1beacfc42c7 903 register uint32_t __regSP __ASM("sp");
MikamiUitOpen 4:c1beacfc42c7 904 __regSP = topOfStack;
MikamiUitOpen 4:c1beacfc42c7 905 }
MikamiUitOpen 4:c1beacfc42c7 906 #endif
MikamiUitOpen 4:c1beacfc42c7 907
MikamiUitOpen 4:c1beacfc42c7 908 /** \brief Get link register
MikamiUitOpen 4:c1beacfc42c7 909
MikamiUitOpen 4:c1beacfc42c7 910 This function returns the value of the link register
MikamiUitOpen 4:c1beacfc42c7 911
MikamiUitOpen 4:c1beacfc42c7 912 \return Value of link register
MikamiUitOpen 4:c1beacfc42c7 913 */
MikamiUitOpen 4:c1beacfc42c7 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
MikamiUitOpen 4:c1beacfc42c7 915 {
MikamiUitOpen 4:c1beacfc42c7 916 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 4:c1beacfc42c7 917 return(__reglr);
MikamiUitOpen 4:c1beacfc42c7 918 }
MikamiUitOpen 4:c1beacfc42c7 919
MikamiUitOpen 4:c1beacfc42c7 920 #if 0
MikamiUitOpen 4:c1beacfc42c7 921 /** \brief Set link register
MikamiUitOpen 4:c1beacfc42c7 922
MikamiUitOpen 4:c1beacfc42c7 923 This function sets the value of the link register
MikamiUitOpen 4:c1beacfc42c7 924
MikamiUitOpen 4:c1beacfc42c7 925 \param [in] lr LR value to set
MikamiUitOpen 4:c1beacfc42c7 926 */
MikamiUitOpen 4:c1beacfc42c7 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
MikamiUitOpen 4:c1beacfc42c7 928 {
MikamiUitOpen 4:c1beacfc42c7 929 register uint32_t __reglr __ASM("lr");
MikamiUitOpen 4:c1beacfc42c7 930 __reglr = lr;
MikamiUitOpen 4:c1beacfc42c7 931 }
MikamiUitOpen 4:c1beacfc42c7 932 #endif
MikamiUitOpen 4:c1beacfc42c7 933
MikamiUitOpen 4:c1beacfc42c7 934 /** \brief Set Process Stack Pointer
MikamiUitOpen 4:c1beacfc42c7 935
MikamiUitOpen 4:c1beacfc42c7 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
MikamiUitOpen 4:c1beacfc42c7 937
MikamiUitOpen 4:c1beacfc42c7 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
MikamiUitOpen 4:c1beacfc42c7 939 */
MikamiUitOpen 4:c1beacfc42c7 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
MikamiUitOpen 4:c1beacfc42c7 941 {
MikamiUitOpen 4:c1beacfc42c7 942 __asm__ volatile (
MikamiUitOpen 4:c1beacfc42c7 943 ".ARM;"
MikamiUitOpen 4:c1beacfc42c7 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
MikamiUitOpen 4:c1beacfc42c7 945
MikamiUitOpen 4:c1beacfc42c7 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
MikamiUitOpen 4:c1beacfc42c7 947 "MRS R1, CPSR;"
MikamiUitOpen 4:c1beacfc42c7 948 "CPS %0;" /* ;no effect in USR mode */
MikamiUitOpen 4:c1beacfc42c7 949 "MOV SP, R0;"
MikamiUitOpen 4:c1beacfc42c7 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
MikamiUitOpen 4:c1beacfc42c7 951 "ISB;"
MikamiUitOpen 4:c1beacfc42c7 952 //"BX LR;"
MikamiUitOpen 4:c1beacfc42c7 953 :
MikamiUitOpen 4:c1beacfc42c7 954 : "i"(MODE_SYS)
MikamiUitOpen 4:c1beacfc42c7 955 : "r0", "r1");
MikamiUitOpen 4:c1beacfc42c7 956 return;
MikamiUitOpen 4:c1beacfc42c7 957 }
MikamiUitOpen 4:c1beacfc42c7 958
MikamiUitOpen 4:c1beacfc42c7 959 /** \brief Set User Mode
MikamiUitOpen 4:c1beacfc42c7 960
MikamiUitOpen 4:c1beacfc42c7 961 This function changes the processor state to User Mode
MikamiUitOpen 4:c1beacfc42c7 962 */
MikamiUitOpen 4:c1beacfc42c7 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
MikamiUitOpen 4:c1beacfc42c7 964 {
MikamiUitOpen 4:c1beacfc42c7 965 __asm__ volatile (
MikamiUitOpen 4:c1beacfc42c7 966 ".ARM;"
MikamiUitOpen 4:c1beacfc42c7 967
MikamiUitOpen 4:c1beacfc42c7 968 "CPS %0;"
MikamiUitOpen 4:c1beacfc42c7 969 //"BX LR;"
MikamiUitOpen 4:c1beacfc42c7 970 :
MikamiUitOpen 4:c1beacfc42c7 971 : "i"(MODE_USR)
MikamiUitOpen 4:c1beacfc42c7 972 : );
MikamiUitOpen 4:c1beacfc42c7 973 return;
MikamiUitOpen 4:c1beacfc42c7 974 }
MikamiUitOpen 4:c1beacfc42c7 975
MikamiUitOpen 4:c1beacfc42c7 976
MikamiUitOpen 4:c1beacfc42c7 977 /** \brief Enable FIQ
MikamiUitOpen 4:c1beacfc42c7 978
MikamiUitOpen 4:c1beacfc42c7 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 980 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 981 */
MikamiUitOpen 4:c1beacfc42c7 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
MikamiUitOpen 4:c1beacfc42c7 983
MikamiUitOpen 4:c1beacfc42c7 984
MikamiUitOpen 4:c1beacfc42c7 985 /** \brief Disable FIQ
MikamiUitOpen 4:c1beacfc42c7 986
MikamiUitOpen 4:c1beacfc42c7 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
MikamiUitOpen 4:c1beacfc42c7 988 Can only be executed in Privileged modes.
MikamiUitOpen 4:c1beacfc42c7 989 */
MikamiUitOpen 4:c1beacfc42c7 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
MikamiUitOpen 4:c1beacfc42c7 991
MikamiUitOpen 4:c1beacfc42c7 992
MikamiUitOpen 4:c1beacfc42c7 993 /** \brief Get FPSCR
MikamiUitOpen 4:c1beacfc42c7 994
MikamiUitOpen 4:c1beacfc42c7 995 This function returns the current value of the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 996
MikamiUitOpen 4:c1beacfc42c7 997 \return Floating Point Status/Control register value
MikamiUitOpen 4:c1beacfc42c7 998 */
MikamiUitOpen 4:c1beacfc42c7 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
MikamiUitOpen 4:c1beacfc42c7 1000 {
MikamiUitOpen 4:c1beacfc42c7 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 1002 #if 1
MikamiUitOpen 4:c1beacfc42c7 1003 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 1004
MikamiUitOpen 4:c1beacfc42c7 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
MikamiUitOpen 4:c1beacfc42c7 1006 return (result);
MikamiUitOpen 4:c1beacfc42c7 1007 #else
MikamiUitOpen 4:c1beacfc42c7 1008 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 1009 return(__regfpscr);
MikamiUitOpen 4:c1beacfc42c7 1010 #endif
MikamiUitOpen 4:c1beacfc42c7 1011 #else
MikamiUitOpen 4:c1beacfc42c7 1012 return(0);
MikamiUitOpen 4:c1beacfc42c7 1013 #endif
MikamiUitOpen 4:c1beacfc42c7 1014 }
MikamiUitOpen 4:c1beacfc42c7 1015
MikamiUitOpen 4:c1beacfc42c7 1016
MikamiUitOpen 4:c1beacfc42c7 1017 /** \brief Set FPSCR
MikamiUitOpen 4:c1beacfc42c7 1018
MikamiUitOpen 4:c1beacfc42c7 1019 This function assigns the given value to the Floating Point Status/Control register.
MikamiUitOpen 4:c1beacfc42c7 1020
MikamiUitOpen 4:c1beacfc42c7 1021 \param [in] fpscr Floating Point Status/Control value to set
MikamiUitOpen 4:c1beacfc42c7 1022 */
MikamiUitOpen 4:c1beacfc42c7 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
MikamiUitOpen 4:c1beacfc42c7 1024 {
MikamiUitOpen 4:c1beacfc42c7 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MikamiUitOpen 4:c1beacfc42c7 1026 #if 1
MikamiUitOpen 4:c1beacfc42c7 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
MikamiUitOpen 4:c1beacfc42c7 1028 #else
MikamiUitOpen 4:c1beacfc42c7 1029 register uint32_t __regfpscr __ASM("fpscr");
MikamiUitOpen 4:c1beacfc42c7 1030 __regfpscr = (fpscr);
MikamiUitOpen 4:c1beacfc42c7 1031 #endif
MikamiUitOpen 4:c1beacfc42c7 1032 #endif
MikamiUitOpen 4:c1beacfc42c7 1033 }
MikamiUitOpen 4:c1beacfc42c7 1034
MikamiUitOpen 4:c1beacfc42c7 1035 /** \brief Get FPEXC
MikamiUitOpen 4:c1beacfc42c7 1036
MikamiUitOpen 4:c1beacfc42c7 1037 This function returns the current value of the Floating Point Exception Control register.
MikamiUitOpen 4:c1beacfc42c7 1038
MikamiUitOpen 4:c1beacfc42c7 1039 \return Floating Point Exception Control register value
MikamiUitOpen 4:c1beacfc42c7 1040 */
MikamiUitOpen 4:c1beacfc42c7 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
MikamiUitOpen 4:c1beacfc42c7 1042 {
MikamiUitOpen 4:c1beacfc42c7 1043 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 1044 #if 1
MikamiUitOpen 4:c1beacfc42c7 1045 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 1046
MikamiUitOpen 4:c1beacfc42c7 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
MikamiUitOpen 4:c1beacfc42c7 1048 return (result);
MikamiUitOpen 4:c1beacfc42c7 1049 #else
MikamiUitOpen 4:c1beacfc42c7 1050 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 4:c1beacfc42c7 1051 return(__regfpexc);
MikamiUitOpen 4:c1beacfc42c7 1052 #endif
MikamiUitOpen 4:c1beacfc42c7 1053 #else
MikamiUitOpen 4:c1beacfc42c7 1054 return(0);
MikamiUitOpen 4:c1beacfc42c7 1055 #endif
MikamiUitOpen 4:c1beacfc42c7 1056 }
MikamiUitOpen 4:c1beacfc42c7 1057
MikamiUitOpen 4:c1beacfc42c7 1058
MikamiUitOpen 4:c1beacfc42c7 1059 /** \brief Set FPEXC
MikamiUitOpen 4:c1beacfc42c7 1060
MikamiUitOpen 4:c1beacfc42c7 1061 This function assigns the given value to the Floating Point Exception Control register.
MikamiUitOpen 4:c1beacfc42c7 1062
MikamiUitOpen 4:c1beacfc42c7 1063 \param [in] fpscr Floating Point Exception Control value to set
MikamiUitOpen 4:c1beacfc42c7 1064 */
MikamiUitOpen 4:c1beacfc42c7 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
MikamiUitOpen 4:c1beacfc42c7 1066 {
MikamiUitOpen 4:c1beacfc42c7 1067 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 1068 #if 1
MikamiUitOpen 4:c1beacfc42c7 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
MikamiUitOpen 4:c1beacfc42c7 1070 #else
MikamiUitOpen 4:c1beacfc42c7 1071 register uint32_t __regfpexc __ASM("fpexc");
MikamiUitOpen 4:c1beacfc42c7 1072 __regfpexc = (fpexc);
MikamiUitOpen 4:c1beacfc42c7 1073 #endif
MikamiUitOpen 4:c1beacfc42c7 1074 #endif
MikamiUitOpen 4:c1beacfc42c7 1075 }
MikamiUitOpen 4:c1beacfc42c7 1076
MikamiUitOpen 4:c1beacfc42c7 1077 /** \brief Get CPACR
MikamiUitOpen 4:c1beacfc42c7 1078
MikamiUitOpen 4:c1beacfc42c7 1079 This function returns the current value of the Coprocessor Access Control register.
MikamiUitOpen 4:c1beacfc42c7 1080
MikamiUitOpen 4:c1beacfc42c7 1081 \return Coprocessor Access Control register value
MikamiUitOpen 4:c1beacfc42c7 1082 */
MikamiUitOpen 4:c1beacfc42c7 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
MikamiUitOpen 4:c1beacfc42c7 1084 {
MikamiUitOpen 4:c1beacfc42c7 1085 #if 1
MikamiUitOpen 4:c1beacfc42c7 1086 register uint32_t __regCPACR;
MikamiUitOpen 4:c1beacfc42c7 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
MikamiUitOpen 4:c1beacfc42c7 1088 #else
MikamiUitOpen 4:c1beacfc42c7 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 4:c1beacfc42c7 1090 #endif
MikamiUitOpen 4:c1beacfc42c7 1091 return __regCPACR;
MikamiUitOpen 4:c1beacfc42c7 1092 }
MikamiUitOpen 4:c1beacfc42c7 1093
MikamiUitOpen 4:c1beacfc42c7 1094 /** \brief Set CPACR
MikamiUitOpen 4:c1beacfc42c7 1095
MikamiUitOpen 4:c1beacfc42c7 1096 This function assigns the given value to the Coprocessor Access Control register.
MikamiUitOpen 4:c1beacfc42c7 1097
MikamiUitOpen 4:c1beacfc42c7 1098 \param [in] cpacr Coprocessor Acccess Control value to set
MikamiUitOpen 4:c1beacfc42c7 1099 */
MikamiUitOpen 4:c1beacfc42c7 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
MikamiUitOpen 4:c1beacfc42c7 1101 {
MikamiUitOpen 4:c1beacfc42c7 1102 #if 1
MikamiUitOpen 4:c1beacfc42c7 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
MikamiUitOpen 4:c1beacfc42c7 1104 #else
MikamiUitOpen 4:c1beacfc42c7 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
MikamiUitOpen 4:c1beacfc42c7 1106 __regCPACR = cpacr;
MikamiUitOpen 4:c1beacfc42c7 1107 #endif
MikamiUitOpen 4:c1beacfc42c7 1108 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1109 }
MikamiUitOpen 4:c1beacfc42c7 1110
MikamiUitOpen 4:c1beacfc42c7 1111 /** \brief Get CBAR
MikamiUitOpen 4:c1beacfc42c7 1112
MikamiUitOpen 4:c1beacfc42c7 1113 This function returns the value of the Configuration Base Address register.
MikamiUitOpen 4:c1beacfc42c7 1114
MikamiUitOpen 4:c1beacfc42c7 1115 \return Configuration Base Address register value
MikamiUitOpen 4:c1beacfc42c7 1116 */
MikamiUitOpen 4:c1beacfc42c7 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
MikamiUitOpen 4:c1beacfc42c7 1118 #if 1
MikamiUitOpen 4:c1beacfc42c7 1119 register uint32_t __regCBAR;
MikamiUitOpen 4:c1beacfc42c7 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
MikamiUitOpen 4:c1beacfc42c7 1121 #else
MikamiUitOpen 4:c1beacfc42c7 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1123 #endif
MikamiUitOpen 4:c1beacfc42c7 1124 return(__regCBAR);
MikamiUitOpen 4:c1beacfc42c7 1125 }
MikamiUitOpen 4:c1beacfc42c7 1126
MikamiUitOpen 4:c1beacfc42c7 1127 /** \brief Get TTBR0
MikamiUitOpen 4:c1beacfc42c7 1128
MikamiUitOpen 4:c1beacfc42c7 1129 This function returns the value of the Translation Table Base Register 0.
MikamiUitOpen 4:c1beacfc42c7 1130
MikamiUitOpen 4:c1beacfc42c7 1131 \return Translation Table Base Register 0 value
MikamiUitOpen 4:c1beacfc42c7 1132 */
MikamiUitOpen 4:c1beacfc42c7 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
MikamiUitOpen 4:c1beacfc42c7 1134 #if 1
MikamiUitOpen 4:c1beacfc42c7 1135 register uint32_t __regTTBR0;
MikamiUitOpen 4:c1beacfc42c7 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
MikamiUitOpen 4:c1beacfc42c7 1137 #else
MikamiUitOpen 4:c1beacfc42c7 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1139 #endif
MikamiUitOpen 4:c1beacfc42c7 1140 return(__regTTBR0);
MikamiUitOpen 4:c1beacfc42c7 1141 }
MikamiUitOpen 4:c1beacfc42c7 1142
MikamiUitOpen 4:c1beacfc42c7 1143 /** \brief Set TTBR0
MikamiUitOpen 4:c1beacfc42c7 1144
MikamiUitOpen 4:c1beacfc42c7 1145 This function assigns the given value to the Translation Table Base Register 0.
MikamiUitOpen 4:c1beacfc42c7 1146
MikamiUitOpen 4:c1beacfc42c7 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
MikamiUitOpen 4:c1beacfc42c7 1148 */
MikamiUitOpen 4:c1beacfc42c7 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
MikamiUitOpen 4:c1beacfc42c7 1150 #if 1
MikamiUitOpen 4:c1beacfc42c7 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
MikamiUitOpen 4:c1beacfc42c7 1152 #else
MikamiUitOpen 4:c1beacfc42c7 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1154 __regTTBR0 = ttbr0;
MikamiUitOpen 4:c1beacfc42c7 1155 #endif
MikamiUitOpen 4:c1beacfc42c7 1156 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1157 }
MikamiUitOpen 4:c1beacfc42c7 1158
MikamiUitOpen 4:c1beacfc42c7 1159 /** \brief Get DACR
MikamiUitOpen 4:c1beacfc42c7 1160
MikamiUitOpen 4:c1beacfc42c7 1161 This function returns the value of the Domain Access Control Register.
MikamiUitOpen 4:c1beacfc42c7 1162
MikamiUitOpen 4:c1beacfc42c7 1163 \return Domain Access Control Register value
MikamiUitOpen 4:c1beacfc42c7 1164 */
MikamiUitOpen 4:c1beacfc42c7 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
MikamiUitOpen 4:c1beacfc42c7 1166 #if 1
MikamiUitOpen 4:c1beacfc42c7 1167 register uint32_t __regDACR;
MikamiUitOpen 4:c1beacfc42c7 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
MikamiUitOpen 4:c1beacfc42c7 1169 #else
MikamiUitOpen 4:c1beacfc42c7 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1171 #endif
MikamiUitOpen 4:c1beacfc42c7 1172 return(__regDACR);
MikamiUitOpen 4:c1beacfc42c7 1173 }
MikamiUitOpen 4:c1beacfc42c7 1174
MikamiUitOpen 4:c1beacfc42c7 1175 /** \brief Set DACR
MikamiUitOpen 4:c1beacfc42c7 1176
MikamiUitOpen 4:c1beacfc42c7 1177 This function assigns the given value to the Domain Access Control Register.
MikamiUitOpen 4:c1beacfc42c7 1178
MikamiUitOpen 4:c1beacfc42c7 1179 \param [in] dacr Domain Access Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 1180 */
MikamiUitOpen 4:c1beacfc42c7 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
MikamiUitOpen 4:c1beacfc42c7 1182 #if 1
MikamiUitOpen 4:c1beacfc42c7 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
MikamiUitOpen 4:c1beacfc42c7 1184 #else
MikamiUitOpen 4:c1beacfc42c7 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1186 __regDACR = dacr;
MikamiUitOpen 4:c1beacfc42c7 1187 #endif
MikamiUitOpen 4:c1beacfc42c7 1188 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1189 }
MikamiUitOpen 4:c1beacfc42c7 1190
MikamiUitOpen 4:c1beacfc42c7 1191 /******************************** Cache and BTAC enable ****************************************************/
MikamiUitOpen 4:c1beacfc42c7 1192
MikamiUitOpen 4:c1beacfc42c7 1193 /** \brief Set SCTLR
MikamiUitOpen 4:c1beacfc42c7 1194
MikamiUitOpen 4:c1beacfc42c7 1195 This function assigns the given value to the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 1196
MikamiUitOpen 4:c1beacfc42c7 1197 \param [in] sctlr System Control Register value to set
MikamiUitOpen 4:c1beacfc42c7 1198 */
MikamiUitOpen 4:c1beacfc42c7 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
MikamiUitOpen 4:c1beacfc42c7 1200 {
MikamiUitOpen 4:c1beacfc42c7 1201 #if 1
MikamiUitOpen 4:c1beacfc42c7 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
MikamiUitOpen 4:c1beacfc42c7 1203 #else
MikamiUitOpen 4:c1beacfc42c7 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1205 __regSCTLR = sctlr;
MikamiUitOpen 4:c1beacfc42c7 1206 #endif
MikamiUitOpen 4:c1beacfc42c7 1207 }
MikamiUitOpen 4:c1beacfc42c7 1208
MikamiUitOpen 4:c1beacfc42c7 1209 /** \brief Get SCTLR
MikamiUitOpen 4:c1beacfc42c7 1210
MikamiUitOpen 4:c1beacfc42c7 1211 This function returns the value of the System Control Register.
MikamiUitOpen 4:c1beacfc42c7 1212
MikamiUitOpen 4:c1beacfc42c7 1213 \return System Control Register value
MikamiUitOpen 4:c1beacfc42c7 1214 */
MikamiUitOpen 4:c1beacfc42c7 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
MikamiUitOpen 4:c1beacfc42c7 1216 #if 1
MikamiUitOpen 4:c1beacfc42c7 1217 register uint32_t __regSCTLR;
MikamiUitOpen 4:c1beacfc42c7 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
MikamiUitOpen 4:c1beacfc42c7 1219 #else
MikamiUitOpen 4:c1beacfc42c7 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
MikamiUitOpen 4:c1beacfc42c7 1221 #endif
MikamiUitOpen 4:c1beacfc42c7 1222 return(__regSCTLR);
MikamiUitOpen 4:c1beacfc42c7 1223 }
MikamiUitOpen 4:c1beacfc42c7 1224
MikamiUitOpen 4:c1beacfc42c7 1225 /** \brief Enable Caches
MikamiUitOpen 4:c1beacfc42c7 1226
MikamiUitOpen 4:c1beacfc42c7 1227 Enable Caches
MikamiUitOpen 4:c1beacfc42c7 1228 */
MikamiUitOpen 4:c1beacfc42c7 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
MikamiUitOpen 4:c1beacfc42c7 1230 // Set I bit 12 to enable I Cache
MikamiUitOpen 4:c1beacfc42c7 1231 // Set C bit 2 to enable D Cache
MikamiUitOpen 4:c1beacfc42c7 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
MikamiUitOpen 4:c1beacfc42c7 1233 }
MikamiUitOpen 4:c1beacfc42c7 1234
MikamiUitOpen 4:c1beacfc42c7 1235 /** \brief Disable Caches
MikamiUitOpen 4:c1beacfc42c7 1236
MikamiUitOpen 4:c1beacfc42c7 1237 Disable Caches
MikamiUitOpen 4:c1beacfc42c7 1238 */
MikamiUitOpen 4:c1beacfc42c7 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
MikamiUitOpen 4:c1beacfc42c7 1240 // Clear I bit 12 to disable I Cache
MikamiUitOpen 4:c1beacfc42c7 1241 // Clear C bit 2 to disable D Cache
MikamiUitOpen 4:c1beacfc42c7 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
MikamiUitOpen 4:c1beacfc42c7 1243 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1244 }
MikamiUitOpen 4:c1beacfc42c7 1245
MikamiUitOpen 4:c1beacfc42c7 1246 /** \brief Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 1247
MikamiUitOpen 4:c1beacfc42c7 1248 Enable BTAC
MikamiUitOpen 4:c1beacfc42c7 1249 */
MikamiUitOpen 4:c1beacfc42c7 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 1251 // Set Z bit 11 to enable branch prediction
MikamiUitOpen 4:c1beacfc42c7 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
MikamiUitOpen 4:c1beacfc42c7 1253 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1254 }
MikamiUitOpen 4:c1beacfc42c7 1255
MikamiUitOpen 4:c1beacfc42c7 1256 /** \brief Disable BTAC
MikamiUitOpen 4:c1beacfc42c7 1257
MikamiUitOpen 4:c1beacfc42c7 1258 Disable BTAC
MikamiUitOpen 4:c1beacfc42c7 1259 */
MikamiUitOpen 4:c1beacfc42c7 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 1261 // Clear Z bit 11 to disable branch prediction
MikamiUitOpen 4:c1beacfc42c7 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
MikamiUitOpen 4:c1beacfc42c7 1263 }
MikamiUitOpen 4:c1beacfc42c7 1264
MikamiUitOpen 4:c1beacfc42c7 1265
MikamiUitOpen 4:c1beacfc42c7 1266 /** \brief Enable MMU
MikamiUitOpen 4:c1beacfc42c7 1267
MikamiUitOpen 4:c1beacfc42c7 1268 Enable MMU
MikamiUitOpen 4:c1beacfc42c7 1269 */
MikamiUitOpen 4:c1beacfc42c7 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
MikamiUitOpen 4:c1beacfc42c7 1271 // Set M bit 0 to enable the MMU
MikamiUitOpen 4:c1beacfc42c7 1272 // Set AFE bit to enable simplified access permissions model
MikamiUitOpen 4:c1beacfc42c7 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
MikamiUitOpen 4:c1beacfc42c7 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
MikamiUitOpen 4:c1beacfc42c7 1275 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1276 }
MikamiUitOpen 4:c1beacfc42c7 1277
MikamiUitOpen 4:c1beacfc42c7 1278 /** \brief Disable MMU
MikamiUitOpen 4:c1beacfc42c7 1279
MikamiUitOpen 4:c1beacfc42c7 1280 Disable MMU
MikamiUitOpen 4:c1beacfc42c7 1281 */
MikamiUitOpen 4:c1beacfc42c7 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
MikamiUitOpen 4:c1beacfc42c7 1283 // Clear M bit 0 to disable the MMU
MikamiUitOpen 4:c1beacfc42c7 1284 __set_SCTLR( __get_SCTLR() & ~1);
MikamiUitOpen 4:c1beacfc42c7 1285 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1286 }
MikamiUitOpen 4:c1beacfc42c7 1287
MikamiUitOpen 4:c1beacfc42c7 1288 /******************************** TLB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 1289 /** \brief Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 1290
MikamiUitOpen 4:c1beacfc42c7 1291 TLBIALL. Invalidate the whole tlb
MikamiUitOpen 4:c1beacfc42c7 1292 */
MikamiUitOpen 4:c1beacfc42c7 1293
MikamiUitOpen 4:c1beacfc42c7 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
MikamiUitOpen 4:c1beacfc42c7 1295 #if 1
MikamiUitOpen 4:c1beacfc42c7 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
MikamiUitOpen 4:c1beacfc42c7 1297 #else
MikamiUitOpen 4:c1beacfc42c7 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
MikamiUitOpen 4:c1beacfc42c7 1299 __TLBIALL = 0;
MikamiUitOpen 4:c1beacfc42c7 1300 #endif
MikamiUitOpen 4:c1beacfc42c7 1301 __DSB();
MikamiUitOpen 4:c1beacfc42c7 1302 __ISB();
MikamiUitOpen 4:c1beacfc42c7 1303 }
MikamiUitOpen 4:c1beacfc42c7 1304
MikamiUitOpen 4:c1beacfc42c7 1305 /******************************** BTB maintenance operations ************************************************/
MikamiUitOpen 4:c1beacfc42c7 1306 /** \brief Invalidate entire branch predictor array
MikamiUitOpen 4:c1beacfc42c7 1307
MikamiUitOpen 4:c1beacfc42c7 1308 BPIALL. Branch Predictor Invalidate All.
MikamiUitOpen 4:c1beacfc42c7 1309 */
MikamiUitOpen 4:c1beacfc42c7 1310
MikamiUitOpen 4:c1beacfc42c7 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
MikamiUitOpen 4:c1beacfc42c7 1312 #if 1
MikamiUitOpen 4:c1beacfc42c7 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
MikamiUitOpen 4:c1beacfc42c7 1314 #else
MikamiUitOpen 4:c1beacfc42c7 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
MikamiUitOpen 4:c1beacfc42c7 1316 __BPIALL = 0;
MikamiUitOpen 4:c1beacfc42c7 1317 #endif
MikamiUitOpen 4:c1beacfc42c7 1318 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 1319 __ISB(); //ensure instruction fetch path sees new state
MikamiUitOpen 4:c1beacfc42c7 1320 }
MikamiUitOpen 4:c1beacfc42c7 1321
MikamiUitOpen 4:c1beacfc42c7 1322
MikamiUitOpen 4:c1beacfc42c7 1323 /******************************** L1 cache operations ******************************************************/
MikamiUitOpen 4:c1beacfc42c7 1324
MikamiUitOpen 4:c1beacfc42c7 1325 /** \brief Invalidate the whole I$
MikamiUitOpen 4:c1beacfc42c7 1326
MikamiUitOpen 4:c1beacfc42c7 1327 ICIALLU. Instruction Cache Invalidate All to PoU
MikamiUitOpen 4:c1beacfc42c7 1328 */
MikamiUitOpen 4:c1beacfc42c7 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 1330 #if 1
MikamiUitOpen 4:c1beacfc42c7 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
MikamiUitOpen 4:c1beacfc42c7 1332 #else
MikamiUitOpen 4:c1beacfc42c7 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
MikamiUitOpen 4:c1beacfc42c7 1334 __ICIALLU = 0;
MikamiUitOpen 4:c1beacfc42c7 1335 #endif
MikamiUitOpen 4:c1beacfc42c7 1336 __DSB(); //ensure completion of the invalidation
MikamiUitOpen 4:c1beacfc42c7 1337 __ISB(); //ensure instruction fetch path sees new I cache state
MikamiUitOpen 4:c1beacfc42c7 1338 }
MikamiUitOpen 4:c1beacfc42c7 1339
MikamiUitOpen 4:c1beacfc42c7 1340 /** \brief Clean D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 1341
MikamiUitOpen 4:c1beacfc42c7 1342 DCCMVAC. Data cache clean by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 1343 */
MikamiUitOpen 4:c1beacfc42c7 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 1345 #if 1
MikamiUitOpen 4:c1beacfc42c7 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 4:c1beacfc42c7 1347 #else
MikamiUitOpen 4:c1beacfc42c7 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
MikamiUitOpen 4:c1beacfc42c7 1349 __DCCMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 1350 #endif
MikamiUitOpen 4:c1beacfc42c7 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 1352 }
MikamiUitOpen 4:c1beacfc42c7 1353
MikamiUitOpen 4:c1beacfc42c7 1354 /** \brief Invalidate D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 1355
MikamiUitOpen 4:c1beacfc42c7 1356 DCIMVAC. Data cache invalidate by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 1357 */
MikamiUitOpen 4:c1beacfc42c7 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 1359 #if 1
MikamiUitOpen 4:c1beacfc42c7 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 4:c1beacfc42c7 1361 #else
MikamiUitOpen 4:c1beacfc42c7 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
MikamiUitOpen 4:c1beacfc42c7 1363 __DCIMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 1364 #endif
MikamiUitOpen 4:c1beacfc42c7 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 1366 }
MikamiUitOpen 4:c1beacfc42c7 1367
MikamiUitOpen 4:c1beacfc42c7 1368 /** \brief Clean and Invalidate D$ by MVA
MikamiUitOpen 4:c1beacfc42c7 1369
MikamiUitOpen 4:c1beacfc42c7 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
MikamiUitOpen 4:c1beacfc42c7 1371 */
MikamiUitOpen 4:c1beacfc42c7 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
MikamiUitOpen 4:c1beacfc42c7 1373 #if 1
MikamiUitOpen 4:c1beacfc42c7 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
MikamiUitOpen 4:c1beacfc42c7 1375 #else
MikamiUitOpen 4:c1beacfc42c7 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
MikamiUitOpen 4:c1beacfc42c7 1377 __DCCIMVAC = (uint32_t)va;
MikamiUitOpen 4:c1beacfc42c7 1378 #endif
MikamiUitOpen 4:c1beacfc42c7 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
MikamiUitOpen 4:c1beacfc42c7 1380 }
MikamiUitOpen 4:c1beacfc42c7 1381
MikamiUitOpen 4:c1beacfc42c7 1382 /** \brief Clean and Invalidate the entire data or unified cache
MikamiUitOpen 4:c1beacfc42c7 1383
MikamiUitOpen 4:c1beacfc42c7 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
MikamiUitOpen 4:c1beacfc42c7 1385 */
MikamiUitOpen 4:c1beacfc42c7 1386 extern void __v7_all_cache(uint32_t op);
MikamiUitOpen 4:c1beacfc42c7 1387
MikamiUitOpen 4:c1beacfc42c7 1388
MikamiUitOpen 4:c1beacfc42c7 1389 /** \brief Invalidate the whole D$
MikamiUitOpen 4:c1beacfc42c7 1390
MikamiUitOpen 4:c1beacfc42c7 1391 DCISW. Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 1392 */
MikamiUitOpen 4:c1beacfc42c7 1393
MikamiUitOpen 4:c1beacfc42c7 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 1395 __v7_all_cache(0);
MikamiUitOpen 4:c1beacfc42c7 1396 }
MikamiUitOpen 4:c1beacfc42c7 1397
MikamiUitOpen 4:c1beacfc42c7 1398 /** \brief Clean the whole D$
MikamiUitOpen 4:c1beacfc42c7 1399
MikamiUitOpen 4:c1beacfc42c7 1400 DCCSW. Clean by Set/Way
MikamiUitOpen 4:c1beacfc42c7 1401 */
MikamiUitOpen 4:c1beacfc42c7 1402
MikamiUitOpen 4:c1beacfc42c7 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 1404 __v7_all_cache(1);
MikamiUitOpen 4:c1beacfc42c7 1405 }
MikamiUitOpen 4:c1beacfc42c7 1406
MikamiUitOpen 4:c1beacfc42c7 1407 /** \brief Clean and invalidate the whole D$
MikamiUitOpen 4:c1beacfc42c7 1408
MikamiUitOpen 4:c1beacfc42c7 1409 DCCISW. Clean and Invalidate by Set/Way
MikamiUitOpen 4:c1beacfc42c7 1410 */
MikamiUitOpen 4:c1beacfc42c7 1411
MikamiUitOpen 4:c1beacfc42c7 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
MikamiUitOpen 4:c1beacfc42c7 1413 __v7_all_cache(2);
MikamiUitOpen 4:c1beacfc42c7 1414 }
MikamiUitOpen 4:c1beacfc42c7 1415
MikamiUitOpen 4:c1beacfc42c7 1416 #include "core_ca_mmu.h"
MikamiUitOpen 4:c1beacfc42c7 1417
MikamiUitOpen 4:c1beacfc42c7 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 1419
MikamiUitOpen 4:c1beacfc42c7 1420 #error TASKING Compiler support not implemented for Cortex-A
MikamiUitOpen 4:c1beacfc42c7 1421
MikamiUitOpen 4:c1beacfc42c7 1422 #endif
MikamiUitOpen 4:c1beacfc42c7 1423
MikamiUitOpen 4:c1beacfc42c7 1424 /*@} end of CMSIS_Core_RegAccFunctions */
MikamiUitOpen 4:c1beacfc42c7 1425
MikamiUitOpen 4:c1beacfc42c7 1426
MikamiUitOpen 4:c1beacfc42c7 1427 #endif /* __CORE_CAFUNC_H__ */