不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cmSimd.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_cmSimd.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-M SIMD Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V4.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 18. March 2015
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #if defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 4:c1beacfc42c7 40 #endif
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 #ifndef __CORE_CMSIMD_H
MikamiUitOpen 4:c1beacfc42c7 43 #define __CORE_CMSIMD_H
MikamiUitOpen 4:c1beacfc42c7 44
MikamiUitOpen 4:c1beacfc42c7 45 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 46 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 47 #endif
MikamiUitOpen 4:c1beacfc42c7 48
MikamiUitOpen 4:c1beacfc42c7 49
MikamiUitOpen 4:c1beacfc42c7 50 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 51 * Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 52 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 53
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 /* ################### Compiler specific Intrinsics ########################### */
MikamiUitOpen 4:c1beacfc42c7 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MikamiUitOpen 4:c1beacfc42c7 57 Access to dedicated SIMD instructions
MikamiUitOpen 4:c1beacfc42c7 58 @{
MikamiUitOpen 4:c1beacfc42c7 59 */
MikamiUitOpen 4:c1beacfc42c7 60
MikamiUitOpen 4:c1beacfc42c7 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 62 /* ARM armcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 63 #define __SADD8 __sadd8
MikamiUitOpen 4:c1beacfc42c7 64 #define __QADD8 __qadd8
MikamiUitOpen 4:c1beacfc42c7 65 #define __SHADD8 __shadd8
MikamiUitOpen 4:c1beacfc42c7 66 #define __UADD8 __uadd8
MikamiUitOpen 4:c1beacfc42c7 67 #define __UQADD8 __uqadd8
MikamiUitOpen 4:c1beacfc42c7 68 #define __UHADD8 __uhadd8
MikamiUitOpen 4:c1beacfc42c7 69 #define __SSUB8 __ssub8
MikamiUitOpen 4:c1beacfc42c7 70 #define __QSUB8 __qsub8
MikamiUitOpen 4:c1beacfc42c7 71 #define __SHSUB8 __shsub8
MikamiUitOpen 4:c1beacfc42c7 72 #define __USUB8 __usub8
MikamiUitOpen 4:c1beacfc42c7 73 #define __UQSUB8 __uqsub8
MikamiUitOpen 4:c1beacfc42c7 74 #define __UHSUB8 __uhsub8
MikamiUitOpen 4:c1beacfc42c7 75 #define __SADD16 __sadd16
MikamiUitOpen 4:c1beacfc42c7 76 #define __QADD16 __qadd16
MikamiUitOpen 4:c1beacfc42c7 77 #define __SHADD16 __shadd16
MikamiUitOpen 4:c1beacfc42c7 78 #define __UADD16 __uadd16
MikamiUitOpen 4:c1beacfc42c7 79 #define __UQADD16 __uqadd16
MikamiUitOpen 4:c1beacfc42c7 80 #define __UHADD16 __uhadd16
MikamiUitOpen 4:c1beacfc42c7 81 #define __SSUB16 __ssub16
MikamiUitOpen 4:c1beacfc42c7 82 #define __QSUB16 __qsub16
MikamiUitOpen 4:c1beacfc42c7 83 #define __SHSUB16 __shsub16
MikamiUitOpen 4:c1beacfc42c7 84 #define __USUB16 __usub16
MikamiUitOpen 4:c1beacfc42c7 85 #define __UQSUB16 __uqsub16
MikamiUitOpen 4:c1beacfc42c7 86 #define __UHSUB16 __uhsub16
MikamiUitOpen 4:c1beacfc42c7 87 #define __SASX __sasx
MikamiUitOpen 4:c1beacfc42c7 88 #define __QASX __qasx
MikamiUitOpen 4:c1beacfc42c7 89 #define __SHASX __shasx
MikamiUitOpen 4:c1beacfc42c7 90 #define __UASX __uasx
MikamiUitOpen 4:c1beacfc42c7 91 #define __UQASX __uqasx
MikamiUitOpen 4:c1beacfc42c7 92 #define __UHASX __uhasx
MikamiUitOpen 4:c1beacfc42c7 93 #define __SSAX __ssax
MikamiUitOpen 4:c1beacfc42c7 94 #define __QSAX __qsax
MikamiUitOpen 4:c1beacfc42c7 95 #define __SHSAX __shsax
MikamiUitOpen 4:c1beacfc42c7 96 #define __USAX __usax
MikamiUitOpen 4:c1beacfc42c7 97 #define __UQSAX __uqsax
MikamiUitOpen 4:c1beacfc42c7 98 #define __UHSAX __uhsax
MikamiUitOpen 4:c1beacfc42c7 99 #define __USAD8 __usad8
MikamiUitOpen 4:c1beacfc42c7 100 #define __USADA8 __usada8
MikamiUitOpen 4:c1beacfc42c7 101 #define __SSAT16 __ssat16
MikamiUitOpen 4:c1beacfc42c7 102 #define __USAT16 __usat16
MikamiUitOpen 4:c1beacfc42c7 103 #define __UXTB16 __uxtb16
MikamiUitOpen 4:c1beacfc42c7 104 #define __UXTAB16 __uxtab16
MikamiUitOpen 4:c1beacfc42c7 105 #define __SXTB16 __sxtb16
MikamiUitOpen 4:c1beacfc42c7 106 #define __SXTAB16 __sxtab16
MikamiUitOpen 4:c1beacfc42c7 107 #define __SMUAD __smuad
MikamiUitOpen 4:c1beacfc42c7 108 #define __SMUADX __smuadx
MikamiUitOpen 4:c1beacfc42c7 109 #define __SMLAD __smlad
MikamiUitOpen 4:c1beacfc42c7 110 #define __SMLADX __smladx
MikamiUitOpen 4:c1beacfc42c7 111 #define __SMLALD __smlald
MikamiUitOpen 4:c1beacfc42c7 112 #define __SMLALDX __smlaldx
MikamiUitOpen 4:c1beacfc42c7 113 #define __SMUSD __smusd
MikamiUitOpen 4:c1beacfc42c7 114 #define __SMUSDX __smusdx
MikamiUitOpen 4:c1beacfc42c7 115 #define __SMLSD __smlsd
MikamiUitOpen 4:c1beacfc42c7 116 #define __SMLSDX __smlsdx
MikamiUitOpen 4:c1beacfc42c7 117 #define __SMLSLD __smlsld
MikamiUitOpen 4:c1beacfc42c7 118 #define __SMLSLDX __smlsldx
MikamiUitOpen 4:c1beacfc42c7 119 #define __SEL __sel
MikamiUitOpen 4:c1beacfc42c7 120 #define __QADD __qadd
MikamiUitOpen 4:c1beacfc42c7 121 #define __QSUB __qsub
MikamiUitOpen 4:c1beacfc42c7 122
MikamiUitOpen 4:c1beacfc42c7 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MikamiUitOpen 4:c1beacfc42c7 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MikamiUitOpen 4:c1beacfc42c7 125
MikamiUitOpen 4:c1beacfc42c7 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MikamiUitOpen 4:c1beacfc42c7 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MikamiUitOpen 4:c1beacfc42c7 128
MikamiUitOpen 4:c1beacfc42c7 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MikamiUitOpen 4:c1beacfc42c7 130 ((int64_t)(ARG3) << 32) ) >> 32))
MikamiUitOpen 4:c1beacfc42c7 131
MikamiUitOpen 4:c1beacfc42c7 132
MikamiUitOpen 4:c1beacfc42c7 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 134 /* GNU gcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 136 {
MikamiUitOpen 4:c1beacfc42c7 137 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 138
MikamiUitOpen 4:c1beacfc42c7 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 140 return(result);
MikamiUitOpen 4:c1beacfc42c7 141 }
MikamiUitOpen 4:c1beacfc42c7 142
MikamiUitOpen 4:c1beacfc42c7 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 144 {
MikamiUitOpen 4:c1beacfc42c7 145 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 148 return(result);
MikamiUitOpen 4:c1beacfc42c7 149 }
MikamiUitOpen 4:c1beacfc42c7 150
MikamiUitOpen 4:c1beacfc42c7 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 152 {
MikamiUitOpen 4:c1beacfc42c7 153 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 154
MikamiUitOpen 4:c1beacfc42c7 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 156 return(result);
MikamiUitOpen 4:c1beacfc42c7 157 }
MikamiUitOpen 4:c1beacfc42c7 158
MikamiUitOpen 4:c1beacfc42c7 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 160 {
MikamiUitOpen 4:c1beacfc42c7 161 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 162
MikamiUitOpen 4:c1beacfc42c7 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 164 return(result);
MikamiUitOpen 4:c1beacfc42c7 165 }
MikamiUitOpen 4:c1beacfc42c7 166
MikamiUitOpen 4:c1beacfc42c7 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 168 {
MikamiUitOpen 4:c1beacfc42c7 169 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 170
MikamiUitOpen 4:c1beacfc42c7 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 172 return(result);
MikamiUitOpen 4:c1beacfc42c7 173 }
MikamiUitOpen 4:c1beacfc42c7 174
MikamiUitOpen 4:c1beacfc42c7 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 176 {
MikamiUitOpen 4:c1beacfc42c7 177 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 178
MikamiUitOpen 4:c1beacfc42c7 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 180 return(result);
MikamiUitOpen 4:c1beacfc42c7 181 }
MikamiUitOpen 4:c1beacfc42c7 182
MikamiUitOpen 4:c1beacfc42c7 183
MikamiUitOpen 4:c1beacfc42c7 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 185 {
MikamiUitOpen 4:c1beacfc42c7 186 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 187
MikamiUitOpen 4:c1beacfc42c7 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 189 return(result);
MikamiUitOpen 4:c1beacfc42c7 190 }
MikamiUitOpen 4:c1beacfc42c7 191
MikamiUitOpen 4:c1beacfc42c7 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 193 {
MikamiUitOpen 4:c1beacfc42c7 194 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 195
MikamiUitOpen 4:c1beacfc42c7 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 197 return(result);
MikamiUitOpen 4:c1beacfc42c7 198 }
MikamiUitOpen 4:c1beacfc42c7 199
MikamiUitOpen 4:c1beacfc42c7 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 201 {
MikamiUitOpen 4:c1beacfc42c7 202 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 203
MikamiUitOpen 4:c1beacfc42c7 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 205 return(result);
MikamiUitOpen 4:c1beacfc42c7 206 }
MikamiUitOpen 4:c1beacfc42c7 207
MikamiUitOpen 4:c1beacfc42c7 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 209 {
MikamiUitOpen 4:c1beacfc42c7 210 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 211
MikamiUitOpen 4:c1beacfc42c7 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 213 return(result);
MikamiUitOpen 4:c1beacfc42c7 214 }
MikamiUitOpen 4:c1beacfc42c7 215
MikamiUitOpen 4:c1beacfc42c7 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 217 {
MikamiUitOpen 4:c1beacfc42c7 218 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 219
MikamiUitOpen 4:c1beacfc42c7 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 221 return(result);
MikamiUitOpen 4:c1beacfc42c7 222 }
MikamiUitOpen 4:c1beacfc42c7 223
MikamiUitOpen 4:c1beacfc42c7 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 225 {
MikamiUitOpen 4:c1beacfc42c7 226 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 227
MikamiUitOpen 4:c1beacfc42c7 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 229 return(result);
MikamiUitOpen 4:c1beacfc42c7 230 }
MikamiUitOpen 4:c1beacfc42c7 231
MikamiUitOpen 4:c1beacfc42c7 232
MikamiUitOpen 4:c1beacfc42c7 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 234 {
MikamiUitOpen 4:c1beacfc42c7 235 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 236
MikamiUitOpen 4:c1beacfc42c7 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 238 return(result);
MikamiUitOpen 4:c1beacfc42c7 239 }
MikamiUitOpen 4:c1beacfc42c7 240
MikamiUitOpen 4:c1beacfc42c7 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 242 {
MikamiUitOpen 4:c1beacfc42c7 243 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 244
MikamiUitOpen 4:c1beacfc42c7 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 246 return(result);
MikamiUitOpen 4:c1beacfc42c7 247 }
MikamiUitOpen 4:c1beacfc42c7 248
MikamiUitOpen 4:c1beacfc42c7 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 250 {
MikamiUitOpen 4:c1beacfc42c7 251 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 252
MikamiUitOpen 4:c1beacfc42c7 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 254 return(result);
MikamiUitOpen 4:c1beacfc42c7 255 }
MikamiUitOpen 4:c1beacfc42c7 256
MikamiUitOpen 4:c1beacfc42c7 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 258 {
MikamiUitOpen 4:c1beacfc42c7 259 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 260
MikamiUitOpen 4:c1beacfc42c7 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 262 return(result);
MikamiUitOpen 4:c1beacfc42c7 263 }
MikamiUitOpen 4:c1beacfc42c7 264
MikamiUitOpen 4:c1beacfc42c7 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 266 {
MikamiUitOpen 4:c1beacfc42c7 267 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 268
MikamiUitOpen 4:c1beacfc42c7 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 270 return(result);
MikamiUitOpen 4:c1beacfc42c7 271 }
MikamiUitOpen 4:c1beacfc42c7 272
MikamiUitOpen 4:c1beacfc42c7 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 274 {
MikamiUitOpen 4:c1beacfc42c7 275 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 276
MikamiUitOpen 4:c1beacfc42c7 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 278 return(result);
MikamiUitOpen 4:c1beacfc42c7 279 }
MikamiUitOpen 4:c1beacfc42c7 280
MikamiUitOpen 4:c1beacfc42c7 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 282 {
MikamiUitOpen 4:c1beacfc42c7 283 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 284
MikamiUitOpen 4:c1beacfc42c7 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 286 return(result);
MikamiUitOpen 4:c1beacfc42c7 287 }
MikamiUitOpen 4:c1beacfc42c7 288
MikamiUitOpen 4:c1beacfc42c7 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 290 {
MikamiUitOpen 4:c1beacfc42c7 291 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 292
MikamiUitOpen 4:c1beacfc42c7 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 294 return(result);
MikamiUitOpen 4:c1beacfc42c7 295 }
MikamiUitOpen 4:c1beacfc42c7 296
MikamiUitOpen 4:c1beacfc42c7 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 298 {
MikamiUitOpen 4:c1beacfc42c7 299 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 300
MikamiUitOpen 4:c1beacfc42c7 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 302 return(result);
MikamiUitOpen 4:c1beacfc42c7 303 }
MikamiUitOpen 4:c1beacfc42c7 304
MikamiUitOpen 4:c1beacfc42c7 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 306 {
MikamiUitOpen 4:c1beacfc42c7 307 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 308
MikamiUitOpen 4:c1beacfc42c7 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 310 return(result);
MikamiUitOpen 4:c1beacfc42c7 311 }
MikamiUitOpen 4:c1beacfc42c7 312
MikamiUitOpen 4:c1beacfc42c7 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 314 {
MikamiUitOpen 4:c1beacfc42c7 315 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 316
MikamiUitOpen 4:c1beacfc42c7 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 318 return(result);
MikamiUitOpen 4:c1beacfc42c7 319 }
MikamiUitOpen 4:c1beacfc42c7 320
MikamiUitOpen 4:c1beacfc42c7 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 322 {
MikamiUitOpen 4:c1beacfc42c7 323 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 324
MikamiUitOpen 4:c1beacfc42c7 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 326 return(result);
MikamiUitOpen 4:c1beacfc42c7 327 }
MikamiUitOpen 4:c1beacfc42c7 328
MikamiUitOpen 4:c1beacfc42c7 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 330 {
MikamiUitOpen 4:c1beacfc42c7 331 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 332
MikamiUitOpen 4:c1beacfc42c7 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 334 return(result);
MikamiUitOpen 4:c1beacfc42c7 335 }
MikamiUitOpen 4:c1beacfc42c7 336
MikamiUitOpen 4:c1beacfc42c7 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 338 {
MikamiUitOpen 4:c1beacfc42c7 339 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 340
MikamiUitOpen 4:c1beacfc42c7 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 342 return(result);
MikamiUitOpen 4:c1beacfc42c7 343 }
MikamiUitOpen 4:c1beacfc42c7 344
MikamiUitOpen 4:c1beacfc42c7 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 346 {
MikamiUitOpen 4:c1beacfc42c7 347 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 348
MikamiUitOpen 4:c1beacfc42c7 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 350 return(result);
MikamiUitOpen 4:c1beacfc42c7 351 }
MikamiUitOpen 4:c1beacfc42c7 352
MikamiUitOpen 4:c1beacfc42c7 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 354 {
MikamiUitOpen 4:c1beacfc42c7 355 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 356
MikamiUitOpen 4:c1beacfc42c7 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 358 return(result);
MikamiUitOpen 4:c1beacfc42c7 359 }
MikamiUitOpen 4:c1beacfc42c7 360
MikamiUitOpen 4:c1beacfc42c7 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 362 {
MikamiUitOpen 4:c1beacfc42c7 363 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 364
MikamiUitOpen 4:c1beacfc42c7 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 366 return(result);
MikamiUitOpen 4:c1beacfc42c7 367 }
MikamiUitOpen 4:c1beacfc42c7 368
MikamiUitOpen 4:c1beacfc42c7 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 370 {
MikamiUitOpen 4:c1beacfc42c7 371 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 372
MikamiUitOpen 4:c1beacfc42c7 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 374 return(result);
MikamiUitOpen 4:c1beacfc42c7 375 }
MikamiUitOpen 4:c1beacfc42c7 376
MikamiUitOpen 4:c1beacfc42c7 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 378 {
MikamiUitOpen 4:c1beacfc42c7 379 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 380
MikamiUitOpen 4:c1beacfc42c7 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 382 return(result);
MikamiUitOpen 4:c1beacfc42c7 383 }
MikamiUitOpen 4:c1beacfc42c7 384
MikamiUitOpen 4:c1beacfc42c7 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 386 {
MikamiUitOpen 4:c1beacfc42c7 387 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 388
MikamiUitOpen 4:c1beacfc42c7 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 390 return(result);
MikamiUitOpen 4:c1beacfc42c7 391 }
MikamiUitOpen 4:c1beacfc42c7 392
MikamiUitOpen 4:c1beacfc42c7 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 394 {
MikamiUitOpen 4:c1beacfc42c7 395 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 396
MikamiUitOpen 4:c1beacfc42c7 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 398 return(result);
MikamiUitOpen 4:c1beacfc42c7 399 }
MikamiUitOpen 4:c1beacfc42c7 400
MikamiUitOpen 4:c1beacfc42c7 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 402 {
MikamiUitOpen 4:c1beacfc42c7 403 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 404
MikamiUitOpen 4:c1beacfc42c7 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 406 return(result);
MikamiUitOpen 4:c1beacfc42c7 407 }
MikamiUitOpen 4:c1beacfc42c7 408
MikamiUitOpen 4:c1beacfc42c7 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 410 {
MikamiUitOpen 4:c1beacfc42c7 411 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 412
MikamiUitOpen 4:c1beacfc42c7 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 414 return(result);
MikamiUitOpen 4:c1beacfc42c7 415 }
MikamiUitOpen 4:c1beacfc42c7 416
MikamiUitOpen 4:c1beacfc42c7 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 418 {
MikamiUitOpen 4:c1beacfc42c7 419 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 420
MikamiUitOpen 4:c1beacfc42c7 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 422 return(result);
MikamiUitOpen 4:c1beacfc42c7 423 }
MikamiUitOpen 4:c1beacfc42c7 424
MikamiUitOpen 4:c1beacfc42c7 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 426 {
MikamiUitOpen 4:c1beacfc42c7 427 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 428
MikamiUitOpen 4:c1beacfc42c7 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 430 return(result);
MikamiUitOpen 4:c1beacfc42c7 431 }
MikamiUitOpen 4:c1beacfc42c7 432
MikamiUitOpen 4:c1beacfc42c7 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 434 {
MikamiUitOpen 4:c1beacfc42c7 435 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 436
MikamiUitOpen 4:c1beacfc42c7 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 438 return(result);
MikamiUitOpen 4:c1beacfc42c7 439 }
MikamiUitOpen 4:c1beacfc42c7 440
MikamiUitOpen 4:c1beacfc42c7 441 #define __SSAT16(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 442 ({ \
MikamiUitOpen 4:c1beacfc42c7 443 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 445 __RES; \
MikamiUitOpen 4:c1beacfc42c7 446 })
MikamiUitOpen 4:c1beacfc42c7 447
MikamiUitOpen 4:c1beacfc42c7 448 #define __USAT16(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 449 ({ \
MikamiUitOpen 4:c1beacfc42c7 450 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 452 __RES; \
MikamiUitOpen 4:c1beacfc42c7 453 })
MikamiUitOpen 4:c1beacfc42c7 454
MikamiUitOpen 4:c1beacfc42c7 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MikamiUitOpen 4:c1beacfc42c7 456 {
MikamiUitOpen 4:c1beacfc42c7 457 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 458
MikamiUitOpen 4:c1beacfc42c7 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 4:c1beacfc42c7 460 return(result);
MikamiUitOpen 4:c1beacfc42c7 461 }
MikamiUitOpen 4:c1beacfc42c7 462
MikamiUitOpen 4:c1beacfc42c7 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 464 {
MikamiUitOpen 4:c1beacfc42c7 465 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 466
MikamiUitOpen 4:c1beacfc42c7 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 468 return(result);
MikamiUitOpen 4:c1beacfc42c7 469 }
MikamiUitOpen 4:c1beacfc42c7 470
MikamiUitOpen 4:c1beacfc42c7 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MikamiUitOpen 4:c1beacfc42c7 472 {
MikamiUitOpen 4:c1beacfc42c7 473 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 474
MikamiUitOpen 4:c1beacfc42c7 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 4:c1beacfc42c7 476 return(result);
MikamiUitOpen 4:c1beacfc42c7 477 }
MikamiUitOpen 4:c1beacfc42c7 478
MikamiUitOpen 4:c1beacfc42c7 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 480 {
MikamiUitOpen 4:c1beacfc42c7 481 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 482
MikamiUitOpen 4:c1beacfc42c7 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 484 return(result);
MikamiUitOpen 4:c1beacfc42c7 485 }
MikamiUitOpen 4:c1beacfc42c7 486
MikamiUitOpen 4:c1beacfc42c7 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 488 {
MikamiUitOpen 4:c1beacfc42c7 489 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 490
MikamiUitOpen 4:c1beacfc42c7 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 492 return(result);
MikamiUitOpen 4:c1beacfc42c7 493 }
MikamiUitOpen 4:c1beacfc42c7 494
MikamiUitOpen 4:c1beacfc42c7 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 496 {
MikamiUitOpen 4:c1beacfc42c7 497 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 498
MikamiUitOpen 4:c1beacfc42c7 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 500 return(result);
MikamiUitOpen 4:c1beacfc42c7 501 }
MikamiUitOpen 4:c1beacfc42c7 502
MikamiUitOpen 4:c1beacfc42c7 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 504 {
MikamiUitOpen 4:c1beacfc42c7 505 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 506
MikamiUitOpen 4:c1beacfc42c7 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 508 return(result);
MikamiUitOpen 4:c1beacfc42c7 509 }
MikamiUitOpen 4:c1beacfc42c7 510
MikamiUitOpen 4:c1beacfc42c7 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 512 {
MikamiUitOpen 4:c1beacfc42c7 513 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 514
MikamiUitOpen 4:c1beacfc42c7 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 516 return(result);
MikamiUitOpen 4:c1beacfc42c7 517 }
MikamiUitOpen 4:c1beacfc42c7 518
MikamiUitOpen 4:c1beacfc42c7 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 4:c1beacfc42c7 520 {
MikamiUitOpen 4:c1beacfc42c7 521 union llreg_u{
MikamiUitOpen 4:c1beacfc42c7 522 uint32_t w32[2];
MikamiUitOpen 4:c1beacfc42c7 523 uint64_t w64;
MikamiUitOpen 4:c1beacfc42c7 524 } llr;
MikamiUitOpen 4:c1beacfc42c7 525 llr.w64 = acc;
MikamiUitOpen 4:c1beacfc42c7 526
MikamiUitOpen 4:c1beacfc42c7 527 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 4:c1beacfc42c7 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 4:c1beacfc42c7 529 #else // Big endian
MikamiUitOpen 4:c1beacfc42c7 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 4:c1beacfc42c7 531 #endif
MikamiUitOpen 4:c1beacfc42c7 532
MikamiUitOpen 4:c1beacfc42c7 533 return(llr.w64);
MikamiUitOpen 4:c1beacfc42c7 534 }
MikamiUitOpen 4:c1beacfc42c7 535
MikamiUitOpen 4:c1beacfc42c7 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 4:c1beacfc42c7 537 {
MikamiUitOpen 4:c1beacfc42c7 538 union llreg_u{
MikamiUitOpen 4:c1beacfc42c7 539 uint32_t w32[2];
MikamiUitOpen 4:c1beacfc42c7 540 uint64_t w64;
MikamiUitOpen 4:c1beacfc42c7 541 } llr;
MikamiUitOpen 4:c1beacfc42c7 542 llr.w64 = acc;
MikamiUitOpen 4:c1beacfc42c7 543
MikamiUitOpen 4:c1beacfc42c7 544 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 4:c1beacfc42c7 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 4:c1beacfc42c7 546 #else // Big endian
MikamiUitOpen 4:c1beacfc42c7 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 4:c1beacfc42c7 548 #endif
MikamiUitOpen 4:c1beacfc42c7 549
MikamiUitOpen 4:c1beacfc42c7 550 return(llr.w64);
MikamiUitOpen 4:c1beacfc42c7 551 }
MikamiUitOpen 4:c1beacfc42c7 552
MikamiUitOpen 4:c1beacfc42c7 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 554 {
MikamiUitOpen 4:c1beacfc42c7 555 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 556
MikamiUitOpen 4:c1beacfc42c7 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 558 return(result);
MikamiUitOpen 4:c1beacfc42c7 559 }
MikamiUitOpen 4:c1beacfc42c7 560
MikamiUitOpen 4:c1beacfc42c7 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 562 {
MikamiUitOpen 4:c1beacfc42c7 563 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 564
MikamiUitOpen 4:c1beacfc42c7 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 566 return(result);
MikamiUitOpen 4:c1beacfc42c7 567 }
MikamiUitOpen 4:c1beacfc42c7 568
MikamiUitOpen 4:c1beacfc42c7 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 570 {
MikamiUitOpen 4:c1beacfc42c7 571 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 572
MikamiUitOpen 4:c1beacfc42c7 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 574 return(result);
MikamiUitOpen 4:c1beacfc42c7 575 }
MikamiUitOpen 4:c1beacfc42c7 576
MikamiUitOpen 4:c1beacfc42c7 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 4:c1beacfc42c7 578 {
MikamiUitOpen 4:c1beacfc42c7 579 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 580
MikamiUitOpen 4:c1beacfc42c7 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 582 return(result);
MikamiUitOpen 4:c1beacfc42c7 583 }
MikamiUitOpen 4:c1beacfc42c7 584
MikamiUitOpen 4:c1beacfc42c7 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 4:c1beacfc42c7 586 {
MikamiUitOpen 4:c1beacfc42c7 587 union llreg_u{
MikamiUitOpen 4:c1beacfc42c7 588 uint32_t w32[2];
MikamiUitOpen 4:c1beacfc42c7 589 uint64_t w64;
MikamiUitOpen 4:c1beacfc42c7 590 } llr;
MikamiUitOpen 4:c1beacfc42c7 591 llr.w64 = acc;
MikamiUitOpen 4:c1beacfc42c7 592
MikamiUitOpen 4:c1beacfc42c7 593 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 4:c1beacfc42c7 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 4:c1beacfc42c7 595 #else // Big endian
MikamiUitOpen 4:c1beacfc42c7 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 4:c1beacfc42c7 597 #endif
MikamiUitOpen 4:c1beacfc42c7 598
MikamiUitOpen 4:c1beacfc42c7 599 return(llr.w64);
MikamiUitOpen 4:c1beacfc42c7 600 }
MikamiUitOpen 4:c1beacfc42c7 601
MikamiUitOpen 4:c1beacfc42c7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
MikamiUitOpen 4:c1beacfc42c7 603 {
MikamiUitOpen 4:c1beacfc42c7 604 union llreg_u{
MikamiUitOpen 4:c1beacfc42c7 605 uint32_t w32[2];
MikamiUitOpen 4:c1beacfc42c7 606 uint64_t w64;
MikamiUitOpen 4:c1beacfc42c7 607 } llr;
MikamiUitOpen 4:c1beacfc42c7 608 llr.w64 = acc;
MikamiUitOpen 4:c1beacfc42c7 609
MikamiUitOpen 4:c1beacfc42c7 610 #ifndef __ARMEB__ // Little endian
MikamiUitOpen 4:c1beacfc42c7 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
MikamiUitOpen 4:c1beacfc42c7 612 #else // Big endian
MikamiUitOpen 4:c1beacfc42c7 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
MikamiUitOpen 4:c1beacfc42c7 614 #endif
MikamiUitOpen 4:c1beacfc42c7 615
MikamiUitOpen 4:c1beacfc42c7 616 return(llr.w64);
MikamiUitOpen 4:c1beacfc42c7 617 }
MikamiUitOpen 4:c1beacfc42c7 618
MikamiUitOpen 4:c1beacfc42c7 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 620 {
MikamiUitOpen 4:c1beacfc42c7 621 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 622
MikamiUitOpen 4:c1beacfc42c7 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 624 return(result);
MikamiUitOpen 4:c1beacfc42c7 625 }
MikamiUitOpen 4:c1beacfc42c7 626
MikamiUitOpen 4:c1beacfc42c7 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 628 {
MikamiUitOpen 4:c1beacfc42c7 629 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 630
MikamiUitOpen 4:c1beacfc42c7 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 632 return(result);
MikamiUitOpen 4:c1beacfc42c7 633 }
MikamiUitOpen 4:c1beacfc42c7 634
MikamiUitOpen 4:c1beacfc42c7 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 636 {
MikamiUitOpen 4:c1beacfc42c7 637 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 638
MikamiUitOpen 4:c1beacfc42c7 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 4:c1beacfc42c7 640 return(result);
MikamiUitOpen 4:c1beacfc42c7 641 }
MikamiUitOpen 4:c1beacfc42c7 642
MikamiUitOpen 4:c1beacfc42c7 643 #define __PKHBT(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 644 ({ \
MikamiUitOpen 4:c1beacfc42c7 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 4:c1beacfc42c7 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 4:c1beacfc42c7 647 __RES; \
MikamiUitOpen 4:c1beacfc42c7 648 })
MikamiUitOpen 4:c1beacfc42c7 649
MikamiUitOpen 4:c1beacfc42c7 650 #define __PKHTB(ARG1,ARG2,ARG3) \
MikamiUitOpen 4:c1beacfc42c7 651 ({ \
MikamiUitOpen 4:c1beacfc42c7 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 4:c1beacfc42c7 653 if (ARG3 == 0) \
MikamiUitOpen 4:c1beacfc42c7 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MikamiUitOpen 4:c1beacfc42c7 655 else \
MikamiUitOpen 4:c1beacfc42c7 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 4:c1beacfc42c7 657 __RES; \
MikamiUitOpen 4:c1beacfc42c7 658 })
MikamiUitOpen 4:c1beacfc42c7 659
MikamiUitOpen 4:c1beacfc42c7 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MikamiUitOpen 4:c1beacfc42c7 661 {
MikamiUitOpen 4:c1beacfc42c7 662 int32_t result;
MikamiUitOpen 4:c1beacfc42c7 663
MikamiUitOpen 4:c1beacfc42c7 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 4:c1beacfc42c7 665 return(result);
MikamiUitOpen 4:c1beacfc42c7 666 }
MikamiUitOpen 4:c1beacfc42c7 667
MikamiUitOpen 4:c1beacfc42c7 668
MikamiUitOpen 4:c1beacfc42c7 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 670 /* IAR iccarm specific functions */
MikamiUitOpen 4:c1beacfc42c7 671 #include <cmsis_iar.h>
MikamiUitOpen 4:c1beacfc42c7 672
MikamiUitOpen 4:c1beacfc42c7 673
MikamiUitOpen 4:c1beacfc42c7 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 4:c1beacfc42c7 675 /* TI CCS specific functions */
MikamiUitOpen 4:c1beacfc42c7 676 #include <cmsis_ccs.h>
MikamiUitOpen 4:c1beacfc42c7 677
MikamiUitOpen 4:c1beacfc42c7 678
MikamiUitOpen 4:c1beacfc42c7 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 4:c1beacfc42c7 680 /* TASKING carm specific functions */
MikamiUitOpen 4:c1beacfc42c7 681 /* not yet supported */
MikamiUitOpen 4:c1beacfc42c7 682
MikamiUitOpen 4:c1beacfc42c7 683
MikamiUitOpen 4:c1beacfc42c7 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 685 /* Cosmic specific functions */
MikamiUitOpen 4:c1beacfc42c7 686 #include <cmsis_csm.h>
MikamiUitOpen 4:c1beacfc42c7 687
MikamiUitOpen 4:c1beacfc42c7 688 #endif
MikamiUitOpen 4:c1beacfc42c7 689
MikamiUitOpen 4:c1beacfc42c7 690 /*@} end of group CMSIS_SIMD_intrinsics */
MikamiUitOpen 4:c1beacfc42c7 691
MikamiUitOpen 4:c1beacfc42c7 692
MikamiUitOpen 4:c1beacfc42c7 693 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 694 }
MikamiUitOpen 4:c1beacfc42c7 695 #endif
MikamiUitOpen 4:c1beacfc42c7 696
MikamiUitOpen 4:c1beacfc42c7 697 #endif /* __CORE_CMSIMD_H */