Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム.入力:MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_ca9.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version
MikamiUitOpen 4:c1beacfc42c7 5 * @date 25 March 2013
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #if defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 4:c1beacfc42c7 40 #endif
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 43 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 44 #endif
MikamiUitOpen 4:c1beacfc42c7 45
MikamiUitOpen 4:c1beacfc42c7 46 #ifndef __CORE_CA9_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 47 #define __CORE_CA9_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 48
MikamiUitOpen 4:c1beacfc42c7 49
MikamiUitOpen 4:c1beacfc42c7 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 4:c1beacfc42c7 51 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 4:c1beacfc42c7 52
MikamiUitOpen 4:c1beacfc42c7 53 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 4:c1beacfc42c7 54 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 4:c1beacfc42c7 55
MikamiUitOpen 4:c1beacfc42c7 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 4:c1beacfc42c7 57 Unions are used for effective representation of core registers.
MikamiUitOpen 4:c1beacfc42c7 58
MikamiUitOpen 4:c1beacfc42c7 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 4:c1beacfc42c7 60 Function-like macros are used to allow more efficient code.
MikamiUitOpen 4:c1beacfc42c7 61 */
MikamiUitOpen 4:c1beacfc42c7 62
MikamiUitOpen 4:c1beacfc42c7 63
MikamiUitOpen 4:c1beacfc42c7 64 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 65 * CMSIS definitions
MikamiUitOpen 4:c1beacfc42c7 66 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 67 /** \ingroup Cortex_A9
MikamiUitOpen 4:c1beacfc42c7 68 @{
MikamiUitOpen 4:c1beacfc42c7 69 */
MikamiUitOpen 4:c1beacfc42c7 70
MikamiUitOpen 4:c1beacfc42c7 71 /* CMSIS CA9 definitions */
MikamiUitOpen 4:c1beacfc42c7 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 4:c1beacfc42c7 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 4:c1beacfc42c7 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 4:c1beacfc42c7 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 4:c1beacfc42c7 76
MikamiUitOpen 4:c1beacfc42c7 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
MikamiUitOpen 4:c1beacfc42c7 78
MikamiUitOpen 4:c1beacfc42c7 79
MikamiUitOpen 4:c1beacfc42c7 80 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 83 #define __STATIC_INLINE static __inline
MikamiUitOpen 4:c1beacfc42c7 84 #define __STATIC_ASM static __asm
MikamiUitOpen 4:c1beacfc42c7 85
MikamiUitOpen 4:c1beacfc42c7 86 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 4:c1beacfc42c7 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 4:c1beacfc42c7 89 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 90 #define __STATIC_ASM static __asm
MikamiUitOpen 4:c1beacfc42c7 91
MikamiUitOpen 4:c1beacfc42c7 92 #include <stdint.h>
MikamiUitOpen 4:c1beacfc42c7 93 inline uint32_t __get_PSR(void) {
MikamiUitOpen 4:c1beacfc42c7 94 __ASM("mrs r0, cpsr");
MikamiUitOpen 4:c1beacfc42c7 95 }
MikamiUitOpen 4:c1beacfc42c7 96
MikamiUitOpen 4:c1beacfc42c7 97 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 4:c1beacfc42c7 99 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 100 #define __STATIC_ASM static __asm
MikamiUitOpen 4:c1beacfc42c7 101
MikamiUitOpen 4:c1beacfc42c7 102 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 105 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 106 #define __STATIC_ASM static __asm
MikamiUitOpen 4:c1beacfc42c7 107
MikamiUitOpen 4:c1beacfc42c7 108 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 111 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 112 #define __STATIC_ASM static __asm
MikamiUitOpen 4:c1beacfc42c7 113
MikamiUitOpen 4:c1beacfc42c7 114 #endif
MikamiUitOpen 4:c1beacfc42c7 115
MikamiUitOpen 4:c1beacfc42c7 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MikamiUitOpen 4:c1beacfc42c7 117 */
MikamiUitOpen 4:c1beacfc42c7 118 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 119 #if defined __TARGET_FPU_VFP
MikamiUitOpen 4:c1beacfc42c7 120 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 121 #define __FPU_USED 1
MikamiUitOpen 4:c1beacfc42c7 122 #else
MikamiUitOpen 4:c1beacfc42c7 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 124 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 125 #endif
MikamiUitOpen 4:c1beacfc42c7 126 #else
MikamiUitOpen 4:c1beacfc42c7 127 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 128 #endif
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 131 #if defined __ARMVFP__
MikamiUitOpen 4:c1beacfc42c7 132 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 133 #define __FPU_USED 1
MikamiUitOpen 4:c1beacfc42c7 134 #else
MikamiUitOpen 4:c1beacfc42c7 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 136 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 137 #endif
MikamiUitOpen 4:c1beacfc42c7 138 #else
MikamiUitOpen 4:c1beacfc42c7 139 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 140 #endif
MikamiUitOpen 4:c1beacfc42c7 141
MikamiUitOpen 4:c1beacfc42c7 142 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 143 #if defined __TI_VFP_SUPPORT__
MikamiUitOpen 4:c1beacfc42c7 144 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 145 #define __FPU_USED 1
MikamiUitOpen 4:c1beacfc42c7 146 #else
MikamiUitOpen 4:c1beacfc42c7 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 148 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 149 #endif
MikamiUitOpen 4:c1beacfc42c7 150 #else
MikamiUitOpen 4:c1beacfc42c7 151 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 152 #endif
MikamiUitOpen 4:c1beacfc42c7 153
MikamiUitOpen 4:c1beacfc42c7 154 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 4:c1beacfc42c7 156 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 157 #define __FPU_USED 1
MikamiUitOpen 4:c1beacfc42c7 158 #else
MikamiUitOpen 4:c1beacfc42c7 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 160 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 161 #endif
MikamiUitOpen 4:c1beacfc42c7 162 #else
MikamiUitOpen 4:c1beacfc42c7 163 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 164 #endif
MikamiUitOpen 4:c1beacfc42c7 165
MikamiUitOpen 4:c1beacfc42c7 166 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 167 #if defined __FPU_VFP__
MikamiUitOpen 4:c1beacfc42c7 168 #if (__FPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 169 #define __FPU_USED 1
MikamiUitOpen 4:c1beacfc42c7 170 #else
MikamiUitOpen 4:c1beacfc42c7 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 172 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 173 #endif
MikamiUitOpen 4:c1beacfc42c7 174 #else
MikamiUitOpen 4:c1beacfc42c7 175 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 176 #endif
MikamiUitOpen 4:c1beacfc42c7 177 #endif
MikamiUitOpen 4:c1beacfc42c7 178
MikamiUitOpen 4:c1beacfc42c7 179 #include <stdint.h> /*!< standard types definitions */
MikamiUitOpen 4:c1beacfc42c7 180 #include "core_caInstr.h" /*!< Core Instruction Access */
MikamiUitOpen 4:c1beacfc42c7 181 #include "core_caFunc.h" /*!< Core Function Access */
MikamiUitOpen 4:c1beacfc42c7 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
MikamiUitOpen 4:c1beacfc42c7 183
MikamiUitOpen 4:c1beacfc42c7 184 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 4:c1beacfc42c7 185
MikamiUitOpen 4:c1beacfc42c7 186 #ifndef __CMSIS_GENERIC
MikamiUitOpen 4:c1beacfc42c7 187
MikamiUitOpen 4:c1beacfc42c7 188 #ifndef __CORE_CA9_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 189 #define __CORE_CA9_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 190
MikamiUitOpen 4:c1beacfc42c7 191 /* check device defines and use defaults */
MikamiUitOpen 4:c1beacfc42c7 192 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 4:c1beacfc42c7 193 #ifndef __CA9_REV
MikamiUitOpen 4:c1beacfc42c7 194 #define __CA9_REV 0x0000
MikamiUitOpen 4:c1beacfc42c7 195 #warning "__CA9_REV not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 196 #endif
MikamiUitOpen 4:c1beacfc42c7 197
MikamiUitOpen 4:c1beacfc42c7 198 #ifndef __FPU_PRESENT
MikamiUitOpen 4:c1beacfc42c7 199 #define __FPU_PRESENT 1
MikamiUitOpen 4:c1beacfc42c7 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 201 #endif
MikamiUitOpen 4:c1beacfc42c7 202
MikamiUitOpen 4:c1beacfc42c7 203 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 4:c1beacfc42c7 204 #define __Vendor_SysTickConfig 1
MikamiUitOpen 4:c1beacfc42c7 205 #endif
MikamiUitOpen 4:c1beacfc42c7 206
MikamiUitOpen 4:c1beacfc42c7 207 #if __Vendor_SysTickConfig == 0
MikamiUitOpen 4:c1beacfc42c7 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
MikamiUitOpen 4:c1beacfc42c7 209 #endif
MikamiUitOpen 4:c1beacfc42c7 210 #endif
MikamiUitOpen 4:c1beacfc42c7 211
MikamiUitOpen 4:c1beacfc42c7 212 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 4:c1beacfc42c7 213 /**
MikamiUitOpen 4:c1beacfc42c7 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 4:c1beacfc42c7 215
MikamiUitOpen 4:c1beacfc42c7 216 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 4:c1beacfc42c7 217 \li to specify the access to peripheral variables.
MikamiUitOpen 4:c1beacfc42c7 218 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 4:c1beacfc42c7 219 */
MikamiUitOpen 4:c1beacfc42c7 220 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 221 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 222 #else
MikamiUitOpen 4:c1beacfc42c7 223 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 224 #endif
MikamiUitOpen 4:c1beacfc42c7 225 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 4:c1beacfc42c7 226 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 4:c1beacfc42c7 227
MikamiUitOpen 4:c1beacfc42c7 228 /*@} end of group Cortex_A9 */
MikamiUitOpen 4:c1beacfc42c7 229
MikamiUitOpen 4:c1beacfc42c7 230
MikamiUitOpen 4:c1beacfc42c7 231 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 232 * Register Abstraction
MikamiUitOpen 4:c1beacfc42c7 233 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 4:c1beacfc42c7 235 \brief Type definitions and defines for Cortex-A processor based devices.
MikamiUitOpen 4:c1beacfc42c7 236 */
MikamiUitOpen 4:c1beacfc42c7 237
MikamiUitOpen 4:c1beacfc42c7 238 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 239 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 4:c1beacfc42c7 240 \brief Core Register type definitions.
MikamiUitOpen 4:c1beacfc42c7 241 @{
MikamiUitOpen 4:c1beacfc42c7 242 */
MikamiUitOpen 4:c1beacfc42c7 243
MikamiUitOpen 4:c1beacfc42c7 244 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 4:c1beacfc42c7 245 */
MikamiUitOpen 4:c1beacfc42c7 246 typedef union
MikamiUitOpen 4:c1beacfc42c7 247 {
MikamiUitOpen 4:c1beacfc42c7 248 struct
MikamiUitOpen 4:c1beacfc42c7 249 {
MikamiUitOpen 4:c1beacfc42c7 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
MikamiUitOpen 4:c1beacfc42c7 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
MikamiUitOpen 4:c1beacfc42c7 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
MikamiUitOpen 4:c1beacfc42c7 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 4:c1beacfc42c7 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 4:c1beacfc42c7 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 4:c1beacfc42c7 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 4:c1beacfc42c7 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 4:c1beacfc42c7 258 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 259 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 260 } APSR_Type;
MikamiUitOpen 4:c1beacfc42c7 261
MikamiUitOpen 4:c1beacfc42c7 262
MikamiUitOpen 4:c1beacfc42c7 263 /*@} end of group CMSIS_CORE */
MikamiUitOpen 4:c1beacfc42c7 264
MikamiUitOpen 4:c1beacfc42c7 265 /*@} end of CMSIS_Core_FPUFunctions */
MikamiUitOpen 4:c1beacfc42c7 266
MikamiUitOpen 4:c1beacfc42c7 267
MikamiUitOpen 4:c1beacfc42c7 268 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 4:c1beacfc42c7 269
MikamiUitOpen 4:c1beacfc42c7 270 #endif /* __CMSIS_GENERIC */
MikamiUitOpen 4:c1beacfc42c7 271
MikamiUitOpen 4:c1beacfc42c7 272 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 273 }
MikamiUitOpen 4:c1beacfc42c7 274
MikamiUitOpen 4:c1beacfc42c7 275
MikamiUitOpen 4:c1beacfc42c7 276 #endif