不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/hal/spi_api.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /* mbed Microcontroller Library
MikamiUitOpen 4:c1beacfc42c7 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 4:c1beacfc42c7 3 *
MikamiUitOpen 4:c1beacfc42c7 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 4:c1beacfc42c7 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 4:c1beacfc42c7 6 * You may obtain a copy of the License at
MikamiUitOpen 4:c1beacfc42c7 7 *
MikamiUitOpen 4:c1beacfc42c7 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 4:c1beacfc42c7 9 *
MikamiUitOpen 4:c1beacfc42c7 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 4:c1beacfc42c7 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 4:c1beacfc42c7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 4:c1beacfc42c7 13 * See the License for the specific language governing permissions and
MikamiUitOpen 4:c1beacfc42c7 14 * limitations under the License.
MikamiUitOpen 4:c1beacfc42c7 15 */
MikamiUitOpen 4:c1beacfc42c7 16 #ifndef MBED_SPI_API_H
MikamiUitOpen 4:c1beacfc42c7 17 #define MBED_SPI_API_H
MikamiUitOpen 4:c1beacfc42c7 18
MikamiUitOpen 4:c1beacfc42c7 19 #include "device.h"
MikamiUitOpen 4:c1beacfc42c7 20 #include "dma_api.h"
MikamiUitOpen 4:c1beacfc42c7 21 #include "buffer.h"
MikamiUitOpen 4:c1beacfc42c7 22
MikamiUitOpen 4:c1beacfc42c7 23 #if DEVICE_SPI
MikamiUitOpen 4:c1beacfc42c7 24
MikamiUitOpen 4:c1beacfc42c7 25 #define SPI_EVENT_ERROR (1 << 1)
MikamiUitOpen 4:c1beacfc42c7 26 #define SPI_EVENT_COMPLETE (1 << 2)
MikamiUitOpen 4:c1beacfc42c7 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
MikamiUitOpen 4:c1beacfc42c7 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
MikamiUitOpen 4:c1beacfc42c7 29
MikamiUitOpen 4:c1beacfc42c7 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
MikamiUitOpen 4:c1beacfc42c7 31
MikamiUitOpen 4:c1beacfc42c7 32 #define SPI_FILL_WORD (0xFFFF)
MikamiUitOpen 4:c1beacfc42c7 33
MikamiUitOpen 4:c1beacfc42c7 34 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 4:c1beacfc42c7 35 /** Asynch spi hal structure
MikamiUitOpen 4:c1beacfc42c7 36 */
MikamiUitOpen 4:c1beacfc42c7 37 typedef struct {
MikamiUitOpen 4:c1beacfc42c7 38 struct spi_s spi; /**< Target specific spi structure */
MikamiUitOpen 4:c1beacfc42c7 39 struct buffer_s tx_buff; /**< Tx buffer */
MikamiUitOpen 4:c1beacfc42c7 40 struct buffer_s rx_buff; /**< Rx buffer */
MikamiUitOpen 4:c1beacfc42c7 41 } spi_t;
MikamiUitOpen 4:c1beacfc42c7 42
MikamiUitOpen 4:c1beacfc42c7 43 #else
MikamiUitOpen 4:c1beacfc42c7 44 /** Non-asynch spi hal structure
MikamiUitOpen 4:c1beacfc42c7 45 */
MikamiUitOpen 4:c1beacfc42c7 46 typedef struct spi_s spi_t;
MikamiUitOpen 4:c1beacfc42c7 47
MikamiUitOpen 4:c1beacfc42c7 48 #endif
MikamiUitOpen 4:c1beacfc42c7 49
MikamiUitOpen 4:c1beacfc42c7 50 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 51 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 52 #endif
MikamiUitOpen 4:c1beacfc42c7 53
MikamiUitOpen 4:c1beacfc42c7 54 /**
MikamiUitOpen 4:c1beacfc42c7 55 * \defgroup GeneralSPI SPI Configuration Functions
MikamiUitOpen 4:c1beacfc42c7 56 * @{
MikamiUitOpen 4:c1beacfc42c7 57 */
MikamiUitOpen 4:c1beacfc42c7 58
MikamiUitOpen 4:c1beacfc42c7 59 /** Initialize the SPI peripheral
MikamiUitOpen 4:c1beacfc42c7 60 *
MikamiUitOpen 4:c1beacfc42c7 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
MikamiUitOpen 4:c1beacfc42c7 62 * @param[out] obj The SPI object to initialize
MikamiUitOpen 4:c1beacfc42c7 63 * @param[in] mosi The pin to use for MOSI
MikamiUitOpen 4:c1beacfc42c7 64 * @param[in] miso The pin to use for MISO
MikamiUitOpen 4:c1beacfc42c7 65 * @param[in] sclk The pin to use for SCLK
MikamiUitOpen 4:c1beacfc42c7 66 * @param[in] ssel The pin to use for SSEL
MikamiUitOpen 4:c1beacfc42c7 67 */
MikamiUitOpen 4:c1beacfc42c7 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70 /** Release a SPI object
MikamiUitOpen 4:c1beacfc42c7 71 *
MikamiUitOpen 4:c1beacfc42c7 72 * TODO: spi_free is currently unimplemented
MikamiUitOpen 4:c1beacfc42c7 73 * This will require reference counting at the C++ level to be safe
MikamiUitOpen 4:c1beacfc42c7 74 *
MikamiUitOpen 4:c1beacfc42c7 75 * Return the pins owned by the SPI object to their reset state
MikamiUitOpen 4:c1beacfc42c7 76 * Disable the SPI peripheral
MikamiUitOpen 4:c1beacfc42c7 77 * Disable the SPI clock
MikamiUitOpen 4:c1beacfc42c7 78 * @param[in] obj The SPI object to deinitialize
MikamiUitOpen 4:c1beacfc42c7 79 */
MikamiUitOpen 4:c1beacfc42c7 80 void spi_free(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 81
MikamiUitOpen 4:c1beacfc42c7 82 /** Configure the SPI format
MikamiUitOpen 4:c1beacfc42c7 83 *
MikamiUitOpen 4:c1beacfc42c7 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
MikamiUitOpen 4:c1beacfc42c7 85 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 4:c1beacfc42c7 86 * @param[in] bits The number of bits per frame
MikamiUitOpen 4:c1beacfc42c7 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
MikamiUitOpen 4:c1beacfc42c7 88 * @param[in] slave Zero for master mode or non-zero for slave mode
MikamiUitOpen 4:c1beacfc42c7 89 */
MikamiUitOpen 4:c1beacfc42c7 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
MikamiUitOpen 4:c1beacfc42c7 91
MikamiUitOpen 4:c1beacfc42c7 92 /** Set the SPI baud rate
MikamiUitOpen 4:c1beacfc42c7 93 *
MikamiUitOpen 4:c1beacfc42c7 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
MikamiUitOpen 4:c1beacfc42c7 95 * Configures the SPI peripheral's baud rate
MikamiUitOpen 4:c1beacfc42c7 96 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 4:c1beacfc42c7 97 * @param[in] hz The baud rate in Hz
MikamiUitOpen 4:c1beacfc42c7 98 */
MikamiUitOpen 4:c1beacfc42c7 99 void spi_frequency(spi_t *obj, int hz);
MikamiUitOpen 4:c1beacfc42c7 100
MikamiUitOpen 4:c1beacfc42c7 101 /**@}*/
MikamiUitOpen 4:c1beacfc42c7 102 /**
MikamiUitOpen 4:c1beacfc42c7 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 104 * @{
MikamiUitOpen 4:c1beacfc42c7 105 */
MikamiUitOpen 4:c1beacfc42c7 106
MikamiUitOpen 4:c1beacfc42c7 107 /** Write a byte out in master mode and receive a value
MikamiUitOpen 4:c1beacfc42c7 108 *
MikamiUitOpen 4:c1beacfc42c7 109 * @param[in] obj The SPI peripheral to use for sending
MikamiUitOpen 4:c1beacfc42c7 110 * @param[in] value The value to send
MikamiUitOpen 4:c1beacfc42c7 111 * @return Returns the value received during send
MikamiUitOpen 4:c1beacfc42c7 112 */
MikamiUitOpen 4:c1beacfc42c7 113 int spi_master_write(spi_t *obj, int value);
MikamiUitOpen 4:c1beacfc42c7 114
MikamiUitOpen 4:c1beacfc42c7 115 /** Check if a value is available to read
MikamiUitOpen 4:c1beacfc42c7 116 *
MikamiUitOpen 4:c1beacfc42c7 117 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 4:c1beacfc42c7 118 * @return non-zero if a value is available
MikamiUitOpen 4:c1beacfc42c7 119 */
MikamiUitOpen 4:c1beacfc42c7 120 int spi_slave_receive(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 121
MikamiUitOpen 4:c1beacfc42c7 122 /** Get a received value out of the SPI receive buffer in slave mode
MikamiUitOpen 4:c1beacfc42c7 123 *
MikamiUitOpen 4:c1beacfc42c7 124 * Blocks until a value is available
MikamiUitOpen 4:c1beacfc42c7 125 * @param[in] obj The SPI peripheral to read
MikamiUitOpen 4:c1beacfc42c7 126 * @return The value received
MikamiUitOpen 4:c1beacfc42c7 127 */
MikamiUitOpen 4:c1beacfc42c7 128 int spi_slave_read(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 /** Write a value to the SPI peripheral in slave mode
MikamiUitOpen 4:c1beacfc42c7 131 *
MikamiUitOpen 4:c1beacfc42c7 132 * Blocks until the SPI peripheral can be written to
MikamiUitOpen 4:c1beacfc42c7 133 * @param[in] obj The SPI peripheral to write
MikamiUitOpen 4:c1beacfc42c7 134 * @param[in] value The value to write
MikamiUitOpen 4:c1beacfc42c7 135 */
MikamiUitOpen 4:c1beacfc42c7 136 void spi_slave_write(spi_t *obj, int value);
MikamiUitOpen 4:c1beacfc42c7 137
MikamiUitOpen 4:c1beacfc42c7 138 /** Checks if the specified SPI peripheral is in use
MikamiUitOpen 4:c1beacfc42c7 139 *
MikamiUitOpen 4:c1beacfc42c7 140 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 4:c1beacfc42c7 141 * @return non-zero if the peripheral is currently transmitting
MikamiUitOpen 4:c1beacfc42c7 142 */
MikamiUitOpen 4:c1beacfc42c7 143 int spi_busy(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 144
MikamiUitOpen 4:c1beacfc42c7 145 /** Get the module number
MikamiUitOpen 4:c1beacfc42c7 146 *
MikamiUitOpen 4:c1beacfc42c7 147 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 4:c1beacfc42c7 148 * @return The module number
MikamiUitOpen 4:c1beacfc42c7 149 */
MikamiUitOpen 4:c1beacfc42c7 150 uint8_t spi_get_module(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 151
MikamiUitOpen 4:c1beacfc42c7 152 /**@}*/
MikamiUitOpen 4:c1beacfc42c7 153
MikamiUitOpen 4:c1beacfc42c7 154 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 4:c1beacfc42c7 155 /**
MikamiUitOpen 4:c1beacfc42c7 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 157 * @{
MikamiUitOpen 4:c1beacfc42c7 158 */
MikamiUitOpen 4:c1beacfc42c7 159
MikamiUitOpen 4:c1beacfc42c7 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
MikamiUitOpen 4:c1beacfc42c7 161 *
MikamiUitOpen 4:c1beacfc42c7 162 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 4:c1beacfc42c7 163 * @param[in] tx The buffer to send
MikamiUitOpen 4:c1beacfc42c7 164 * @param[in] tx_length The number of words to transmit
MikamiUitOpen 4:c1beacfc42c7 165 * @param[in] rx The buffer to receive
MikamiUitOpen 4:c1beacfc42c7 166 * @param[in] rx_length The number of words to receive
MikamiUitOpen 4:c1beacfc42c7 167 * @param[in] bit_width The bit width of buffer words
MikamiUitOpen 4:c1beacfc42c7 168 * @param[in] event The logical OR of events to be registered
MikamiUitOpen 4:c1beacfc42c7 169 * @param[in] handler SPI interrupt handler
MikamiUitOpen 4:c1beacfc42c7 170 * @param[in] hint A suggestion for how to use DMA with this transfer
MikamiUitOpen 4:c1beacfc42c7 171 */
MikamiUitOpen 4:c1beacfc42c7 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
MikamiUitOpen 4:c1beacfc42c7 173
MikamiUitOpen 4:c1beacfc42c7 174 /** The asynchronous IRQ handler
MikamiUitOpen 4:c1beacfc42c7 175 *
MikamiUitOpen 4:c1beacfc42c7 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
MikamiUitOpen 4:c1beacfc42c7 177 * conditions, such as buffer overflows or transfer complete.
MikamiUitOpen 4:c1beacfc42c7 178 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 4:c1beacfc42c7 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
MikamiUitOpen 4:c1beacfc42c7 180 */
MikamiUitOpen 4:c1beacfc42c7 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 182
MikamiUitOpen 4:c1beacfc42c7 183 /** Attempts to determine if the SPI peripheral is already in use.
MikamiUitOpen 4:c1beacfc42c7 184 *
MikamiUitOpen 4:c1beacfc42c7 185 * If a temporary DMA channel has been allocated, peripheral is in use.
MikamiUitOpen 4:c1beacfc42c7 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
MikamiUitOpen 4:c1beacfc42c7 187 * channel were allocated.
MikamiUitOpen 4:c1beacfc42c7 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
MikamiUitOpen 4:c1beacfc42c7 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
MikamiUitOpen 4:c1beacfc42c7 190 * there are any bytes in the FIFOs.
MikamiUitOpen 4:c1beacfc42c7 191 * @param[in] obj The SPI object to check for activity
MikamiUitOpen 4:c1beacfc42c7 192 * @return non-zero if the SPI port is active or zero if it is not.
MikamiUitOpen 4:c1beacfc42c7 193 */
MikamiUitOpen 4:c1beacfc42c7 194 uint8_t spi_active(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 195
MikamiUitOpen 4:c1beacfc42c7 196 /** Abort an SPI transfer
MikamiUitOpen 4:c1beacfc42c7 197 *
MikamiUitOpen 4:c1beacfc42c7 198 * @param obj The SPI peripheral to stop
MikamiUitOpen 4:c1beacfc42c7 199 */
MikamiUitOpen 4:c1beacfc42c7 200 void spi_abort_asynch(spi_t *obj);
MikamiUitOpen 4:c1beacfc42c7 201
MikamiUitOpen 4:c1beacfc42c7 202
MikamiUitOpen 4:c1beacfc42c7 203 #endif
MikamiUitOpen 4:c1beacfc42c7 204
MikamiUitOpen 4:c1beacfc42c7 205 /**@}*/
MikamiUitOpen 4:c1beacfc42c7 206
MikamiUitOpen 4:c1beacfc42c7 207 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 208 }
MikamiUitOpen 4:c1beacfc42c7 209 #endif // __cplusplus
MikamiUitOpen 4:c1beacfc42c7 210
MikamiUitOpen 4:c1beacfc42c7 211 #endif // SPI_DEVICE
MikamiUitOpen 4:c1beacfc42c7 212
MikamiUitOpen 4:c1beacfc42c7 213 #endif // MBED_SPI_API_H