不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/common/SPI.cpp@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /* mbed Microcontroller Library
MikamiUitOpen 4:c1beacfc42c7 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 4:c1beacfc42c7 3 *
MikamiUitOpen 4:c1beacfc42c7 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 4:c1beacfc42c7 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 4:c1beacfc42c7 6 * You may obtain a copy of the License at
MikamiUitOpen 4:c1beacfc42c7 7 *
MikamiUitOpen 4:c1beacfc42c7 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 4:c1beacfc42c7 9 *
MikamiUitOpen 4:c1beacfc42c7 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 4:c1beacfc42c7 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 4:c1beacfc42c7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 4:c1beacfc42c7 13 * See the License for the specific language governing permissions and
MikamiUitOpen 4:c1beacfc42c7 14 * limitations under the License.
MikamiUitOpen 4:c1beacfc42c7 15 */
MikamiUitOpen 4:c1beacfc42c7 16 #include "SPI.h"
MikamiUitOpen 4:c1beacfc42c7 17
MikamiUitOpen 4:c1beacfc42c7 18 #if DEVICE_SPI
MikamiUitOpen 4:c1beacfc42c7 19
MikamiUitOpen 4:c1beacfc42c7 20 namespace mbed {
MikamiUitOpen 4:c1beacfc42c7 21
MikamiUitOpen 4:c1beacfc42c7 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
MikamiUitOpen 4:c1beacfc42c7 24 #endif
MikamiUitOpen 4:c1beacfc42c7 25
MikamiUitOpen 4:c1beacfc42c7 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
MikamiUitOpen 4:c1beacfc42c7 27 _spi(),
MikamiUitOpen 4:c1beacfc42c7 28 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 4:c1beacfc42c7 29 _irq(this),
MikamiUitOpen 4:c1beacfc42c7 30 _usage(DMA_USAGE_NEVER),
MikamiUitOpen 4:c1beacfc42c7 31 #endif
MikamiUitOpen 4:c1beacfc42c7 32 _bits(8),
MikamiUitOpen 4:c1beacfc42c7 33 _mode(0),
MikamiUitOpen 4:c1beacfc42c7 34 _hz(1000000) {
MikamiUitOpen 4:c1beacfc42c7 35 spi_init(&_spi, mosi, miso, sclk, ssel);
MikamiUitOpen 4:c1beacfc42c7 36 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 4:c1beacfc42c7 37 spi_frequency(&_spi, _hz);
MikamiUitOpen 4:c1beacfc42c7 38 }
MikamiUitOpen 4:c1beacfc42c7 39
MikamiUitOpen 4:c1beacfc42c7 40 void SPI::format(int bits, int mode) {
MikamiUitOpen 4:c1beacfc42c7 41 _bits = bits;
MikamiUitOpen 4:c1beacfc42c7 42 _mode = mode;
MikamiUitOpen 4:c1beacfc42c7 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 4:c1beacfc42c7 44 aquire();
MikamiUitOpen 4:c1beacfc42c7 45 }
MikamiUitOpen 4:c1beacfc42c7 46
MikamiUitOpen 4:c1beacfc42c7 47 void SPI::frequency(int hz) {
MikamiUitOpen 4:c1beacfc42c7 48 _hz = hz;
MikamiUitOpen 4:c1beacfc42c7 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 4:c1beacfc42c7 50 aquire();
MikamiUitOpen 4:c1beacfc42c7 51 }
MikamiUitOpen 4:c1beacfc42c7 52
MikamiUitOpen 4:c1beacfc42c7 53 SPI* SPI::_owner = NULL;
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
MikamiUitOpen 4:c1beacfc42c7 56 void SPI::aquire() {
MikamiUitOpen 4:c1beacfc42c7 57 if (_owner != this) {
MikamiUitOpen 4:c1beacfc42c7 58 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 4:c1beacfc42c7 59 spi_frequency(&_spi, _hz);
MikamiUitOpen 4:c1beacfc42c7 60 _owner = this;
MikamiUitOpen 4:c1beacfc42c7 61 }
MikamiUitOpen 4:c1beacfc42c7 62 }
MikamiUitOpen 4:c1beacfc42c7 63
MikamiUitOpen 4:c1beacfc42c7 64 int SPI::write(int value) {
MikamiUitOpen 4:c1beacfc42c7 65 aquire();
MikamiUitOpen 4:c1beacfc42c7 66 return spi_master_write(&_spi, value);
MikamiUitOpen 4:c1beacfc42c7 67 }
MikamiUitOpen 4:c1beacfc42c7 68
MikamiUitOpen 4:c1beacfc42c7 69 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 4:c1beacfc42c7 70
MikamiUitOpen 4:c1beacfc42c7 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 4:c1beacfc42c7 72 {
MikamiUitOpen 4:c1beacfc42c7 73 if (spi_active(&_spi)) {
MikamiUitOpen 4:c1beacfc42c7 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 4:c1beacfc42c7 75 }
MikamiUitOpen 4:c1beacfc42c7 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 4:c1beacfc42c7 77 return 0;
MikamiUitOpen 4:c1beacfc42c7 78 }
MikamiUitOpen 4:c1beacfc42c7 79
MikamiUitOpen 4:c1beacfc42c7 80 void SPI::abort_transfer()
MikamiUitOpen 4:c1beacfc42c7 81 {
MikamiUitOpen 4:c1beacfc42c7 82 spi_abort_asynch(&_spi);
MikamiUitOpen 4:c1beacfc42c7 83 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 84 dequeue_transaction();
MikamiUitOpen 4:c1beacfc42c7 85 #endif
MikamiUitOpen 4:c1beacfc42c7 86 }
MikamiUitOpen 4:c1beacfc42c7 87
MikamiUitOpen 4:c1beacfc42c7 88
MikamiUitOpen 4:c1beacfc42c7 89 void SPI::clear_transfer_buffer()
MikamiUitOpen 4:c1beacfc42c7 90 {
MikamiUitOpen 4:c1beacfc42c7 91 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 92 _transaction_buffer.reset();
MikamiUitOpen 4:c1beacfc42c7 93 #endif
MikamiUitOpen 4:c1beacfc42c7 94 }
MikamiUitOpen 4:c1beacfc42c7 95
MikamiUitOpen 4:c1beacfc42c7 96 void SPI::abort_all_transfers()
MikamiUitOpen 4:c1beacfc42c7 97 {
MikamiUitOpen 4:c1beacfc42c7 98 clear_transfer_buffer();
MikamiUitOpen 4:c1beacfc42c7 99 abort_transfer();
MikamiUitOpen 4:c1beacfc42c7 100 }
MikamiUitOpen 4:c1beacfc42c7 101
MikamiUitOpen 4:c1beacfc42c7 102 int SPI::set_dma_usage(DMAUsage usage)
MikamiUitOpen 4:c1beacfc42c7 103 {
MikamiUitOpen 4:c1beacfc42c7 104 if (spi_active(&_spi)) {
MikamiUitOpen 4:c1beacfc42c7 105 return -1;
MikamiUitOpen 4:c1beacfc42c7 106 }
MikamiUitOpen 4:c1beacfc42c7 107 _usage = usage;
MikamiUitOpen 4:c1beacfc42c7 108 return 0;
MikamiUitOpen 4:c1beacfc42c7 109 }
MikamiUitOpen 4:c1beacfc42c7 110
MikamiUitOpen 4:c1beacfc42c7 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 4:c1beacfc42c7 112 {
MikamiUitOpen 4:c1beacfc42c7 113 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 114 transaction_t t;
MikamiUitOpen 4:c1beacfc42c7 115
MikamiUitOpen 4:c1beacfc42c7 116 t.tx_buffer = const_cast<void *>(tx_buffer);
MikamiUitOpen 4:c1beacfc42c7 117 t.tx_length = tx_length;
MikamiUitOpen 4:c1beacfc42c7 118 t.rx_buffer = rx_buffer;
MikamiUitOpen 4:c1beacfc42c7 119 t.rx_length = rx_length;
MikamiUitOpen 4:c1beacfc42c7 120 t.event = event;
MikamiUitOpen 4:c1beacfc42c7 121 t.callback = callback;
MikamiUitOpen 4:c1beacfc42c7 122 t.width = bit_width;
MikamiUitOpen 4:c1beacfc42c7 123 Transaction<SPI> transaction(this, t);
MikamiUitOpen 4:c1beacfc42c7 124 if (_transaction_buffer.full()) {
MikamiUitOpen 4:c1beacfc42c7 125 return -1; // the buffer is full
MikamiUitOpen 4:c1beacfc42c7 126 } else {
MikamiUitOpen 4:c1beacfc42c7 127 __disable_irq();
MikamiUitOpen 4:c1beacfc42c7 128 _transaction_buffer.push(transaction);
MikamiUitOpen 4:c1beacfc42c7 129 if (!spi_active(&_spi)) {
MikamiUitOpen 4:c1beacfc42c7 130 dequeue_transaction();
MikamiUitOpen 4:c1beacfc42c7 131 }
MikamiUitOpen 4:c1beacfc42c7 132 __enable_irq();
MikamiUitOpen 4:c1beacfc42c7 133 return 0;
MikamiUitOpen 4:c1beacfc42c7 134 }
MikamiUitOpen 4:c1beacfc42c7 135 #else
MikamiUitOpen 4:c1beacfc42c7 136 return -1;
MikamiUitOpen 4:c1beacfc42c7 137 #endif
MikamiUitOpen 4:c1beacfc42c7 138 }
MikamiUitOpen 4:c1beacfc42c7 139
MikamiUitOpen 4:c1beacfc42c7 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 4:c1beacfc42c7 141 {
MikamiUitOpen 4:c1beacfc42c7 142 aquire();
MikamiUitOpen 4:c1beacfc42c7 143 _callback = callback;
MikamiUitOpen 4:c1beacfc42c7 144 _irq.callback(&SPI::irq_handler_asynch);
MikamiUitOpen 4:c1beacfc42c7 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
MikamiUitOpen 4:c1beacfc42c7 146 }
MikamiUitOpen 4:c1beacfc42c7 147
MikamiUitOpen 4:c1beacfc42c7 148 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 149
MikamiUitOpen 4:c1beacfc42c7 150 void SPI::start_transaction(transaction_t *data)
MikamiUitOpen 4:c1beacfc42c7 151 {
MikamiUitOpen 4:c1beacfc42c7 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
MikamiUitOpen 4:c1beacfc42c7 153 }
MikamiUitOpen 4:c1beacfc42c7 154
MikamiUitOpen 4:c1beacfc42c7 155 void SPI::dequeue_transaction()
MikamiUitOpen 4:c1beacfc42c7 156 {
MikamiUitOpen 4:c1beacfc42c7 157 Transaction<SPI> t;
MikamiUitOpen 4:c1beacfc42c7 158 if (_transaction_buffer.pop(t)) {
MikamiUitOpen 4:c1beacfc42c7 159 SPI* obj = t.get_object();
MikamiUitOpen 4:c1beacfc42c7 160 transaction_t* data = t.get_transaction();
MikamiUitOpen 4:c1beacfc42c7 161 obj->start_transaction(data);
MikamiUitOpen 4:c1beacfc42c7 162 }
MikamiUitOpen 4:c1beacfc42c7 163 }
MikamiUitOpen 4:c1beacfc42c7 164
MikamiUitOpen 4:c1beacfc42c7 165 #endif
MikamiUitOpen 4:c1beacfc42c7 166
MikamiUitOpen 4:c1beacfc42c7 167 void SPI::irq_handler_asynch(void)
MikamiUitOpen 4:c1beacfc42c7 168 {
MikamiUitOpen 4:c1beacfc42c7 169 int event = spi_irq_handler_asynch(&_spi);
MikamiUitOpen 4:c1beacfc42c7 170 if (_callback && (event & SPI_EVENT_ALL)) {
MikamiUitOpen 4:c1beacfc42c7 171 _callback.call(event & SPI_EVENT_ALL);
MikamiUitOpen 4:c1beacfc42c7 172 }
MikamiUitOpen 4:c1beacfc42c7 173 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 4:c1beacfc42c7 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
MikamiUitOpen 4:c1beacfc42c7 175 // SPI peripheral is free (event happend), dequeue transaction
MikamiUitOpen 4:c1beacfc42c7 176 dequeue_transaction();
MikamiUitOpen 4:c1beacfc42c7 177 }
MikamiUitOpen 4:c1beacfc42c7 178 #endif
MikamiUitOpen 4:c1beacfc42c7 179 }
MikamiUitOpen 4:c1beacfc42c7 180
MikamiUitOpen 4:c1beacfc42c7 181 #endif
MikamiUitOpen 4:c1beacfc42c7 182
MikamiUitOpen 4:c1beacfc42c7 183 } // namespace mbed
MikamiUitOpen 4:c1beacfc42c7 184
MikamiUitOpen 4:c1beacfc42c7 185 #endif