不韋 呂 / F746_SD_Player_Demo

Demo program for library named SD_PlayerSkeleton of SD card player skeleton. SD カードプレーヤのための骨組みとして使うためのライブラリ SD_PlayerSkeleton の使用例．このプログラムについては，CQ出版社インターフェース誌 2018年7月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton

mbed_src_STM32F7/hal/spi_api.h@19:3c3833ec00d2, 2017-04-09 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Apr 09 12:44:17 2017 +0000
Revision:
19:3c3833ec00d2
Parent:
2:cf42e62a97dc 
20

Who changed what in which revision?

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MikamiUitOpen 2:cf42e62a97dc 1 /* mbed Microcontroller Library
MikamiUitOpen 2:cf42e62a97dc 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 2:cf42e62a97dc 3 *
MikamiUitOpen 2:cf42e62a97dc 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 2:cf42e62a97dc 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 2:cf42e62a97dc 6 * You may obtain a copy of the License at
MikamiUitOpen 2:cf42e62a97dc 7 *
MikamiUitOpen 2:cf42e62a97dc 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 2:cf42e62a97dc 9 *
MikamiUitOpen 2:cf42e62a97dc 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 2:cf42e62a97dc 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 2:cf42e62a97dc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 2:cf42e62a97dc 13 * See the License for the specific language governing permissions and
MikamiUitOpen 2:cf42e62a97dc 14 * limitations under the License.
MikamiUitOpen 2:cf42e62a97dc 15 */
MikamiUitOpen 2:cf42e62a97dc 16 #ifndef MBED_SPI_API_H
MikamiUitOpen 2:cf42e62a97dc 17 #define MBED_SPI_API_H
MikamiUitOpen 2:cf42e62a97dc 18
MikamiUitOpen 2:cf42e62a97dc 19 #include "device.h"
MikamiUitOpen 2:cf42e62a97dc 20 #include "dma_api.h"
MikamiUitOpen 2:cf42e62a97dc 21 #include "buffer.h"
MikamiUitOpen 2:cf42e62a97dc 22
MikamiUitOpen 2:cf42e62a97dc 23 #if DEVICE_SPI
MikamiUitOpen 2:cf42e62a97dc 24
MikamiUitOpen 2:cf42e62a97dc 25 #define SPI_EVENT_ERROR (1 << 1)
MikamiUitOpen 2:cf42e62a97dc 26 #define SPI_EVENT_COMPLETE (1 << 2)
MikamiUitOpen 2:cf42e62a97dc 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
MikamiUitOpen 2:cf42e62a97dc 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
MikamiUitOpen 2:cf42e62a97dc 29
MikamiUitOpen 2:cf42e62a97dc 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
MikamiUitOpen 2:cf42e62a97dc 31
MikamiUitOpen 2:cf42e62a97dc 32 #define SPI_FILL_WORD (0xFFFF)
MikamiUitOpen 2:cf42e62a97dc 33
MikamiUitOpen 2:cf42e62a97dc 34 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 35 /** Asynch spi hal structure
MikamiUitOpen 2:cf42e62a97dc 36 */
MikamiUitOpen 2:cf42e62a97dc 37 typedef struct {
MikamiUitOpen 2:cf42e62a97dc 38 struct spi_s spi; /**< Target specific spi structure */
MikamiUitOpen 2:cf42e62a97dc 39 struct buffer_s tx_buff; /**< Tx buffer */
MikamiUitOpen 2:cf42e62a97dc 40 struct buffer_s rx_buff; /**< Rx buffer */
MikamiUitOpen 2:cf42e62a97dc 41 } spi_t;
MikamiUitOpen 2:cf42e62a97dc 42
MikamiUitOpen 2:cf42e62a97dc 43 #else
MikamiUitOpen 2:cf42e62a97dc 44 /** Non-asynch spi hal structure
MikamiUitOpen 2:cf42e62a97dc 45 */
MikamiUitOpen 2:cf42e62a97dc 46 typedef struct spi_s spi_t;
MikamiUitOpen 2:cf42e62a97dc 47
MikamiUitOpen 2:cf42e62a97dc 48 #endif
MikamiUitOpen 2:cf42e62a97dc 49
MikamiUitOpen 2:cf42e62a97dc 50 #ifdef __cplusplus
MikamiUitOpen 2:cf42e62a97dc 51 extern "C" {
MikamiUitOpen 2:cf42e62a97dc 52 #endif
MikamiUitOpen 2:cf42e62a97dc 53
MikamiUitOpen 2:cf42e62a97dc 54 /**
MikamiUitOpen 2:cf42e62a97dc 55 * \defgroup GeneralSPI SPI Configuration Functions
MikamiUitOpen 2:cf42e62a97dc 56 * @{
MikamiUitOpen 2:cf42e62a97dc 57 */
MikamiUitOpen 2:cf42e62a97dc 58
MikamiUitOpen 2:cf42e62a97dc 59 /** Initialize the SPI peripheral
MikamiUitOpen 2:cf42e62a97dc 60 *
MikamiUitOpen 2:cf42e62a97dc 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
MikamiUitOpen 2:cf42e62a97dc 62 * @param[out] obj The SPI object to initialize
MikamiUitOpen 2:cf42e62a97dc 63 * @param[in] mosi The pin to use for MOSI
MikamiUitOpen 2:cf42e62a97dc 64 * @param[in] miso The pin to use for MISO
MikamiUitOpen 2:cf42e62a97dc 65 * @param[in] sclk The pin to use for SCLK
MikamiUitOpen 2:cf42e62a97dc 66 * @param[in] ssel The pin to use for SSEL
MikamiUitOpen 2:cf42e62a97dc 67 */
MikamiUitOpen 2:cf42e62a97dc 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
MikamiUitOpen 2:cf42e62a97dc 69
MikamiUitOpen 2:cf42e62a97dc 70 /** Release a SPI object
MikamiUitOpen 2:cf42e62a97dc 71 *
MikamiUitOpen 2:cf42e62a97dc 72 * TODO: spi_free is currently unimplemented
MikamiUitOpen 2:cf42e62a97dc 73 * This will require reference counting at the C++ level to be safe
MikamiUitOpen 2:cf42e62a97dc 74 *
MikamiUitOpen 2:cf42e62a97dc 75 * Return the pins owned by the SPI object to their reset state
MikamiUitOpen 2:cf42e62a97dc 76 * Disable the SPI peripheral
MikamiUitOpen 2:cf42e62a97dc 77 * Disable the SPI clock
MikamiUitOpen 2:cf42e62a97dc 78 * @param[in] obj The SPI object to deinitialize
MikamiUitOpen 2:cf42e62a97dc 79 */
MikamiUitOpen 2:cf42e62a97dc 80 void spi_free(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 81
MikamiUitOpen 2:cf42e62a97dc 82 /** Configure the SPI format
MikamiUitOpen 2:cf42e62a97dc 83 *
MikamiUitOpen 2:cf42e62a97dc 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
MikamiUitOpen 2:cf42e62a97dc 85 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 2:cf42e62a97dc 86 * @param[in] bits The number of bits per frame
MikamiUitOpen 2:cf42e62a97dc 87 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
MikamiUitOpen 2:cf42e62a97dc 88 * @param[in] slave Zero for master mode or non-zero for slave mode
MikamiUitOpen 2:cf42e62a97dc 89 */
MikamiUitOpen 2:cf42e62a97dc 90 void spi_format(spi_t *obj, int bits, int mode, int slave);
MikamiUitOpen 2:cf42e62a97dc 91
MikamiUitOpen 2:cf42e62a97dc 92 /** Set the SPI baud rate
MikamiUitOpen 2:cf42e62a97dc 93 *
MikamiUitOpen 2:cf42e62a97dc 94 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
MikamiUitOpen 2:cf42e62a97dc 95 * Configures the SPI peripheral's baud rate
MikamiUitOpen 2:cf42e62a97dc 96 * @param[in,out] obj The SPI object to configure
MikamiUitOpen 2:cf42e62a97dc 97 * @param[in] hz The baud rate in Hz
MikamiUitOpen 2:cf42e62a97dc 98 */
MikamiUitOpen 2:cf42e62a97dc 99 void spi_frequency(spi_t *obj, int hz);
MikamiUitOpen 2:cf42e62a97dc 100
MikamiUitOpen 2:cf42e62a97dc 101 /**@}*/
MikamiUitOpen 2:cf42e62a97dc 102 /**
MikamiUitOpen 2:cf42e62a97dc 103 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
MikamiUitOpen 2:cf42e62a97dc 104 * @{
MikamiUitOpen 2:cf42e62a97dc 105 */
MikamiUitOpen 2:cf42e62a97dc 106
MikamiUitOpen 2:cf42e62a97dc 107 /** Write a byte out in master mode and receive a value
MikamiUitOpen 2:cf42e62a97dc 108 *
MikamiUitOpen 2:cf42e62a97dc 109 * @param[in] obj The SPI peripheral to use for sending
MikamiUitOpen 2:cf42e62a97dc 110 * @param[in] value The value to send
MikamiUitOpen 2:cf42e62a97dc 111 * @return Returns the value received during send
MikamiUitOpen 2:cf42e62a97dc 112 */
MikamiUitOpen 2:cf42e62a97dc 113 int spi_master_write(spi_t *obj, int value);
MikamiUitOpen 2:cf42e62a97dc 114
MikamiUitOpen 2:cf42e62a97dc 115 /** Check if a value is available to read
MikamiUitOpen 2:cf42e62a97dc 116 *
MikamiUitOpen 2:cf42e62a97dc 117 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 2:cf42e62a97dc 118 * @return non-zero if a value is available
MikamiUitOpen 2:cf42e62a97dc 119 */
MikamiUitOpen 2:cf42e62a97dc 120 int spi_slave_receive(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 121
MikamiUitOpen 2:cf42e62a97dc 122 /** Get a received value out of the SPI receive buffer in slave mode
MikamiUitOpen 2:cf42e62a97dc 123 *
MikamiUitOpen 2:cf42e62a97dc 124 * Blocks until a value is available
MikamiUitOpen 2:cf42e62a97dc 125 * @param[in] obj The SPI peripheral to read
MikamiUitOpen 2:cf42e62a97dc 126 * @return The value received
MikamiUitOpen 2:cf42e62a97dc 127 */
MikamiUitOpen 2:cf42e62a97dc 128 int spi_slave_read(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 129
MikamiUitOpen 2:cf42e62a97dc 130 /** Write a value to the SPI peripheral in slave mode
MikamiUitOpen 2:cf42e62a97dc 131 *
MikamiUitOpen 2:cf42e62a97dc 132 * Blocks until the SPI peripheral can be written to
MikamiUitOpen 2:cf42e62a97dc 133 * @param[in] obj The SPI peripheral to write
MikamiUitOpen 2:cf42e62a97dc 134 * @param[in] value The value to write
MikamiUitOpen 2:cf42e62a97dc 135 */
MikamiUitOpen 2:cf42e62a97dc 136 void spi_slave_write(spi_t *obj, int value);
MikamiUitOpen 2:cf42e62a97dc 137
MikamiUitOpen 2:cf42e62a97dc 138 /** Checks if the specified SPI peripheral is in use
MikamiUitOpen 2:cf42e62a97dc 139 *
MikamiUitOpen 2:cf42e62a97dc 140 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 2:cf42e62a97dc 141 * @return non-zero if the peripheral is currently transmitting
MikamiUitOpen 2:cf42e62a97dc 142 */
MikamiUitOpen 2:cf42e62a97dc 143 int spi_busy(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 144
MikamiUitOpen 2:cf42e62a97dc 145 /** Get the module number
MikamiUitOpen 2:cf42e62a97dc 146 *
MikamiUitOpen 2:cf42e62a97dc 147 * @param[in] obj The SPI peripheral to check
MikamiUitOpen 2:cf42e62a97dc 148 * @return The module number
MikamiUitOpen 2:cf42e62a97dc 149 */
MikamiUitOpen 2:cf42e62a97dc 150 uint8_t spi_get_module(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 151
MikamiUitOpen 2:cf42e62a97dc 152 /**@}*/
MikamiUitOpen 2:cf42e62a97dc 153
MikamiUitOpen 2:cf42e62a97dc 154 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 155 /**
MikamiUitOpen 2:cf42e62a97dc 156 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
MikamiUitOpen 2:cf42e62a97dc 157 * @{
MikamiUitOpen 2:cf42e62a97dc 158 */
MikamiUitOpen 2:cf42e62a97dc 159
MikamiUitOpen 2:cf42e62a97dc 160 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
MikamiUitOpen 2:cf42e62a97dc 161 *
MikamiUitOpen 2:cf42e62a97dc 162 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 2:cf42e62a97dc 163 * @param[in] tx The buffer to send
MikamiUitOpen 2:cf42e62a97dc 164 * @param[in] tx_length The number of words to transmit
MikamiUitOpen 2:cf42e62a97dc 165 * @param[in] rx The buffer to receive
MikamiUitOpen 2:cf42e62a97dc 166 * @param[in] rx_length The number of words to receive
MikamiUitOpen 2:cf42e62a97dc 167 * @param[in] bit_width The bit width of buffer words
MikamiUitOpen 2:cf42e62a97dc 168 * @param[in] event The logical OR of events to be registered
MikamiUitOpen 2:cf42e62a97dc 169 * @param[in] handler SPI interrupt handler
MikamiUitOpen 2:cf42e62a97dc 170 * @param[in] hint A suggestion for how to use DMA with this transfer
MikamiUitOpen 2:cf42e62a97dc 171 */
MikamiUitOpen 2:cf42e62a97dc 172 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
MikamiUitOpen 2:cf42e62a97dc 173
MikamiUitOpen 2:cf42e62a97dc 174 /** The asynchronous IRQ handler
MikamiUitOpen 2:cf42e62a97dc 175 *
MikamiUitOpen 2:cf42e62a97dc 176 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
MikamiUitOpen 2:cf42e62a97dc 177 * conditions, such as buffer overflows or transfer complete.
MikamiUitOpen 2:cf42e62a97dc 178 * @param[in] obj The SPI object which holds the transfer information
MikamiUitOpen 2:cf42e62a97dc 179 * @return event flags if a transfer termination condition was met or 0 otherwise.
MikamiUitOpen 2:cf42e62a97dc 180 */
MikamiUitOpen 2:cf42e62a97dc 181 uint32_t spi_irq_handler_asynch(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 182
MikamiUitOpen 2:cf42e62a97dc 183 /** Attempts to determine if the SPI peripheral is already in use.
MikamiUitOpen 2:cf42e62a97dc 184 *
MikamiUitOpen 2:cf42e62a97dc 185 * If a temporary DMA channel has been allocated, peripheral is in use.
MikamiUitOpen 2:cf42e62a97dc 186 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
MikamiUitOpen 2:cf42e62a97dc 187 * channel were allocated.
MikamiUitOpen 2:cf42e62a97dc 188 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
MikamiUitOpen 2:cf42e62a97dc 189 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
MikamiUitOpen 2:cf42e62a97dc 190 * there are any bytes in the FIFOs.
MikamiUitOpen 2:cf42e62a97dc 191 * @param[in] obj The SPI object to check for activity
MikamiUitOpen 2:cf42e62a97dc 192 * @return non-zero if the SPI port is active or zero if it is not.
MikamiUitOpen 2:cf42e62a97dc 193 */
MikamiUitOpen 2:cf42e62a97dc 194 uint8_t spi_active(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 195
MikamiUitOpen 2:cf42e62a97dc 196 /** Abort an SPI transfer
MikamiUitOpen 2:cf42e62a97dc 197 *
MikamiUitOpen 2:cf42e62a97dc 198 * @param obj The SPI peripheral to stop
MikamiUitOpen 2:cf42e62a97dc 199 */
MikamiUitOpen 2:cf42e62a97dc 200 void spi_abort_asynch(spi_t *obj);
MikamiUitOpen 2:cf42e62a97dc 201
MikamiUitOpen 2:cf42e62a97dc 202
MikamiUitOpen 2:cf42e62a97dc 203 #endif
MikamiUitOpen 2:cf42e62a97dc 204
MikamiUitOpen 2:cf42e62a97dc 205 /**@}*/
MikamiUitOpen 2:cf42e62a97dc 206
MikamiUitOpen 2:cf42e62a97dc 207 #ifdef __cplusplus
MikamiUitOpen 2:cf42e62a97dc 208 }
MikamiUitOpen 2:cf42e62a97dc 209 #endif // __cplusplus
MikamiUitOpen 2:cf42e62a97dc 210
MikamiUitOpen 2:cf42e62a97dc 211 #endif // SPI_DEVICE
MikamiUitOpen 2:cf42e62a97dc 212
MikamiUitOpen 2:cf42e62a97dc 213 #endif // MBED_SPI_API_H