不韋 呂 / F746_SD_GraphicEqualizer

Output the audio signal with filtering by graphic equalizer in the *.wav file on the SD card using onboard CODEC. SD カードの *.wav ファイルのオーディオ信号をグラフィック･イコライザを通して，ボードに搭載されているCODEC で出力する．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton FrequencyResponseDrawer

mbed_src_STM32F7/common/SPI.cpp@16:cbb726ac20d8, 2016-10-02 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Oct 02 06:33:59 2016 +0000
Revision:
16:cbb726ac20d8
17

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 16:cbb726ac20d8 1 /* mbed Microcontroller Library
MikamiUitOpen 16:cbb726ac20d8 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 16:cbb726ac20d8 3 *
MikamiUitOpen 16:cbb726ac20d8 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 16:cbb726ac20d8 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 16:cbb726ac20d8 6 * You may obtain a copy of the License at
MikamiUitOpen 16:cbb726ac20d8 7 *
MikamiUitOpen 16:cbb726ac20d8 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 16:cbb726ac20d8 9 *
MikamiUitOpen 16:cbb726ac20d8 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 16:cbb726ac20d8 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 16:cbb726ac20d8 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 16:cbb726ac20d8 13 * See the License for the specific language governing permissions and
MikamiUitOpen 16:cbb726ac20d8 14 * limitations under the License.
MikamiUitOpen 16:cbb726ac20d8 15 */
MikamiUitOpen 16:cbb726ac20d8 16 #include "SPI.h"
MikamiUitOpen 16:cbb726ac20d8 17
MikamiUitOpen 16:cbb726ac20d8 18 #if DEVICE_SPI
MikamiUitOpen 16:cbb726ac20d8 19
MikamiUitOpen 16:cbb726ac20d8 20 namespace mbed {
MikamiUitOpen 16:cbb726ac20d8 21
MikamiUitOpen 16:cbb726ac20d8 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
MikamiUitOpen 16:cbb726ac20d8 24 #endif
MikamiUitOpen 16:cbb726ac20d8 25
MikamiUitOpen 16:cbb726ac20d8 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
MikamiUitOpen 16:cbb726ac20d8 27 _spi(),
MikamiUitOpen 16:cbb726ac20d8 28 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 16:cbb726ac20d8 29 _irq(this),
MikamiUitOpen 16:cbb726ac20d8 30 _usage(DMA_USAGE_NEVER),
MikamiUitOpen 16:cbb726ac20d8 31 #endif
MikamiUitOpen 16:cbb726ac20d8 32 _bits(8),
MikamiUitOpen 16:cbb726ac20d8 33 _mode(0),
MikamiUitOpen 16:cbb726ac20d8 34 _hz(1000000) {
MikamiUitOpen 16:cbb726ac20d8 35 spi_init(&_spi, mosi, miso, sclk, ssel);
MikamiUitOpen 16:cbb726ac20d8 36 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 16:cbb726ac20d8 37 spi_frequency(&_spi, _hz);
MikamiUitOpen 16:cbb726ac20d8 38 }
MikamiUitOpen 16:cbb726ac20d8 39
MikamiUitOpen 16:cbb726ac20d8 40 void SPI::format(int bits, int mode) {
MikamiUitOpen 16:cbb726ac20d8 41 _bits = bits;
MikamiUitOpen 16:cbb726ac20d8 42 _mode = mode;
MikamiUitOpen 16:cbb726ac20d8 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 16:cbb726ac20d8 44 aquire();
MikamiUitOpen 16:cbb726ac20d8 45 }
MikamiUitOpen 16:cbb726ac20d8 46
MikamiUitOpen 16:cbb726ac20d8 47 void SPI::frequency(int hz) {
MikamiUitOpen 16:cbb726ac20d8 48 _hz = hz;
MikamiUitOpen 16:cbb726ac20d8 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 16:cbb726ac20d8 50 aquire();
MikamiUitOpen 16:cbb726ac20d8 51 }
MikamiUitOpen 16:cbb726ac20d8 52
MikamiUitOpen 16:cbb726ac20d8 53 SPI* SPI::_owner = NULL;
MikamiUitOpen 16:cbb726ac20d8 54
MikamiUitOpen 16:cbb726ac20d8 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
MikamiUitOpen 16:cbb726ac20d8 56 void SPI::aquire() {
MikamiUitOpen 16:cbb726ac20d8 57 if (_owner != this) {
MikamiUitOpen 16:cbb726ac20d8 58 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 16:cbb726ac20d8 59 spi_frequency(&_spi, _hz);
MikamiUitOpen 16:cbb726ac20d8 60 _owner = this;
MikamiUitOpen 16:cbb726ac20d8 61 }
MikamiUitOpen 16:cbb726ac20d8 62 }
MikamiUitOpen 16:cbb726ac20d8 63
MikamiUitOpen 16:cbb726ac20d8 64 int SPI::write(int value) {
MikamiUitOpen 16:cbb726ac20d8 65 aquire();
MikamiUitOpen 16:cbb726ac20d8 66 return spi_master_write(&_spi, value);
MikamiUitOpen 16:cbb726ac20d8 67 }
MikamiUitOpen 16:cbb726ac20d8 68
MikamiUitOpen 16:cbb726ac20d8 69 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 16:cbb726ac20d8 70
MikamiUitOpen 16:cbb726ac20d8 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 16:cbb726ac20d8 72 {
MikamiUitOpen 16:cbb726ac20d8 73 if (spi_active(&_spi)) {
MikamiUitOpen 16:cbb726ac20d8 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 16:cbb726ac20d8 75 }
MikamiUitOpen 16:cbb726ac20d8 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 16:cbb726ac20d8 77 return 0;
MikamiUitOpen 16:cbb726ac20d8 78 }
MikamiUitOpen 16:cbb726ac20d8 79
MikamiUitOpen 16:cbb726ac20d8 80 void SPI::abort_transfer()
MikamiUitOpen 16:cbb726ac20d8 81 {
MikamiUitOpen 16:cbb726ac20d8 82 spi_abort_asynch(&_spi);
MikamiUitOpen 16:cbb726ac20d8 83 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 84 dequeue_transaction();
MikamiUitOpen 16:cbb726ac20d8 85 #endif
MikamiUitOpen 16:cbb726ac20d8 86 }
MikamiUitOpen 16:cbb726ac20d8 87
MikamiUitOpen 16:cbb726ac20d8 88
MikamiUitOpen 16:cbb726ac20d8 89 void SPI::clear_transfer_buffer()
MikamiUitOpen 16:cbb726ac20d8 90 {
MikamiUitOpen 16:cbb726ac20d8 91 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 92 _transaction_buffer.reset();
MikamiUitOpen 16:cbb726ac20d8 93 #endif
MikamiUitOpen 16:cbb726ac20d8 94 }
MikamiUitOpen 16:cbb726ac20d8 95
MikamiUitOpen 16:cbb726ac20d8 96 void SPI::abort_all_transfers()
MikamiUitOpen 16:cbb726ac20d8 97 {
MikamiUitOpen 16:cbb726ac20d8 98 clear_transfer_buffer();
MikamiUitOpen 16:cbb726ac20d8 99 abort_transfer();
MikamiUitOpen 16:cbb726ac20d8 100 }
MikamiUitOpen 16:cbb726ac20d8 101
MikamiUitOpen 16:cbb726ac20d8 102 int SPI::set_dma_usage(DMAUsage usage)
MikamiUitOpen 16:cbb726ac20d8 103 {
MikamiUitOpen 16:cbb726ac20d8 104 if (spi_active(&_spi)) {
MikamiUitOpen 16:cbb726ac20d8 105 return -1;
MikamiUitOpen 16:cbb726ac20d8 106 }
MikamiUitOpen 16:cbb726ac20d8 107 _usage = usage;
MikamiUitOpen 16:cbb726ac20d8 108 return 0;
MikamiUitOpen 16:cbb726ac20d8 109 }
MikamiUitOpen 16:cbb726ac20d8 110
MikamiUitOpen 16:cbb726ac20d8 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 16:cbb726ac20d8 112 {
MikamiUitOpen 16:cbb726ac20d8 113 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 114 transaction_t t;
MikamiUitOpen 16:cbb726ac20d8 115
MikamiUitOpen 16:cbb726ac20d8 116 t.tx_buffer = const_cast<void *>(tx_buffer);
MikamiUitOpen 16:cbb726ac20d8 117 t.tx_length = tx_length;
MikamiUitOpen 16:cbb726ac20d8 118 t.rx_buffer = rx_buffer;
MikamiUitOpen 16:cbb726ac20d8 119 t.rx_length = rx_length;
MikamiUitOpen 16:cbb726ac20d8 120 t.event = event;
MikamiUitOpen 16:cbb726ac20d8 121 t.callback = callback;
MikamiUitOpen 16:cbb726ac20d8 122 t.width = bit_width;
MikamiUitOpen 16:cbb726ac20d8 123 Transaction<SPI> transaction(this, t);
MikamiUitOpen 16:cbb726ac20d8 124 if (_transaction_buffer.full()) {
MikamiUitOpen 16:cbb726ac20d8 125 return -1; // the buffer is full
MikamiUitOpen 16:cbb726ac20d8 126 } else {
MikamiUitOpen 16:cbb726ac20d8 127 __disable_irq();
MikamiUitOpen 16:cbb726ac20d8 128 _transaction_buffer.push(transaction);
MikamiUitOpen 16:cbb726ac20d8 129 if (!spi_active(&_spi)) {
MikamiUitOpen 16:cbb726ac20d8 130 dequeue_transaction();
MikamiUitOpen 16:cbb726ac20d8 131 }
MikamiUitOpen 16:cbb726ac20d8 132 __enable_irq();
MikamiUitOpen 16:cbb726ac20d8 133 return 0;
MikamiUitOpen 16:cbb726ac20d8 134 }
MikamiUitOpen 16:cbb726ac20d8 135 #else
MikamiUitOpen 16:cbb726ac20d8 136 return -1;
MikamiUitOpen 16:cbb726ac20d8 137 #endif
MikamiUitOpen 16:cbb726ac20d8 138 }
MikamiUitOpen 16:cbb726ac20d8 139
MikamiUitOpen 16:cbb726ac20d8 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 16:cbb726ac20d8 141 {
MikamiUitOpen 16:cbb726ac20d8 142 aquire();
MikamiUitOpen 16:cbb726ac20d8 143 _callback = callback;
MikamiUitOpen 16:cbb726ac20d8 144 _irq.callback(&SPI::irq_handler_asynch);
MikamiUitOpen 16:cbb726ac20d8 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
MikamiUitOpen 16:cbb726ac20d8 146 }
MikamiUitOpen 16:cbb726ac20d8 147
MikamiUitOpen 16:cbb726ac20d8 148 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 149
MikamiUitOpen 16:cbb726ac20d8 150 void SPI::start_transaction(transaction_t *data)
MikamiUitOpen 16:cbb726ac20d8 151 {
MikamiUitOpen 16:cbb726ac20d8 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
MikamiUitOpen 16:cbb726ac20d8 153 }
MikamiUitOpen 16:cbb726ac20d8 154
MikamiUitOpen 16:cbb726ac20d8 155 void SPI::dequeue_transaction()
MikamiUitOpen 16:cbb726ac20d8 156 {
MikamiUitOpen 16:cbb726ac20d8 157 Transaction<SPI> t;
MikamiUitOpen 16:cbb726ac20d8 158 if (_transaction_buffer.pop(t)) {
MikamiUitOpen 16:cbb726ac20d8 159 SPI* obj = t.get_object();
MikamiUitOpen 16:cbb726ac20d8 160 transaction_t* data = t.get_transaction();
MikamiUitOpen 16:cbb726ac20d8 161 obj->start_transaction(data);
MikamiUitOpen 16:cbb726ac20d8 162 }
MikamiUitOpen 16:cbb726ac20d8 163 }
MikamiUitOpen 16:cbb726ac20d8 164
MikamiUitOpen 16:cbb726ac20d8 165 #endif
MikamiUitOpen 16:cbb726ac20d8 166
MikamiUitOpen 16:cbb726ac20d8 167 void SPI::irq_handler_asynch(void)
MikamiUitOpen 16:cbb726ac20d8 168 {
MikamiUitOpen 16:cbb726ac20d8 169 int event = spi_irq_handler_asynch(&_spi);
MikamiUitOpen 16:cbb726ac20d8 170 if (_callback && (event & SPI_EVENT_ALL)) {
MikamiUitOpen 16:cbb726ac20d8 171 _callback.call(event & SPI_EVENT_ALL);
MikamiUitOpen 16:cbb726ac20d8 172 }
MikamiUitOpen 16:cbb726ac20d8 173 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 16:cbb726ac20d8 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
MikamiUitOpen 16:cbb726ac20d8 175 // SPI peripheral is free (event happend), dequeue transaction
MikamiUitOpen 16:cbb726ac20d8 176 dequeue_transaction();
MikamiUitOpen 16:cbb726ac20d8 177 }
MikamiUitOpen 16:cbb726ac20d8 178 #endif
MikamiUitOpen 16:cbb726ac20d8 179 }
MikamiUitOpen 16:cbb726ac20d8 180
MikamiUitOpen 16:cbb726ac20d8 181 #endif
MikamiUitOpen 16:cbb726ac20d8 182
MikamiUitOpen 16:cbb726ac20d8 183 } // namespace mbed
MikamiUitOpen 16:cbb726ac20d8 184
MikamiUitOpen 16:cbb726ac20d8 185 #endif