不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cm4_simd.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cm4_simd.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M4 SIMD Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V3.20
MikamiUitOpen 6:38f7dce055d0 5 * @date 25. February 2013
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 39 extern "C" {
MikamiUitOpen 6:38f7dce055d0 40 #endif
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 #ifndef __CORE_CM4_SIMD_H
MikamiUitOpen 6:38f7dce055d0 43 #define __CORE_CM4_SIMD_H
MikamiUitOpen 6:38f7dce055d0 44
MikamiUitOpen 6:38f7dce055d0 45
MikamiUitOpen 6:38f7dce055d0 46 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 47 * Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 48 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 49
MikamiUitOpen 6:38f7dce055d0 50
MikamiUitOpen 6:38f7dce055d0 51 /* ################### Compiler specific Intrinsics ########################### */
MikamiUitOpen 6:38f7dce055d0 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
MikamiUitOpen 6:38f7dce055d0 53 Access to dedicated SIMD instructions
MikamiUitOpen 6:38f7dce055d0 54 @{
MikamiUitOpen 6:38f7dce055d0 55 */
MikamiUitOpen 6:38f7dce055d0 56
MikamiUitOpen 6:38f7dce055d0 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 6:38f7dce055d0 58 /* ARM armcc specific functions */
MikamiUitOpen 6:38f7dce055d0 59
MikamiUitOpen 6:38f7dce055d0 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 61 #define __SADD8 __sadd8
MikamiUitOpen 6:38f7dce055d0 62 #define __QADD8 __qadd8
MikamiUitOpen 6:38f7dce055d0 63 #define __SHADD8 __shadd8
MikamiUitOpen 6:38f7dce055d0 64 #define __UADD8 __uadd8
MikamiUitOpen 6:38f7dce055d0 65 #define __UQADD8 __uqadd8
MikamiUitOpen 6:38f7dce055d0 66 #define __UHADD8 __uhadd8
MikamiUitOpen 6:38f7dce055d0 67 #define __SSUB8 __ssub8
MikamiUitOpen 6:38f7dce055d0 68 #define __QSUB8 __qsub8
MikamiUitOpen 6:38f7dce055d0 69 #define __SHSUB8 __shsub8
MikamiUitOpen 6:38f7dce055d0 70 #define __USUB8 __usub8
MikamiUitOpen 6:38f7dce055d0 71 #define __UQSUB8 __uqsub8
MikamiUitOpen 6:38f7dce055d0 72 #define __UHSUB8 __uhsub8
MikamiUitOpen 6:38f7dce055d0 73 #define __SADD16 __sadd16
MikamiUitOpen 6:38f7dce055d0 74 #define __QADD16 __qadd16
MikamiUitOpen 6:38f7dce055d0 75 #define __SHADD16 __shadd16
MikamiUitOpen 6:38f7dce055d0 76 #define __UADD16 __uadd16
MikamiUitOpen 6:38f7dce055d0 77 #define __UQADD16 __uqadd16
MikamiUitOpen 6:38f7dce055d0 78 #define __UHADD16 __uhadd16
MikamiUitOpen 6:38f7dce055d0 79 #define __SSUB16 __ssub16
MikamiUitOpen 6:38f7dce055d0 80 #define __QSUB16 __qsub16
MikamiUitOpen 6:38f7dce055d0 81 #define __SHSUB16 __shsub16
MikamiUitOpen 6:38f7dce055d0 82 #define __USUB16 __usub16
MikamiUitOpen 6:38f7dce055d0 83 #define __UQSUB16 __uqsub16
MikamiUitOpen 6:38f7dce055d0 84 #define __UHSUB16 __uhsub16
MikamiUitOpen 6:38f7dce055d0 85 #define __SASX __sasx
MikamiUitOpen 6:38f7dce055d0 86 #define __QASX __qasx
MikamiUitOpen 6:38f7dce055d0 87 #define __SHASX __shasx
MikamiUitOpen 6:38f7dce055d0 88 #define __UASX __uasx
MikamiUitOpen 6:38f7dce055d0 89 #define __UQASX __uqasx
MikamiUitOpen 6:38f7dce055d0 90 #define __UHASX __uhasx
MikamiUitOpen 6:38f7dce055d0 91 #define __SSAX __ssax
MikamiUitOpen 6:38f7dce055d0 92 #define __QSAX __qsax
MikamiUitOpen 6:38f7dce055d0 93 #define __SHSAX __shsax
MikamiUitOpen 6:38f7dce055d0 94 #define __USAX __usax
MikamiUitOpen 6:38f7dce055d0 95 #define __UQSAX __uqsax
MikamiUitOpen 6:38f7dce055d0 96 #define __UHSAX __uhsax
MikamiUitOpen 6:38f7dce055d0 97 #define __USAD8 __usad8
MikamiUitOpen 6:38f7dce055d0 98 #define __USADA8 __usada8
MikamiUitOpen 6:38f7dce055d0 99 #define __SSAT16 __ssat16
MikamiUitOpen 6:38f7dce055d0 100 #define __USAT16 __usat16
MikamiUitOpen 6:38f7dce055d0 101 #define __UXTB16 __uxtb16
MikamiUitOpen 6:38f7dce055d0 102 #define __UXTAB16 __uxtab16
MikamiUitOpen 6:38f7dce055d0 103 #define __SXTB16 __sxtb16
MikamiUitOpen 6:38f7dce055d0 104 #define __SXTAB16 __sxtab16
MikamiUitOpen 6:38f7dce055d0 105 #define __SMUAD __smuad
MikamiUitOpen 6:38f7dce055d0 106 #define __SMUADX __smuadx
MikamiUitOpen 6:38f7dce055d0 107 #define __SMLAD __smlad
MikamiUitOpen 6:38f7dce055d0 108 #define __SMLADX __smladx
MikamiUitOpen 6:38f7dce055d0 109 #define __SMLALD __smlald
MikamiUitOpen 6:38f7dce055d0 110 #define __SMLALDX __smlaldx
MikamiUitOpen 6:38f7dce055d0 111 #define __SMUSD __smusd
MikamiUitOpen 6:38f7dce055d0 112 #define __SMUSDX __smusdx
MikamiUitOpen 6:38f7dce055d0 113 #define __SMLSD __smlsd
MikamiUitOpen 6:38f7dce055d0 114 #define __SMLSDX __smlsdx
MikamiUitOpen 6:38f7dce055d0 115 #define __SMLSLD __smlsld
MikamiUitOpen 6:38f7dce055d0 116 #define __SMLSLDX __smlsldx
MikamiUitOpen 6:38f7dce055d0 117 #define __SEL __sel
MikamiUitOpen 6:38f7dce055d0 118 #define __QADD __qadd
MikamiUitOpen 6:38f7dce055d0 119 #define __QSUB __qsub
MikamiUitOpen 6:38f7dce055d0 120
MikamiUitOpen 6:38f7dce055d0 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
MikamiUitOpen 6:38f7dce055d0 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
MikamiUitOpen 6:38f7dce055d0 123
MikamiUitOpen 6:38f7dce055d0 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
MikamiUitOpen 6:38f7dce055d0 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
MikamiUitOpen 6:38f7dce055d0 126
MikamiUitOpen 6:38f7dce055d0 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
MikamiUitOpen 6:38f7dce055d0 128 ((int64_t)(ARG3) << 32) ) >> 32))
MikamiUitOpen 6:38f7dce055d0 129
MikamiUitOpen 6:38f7dce055d0 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 131
MikamiUitOpen 6:38f7dce055d0 132
MikamiUitOpen 6:38f7dce055d0 133
MikamiUitOpen 6:38f7dce055d0 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 6:38f7dce055d0 135 /* IAR iccarm specific functions */
MikamiUitOpen 6:38f7dce055d0 136
MikamiUitOpen 6:38f7dce055d0 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 138 #include <cmsis_iar.h>
MikamiUitOpen 6:38f7dce055d0 139
MikamiUitOpen 6:38f7dce055d0 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 141
MikamiUitOpen 6:38f7dce055d0 142
MikamiUitOpen 6:38f7dce055d0 143
MikamiUitOpen 6:38f7dce055d0 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 6:38f7dce055d0 145 /* TI CCS specific functions */
MikamiUitOpen 6:38f7dce055d0 146
MikamiUitOpen 6:38f7dce055d0 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 148 #include <cmsis_ccs.h>
MikamiUitOpen 6:38f7dce055d0 149
MikamiUitOpen 6:38f7dce055d0 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 151
MikamiUitOpen 6:38f7dce055d0 152
MikamiUitOpen 6:38f7dce055d0 153
MikamiUitOpen 6:38f7dce055d0 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 6:38f7dce055d0 155 /* GNU gcc specific functions */
MikamiUitOpen 6:38f7dce055d0 156
MikamiUitOpen 6:38f7dce055d0 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 159 {
MikamiUitOpen 6:38f7dce055d0 160 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 161
MikamiUitOpen 6:38f7dce055d0 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 163 return(result);
MikamiUitOpen 6:38f7dce055d0 164 }
MikamiUitOpen 6:38f7dce055d0 165
MikamiUitOpen 6:38f7dce055d0 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 167 {
MikamiUitOpen 6:38f7dce055d0 168 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 169
MikamiUitOpen 6:38f7dce055d0 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 171 return(result);
MikamiUitOpen 6:38f7dce055d0 172 }
MikamiUitOpen 6:38f7dce055d0 173
MikamiUitOpen 6:38f7dce055d0 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 175 {
MikamiUitOpen 6:38f7dce055d0 176 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 177
MikamiUitOpen 6:38f7dce055d0 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 179 return(result);
MikamiUitOpen 6:38f7dce055d0 180 }
MikamiUitOpen 6:38f7dce055d0 181
MikamiUitOpen 6:38f7dce055d0 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 183 {
MikamiUitOpen 6:38f7dce055d0 184 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 185
MikamiUitOpen 6:38f7dce055d0 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 187 return(result);
MikamiUitOpen 6:38f7dce055d0 188 }
MikamiUitOpen 6:38f7dce055d0 189
MikamiUitOpen 6:38f7dce055d0 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 191 {
MikamiUitOpen 6:38f7dce055d0 192 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 193
MikamiUitOpen 6:38f7dce055d0 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 195 return(result);
MikamiUitOpen 6:38f7dce055d0 196 }
MikamiUitOpen 6:38f7dce055d0 197
MikamiUitOpen 6:38f7dce055d0 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 199 {
MikamiUitOpen 6:38f7dce055d0 200 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 201
MikamiUitOpen 6:38f7dce055d0 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 203 return(result);
MikamiUitOpen 6:38f7dce055d0 204 }
MikamiUitOpen 6:38f7dce055d0 205
MikamiUitOpen 6:38f7dce055d0 206
MikamiUitOpen 6:38f7dce055d0 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 208 {
MikamiUitOpen 6:38f7dce055d0 209 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 210
MikamiUitOpen 6:38f7dce055d0 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 212 return(result);
MikamiUitOpen 6:38f7dce055d0 213 }
MikamiUitOpen 6:38f7dce055d0 214
MikamiUitOpen 6:38f7dce055d0 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 216 {
MikamiUitOpen 6:38f7dce055d0 217 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 218
MikamiUitOpen 6:38f7dce055d0 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 220 return(result);
MikamiUitOpen 6:38f7dce055d0 221 }
MikamiUitOpen 6:38f7dce055d0 222
MikamiUitOpen 6:38f7dce055d0 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 224 {
MikamiUitOpen 6:38f7dce055d0 225 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 226
MikamiUitOpen 6:38f7dce055d0 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 228 return(result);
MikamiUitOpen 6:38f7dce055d0 229 }
MikamiUitOpen 6:38f7dce055d0 230
MikamiUitOpen 6:38f7dce055d0 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 232 {
MikamiUitOpen 6:38f7dce055d0 233 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 234
MikamiUitOpen 6:38f7dce055d0 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 236 return(result);
MikamiUitOpen 6:38f7dce055d0 237 }
MikamiUitOpen 6:38f7dce055d0 238
MikamiUitOpen 6:38f7dce055d0 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 240 {
MikamiUitOpen 6:38f7dce055d0 241 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 242
MikamiUitOpen 6:38f7dce055d0 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 244 return(result);
MikamiUitOpen 6:38f7dce055d0 245 }
MikamiUitOpen 6:38f7dce055d0 246
MikamiUitOpen 6:38f7dce055d0 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 248 {
MikamiUitOpen 6:38f7dce055d0 249 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 250
MikamiUitOpen 6:38f7dce055d0 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 252 return(result);
MikamiUitOpen 6:38f7dce055d0 253 }
MikamiUitOpen 6:38f7dce055d0 254
MikamiUitOpen 6:38f7dce055d0 255
MikamiUitOpen 6:38f7dce055d0 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 257 {
MikamiUitOpen 6:38f7dce055d0 258 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 259
MikamiUitOpen 6:38f7dce055d0 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 261 return(result);
MikamiUitOpen 6:38f7dce055d0 262 }
MikamiUitOpen 6:38f7dce055d0 263
MikamiUitOpen 6:38f7dce055d0 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 265 {
MikamiUitOpen 6:38f7dce055d0 266 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 267
MikamiUitOpen 6:38f7dce055d0 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 269 return(result);
MikamiUitOpen 6:38f7dce055d0 270 }
MikamiUitOpen 6:38f7dce055d0 271
MikamiUitOpen 6:38f7dce055d0 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 273 {
MikamiUitOpen 6:38f7dce055d0 274 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 275
MikamiUitOpen 6:38f7dce055d0 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 277 return(result);
MikamiUitOpen 6:38f7dce055d0 278 }
MikamiUitOpen 6:38f7dce055d0 279
MikamiUitOpen 6:38f7dce055d0 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 281 {
MikamiUitOpen 6:38f7dce055d0 282 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 283
MikamiUitOpen 6:38f7dce055d0 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 285 return(result);
MikamiUitOpen 6:38f7dce055d0 286 }
MikamiUitOpen 6:38f7dce055d0 287
MikamiUitOpen 6:38f7dce055d0 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 289 {
MikamiUitOpen 6:38f7dce055d0 290 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 291
MikamiUitOpen 6:38f7dce055d0 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 293 return(result);
MikamiUitOpen 6:38f7dce055d0 294 }
MikamiUitOpen 6:38f7dce055d0 295
MikamiUitOpen 6:38f7dce055d0 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 297 {
MikamiUitOpen 6:38f7dce055d0 298 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 299
MikamiUitOpen 6:38f7dce055d0 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 301 return(result);
MikamiUitOpen 6:38f7dce055d0 302 }
MikamiUitOpen 6:38f7dce055d0 303
MikamiUitOpen 6:38f7dce055d0 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 305 {
MikamiUitOpen 6:38f7dce055d0 306 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 307
MikamiUitOpen 6:38f7dce055d0 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 309 return(result);
MikamiUitOpen 6:38f7dce055d0 310 }
MikamiUitOpen 6:38f7dce055d0 311
MikamiUitOpen 6:38f7dce055d0 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 313 {
MikamiUitOpen 6:38f7dce055d0 314 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 315
MikamiUitOpen 6:38f7dce055d0 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 317 return(result);
MikamiUitOpen 6:38f7dce055d0 318 }
MikamiUitOpen 6:38f7dce055d0 319
MikamiUitOpen 6:38f7dce055d0 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 321 {
MikamiUitOpen 6:38f7dce055d0 322 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 323
MikamiUitOpen 6:38f7dce055d0 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 325 return(result);
MikamiUitOpen 6:38f7dce055d0 326 }
MikamiUitOpen 6:38f7dce055d0 327
MikamiUitOpen 6:38f7dce055d0 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 329 {
MikamiUitOpen 6:38f7dce055d0 330 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 331
MikamiUitOpen 6:38f7dce055d0 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 333 return(result);
MikamiUitOpen 6:38f7dce055d0 334 }
MikamiUitOpen 6:38f7dce055d0 335
MikamiUitOpen 6:38f7dce055d0 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 337 {
MikamiUitOpen 6:38f7dce055d0 338 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 339
MikamiUitOpen 6:38f7dce055d0 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 341 return(result);
MikamiUitOpen 6:38f7dce055d0 342 }
MikamiUitOpen 6:38f7dce055d0 343
MikamiUitOpen 6:38f7dce055d0 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 345 {
MikamiUitOpen 6:38f7dce055d0 346 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 347
MikamiUitOpen 6:38f7dce055d0 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 349 return(result);
MikamiUitOpen 6:38f7dce055d0 350 }
MikamiUitOpen 6:38f7dce055d0 351
MikamiUitOpen 6:38f7dce055d0 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 353 {
MikamiUitOpen 6:38f7dce055d0 354 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 355
MikamiUitOpen 6:38f7dce055d0 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 357 return(result);
MikamiUitOpen 6:38f7dce055d0 358 }
MikamiUitOpen 6:38f7dce055d0 359
MikamiUitOpen 6:38f7dce055d0 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 361 {
MikamiUitOpen 6:38f7dce055d0 362 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 363
MikamiUitOpen 6:38f7dce055d0 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 365 return(result);
MikamiUitOpen 6:38f7dce055d0 366 }
MikamiUitOpen 6:38f7dce055d0 367
MikamiUitOpen 6:38f7dce055d0 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 369 {
MikamiUitOpen 6:38f7dce055d0 370 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 371
MikamiUitOpen 6:38f7dce055d0 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 373 return(result);
MikamiUitOpen 6:38f7dce055d0 374 }
MikamiUitOpen 6:38f7dce055d0 375
MikamiUitOpen 6:38f7dce055d0 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 377 {
MikamiUitOpen 6:38f7dce055d0 378 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 379
MikamiUitOpen 6:38f7dce055d0 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 381 return(result);
MikamiUitOpen 6:38f7dce055d0 382 }
MikamiUitOpen 6:38f7dce055d0 383
MikamiUitOpen 6:38f7dce055d0 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 385 {
MikamiUitOpen 6:38f7dce055d0 386 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 387
MikamiUitOpen 6:38f7dce055d0 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 389 return(result);
MikamiUitOpen 6:38f7dce055d0 390 }
MikamiUitOpen 6:38f7dce055d0 391
MikamiUitOpen 6:38f7dce055d0 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 393 {
MikamiUitOpen 6:38f7dce055d0 394 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 395
MikamiUitOpen 6:38f7dce055d0 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 397 return(result);
MikamiUitOpen 6:38f7dce055d0 398 }
MikamiUitOpen 6:38f7dce055d0 399
MikamiUitOpen 6:38f7dce055d0 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 401 {
MikamiUitOpen 6:38f7dce055d0 402 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 403
MikamiUitOpen 6:38f7dce055d0 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 405 return(result);
MikamiUitOpen 6:38f7dce055d0 406 }
MikamiUitOpen 6:38f7dce055d0 407
MikamiUitOpen 6:38f7dce055d0 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 409 {
MikamiUitOpen 6:38f7dce055d0 410 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 411
MikamiUitOpen 6:38f7dce055d0 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 413 return(result);
MikamiUitOpen 6:38f7dce055d0 414 }
MikamiUitOpen 6:38f7dce055d0 415
MikamiUitOpen 6:38f7dce055d0 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 417 {
MikamiUitOpen 6:38f7dce055d0 418 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 419
MikamiUitOpen 6:38f7dce055d0 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 421 return(result);
MikamiUitOpen 6:38f7dce055d0 422 }
MikamiUitOpen 6:38f7dce055d0 423
MikamiUitOpen 6:38f7dce055d0 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 425 {
MikamiUitOpen 6:38f7dce055d0 426 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 427
MikamiUitOpen 6:38f7dce055d0 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 429 return(result);
MikamiUitOpen 6:38f7dce055d0 430 }
MikamiUitOpen 6:38f7dce055d0 431
MikamiUitOpen 6:38f7dce055d0 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 433 {
MikamiUitOpen 6:38f7dce055d0 434 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 435
MikamiUitOpen 6:38f7dce055d0 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 437 return(result);
MikamiUitOpen 6:38f7dce055d0 438 }
MikamiUitOpen 6:38f7dce055d0 439
MikamiUitOpen 6:38f7dce055d0 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 441 {
MikamiUitOpen 6:38f7dce055d0 442 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 443
MikamiUitOpen 6:38f7dce055d0 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 445 return(result);
MikamiUitOpen 6:38f7dce055d0 446 }
MikamiUitOpen 6:38f7dce055d0 447
MikamiUitOpen 6:38f7dce055d0 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 449 {
MikamiUitOpen 6:38f7dce055d0 450 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 451
MikamiUitOpen 6:38f7dce055d0 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 453 return(result);
MikamiUitOpen 6:38f7dce055d0 454 }
MikamiUitOpen 6:38f7dce055d0 455
MikamiUitOpen 6:38f7dce055d0 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 457 {
MikamiUitOpen 6:38f7dce055d0 458 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 459
MikamiUitOpen 6:38f7dce055d0 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 461 return(result);
MikamiUitOpen 6:38f7dce055d0 462 }
MikamiUitOpen 6:38f7dce055d0 463
MikamiUitOpen 6:38f7dce055d0 464 #define __SSAT16(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 465 ({ \
MikamiUitOpen 6:38f7dce055d0 466 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 468 __RES; \
MikamiUitOpen 6:38f7dce055d0 469 })
MikamiUitOpen 6:38f7dce055d0 470
MikamiUitOpen 6:38f7dce055d0 471 #define __USAT16(ARG1,ARG2) \
MikamiUitOpen 6:38f7dce055d0 472 ({ \
MikamiUitOpen 6:38f7dce055d0 473 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 6:38f7dce055d0 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 6:38f7dce055d0 475 __RES; \
MikamiUitOpen 6:38f7dce055d0 476 })
MikamiUitOpen 6:38f7dce055d0 477
MikamiUitOpen 6:38f7dce055d0 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
MikamiUitOpen 6:38f7dce055d0 479 {
MikamiUitOpen 6:38f7dce055d0 480 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 481
MikamiUitOpen 6:38f7dce055d0 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 6:38f7dce055d0 483 return(result);
MikamiUitOpen 6:38f7dce055d0 484 }
MikamiUitOpen 6:38f7dce055d0 485
MikamiUitOpen 6:38f7dce055d0 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 487 {
MikamiUitOpen 6:38f7dce055d0 488 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 489
MikamiUitOpen 6:38f7dce055d0 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 491 return(result);
MikamiUitOpen 6:38f7dce055d0 492 }
MikamiUitOpen 6:38f7dce055d0 493
MikamiUitOpen 6:38f7dce055d0 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
MikamiUitOpen 6:38f7dce055d0 495 {
MikamiUitOpen 6:38f7dce055d0 496 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 497
MikamiUitOpen 6:38f7dce055d0 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
MikamiUitOpen 6:38f7dce055d0 499 return(result);
MikamiUitOpen 6:38f7dce055d0 500 }
MikamiUitOpen 6:38f7dce055d0 501
MikamiUitOpen 6:38f7dce055d0 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 503 {
MikamiUitOpen 6:38f7dce055d0 504 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 505
MikamiUitOpen 6:38f7dce055d0 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 507 return(result);
MikamiUitOpen 6:38f7dce055d0 508 }
MikamiUitOpen 6:38f7dce055d0 509
MikamiUitOpen 6:38f7dce055d0 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 511 {
MikamiUitOpen 6:38f7dce055d0 512 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 513
MikamiUitOpen 6:38f7dce055d0 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 515 return(result);
MikamiUitOpen 6:38f7dce055d0 516 }
MikamiUitOpen 6:38f7dce055d0 517
MikamiUitOpen 6:38f7dce055d0 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 519 {
MikamiUitOpen 6:38f7dce055d0 520 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 521
MikamiUitOpen 6:38f7dce055d0 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 523 return(result);
MikamiUitOpen 6:38f7dce055d0 524 }
MikamiUitOpen 6:38f7dce055d0 525
MikamiUitOpen 6:38f7dce055d0 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 527 {
MikamiUitOpen 6:38f7dce055d0 528 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 529
MikamiUitOpen 6:38f7dce055d0 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 531 return(result);
MikamiUitOpen 6:38f7dce055d0 532 }
MikamiUitOpen 6:38f7dce055d0 533
MikamiUitOpen 6:38f7dce055d0 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 535 {
MikamiUitOpen 6:38f7dce055d0 536 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 537
MikamiUitOpen 6:38f7dce055d0 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 539 return(result);
MikamiUitOpen 6:38f7dce055d0 540 }
MikamiUitOpen 6:38f7dce055d0 541
MikamiUitOpen 6:38f7dce055d0 542 #define __SMLALD(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 543 ({ \
MikamiUitOpen 6:38f7dce055d0 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 6:38f7dce055d0 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 6:38f7dce055d0 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 6:38f7dce055d0 547 })
MikamiUitOpen 6:38f7dce055d0 548
MikamiUitOpen 6:38f7dce055d0 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 550 ({ \
MikamiUitOpen 6:38f7dce055d0 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 6:38f7dce055d0 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 6:38f7dce055d0 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 6:38f7dce055d0 554 })
MikamiUitOpen 6:38f7dce055d0 555
MikamiUitOpen 6:38f7dce055d0 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 557 {
MikamiUitOpen 6:38f7dce055d0 558 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 559
MikamiUitOpen 6:38f7dce055d0 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 561 return(result);
MikamiUitOpen 6:38f7dce055d0 562 }
MikamiUitOpen 6:38f7dce055d0 563
MikamiUitOpen 6:38f7dce055d0 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 565 {
MikamiUitOpen 6:38f7dce055d0 566 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 567
MikamiUitOpen 6:38f7dce055d0 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 569 return(result);
MikamiUitOpen 6:38f7dce055d0 570 }
MikamiUitOpen 6:38f7dce055d0 571
MikamiUitOpen 6:38f7dce055d0 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 573 {
MikamiUitOpen 6:38f7dce055d0 574 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 575
MikamiUitOpen 6:38f7dce055d0 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 577 return(result);
MikamiUitOpen 6:38f7dce055d0 578 }
MikamiUitOpen 6:38f7dce055d0 579
MikamiUitOpen 6:38f7dce055d0 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
MikamiUitOpen 6:38f7dce055d0 581 {
MikamiUitOpen 6:38f7dce055d0 582 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 583
MikamiUitOpen 6:38f7dce055d0 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 585 return(result);
MikamiUitOpen 6:38f7dce055d0 586 }
MikamiUitOpen 6:38f7dce055d0 587
MikamiUitOpen 6:38f7dce055d0 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 589 ({ \
MikamiUitOpen 6:38f7dce055d0 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 6:38f7dce055d0 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 6:38f7dce055d0 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 6:38f7dce055d0 593 })
MikamiUitOpen 6:38f7dce055d0 594
MikamiUitOpen 6:38f7dce055d0 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 596 ({ \
MikamiUitOpen 6:38f7dce055d0 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
MikamiUitOpen 6:38f7dce055d0 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
MikamiUitOpen 6:38f7dce055d0 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
MikamiUitOpen 6:38f7dce055d0 600 })
MikamiUitOpen 6:38f7dce055d0 601
MikamiUitOpen 6:38f7dce055d0 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 603 {
MikamiUitOpen 6:38f7dce055d0 604 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 605
MikamiUitOpen 6:38f7dce055d0 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 607 return(result);
MikamiUitOpen 6:38f7dce055d0 608 }
MikamiUitOpen 6:38f7dce055d0 609
MikamiUitOpen 6:38f7dce055d0 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 611 {
MikamiUitOpen 6:38f7dce055d0 612 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 613
MikamiUitOpen 6:38f7dce055d0 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 615 return(result);
MikamiUitOpen 6:38f7dce055d0 616 }
MikamiUitOpen 6:38f7dce055d0 617
MikamiUitOpen 6:38f7dce055d0 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
MikamiUitOpen 6:38f7dce055d0 619 {
MikamiUitOpen 6:38f7dce055d0 620 uint32_t result;
MikamiUitOpen 6:38f7dce055d0 621
MikamiUitOpen 6:38f7dce055d0 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
MikamiUitOpen 6:38f7dce055d0 623 return(result);
MikamiUitOpen 6:38f7dce055d0 624 }
MikamiUitOpen 6:38f7dce055d0 625
MikamiUitOpen 6:38f7dce055d0 626 #define __PKHBT(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 627 ({ \
MikamiUitOpen 6:38f7dce055d0 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 6:38f7dce055d0 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 6:38f7dce055d0 630 __RES; \
MikamiUitOpen 6:38f7dce055d0 631 })
MikamiUitOpen 6:38f7dce055d0 632
MikamiUitOpen 6:38f7dce055d0 633 #define __PKHTB(ARG1,ARG2,ARG3) \
MikamiUitOpen 6:38f7dce055d0 634 ({ \
MikamiUitOpen 6:38f7dce055d0 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
MikamiUitOpen 6:38f7dce055d0 636 if (ARG3 == 0) \
MikamiUitOpen 6:38f7dce055d0 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
MikamiUitOpen 6:38f7dce055d0 638 else \
MikamiUitOpen 6:38f7dce055d0 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
MikamiUitOpen 6:38f7dce055d0 640 __RES; \
MikamiUitOpen 6:38f7dce055d0 641 })
MikamiUitOpen 6:38f7dce055d0 642
MikamiUitOpen 6:38f7dce055d0 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
MikamiUitOpen 6:38f7dce055d0 644 {
MikamiUitOpen 6:38f7dce055d0 645 int32_t result;
MikamiUitOpen 6:38f7dce055d0 646
MikamiUitOpen 6:38f7dce055d0 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
MikamiUitOpen 6:38f7dce055d0 648 return(result);
MikamiUitOpen 6:38f7dce055d0 649 }
MikamiUitOpen 6:38f7dce055d0 650
MikamiUitOpen 6:38f7dce055d0 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 652
MikamiUitOpen 6:38f7dce055d0 653
MikamiUitOpen 6:38f7dce055d0 654
MikamiUitOpen 6:38f7dce055d0 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 6:38f7dce055d0 656 /* TASKING carm specific functions */
MikamiUitOpen 6:38f7dce055d0 657
MikamiUitOpen 6:38f7dce055d0 658
MikamiUitOpen 6:38f7dce055d0 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 660 /* not yet supported */
MikamiUitOpen 6:38f7dce055d0 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 662
MikamiUitOpen 6:38f7dce055d0 663
MikamiUitOpen 6:38f7dce055d0 664 #endif
MikamiUitOpen 6:38f7dce055d0 665
MikamiUitOpen 6:38f7dce055d0 666 /*@} end of group CMSIS_SIMD_intrinsics */
MikamiUitOpen 6:38f7dce055d0 667
MikamiUitOpen 6:38f7dce055d0 668
MikamiUitOpen 6:38f7dce055d0 669 #endif /* __CORE_CM4_SIMD_H */
MikamiUitOpen 6:38f7dce055d0 670
MikamiUitOpen 6:38f7dce055d0 671 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 672 }
MikamiUitOpen 6:38f7dce055d0 673 #endif