不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cm3.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cm3.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V4.10
MikamiUitOpen 6:38f7dce055d0 5 * @date 18. March 2015
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #if defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 6:38f7dce055d0 40 #endif
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 #ifndef __CORE_CM3_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 43 #define __CORE_CM3_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 44
MikamiUitOpen 6:38f7dce055d0 45 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 46 extern "C" {
MikamiUitOpen 6:38f7dce055d0 47 #endif
MikamiUitOpen 6:38f7dce055d0 48
MikamiUitOpen 6:38f7dce055d0 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 6:38f7dce055d0 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 6:38f7dce055d0 51
MikamiUitOpen 6:38f7dce055d0 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 6:38f7dce055d0 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 6:38f7dce055d0 56 Unions are used for effective representation of core registers.
MikamiUitOpen 6:38f7dce055d0 57
MikamiUitOpen 6:38f7dce055d0 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 6:38f7dce055d0 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 6:38f7dce055d0 60 */
MikamiUitOpen 6:38f7dce055d0 61
MikamiUitOpen 6:38f7dce055d0 62
MikamiUitOpen 6:38f7dce055d0 63 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 64 * CMSIS definitions
MikamiUitOpen 6:38f7dce055d0 65 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 66 /** \ingroup Cortex_M3
MikamiUitOpen 6:38f7dce055d0 67 @{
MikamiUitOpen 6:38f7dce055d0 68 */
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70 /* CMSIS CM3 definitions */
MikamiUitOpen 6:38f7dce055d0 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 6:38f7dce055d0 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 6:38f7dce055d0 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 6:38f7dce055d0 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 6:38f7dce055d0 75
MikamiUitOpen 6:38f7dce055d0 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
MikamiUitOpen 6:38f7dce055d0 77
MikamiUitOpen 6:38f7dce055d0 78
MikamiUitOpen 6:38f7dce055d0 79 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 6:38f7dce055d0 83
MikamiUitOpen 6:38f7dce055d0 84 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 87 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 88
MikamiUitOpen 6:38f7dce055d0 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 6:38f7dce055d0 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 6:38f7dce055d0 92 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 93
MikamiUitOpen 6:38f7dce055d0 94 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 6:38f7dce055d0 96 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 97
MikamiUitOpen 6:38f7dce055d0 98 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 101 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 102
MikamiUitOpen 6:38f7dce055d0 103 #elif defined ( __CSMC__ )
MikamiUitOpen 6:38f7dce055d0 104 #define __packed
MikamiUitOpen 6:38f7dce055d0 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 6:38f7dce055d0 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 6:38f7dce055d0 107 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 108
MikamiUitOpen 6:38f7dce055d0 109 #endif
MikamiUitOpen 6:38f7dce055d0 110
MikamiUitOpen 6:38f7dce055d0 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 6:38f7dce055d0 112 This core does not support an FPU at all
MikamiUitOpen 6:38f7dce055d0 113 */
MikamiUitOpen 6:38f7dce055d0 114 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 115
MikamiUitOpen 6:38f7dce055d0 116 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 6:38f7dce055d0 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 119 #endif
MikamiUitOpen 6:38f7dce055d0 120
MikamiUitOpen 6:38f7dce055d0 121 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 6:38f7dce055d0 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 124 #endif
MikamiUitOpen 6:38f7dce055d0 125
MikamiUitOpen 6:38f7dce055d0 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 127 #if defined __ARMVFP__
MikamiUitOpen 6:38f7dce055d0 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 129 #endif
MikamiUitOpen 6:38f7dce055d0 130
MikamiUitOpen 6:38f7dce055d0 131 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 6:38f7dce055d0 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 134 #endif
MikamiUitOpen 6:38f7dce055d0 135
MikamiUitOpen 6:38f7dce055d0 136 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 137 #if defined __FPU_VFP__
MikamiUitOpen 6:38f7dce055d0 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 139 #endif
MikamiUitOpen 6:38f7dce055d0 140
MikamiUitOpen 6:38f7dce055d0 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 6:38f7dce055d0 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 6:38f7dce055d0 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 144 #endif
MikamiUitOpen 6:38f7dce055d0 145 #endif
MikamiUitOpen 6:38f7dce055d0 146
MikamiUitOpen 6:38f7dce055d0 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 6:38f7dce055d0 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 6:38f7dce055d0 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 6:38f7dce055d0 150
MikamiUitOpen 6:38f7dce055d0 151 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 152 }
MikamiUitOpen 6:38f7dce055d0 153 #endif
MikamiUitOpen 6:38f7dce055d0 154
MikamiUitOpen 6:38f7dce055d0 155 #endif /* __CORE_CM3_H_GENERIC */
MikamiUitOpen 6:38f7dce055d0 156
MikamiUitOpen 6:38f7dce055d0 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 6:38f7dce055d0 158
MikamiUitOpen 6:38f7dce055d0 159 #ifndef __CORE_CM3_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 160 #define __CORE_CM3_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 161
MikamiUitOpen 6:38f7dce055d0 162 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 163 extern "C" {
MikamiUitOpen 6:38f7dce055d0 164 #endif
MikamiUitOpen 6:38f7dce055d0 165
MikamiUitOpen 6:38f7dce055d0 166 /* check device defines and use defaults */
MikamiUitOpen 6:38f7dce055d0 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 6:38f7dce055d0 168 #ifndef __CM3_REV
MikamiUitOpen 6:38f7dce055d0 169 #define __CM3_REV 0x0200
MikamiUitOpen 6:38f7dce055d0 170 #warning "__CM3_REV not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 171 #endif
MikamiUitOpen 6:38f7dce055d0 172
MikamiUitOpen 6:38f7dce055d0 173 #ifndef __MPU_PRESENT
MikamiUitOpen 6:38f7dce055d0 174 #define __MPU_PRESENT 0
MikamiUitOpen 6:38f7dce055d0 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 176 #endif
MikamiUitOpen 6:38f7dce055d0 177
MikamiUitOpen 6:38f7dce055d0 178 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 6:38f7dce055d0 179 #define __NVIC_PRIO_BITS 4
MikamiUitOpen 6:38f7dce055d0 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 181 #endif
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 6:38f7dce055d0 184 #define __Vendor_SysTickConfig 0
MikamiUitOpen 6:38f7dce055d0 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 186 #endif
MikamiUitOpen 6:38f7dce055d0 187 #endif
MikamiUitOpen 6:38f7dce055d0 188
MikamiUitOpen 6:38f7dce055d0 189 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 6:38f7dce055d0 190 /**
MikamiUitOpen 6:38f7dce055d0 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 6:38f7dce055d0 192
MikamiUitOpen 6:38f7dce055d0 193 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 6:38f7dce055d0 194 \li to specify the access to peripheral variables.
MikamiUitOpen 6:38f7dce055d0 195 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 6:38f7dce055d0 196 */
MikamiUitOpen 6:38f7dce055d0 197 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 198 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 199 #else
MikamiUitOpen 6:38f7dce055d0 200 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 201 #endif
MikamiUitOpen 6:38f7dce055d0 202 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 6:38f7dce055d0 203 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 6:38f7dce055d0 204
MikamiUitOpen 6:38f7dce055d0 205 /*@} end of group Cortex_M3 */
MikamiUitOpen 6:38f7dce055d0 206
MikamiUitOpen 6:38f7dce055d0 207
MikamiUitOpen 6:38f7dce055d0 208
MikamiUitOpen 6:38f7dce055d0 209 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 210 * Register Abstraction
MikamiUitOpen 6:38f7dce055d0 211 Core Register contain:
MikamiUitOpen 6:38f7dce055d0 212 - Core Register
MikamiUitOpen 6:38f7dce055d0 213 - Core NVIC Register
MikamiUitOpen 6:38f7dce055d0 214 - Core SCB Register
MikamiUitOpen 6:38f7dce055d0 215 - Core SysTick Register
MikamiUitOpen 6:38f7dce055d0 216 - Core Debug Register
MikamiUitOpen 6:38f7dce055d0 217 - Core MPU Register
MikamiUitOpen 6:38f7dce055d0 218 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 6:38f7dce055d0 220 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 6:38f7dce055d0 221 */
MikamiUitOpen 6:38f7dce055d0 222
MikamiUitOpen 6:38f7dce055d0 223 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 224 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 6:38f7dce055d0 225 \brief Core Register type definitions.
MikamiUitOpen 6:38f7dce055d0 226 @{
MikamiUitOpen 6:38f7dce055d0 227 */
MikamiUitOpen 6:38f7dce055d0 228
MikamiUitOpen 6:38f7dce055d0 229 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 6:38f7dce055d0 230 */
MikamiUitOpen 6:38f7dce055d0 231 typedef union
MikamiUitOpen 6:38f7dce055d0 232 {
MikamiUitOpen 6:38f7dce055d0 233 struct
MikamiUitOpen 6:38f7dce055d0 234 {
MikamiUitOpen 6:38f7dce055d0 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
MikamiUitOpen 6:38f7dce055d0 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 6:38f7dce055d0 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 6:38f7dce055d0 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 6:38f7dce055d0 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 6:38f7dce055d0 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 6:38f7dce055d0 241 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 242 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 243 } APSR_Type;
MikamiUitOpen 6:38f7dce055d0 244
MikamiUitOpen 6:38f7dce055d0 245 /* APSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 6:38f7dce055d0 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 6:38f7dce055d0 248
MikamiUitOpen 6:38f7dce055d0 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 6:38f7dce055d0 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 6:38f7dce055d0 251
MikamiUitOpen 6:38f7dce055d0 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 6:38f7dce055d0 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 6:38f7dce055d0 254
MikamiUitOpen 6:38f7dce055d0 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 6:38f7dce055d0 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 6:38f7dce055d0 257
MikamiUitOpen 6:38f7dce055d0 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
MikamiUitOpen 6:38f7dce055d0 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
MikamiUitOpen 6:38f7dce055d0 260
MikamiUitOpen 6:38f7dce055d0 261
MikamiUitOpen 6:38f7dce055d0 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 6:38f7dce055d0 263 */
MikamiUitOpen 6:38f7dce055d0 264 typedef union
MikamiUitOpen 6:38f7dce055d0 265 {
MikamiUitOpen 6:38f7dce055d0 266 struct
MikamiUitOpen 6:38f7dce055d0 267 {
MikamiUitOpen 6:38f7dce055d0 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 6:38f7dce055d0 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 6:38f7dce055d0 270 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 271 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 272 } IPSR_Type;
MikamiUitOpen 6:38f7dce055d0 273
MikamiUitOpen 6:38f7dce055d0 274 /* IPSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 6:38f7dce055d0 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 6:38f7dce055d0 277
MikamiUitOpen 6:38f7dce055d0 278
MikamiUitOpen 6:38f7dce055d0 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 6:38f7dce055d0 280 */
MikamiUitOpen 6:38f7dce055d0 281 typedef union
MikamiUitOpen 6:38f7dce055d0 282 {
MikamiUitOpen 6:38f7dce055d0 283 struct
MikamiUitOpen 6:38f7dce055d0 284 {
MikamiUitOpen 6:38f7dce055d0 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 6:38f7dce055d0 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 6:38f7dce055d0 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 6:38f7dce055d0 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
MikamiUitOpen 6:38f7dce055d0 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 6:38f7dce055d0 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 6:38f7dce055d0 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 6:38f7dce055d0 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 6:38f7dce055d0 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 6:38f7dce055d0 294 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 295 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 296 } xPSR_Type;
MikamiUitOpen 6:38f7dce055d0 297
MikamiUitOpen 6:38f7dce055d0 298 /* xPSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 6:38f7dce055d0 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 6:38f7dce055d0 301
MikamiUitOpen 6:38f7dce055d0 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 6:38f7dce055d0 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 6:38f7dce055d0 304
MikamiUitOpen 6:38f7dce055d0 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 6:38f7dce055d0 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 6:38f7dce055d0 307
MikamiUitOpen 6:38f7dce055d0 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 6:38f7dce055d0 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 6:38f7dce055d0 310
MikamiUitOpen 6:38f7dce055d0 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
MikamiUitOpen 6:38f7dce055d0 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
MikamiUitOpen 6:38f7dce055d0 313
MikamiUitOpen 6:38f7dce055d0 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
MikamiUitOpen 6:38f7dce055d0 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
MikamiUitOpen 6:38f7dce055d0 316
MikamiUitOpen 6:38f7dce055d0 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 6:38f7dce055d0 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 6:38f7dce055d0 319
MikamiUitOpen 6:38f7dce055d0 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 6:38f7dce055d0 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 6:38f7dce055d0 322
MikamiUitOpen 6:38f7dce055d0 323
MikamiUitOpen 6:38f7dce055d0 324 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 6:38f7dce055d0 325 */
MikamiUitOpen 6:38f7dce055d0 326 typedef union
MikamiUitOpen 6:38f7dce055d0 327 {
MikamiUitOpen 6:38f7dce055d0 328 struct
MikamiUitOpen 6:38f7dce055d0 329 {
MikamiUitOpen 6:38f7dce055d0 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
MikamiUitOpen 6:38f7dce055d0 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 6:38f7dce055d0 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 6:38f7dce055d0 333 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 334 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 335 } CONTROL_Type;
MikamiUitOpen 6:38f7dce055d0 336
MikamiUitOpen 6:38f7dce055d0 337 /* CONTROL Register Definitions */
MikamiUitOpen 6:38f7dce055d0 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 6:38f7dce055d0 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 6:38f7dce055d0 340
MikamiUitOpen 6:38f7dce055d0 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
MikamiUitOpen 6:38f7dce055d0 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
MikamiUitOpen 6:38f7dce055d0 343
MikamiUitOpen 6:38f7dce055d0 344 /*@} end of group CMSIS_CORE */
MikamiUitOpen 6:38f7dce055d0 345
MikamiUitOpen 6:38f7dce055d0 346
MikamiUitOpen 6:38f7dce055d0 347 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 6:38f7dce055d0 349 \brief Type definitions for the NVIC Registers
MikamiUitOpen 6:38f7dce055d0 350 @{
MikamiUitOpen 6:38f7dce055d0 351 */
MikamiUitOpen 6:38f7dce055d0 352
MikamiUitOpen 6:38f7dce055d0 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 6:38f7dce055d0 354 */
MikamiUitOpen 6:38f7dce055d0 355 typedef struct
MikamiUitOpen 6:38f7dce055d0 356 {
MikamiUitOpen 6:38f7dce055d0 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 6:38f7dce055d0 358 uint32_t RESERVED0[24];
MikamiUitOpen 6:38f7dce055d0 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 6:38f7dce055d0 360 uint32_t RSERVED1[24];
MikamiUitOpen 6:38f7dce055d0 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 6:38f7dce055d0 362 uint32_t RESERVED2[24];
MikamiUitOpen 6:38f7dce055d0 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 6:38f7dce055d0 364 uint32_t RESERVED3[24];
MikamiUitOpen 6:38f7dce055d0 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
MikamiUitOpen 6:38f7dce055d0 366 uint32_t RESERVED4[56];
MikamiUitOpen 6:38f7dce055d0 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
MikamiUitOpen 6:38f7dce055d0 368 uint32_t RESERVED5[644];
MikamiUitOpen 6:38f7dce055d0 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
MikamiUitOpen 6:38f7dce055d0 370 } NVIC_Type;
MikamiUitOpen 6:38f7dce055d0 371
MikamiUitOpen 6:38f7dce055d0 372 /* Software Triggered Interrupt Register Definitions */
MikamiUitOpen 6:38f7dce055d0 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
MikamiUitOpen 6:38f7dce055d0 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
MikamiUitOpen 6:38f7dce055d0 375
MikamiUitOpen 6:38f7dce055d0 376 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 6:38f7dce055d0 377
MikamiUitOpen 6:38f7dce055d0 378
MikamiUitOpen 6:38f7dce055d0 379 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 380 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 6:38f7dce055d0 381 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 6:38f7dce055d0 382 @{
MikamiUitOpen 6:38f7dce055d0 383 */
MikamiUitOpen 6:38f7dce055d0 384
MikamiUitOpen 6:38f7dce055d0 385 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 6:38f7dce055d0 386 */
MikamiUitOpen 6:38f7dce055d0 387 typedef struct
MikamiUitOpen 6:38f7dce055d0 388 {
MikamiUitOpen 6:38f7dce055d0 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 6:38f7dce055d0 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 6:38f7dce055d0 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
MikamiUitOpen 6:38f7dce055d0 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 6:38f7dce055d0 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 6:38f7dce055d0 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 6:38f7dce055d0 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
MikamiUitOpen 6:38f7dce055d0 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 6:38f7dce055d0 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
MikamiUitOpen 6:38f7dce055d0 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
MikamiUitOpen 6:38f7dce055d0 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
MikamiUitOpen 6:38f7dce055d0 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
MikamiUitOpen 6:38f7dce055d0 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
MikamiUitOpen 6:38f7dce055d0 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
MikamiUitOpen 6:38f7dce055d0 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
MikamiUitOpen 6:38f7dce055d0 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
MikamiUitOpen 6:38f7dce055d0 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
MikamiUitOpen 6:38f7dce055d0 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
MikamiUitOpen 6:38f7dce055d0 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
MikamiUitOpen 6:38f7dce055d0 408 uint32_t RESERVED0[5];
MikamiUitOpen 6:38f7dce055d0 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
MikamiUitOpen 6:38f7dce055d0 410 } SCB_Type;
MikamiUitOpen 6:38f7dce055d0 411
MikamiUitOpen 6:38f7dce055d0 412 /* SCB CPUID Register Definitions */
MikamiUitOpen 6:38f7dce055d0 413 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 6:38f7dce055d0 414 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 6:38f7dce055d0 415
MikamiUitOpen 6:38f7dce055d0 416 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 6:38f7dce055d0 417 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 6:38f7dce055d0 418
MikamiUitOpen 6:38f7dce055d0 419 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 6:38f7dce055d0 420 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 6:38f7dce055d0 421
MikamiUitOpen 6:38f7dce055d0 422 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 6:38f7dce055d0 423 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 6:38f7dce055d0 424
MikamiUitOpen 6:38f7dce055d0 425 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 6:38f7dce055d0 426 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 6:38f7dce055d0 427
MikamiUitOpen 6:38f7dce055d0 428 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 6:38f7dce055d0 429 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 6:38f7dce055d0 430 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 6:38f7dce055d0 431
MikamiUitOpen 6:38f7dce055d0 432 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 6:38f7dce055d0 433 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 6:38f7dce055d0 434
MikamiUitOpen 6:38f7dce055d0 435 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 6:38f7dce055d0 436 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 6:38f7dce055d0 437
MikamiUitOpen 6:38f7dce055d0 438 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 6:38f7dce055d0 439 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 6:38f7dce055d0 440
MikamiUitOpen 6:38f7dce055d0 441 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 6:38f7dce055d0 442 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 6:38f7dce055d0 443
MikamiUitOpen 6:38f7dce055d0 444 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 6:38f7dce055d0 445 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 6:38f7dce055d0 446
MikamiUitOpen 6:38f7dce055d0 447 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 6:38f7dce055d0 448 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 6:38f7dce055d0 449
MikamiUitOpen 6:38f7dce055d0 450 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 6:38f7dce055d0 451 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 6:38f7dce055d0 452
MikamiUitOpen 6:38f7dce055d0 453 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
MikamiUitOpen 6:38f7dce055d0 454 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
MikamiUitOpen 6:38f7dce055d0 455
MikamiUitOpen 6:38f7dce055d0 456 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 6:38f7dce055d0 457 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 6:38f7dce055d0 458
MikamiUitOpen 6:38f7dce055d0 459 /* SCB Vector Table Offset Register Definitions */
MikamiUitOpen 6:38f7dce055d0 460 #if (__CM3_REV < 0x0201) /* core r2p1 */
MikamiUitOpen 6:38f7dce055d0 461 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
MikamiUitOpen 6:38f7dce055d0 462 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
MikamiUitOpen 6:38f7dce055d0 463
MikamiUitOpen 6:38f7dce055d0 464 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 6:38f7dce055d0 465 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 6:38f7dce055d0 466 #else
MikamiUitOpen 6:38f7dce055d0 467 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 6:38f7dce055d0 468 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 6:38f7dce055d0 469 #endif
MikamiUitOpen 6:38f7dce055d0 470
MikamiUitOpen 6:38f7dce055d0 471 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 6:38f7dce055d0 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 6:38f7dce055d0 474
MikamiUitOpen 6:38f7dce055d0 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 6:38f7dce055d0 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 6:38f7dce055d0 477
MikamiUitOpen 6:38f7dce055d0 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 6:38f7dce055d0 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 6:38f7dce055d0 480
MikamiUitOpen 6:38f7dce055d0 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
MikamiUitOpen 6:38f7dce055d0 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
MikamiUitOpen 6:38f7dce055d0 483
MikamiUitOpen 6:38f7dce055d0 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 6:38f7dce055d0 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 6:38f7dce055d0 486
MikamiUitOpen 6:38f7dce055d0 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 6:38f7dce055d0 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 6:38f7dce055d0 489
MikamiUitOpen 6:38f7dce055d0 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
MikamiUitOpen 6:38f7dce055d0 491 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
MikamiUitOpen 6:38f7dce055d0 492
MikamiUitOpen 6:38f7dce055d0 493 /* SCB System Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 6:38f7dce055d0 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 6:38f7dce055d0 496
MikamiUitOpen 6:38f7dce055d0 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 6:38f7dce055d0 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 6:38f7dce055d0 499
MikamiUitOpen 6:38f7dce055d0 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 6:38f7dce055d0 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 6:38f7dce055d0 502
MikamiUitOpen 6:38f7dce055d0 503 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 6:38f7dce055d0 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 6:38f7dce055d0 506
MikamiUitOpen 6:38f7dce055d0 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
MikamiUitOpen 6:38f7dce055d0 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
MikamiUitOpen 6:38f7dce055d0 509
MikamiUitOpen 6:38f7dce055d0 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
MikamiUitOpen 6:38f7dce055d0 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
MikamiUitOpen 6:38f7dce055d0 512
MikamiUitOpen 6:38f7dce055d0 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 6:38f7dce055d0 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 6:38f7dce055d0 515
MikamiUitOpen 6:38f7dce055d0 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
MikamiUitOpen 6:38f7dce055d0 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
MikamiUitOpen 6:38f7dce055d0 518
MikamiUitOpen 6:38f7dce055d0 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
MikamiUitOpen 6:38f7dce055d0 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
MikamiUitOpen 6:38f7dce055d0 521
MikamiUitOpen 6:38f7dce055d0 522 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 6:38f7dce055d0 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
MikamiUitOpen 6:38f7dce055d0 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
MikamiUitOpen 6:38f7dce055d0 525
MikamiUitOpen 6:38f7dce055d0 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
MikamiUitOpen 6:38f7dce055d0 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
MikamiUitOpen 6:38f7dce055d0 528
MikamiUitOpen 6:38f7dce055d0 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
MikamiUitOpen 6:38f7dce055d0 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
MikamiUitOpen 6:38f7dce055d0 531
MikamiUitOpen 6:38f7dce055d0 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 6:38f7dce055d0 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 6:38f7dce055d0 534
MikamiUitOpen 6:38f7dce055d0 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
MikamiUitOpen 6:38f7dce055d0 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
MikamiUitOpen 6:38f7dce055d0 537
MikamiUitOpen 6:38f7dce055d0 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
MikamiUitOpen 6:38f7dce055d0 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
MikamiUitOpen 6:38f7dce055d0 540
MikamiUitOpen 6:38f7dce055d0 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
MikamiUitOpen 6:38f7dce055d0 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
MikamiUitOpen 6:38f7dce055d0 543
MikamiUitOpen 6:38f7dce055d0 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
MikamiUitOpen 6:38f7dce055d0 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
MikamiUitOpen 6:38f7dce055d0 546
MikamiUitOpen 6:38f7dce055d0 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
MikamiUitOpen 6:38f7dce055d0 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
MikamiUitOpen 6:38f7dce055d0 549
MikamiUitOpen 6:38f7dce055d0 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
MikamiUitOpen 6:38f7dce055d0 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
MikamiUitOpen 6:38f7dce055d0 552
MikamiUitOpen 6:38f7dce055d0 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
MikamiUitOpen 6:38f7dce055d0 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
MikamiUitOpen 6:38f7dce055d0 555
MikamiUitOpen 6:38f7dce055d0 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
MikamiUitOpen 6:38f7dce055d0 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
MikamiUitOpen 6:38f7dce055d0 558
MikamiUitOpen 6:38f7dce055d0 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
MikamiUitOpen 6:38f7dce055d0 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
MikamiUitOpen 6:38f7dce055d0 561
MikamiUitOpen 6:38f7dce055d0 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
MikamiUitOpen 6:38f7dce055d0 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
MikamiUitOpen 6:38f7dce055d0 564
MikamiUitOpen 6:38f7dce055d0 565 /* SCB Configurable Fault Status Registers Definitions */
MikamiUitOpen 6:38f7dce055d0 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
MikamiUitOpen 6:38f7dce055d0 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
MikamiUitOpen 6:38f7dce055d0 568
MikamiUitOpen 6:38f7dce055d0 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
MikamiUitOpen 6:38f7dce055d0 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
MikamiUitOpen 6:38f7dce055d0 571
MikamiUitOpen 6:38f7dce055d0 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
MikamiUitOpen 6:38f7dce055d0 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
MikamiUitOpen 6:38f7dce055d0 574
MikamiUitOpen 6:38f7dce055d0 575 /* SCB Hard Fault Status Registers Definitions */
MikamiUitOpen 6:38f7dce055d0 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
MikamiUitOpen 6:38f7dce055d0 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
MikamiUitOpen 6:38f7dce055d0 578
MikamiUitOpen 6:38f7dce055d0 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
MikamiUitOpen 6:38f7dce055d0 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
MikamiUitOpen 6:38f7dce055d0 581
MikamiUitOpen 6:38f7dce055d0 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
MikamiUitOpen 6:38f7dce055d0 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
MikamiUitOpen 6:38f7dce055d0 584
MikamiUitOpen 6:38f7dce055d0 585 /* SCB Debug Fault Status Register Definitions */
MikamiUitOpen 6:38f7dce055d0 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
MikamiUitOpen 6:38f7dce055d0 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
MikamiUitOpen 6:38f7dce055d0 588
MikamiUitOpen 6:38f7dce055d0 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
MikamiUitOpen 6:38f7dce055d0 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
MikamiUitOpen 6:38f7dce055d0 591
MikamiUitOpen 6:38f7dce055d0 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
MikamiUitOpen 6:38f7dce055d0 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
MikamiUitOpen 6:38f7dce055d0 594
MikamiUitOpen 6:38f7dce055d0 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
MikamiUitOpen 6:38f7dce055d0 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
MikamiUitOpen 6:38f7dce055d0 597
MikamiUitOpen 6:38f7dce055d0 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
MikamiUitOpen 6:38f7dce055d0 599 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
MikamiUitOpen 6:38f7dce055d0 600
MikamiUitOpen 6:38f7dce055d0 601 /*@} end of group CMSIS_SCB */
MikamiUitOpen 6:38f7dce055d0 602
MikamiUitOpen 6:38f7dce055d0 603
MikamiUitOpen 6:38f7dce055d0 604 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MikamiUitOpen 6:38f7dce055d0 606 \brief Type definitions for the System Control and ID Register not in the SCB
MikamiUitOpen 6:38f7dce055d0 607 @{
MikamiUitOpen 6:38f7dce055d0 608 */
MikamiUitOpen 6:38f7dce055d0 609
MikamiUitOpen 6:38f7dce055d0 610 /** \brief Structure type to access the System Control and ID Register not in the SCB.
MikamiUitOpen 6:38f7dce055d0 611 */
MikamiUitOpen 6:38f7dce055d0 612 typedef struct
MikamiUitOpen 6:38f7dce055d0 613 {
MikamiUitOpen 6:38f7dce055d0 614 uint32_t RESERVED0[1];
MikamiUitOpen 6:38f7dce055d0 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
MikamiUitOpen 6:38f7dce055d0 616 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
MikamiUitOpen 6:38f7dce055d0 617 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
MikamiUitOpen 6:38f7dce055d0 618 #else
MikamiUitOpen 6:38f7dce055d0 619 uint32_t RESERVED1[1];
MikamiUitOpen 6:38f7dce055d0 620 #endif
MikamiUitOpen 6:38f7dce055d0 621 } SCnSCB_Type;
MikamiUitOpen 6:38f7dce055d0 622
MikamiUitOpen 6:38f7dce055d0 623 /* Interrupt Controller Type Register Definitions */
MikamiUitOpen 6:38f7dce055d0 624 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
MikamiUitOpen 6:38f7dce055d0 625 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
MikamiUitOpen 6:38f7dce055d0 626
MikamiUitOpen 6:38f7dce055d0 627 /* Auxiliary Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 628
MikamiUitOpen 6:38f7dce055d0 629 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
MikamiUitOpen 6:38f7dce055d0 630 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
MikamiUitOpen 6:38f7dce055d0 631
MikamiUitOpen 6:38f7dce055d0 632 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
MikamiUitOpen 6:38f7dce055d0 633 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
MikamiUitOpen 6:38f7dce055d0 634
MikamiUitOpen 6:38f7dce055d0 635 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
MikamiUitOpen 6:38f7dce055d0 636 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
MikamiUitOpen 6:38f7dce055d0 637
MikamiUitOpen 6:38f7dce055d0 638 /*@} end of group CMSIS_SCnotSCB */
MikamiUitOpen 6:38f7dce055d0 639
MikamiUitOpen 6:38f7dce055d0 640
MikamiUitOpen 6:38f7dce055d0 641 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 642 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 6:38f7dce055d0 643 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 6:38f7dce055d0 644 @{
MikamiUitOpen 6:38f7dce055d0 645 */
MikamiUitOpen 6:38f7dce055d0 646
MikamiUitOpen 6:38f7dce055d0 647 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 6:38f7dce055d0 648 */
MikamiUitOpen 6:38f7dce055d0 649 typedef struct
MikamiUitOpen 6:38f7dce055d0 650 {
MikamiUitOpen 6:38f7dce055d0 651 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 6:38f7dce055d0 652 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 6:38f7dce055d0 653 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 6:38f7dce055d0 654 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 6:38f7dce055d0 655 } SysTick_Type;
MikamiUitOpen 6:38f7dce055d0 656
MikamiUitOpen 6:38f7dce055d0 657 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 6:38f7dce055d0 658 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 6:38f7dce055d0 659 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 6:38f7dce055d0 660
MikamiUitOpen 6:38f7dce055d0 661 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 6:38f7dce055d0 662 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 6:38f7dce055d0 663
MikamiUitOpen 6:38f7dce055d0 664 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 6:38f7dce055d0 665 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 6:38f7dce055d0 666
MikamiUitOpen 6:38f7dce055d0 667 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 6:38f7dce055d0 668 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 6:38f7dce055d0 669
MikamiUitOpen 6:38f7dce055d0 670 /* SysTick Reload Register Definitions */
MikamiUitOpen 6:38f7dce055d0 671 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 6:38f7dce055d0 672 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 6:38f7dce055d0 673
MikamiUitOpen 6:38f7dce055d0 674 /* SysTick Current Register Definitions */
MikamiUitOpen 6:38f7dce055d0 675 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 6:38f7dce055d0 676 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 6:38f7dce055d0 677
MikamiUitOpen 6:38f7dce055d0 678 /* SysTick Calibration Register Definitions */
MikamiUitOpen 6:38f7dce055d0 679 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 6:38f7dce055d0 680 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 6:38f7dce055d0 681
MikamiUitOpen 6:38f7dce055d0 682 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 6:38f7dce055d0 683 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 6:38f7dce055d0 684
MikamiUitOpen 6:38f7dce055d0 685 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 6:38f7dce055d0 686 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 6:38f7dce055d0 687
MikamiUitOpen 6:38f7dce055d0 688 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 6:38f7dce055d0 689
MikamiUitOpen 6:38f7dce055d0 690
MikamiUitOpen 6:38f7dce055d0 691 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 692 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
MikamiUitOpen 6:38f7dce055d0 693 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
MikamiUitOpen 6:38f7dce055d0 694 @{
MikamiUitOpen 6:38f7dce055d0 695 */
MikamiUitOpen 6:38f7dce055d0 696
MikamiUitOpen 6:38f7dce055d0 697 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
MikamiUitOpen 6:38f7dce055d0 698 */
MikamiUitOpen 6:38f7dce055d0 699 typedef struct
MikamiUitOpen 6:38f7dce055d0 700 {
MikamiUitOpen 6:38f7dce055d0 701 __O union
MikamiUitOpen 6:38f7dce055d0 702 {
MikamiUitOpen 6:38f7dce055d0 703 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
MikamiUitOpen 6:38f7dce055d0 704 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
MikamiUitOpen 6:38f7dce055d0 705 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
MikamiUitOpen 6:38f7dce055d0 706 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
MikamiUitOpen 6:38f7dce055d0 707 uint32_t RESERVED0[864];
MikamiUitOpen 6:38f7dce055d0 708 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
MikamiUitOpen 6:38f7dce055d0 709 uint32_t RESERVED1[15];
MikamiUitOpen 6:38f7dce055d0 710 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
MikamiUitOpen 6:38f7dce055d0 711 uint32_t RESERVED2[15];
MikamiUitOpen 6:38f7dce055d0 712 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
MikamiUitOpen 6:38f7dce055d0 713 uint32_t RESERVED3[29];
MikamiUitOpen 6:38f7dce055d0 714 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
MikamiUitOpen 6:38f7dce055d0 715 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
MikamiUitOpen 6:38f7dce055d0 716 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
MikamiUitOpen 6:38f7dce055d0 717 uint32_t RESERVED4[43];
MikamiUitOpen 6:38f7dce055d0 718 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
MikamiUitOpen 6:38f7dce055d0 719 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
MikamiUitOpen 6:38f7dce055d0 720 uint32_t RESERVED5[6];
MikamiUitOpen 6:38f7dce055d0 721 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
MikamiUitOpen 6:38f7dce055d0 722 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
MikamiUitOpen 6:38f7dce055d0 723 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
MikamiUitOpen 6:38f7dce055d0 724 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
MikamiUitOpen 6:38f7dce055d0 725 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
MikamiUitOpen 6:38f7dce055d0 726 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
MikamiUitOpen 6:38f7dce055d0 727 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
MikamiUitOpen 6:38f7dce055d0 728 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
MikamiUitOpen 6:38f7dce055d0 729 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
MikamiUitOpen 6:38f7dce055d0 730 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
MikamiUitOpen 6:38f7dce055d0 731 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
MikamiUitOpen 6:38f7dce055d0 732 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
MikamiUitOpen 6:38f7dce055d0 733 } ITM_Type;
MikamiUitOpen 6:38f7dce055d0 734
MikamiUitOpen 6:38f7dce055d0 735 /* ITM Trace Privilege Register Definitions */
MikamiUitOpen 6:38f7dce055d0 736 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
MikamiUitOpen 6:38f7dce055d0 737 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
MikamiUitOpen 6:38f7dce055d0 738
MikamiUitOpen 6:38f7dce055d0 739 /* ITM Trace Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 740 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
MikamiUitOpen 6:38f7dce055d0 741 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
MikamiUitOpen 6:38f7dce055d0 742
MikamiUitOpen 6:38f7dce055d0 743 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
MikamiUitOpen 6:38f7dce055d0 744 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
MikamiUitOpen 6:38f7dce055d0 745
MikamiUitOpen 6:38f7dce055d0 746 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
MikamiUitOpen 6:38f7dce055d0 747 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
MikamiUitOpen 6:38f7dce055d0 748
MikamiUitOpen 6:38f7dce055d0 749 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
MikamiUitOpen 6:38f7dce055d0 750 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
MikamiUitOpen 6:38f7dce055d0 751
MikamiUitOpen 6:38f7dce055d0 752 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
MikamiUitOpen 6:38f7dce055d0 753 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
MikamiUitOpen 6:38f7dce055d0 754
MikamiUitOpen 6:38f7dce055d0 755 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
MikamiUitOpen 6:38f7dce055d0 756 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
MikamiUitOpen 6:38f7dce055d0 757
MikamiUitOpen 6:38f7dce055d0 758 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
MikamiUitOpen 6:38f7dce055d0 759 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
MikamiUitOpen 6:38f7dce055d0 760
MikamiUitOpen 6:38f7dce055d0 761 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
MikamiUitOpen 6:38f7dce055d0 762 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
MikamiUitOpen 6:38f7dce055d0 763
MikamiUitOpen 6:38f7dce055d0 764 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
MikamiUitOpen 6:38f7dce055d0 765 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
MikamiUitOpen 6:38f7dce055d0 766
MikamiUitOpen 6:38f7dce055d0 767 /* ITM Integration Write Register Definitions */
MikamiUitOpen 6:38f7dce055d0 768 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
MikamiUitOpen 6:38f7dce055d0 769 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
MikamiUitOpen 6:38f7dce055d0 770
MikamiUitOpen 6:38f7dce055d0 771 /* ITM Integration Read Register Definitions */
MikamiUitOpen 6:38f7dce055d0 772 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
MikamiUitOpen 6:38f7dce055d0 773 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
MikamiUitOpen 6:38f7dce055d0 774
MikamiUitOpen 6:38f7dce055d0 775 /* ITM Integration Mode Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 776 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
MikamiUitOpen 6:38f7dce055d0 777 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
MikamiUitOpen 6:38f7dce055d0 778
MikamiUitOpen 6:38f7dce055d0 779 /* ITM Lock Status Register Definitions */
MikamiUitOpen 6:38f7dce055d0 780 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
MikamiUitOpen 6:38f7dce055d0 781 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
MikamiUitOpen 6:38f7dce055d0 782
MikamiUitOpen 6:38f7dce055d0 783 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
MikamiUitOpen 6:38f7dce055d0 784 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
MikamiUitOpen 6:38f7dce055d0 785
MikamiUitOpen 6:38f7dce055d0 786 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
MikamiUitOpen 6:38f7dce055d0 787 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
MikamiUitOpen 6:38f7dce055d0 788
MikamiUitOpen 6:38f7dce055d0 789 /*@}*/ /* end of group CMSIS_ITM */
MikamiUitOpen 6:38f7dce055d0 790
MikamiUitOpen 6:38f7dce055d0 791
MikamiUitOpen 6:38f7dce055d0 792 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 793 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
MikamiUitOpen 6:38f7dce055d0 794 \brief Type definitions for the Data Watchpoint and Trace (DWT)
MikamiUitOpen 6:38f7dce055d0 795 @{
MikamiUitOpen 6:38f7dce055d0 796 */
MikamiUitOpen 6:38f7dce055d0 797
MikamiUitOpen 6:38f7dce055d0 798 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
MikamiUitOpen 6:38f7dce055d0 799 */
MikamiUitOpen 6:38f7dce055d0 800 typedef struct
MikamiUitOpen 6:38f7dce055d0 801 {
MikamiUitOpen 6:38f7dce055d0 802 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
MikamiUitOpen 6:38f7dce055d0 803 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
MikamiUitOpen 6:38f7dce055d0 804 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
MikamiUitOpen 6:38f7dce055d0 805 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
MikamiUitOpen 6:38f7dce055d0 806 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
MikamiUitOpen 6:38f7dce055d0 807 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
MikamiUitOpen 6:38f7dce055d0 808 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
MikamiUitOpen 6:38f7dce055d0 809 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
MikamiUitOpen 6:38f7dce055d0 810 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
MikamiUitOpen 6:38f7dce055d0 811 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
MikamiUitOpen 6:38f7dce055d0 812 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
MikamiUitOpen 6:38f7dce055d0 813 uint32_t RESERVED0[1];
MikamiUitOpen 6:38f7dce055d0 814 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
MikamiUitOpen 6:38f7dce055d0 815 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
MikamiUitOpen 6:38f7dce055d0 816 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
MikamiUitOpen 6:38f7dce055d0 817 uint32_t RESERVED1[1];
MikamiUitOpen 6:38f7dce055d0 818 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
MikamiUitOpen 6:38f7dce055d0 819 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
MikamiUitOpen 6:38f7dce055d0 820 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
MikamiUitOpen 6:38f7dce055d0 821 uint32_t RESERVED2[1];
MikamiUitOpen 6:38f7dce055d0 822 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
MikamiUitOpen 6:38f7dce055d0 823 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
MikamiUitOpen 6:38f7dce055d0 824 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
MikamiUitOpen 6:38f7dce055d0 825 } DWT_Type;
MikamiUitOpen 6:38f7dce055d0 826
MikamiUitOpen 6:38f7dce055d0 827 /* DWT Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 828 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
MikamiUitOpen 6:38f7dce055d0 829 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
MikamiUitOpen 6:38f7dce055d0 830
MikamiUitOpen 6:38f7dce055d0 831 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
MikamiUitOpen 6:38f7dce055d0 832 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
MikamiUitOpen 6:38f7dce055d0 833
MikamiUitOpen 6:38f7dce055d0 834 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
MikamiUitOpen 6:38f7dce055d0 835 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
MikamiUitOpen 6:38f7dce055d0 836
MikamiUitOpen 6:38f7dce055d0 837 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
MikamiUitOpen 6:38f7dce055d0 838 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
MikamiUitOpen 6:38f7dce055d0 839
MikamiUitOpen 6:38f7dce055d0 840 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
MikamiUitOpen 6:38f7dce055d0 841 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
MikamiUitOpen 6:38f7dce055d0 842
MikamiUitOpen 6:38f7dce055d0 843 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 844 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 845
MikamiUitOpen 6:38f7dce055d0 846 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 847 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 848
MikamiUitOpen 6:38f7dce055d0 849 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 850 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 851
MikamiUitOpen 6:38f7dce055d0 852 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 853 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 854
MikamiUitOpen 6:38f7dce055d0 855 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 856 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 857
MikamiUitOpen 6:38f7dce055d0 858 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
MikamiUitOpen 6:38f7dce055d0 859 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
MikamiUitOpen 6:38f7dce055d0 860
MikamiUitOpen 6:38f7dce055d0 861 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
MikamiUitOpen 6:38f7dce055d0 862 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
MikamiUitOpen 6:38f7dce055d0 863
MikamiUitOpen 6:38f7dce055d0 864 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
MikamiUitOpen 6:38f7dce055d0 865 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
MikamiUitOpen 6:38f7dce055d0 866
MikamiUitOpen 6:38f7dce055d0 867 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
MikamiUitOpen 6:38f7dce055d0 868 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
MikamiUitOpen 6:38f7dce055d0 869
MikamiUitOpen 6:38f7dce055d0 870 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
MikamiUitOpen 6:38f7dce055d0 871 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
MikamiUitOpen 6:38f7dce055d0 872
MikamiUitOpen 6:38f7dce055d0 873 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
MikamiUitOpen 6:38f7dce055d0 874 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
MikamiUitOpen 6:38f7dce055d0 875
MikamiUitOpen 6:38f7dce055d0 876 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
MikamiUitOpen 6:38f7dce055d0 877 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
MikamiUitOpen 6:38f7dce055d0 878
MikamiUitOpen 6:38f7dce055d0 879 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
MikamiUitOpen 6:38f7dce055d0 880 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
MikamiUitOpen 6:38f7dce055d0 881
MikamiUitOpen 6:38f7dce055d0 882 /* DWT CPI Count Register Definitions */
MikamiUitOpen 6:38f7dce055d0 883 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
MikamiUitOpen 6:38f7dce055d0 884 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
MikamiUitOpen 6:38f7dce055d0 885
MikamiUitOpen 6:38f7dce055d0 886 /* DWT Exception Overhead Count Register Definitions */
MikamiUitOpen 6:38f7dce055d0 887 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
MikamiUitOpen 6:38f7dce055d0 888 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
MikamiUitOpen 6:38f7dce055d0 889
MikamiUitOpen 6:38f7dce055d0 890 /* DWT Sleep Count Register Definitions */
MikamiUitOpen 6:38f7dce055d0 891 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
MikamiUitOpen 6:38f7dce055d0 892 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
MikamiUitOpen 6:38f7dce055d0 893
MikamiUitOpen 6:38f7dce055d0 894 /* DWT LSU Count Register Definitions */
MikamiUitOpen 6:38f7dce055d0 895 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
MikamiUitOpen 6:38f7dce055d0 896 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
MikamiUitOpen 6:38f7dce055d0 897
MikamiUitOpen 6:38f7dce055d0 898 /* DWT Folded-instruction Count Register Definitions */
MikamiUitOpen 6:38f7dce055d0 899 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
MikamiUitOpen 6:38f7dce055d0 900 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
MikamiUitOpen 6:38f7dce055d0 901
MikamiUitOpen 6:38f7dce055d0 902 /* DWT Comparator Mask Register Definitions */
MikamiUitOpen 6:38f7dce055d0 903 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
MikamiUitOpen 6:38f7dce055d0 904 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
MikamiUitOpen 6:38f7dce055d0 905
MikamiUitOpen 6:38f7dce055d0 906 /* DWT Comparator Function Register Definitions */
MikamiUitOpen 6:38f7dce055d0 907 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
MikamiUitOpen 6:38f7dce055d0 908 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
MikamiUitOpen 6:38f7dce055d0 909
MikamiUitOpen 6:38f7dce055d0 910 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
MikamiUitOpen 6:38f7dce055d0 911 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
MikamiUitOpen 6:38f7dce055d0 912
MikamiUitOpen 6:38f7dce055d0 913 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
MikamiUitOpen 6:38f7dce055d0 914 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
MikamiUitOpen 6:38f7dce055d0 915
MikamiUitOpen 6:38f7dce055d0 916 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
MikamiUitOpen 6:38f7dce055d0 917 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
MikamiUitOpen 6:38f7dce055d0 918
MikamiUitOpen 6:38f7dce055d0 919 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
MikamiUitOpen 6:38f7dce055d0 920 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
MikamiUitOpen 6:38f7dce055d0 921
MikamiUitOpen 6:38f7dce055d0 922 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
MikamiUitOpen 6:38f7dce055d0 923 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
MikamiUitOpen 6:38f7dce055d0 924
MikamiUitOpen 6:38f7dce055d0 925 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
MikamiUitOpen 6:38f7dce055d0 926 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
MikamiUitOpen 6:38f7dce055d0 927
MikamiUitOpen 6:38f7dce055d0 928 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
MikamiUitOpen 6:38f7dce055d0 929 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
MikamiUitOpen 6:38f7dce055d0 930
MikamiUitOpen 6:38f7dce055d0 931 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
MikamiUitOpen 6:38f7dce055d0 932 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
MikamiUitOpen 6:38f7dce055d0 933
MikamiUitOpen 6:38f7dce055d0 934 /*@}*/ /* end of group CMSIS_DWT */
MikamiUitOpen 6:38f7dce055d0 935
MikamiUitOpen 6:38f7dce055d0 936
MikamiUitOpen 6:38f7dce055d0 937 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 938 \defgroup CMSIS_TPI Trace Port Interface (TPI)
MikamiUitOpen 6:38f7dce055d0 939 \brief Type definitions for the Trace Port Interface (TPI)
MikamiUitOpen 6:38f7dce055d0 940 @{
MikamiUitOpen 6:38f7dce055d0 941 */
MikamiUitOpen 6:38f7dce055d0 942
MikamiUitOpen 6:38f7dce055d0 943 /** \brief Structure type to access the Trace Port Interface Register (TPI).
MikamiUitOpen 6:38f7dce055d0 944 */
MikamiUitOpen 6:38f7dce055d0 945 typedef struct
MikamiUitOpen 6:38f7dce055d0 946 {
MikamiUitOpen 6:38f7dce055d0 947 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
MikamiUitOpen 6:38f7dce055d0 948 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
MikamiUitOpen 6:38f7dce055d0 949 uint32_t RESERVED0[2];
MikamiUitOpen 6:38f7dce055d0 950 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
MikamiUitOpen 6:38f7dce055d0 951 uint32_t RESERVED1[55];
MikamiUitOpen 6:38f7dce055d0 952 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
MikamiUitOpen 6:38f7dce055d0 953 uint32_t RESERVED2[131];
MikamiUitOpen 6:38f7dce055d0 954 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
MikamiUitOpen 6:38f7dce055d0 955 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
MikamiUitOpen 6:38f7dce055d0 956 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
MikamiUitOpen 6:38f7dce055d0 957 uint32_t RESERVED3[759];
MikamiUitOpen 6:38f7dce055d0 958 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
MikamiUitOpen 6:38f7dce055d0 959 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
MikamiUitOpen 6:38f7dce055d0 960 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
MikamiUitOpen 6:38f7dce055d0 961 uint32_t RESERVED4[1];
MikamiUitOpen 6:38f7dce055d0 962 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
MikamiUitOpen 6:38f7dce055d0 963 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
MikamiUitOpen 6:38f7dce055d0 964 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
MikamiUitOpen 6:38f7dce055d0 965 uint32_t RESERVED5[39];
MikamiUitOpen 6:38f7dce055d0 966 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
MikamiUitOpen 6:38f7dce055d0 967 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
MikamiUitOpen 6:38f7dce055d0 968 uint32_t RESERVED7[8];
MikamiUitOpen 6:38f7dce055d0 969 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
MikamiUitOpen 6:38f7dce055d0 970 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
MikamiUitOpen 6:38f7dce055d0 971 } TPI_Type;
MikamiUitOpen 6:38f7dce055d0 972
MikamiUitOpen 6:38f7dce055d0 973 /* TPI Asynchronous Clock Prescaler Register Definitions */
MikamiUitOpen 6:38f7dce055d0 974 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
MikamiUitOpen 6:38f7dce055d0 975 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
MikamiUitOpen 6:38f7dce055d0 976
MikamiUitOpen 6:38f7dce055d0 977 /* TPI Selected Pin Protocol Register Definitions */
MikamiUitOpen 6:38f7dce055d0 978 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
MikamiUitOpen 6:38f7dce055d0 979 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
MikamiUitOpen 6:38f7dce055d0 980
MikamiUitOpen 6:38f7dce055d0 981 /* TPI Formatter and Flush Status Register Definitions */
MikamiUitOpen 6:38f7dce055d0 982 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
MikamiUitOpen 6:38f7dce055d0 983 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
MikamiUitOpen 6:38f7dce055d0 984
MikamiUitOpen 6:38f7dce055d0 985 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
MikamiUitOpen 6:38f7dce055d0 986 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
MikamiUitOpen 6:38f7dce055d0 987
MikamiUitOpen 6:38f7dce055d0 988 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
MikamiUitOpen 6:38f7dce055d0 989 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
MikamiUitOpen 6:38f7dce055d0 990
MikamiUitOpen 6:38f7dce055d0 991 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
MikamiUitOpen 6:38f7dce055d0 992 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
MikamiUitOpen 6:38f7dce055d0 993
MikamiUitOpen 6:38f7dce055d0 994 /* TPI Formatter and Flush Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 995 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
MikamiUitOpen 6:38f7dce055d0 996 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
MikamiUitOpen 6:38f7dce055d0 997
MikamiUitOpen 6:38f7dce055d0 998 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
MikamiUitOpen 6:38f7dce055d0 999 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
MikamiUitOpen 6:38f7dce055d0 1000
MikamiUitOpen 6:38f7dce055d0 1001 /* TPI TRIGGER Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1002 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
MikamiUitOpen 6:38f7dce055d0 1003 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
MikamiUitOpen 6:38f7dce055d0 1004
MikamiUitOpen 6:38f7dce055d0 1005 /* TPI Integration ETM Data Register Definitions (FIFO0) */
MikamiUitOpen 6:38f7dce055d0 1006 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
MikamiUitOpen 6:38f7dce055d0 1007 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1008
MikamiUitOpen 6:38f7dce055d0 1009 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
MikamiUitOpen 6:38f7dce055d0 1010 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
MikamiUitOpen 6:38f7dce055d0 1011
MikamiUitOpen 6:38f7dce055d0 1012 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
MikamiUitOpen 6:38f7dce055d0 1013 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1014
MikamiUitOpen 6:38f7dce055d0 1015 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
MikamiUitOpen 6:38f7dce055d0 1016 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
MikamiUitOpen 6:38f7dce055d0 1017
MikamiUitOpen 6:38f7dce055d0 1018 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
MikamiUitOpen 6:38f7dce055d0 1019 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
MikamiUitOpen 6:38f7dce055d0 1020
MikamiUitOpen 6:38f7dce055d0 1021 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
MikamiUitOpen 6:38f7dce055d0 1022 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
MikamiUitOpen 6:38f7dce055d0 1023
MikamiUitOpen 6:38f7dce055d0 1024 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
MikamiUitOpen 6:38f7dce055d0 1025 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
MikamiUitOpen 6:38f7dce055d0 1026
MikamiUitOpen 6:38f7dce055d0 1027 /* TPI ITATBCTR2 Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1028 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
MikamiUitOpen 6:38f7dce055d0 1029 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
MikamiUitOpen 6:38f7dce055d0 1030
MikamiUitOpen 6:38f7dce055d0 1031 /* TPI Integration ITM Data Register Definitions (FIFO1) */
MikamiUitOpen 6:38f7dce055d0 1032 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
MikamiUitOpen 6:38f7dce055d0 1033 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1034
MikamiUitOpen 6:38f7dce055d0 1035 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
MikamiUitOpen 6:38f7dce055d0 1036 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
MikamiUitOpen 6:38f7dce055d0 1037
MikamiUitOpen 6:38f7dce055d0 1038 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
MikamiUitOpen 6:38f7dce055d0 1039 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1040
MikamiUitOpen 6:38f7dce055d0 1041 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
MikamiUitOpen 6:38f7dce055d0 1042 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
MikamiUitOpen 6:38f7dce055d0 1043
MikamiUitOpen 6:38f7dce055d0 1044 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
MikamiUitOpen 6:38f7dce055d0 1045 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
MikamiUitOpen 6:38f7dce055d0 1046
MikamiUitOpen 6:38f7dce055d0 1047 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
MikamiUitOpen 6:38f7dce055d0 1048 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
MikamiUitOpen 6:38f7dce055d0 1049
MikamiUitOpen 6:38f7dce055d0 1050 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
MikamiUitOpen 6:38f7dce055d0 1051 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
MikamiUitOpen 6:38f7dce055d0 1052
MikamiUitOpen 6:38f7dce055d0 1053 /* TPI ITATBCTR0 Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1054 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
MikamiUitOpen 6:38f7dce055d0 1055 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
MikamiUitOpen 6:38f7dce055d0 1056
MikamiUitOpen 6:38f7dce055d0 1057 /* TPI Integration Mode Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1058 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
MikamiUitOpen 6:38f7dce055d0 1059 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
MikamiUitOpen 6:38f7dce055d0 1060
MikamiUitOpen 6:38f7dce055d0 1061 /* TPI DEVID Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1062 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
MikamiUitOpen 6:38f7dce055d0 1063 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1064
MikamiUitOpen 6:38f7dce055d0 1065 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
MikamiUitOpen 6:38f7dce055d0 1066 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1067
MikamiUitOpen 6:38f7dce055d0 1068 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
MikamiUitOpen 6:38f7dce055d0 1069 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
MikamiUitOpen 6:38f7dce055d0 1070
MikamiUitOpen 6:38f7dce055d0 1071 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
MikamiUitOpen 6:38f7dce055d0 1072 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
MikamiUitOpen 6:38f7dce055d0 1073
MikamiUitOpen 6:38f7dce055d0 1074 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
MikamiUitOpen 6:38f7dce055d0 1075 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
MikamiUitOpen 6:38f7dce055d0 1076
MikamiUitOpen 6:38f7dce055d0 1077 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
MikamiUitOpen 6:38f7dce055d0 1078 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
MikamiUitOpen 6:38f7dce055d0 1079
MikamiUitOpen 6:38f7dce055d0 1080 /* TPI DEVTYPE Register Definitions */
MikamiUitOpen 6:38f7dce055d0 1081 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
MikamiUitOpen 6:38f7dce055d0 1082 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
MikamiUitOpen 6:38f7dce055d0 1083
MikamiUitOpen 6:38f7dce055d0 1084 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
MikamiUitOpen 6:38f7dce055d0 1085 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
MikamiUitOpen 6:38f7dce055d0 1086
MikamiUitOpen 6:38f7dce055d0 1087 /*@}*/ /* end of group CMSIS_TPI */
MikamiUitOpen 6:38f7dce055d0 1088
MikamiUitOpen 6:38f7dce055d0 1089
MikamiUitOpen 6:38f7dce055d0 1090 #if (__MPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 1091 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 1092 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen 6:38f7dce055d0 1093 \brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen 6:38f7dce055d0 1094 @{
MikamiUitOpen 6:38f7dce055d0 1095 */
MikamiUitOpen 6:38f7dce055d0 1096
MikamiUitOpen 6:38f7dce055d0 1097 /** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen 6:38f7dce055d0 1098 */
MikamiUitOpen 6:38f7dce055d0 1099 typedef struct
MikamiUitOpen 6:38f7dce055d0 1100 {
MikamiUitOpen 6:38f7dce055d0 1101 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
MikamiUitOpen 6:38f7dce055d0 1102 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
MikamiUitOpen 6:38f7dce055d0 1103 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
MikamiUitOpen 6:38f7dce055d0 1104 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 1105 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 1106 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 1107 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 1108 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 1109 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 1110 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 1111 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 1112 } MPU_Type;
MikamiUitOpen 6:38f7dce055d0 1113
MikamiUitOpen 6:38f7dce055d0 1114 /* MPU Type Register */
MikamiUitOpen 6:38f7dce055d0 1115 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
MikamiUitOpen 6:38f7dce055d0 1116 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
MikamiUitOpen 6:38f7dce055d0 1117
MikamiUitOpen 6:38f7dce055d0 1118 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
MikamiUitOpen 6:38f7dce055d0 1119 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
MikamiUitOpen 6:38f7dce055d0 1120
MikamiUitOpen 6:38f7dce055d0 1121 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
MikamiUitOpen 6:38f7dce055d0 1122 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
MikamiUitOpen 6:38f7dce055d0 1123
MikamiUitOpen 6:38f7dce055d0 1124 /* MPU Control Register */
MikamiUitOpen 6:38f7dce055d0 1125 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
MikamiUitOpen 6:38f7dce055d0 1126 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
MikamiUitOpen 6:38f7dce055d0 1127
MikamiUitOpen 6:38f7dce055d0 1128 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
MikamiUitOpen 6:38f7dce055d0 1129 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
MikamiUitOpen 6:38f7dce055d0 1130
MikamiUitOpen 6:38f7dce055d0 1131 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
MikamiUitOpen 6:38f7dce055d0 1132 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
MikamiUitOpen 6:38f7dce055d0 1133
MikamiUitOpen 6:38f7dce055d0 1134 /* MPU Region Number Register */
MikamiUitOpen 6:38f7dce055d0 1135 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
MikamiUitOpen 6:38f7dce055d0 1136 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
MikamiUitOpen 6:38f7dce055d0 1137
MikamiUitOpen 6:38f7dce055d0 1138 /* MPU Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 1139 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
MikamiUitOpen 6:38f7dce055d0 1140 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
MikamiUitOpen 6:38f7dce055d0 1141
MikamiUitOpen 6:38f7dce055d0 1142 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
MikamiUitOpen 6:38f7dce055d0 1143 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
MikamiUitOpen 6:38f7dce055d0 1144
MikamiUitOpen 6:38f7dce055d0 1145 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
MikamiUitOpen 6:38f7dce055d0 1146 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
MikamiUitOpen 6:38f7dce055d0 1147
MikamiUitOpen 6:38f7dce055d0 1148 /* MPU Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 1149 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
MikamiUitOpen 6:38f7dce055d0 1150 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
MikamiUitOpen 6:38f7dce055d0 1151
MikamiUitOpen 6:38f7dce055d0 1152 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
MikamiUitOpen 6:38f7dce055d0 1153 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
MikamiUitOpen 6:38f7dce055d0 1154
MikamiUitOpen 6:38f7dce055d0 1155 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
MikamiUitOpen 6:38f7dce055d0 1156 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
MikamiUitOpen 6:38f7dce055d0 1157
MikamiUitOpen 6:38f7dce055d0 1158 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
MikamiUitOpen 6:38f7dce055d0 1159 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
MikamiUitOpen 6:38f7dce055d0 1160
MikamiUitOpen 6:38f7dce055d0 1161 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
MikamiUitOpen 6:38f7dce055d0 1162 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
MikamiUitOpen 6:38f7dce055d0 1163
MikamiUitOpen 6:38f7dce055d0 1164 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
MikamiUitOpen 6:38f7dce055d0 1165 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
MikamiUitOpen 6:38f7dce055d0 1166
MikamiUitOpen 6:38f7dce055d0 1167 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
MikamiUitOpen 6:38f7dce055d0 1168 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
MikamiUitOpen 6:38f7dce055d0 1169
MikamiUitOpen 6:38f7dce055d0 1170 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
MikamiUitOpen 6:38f7dce055d0 1171 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
MikamiUitOpen 6:38f7dce055d0 1172
MikamiUitOpen 6:38f7dce055d0 1173 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
MikamiUitOpen 6:38f7dce055d0 1174 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
MikamiUitOpen 6:38f7dce055d0 1175
MikamiUitOpen 6:38f7dce055d0 1176 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
MikamiUitOpen 6:38f7dce055d0 1177 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
MikamiUitOpen 6:38f7dce055d0 1178
MikamiUitOpen 6:38f7dce055d0 1179 /*@} end of group CMSIS_MPU */
MikamiUitOpen 6:38f7dce055d0 1180 #endif
MikamiUitOpen 6:38f7dce055d0 1181
MikamiUitOpen 6:38f7dce055d0 1182
MikamiUitOpen 6:38f7dce055d0 1183 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 1184 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 6:38f7dce055d0 1185 \brief Type definitions for the Core Debug Registers
MikamiUitOpen 6:38f7dce055d0 1186 @{
MikamiUitOpen 6:38f7dce055d0 1187 */
MikamiUitOpen 6:38f7dce055d0 1188
MikamiUitOpen 6:38f7dce055d0 1189 /** \brief Structure type to access the Core Debug Register (CoreDebug).
MikamiUitOpen 6:38f7dce055d0 1190 */
MikamiUitOpen 6:38f7dce055d0 1191 typedef struct
MikamiUitOpen 6:38f7dce055d0 1192 {
MikamiUitOpen 6:38f7dce055d0 1193 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
MikamiUitOpen 6:38f7dce055d0 1194 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
MikamiUitOpen 6:38f7dce055d0 1195 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
MikamiUitOpen 6:38f7dce055d0 1196 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
MikamiUitOpen 6:38f7dce055d0 1197 } CoreDebug_Type;
MikamiUitOpen 6:38f7dce055d0 1198
MikamiUitOpen 6:38f7dce055d0 1199 /* Debug Halting Control and Status Register */
MikamiUitOpen 6:38f7dce055d0 1200 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
MikamiUitOpen 6:38f7dce055d0 1201 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
MikamiUitOpen 6:38f7dce055d0 1202
MikamiUitOpen 6:38f7dce055d0 1203 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
MikamiUitOpen 6:38f7dce055d0 1204 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
MikamiUitOpen 6:38f7dce055d0 1205
MikamiUitOpen 6:38f7dce055d0 1206 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
MikamiUitOpen 6:38f7dce055d0 1207 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
MikamiUitOpen 6:38f7dce055d0 1208
MikamiUitOpen 6:38f7dce055d0 1209 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
MikamiUitOpen 6:38f7dce055d0 1210 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
MikamiUitOpen 6:38f7dce055d0 1211
MikamiUitOpen 6:38f7dce055d0 1212 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
MikamiUitOpen 6:38f7dce055d0 1213 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
MikamiUitOpen 6:38f7dce055d0 1214
MikamiUitOpen 6:38f7dce055d0 1215 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
MikamiUitOpen 6:38f7dce055d0 1216 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
MikamiUitOpen 6:38f7dce055d0 1217
MikamiUitOpen 6:38f7dce055d0 1218 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
MikamiUitOpen 6:38f7dce055d0 1219 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
MikamiUitOpen 6:38f7dce055d0 1220
MikamiUitOpen 6:38f7dce055d0 1221 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
MikamiUitOpen 6:38f7dce055d0 1222 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
MikamiUitOpen 6:38f7dce055d0 1223
MikamiUitOpen 6:38f7dce055d0 1224 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
MikamiUitOpen 6:38f7dce055d0 1225 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
MikamiUitOpen 6:38f7dce055d0 1226
MikamiUitOpen 6:38f7dce055d0 1227 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
MikamiUitOpen 6:38f7dce055d0 1228 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
MikamiUitOpen 6:38f7dce055d0 1229
MikamiUitOpen 6:38f7dce055d0 1230 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
MikamiUitOpen 6:38f7dce055d0 1231 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
MikamiUitOpen 6:38f7dce055d0 1232
MikamiUitOpen 6:38f7dce055d0 1233 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
MikamiUitOpen 6:38f7dce055d0 1234 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
MikamiUitOpen 6:38f7dce055d0 1235
MikamiUitOpen 6:38f7dce055d0 1236 /* Debug Core Register Selector Register */
MikamiUitOpen 6:38f7dce055d0 1237 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
MikamiUitOpen 6:38f7dce055d0 1238 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
MikamiUitOpen 6:38f7dce055d0 1239
MikamiUitOpen 6:38f7dce055d0 1240 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
MikamiUitOpen 6:38f7dce055d0 1241 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
MikamiUitOpen 6:38f7dce055d0 1242
MikamiUitOpen 6:38f7dce055d0 1243 /* Debug Exception and Monitor Control Register */
MikamiUitOpen 6:38f7dce055d0 1244 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
MikamiUitOpen 6:38f7dce055d0 1245 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
MikamiUitOpen 6:38f7dce055d0 1246
MikamiUitOpen 6:38f7dce055d0 1247 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
MikamiUitOpen 6:38f7dce055d0 1248 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
MikamiUitOpen 6:38f7dce055d0 1249
MikamiUitOpen 6:38f7dce055d0 1250 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
MikamiUitOpen 6:38f7dce055d0 1251 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
MikamiUitOpen 6:38f7dce055d0 1252
MikamiUitOpen 6:38f7dce055d0 1253 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
MikamiUitOpen 6:38f7dce055d0 1254 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
MikamiUitOpen 6:38f7dce055d0 1255
MikamiUitOpen 6:38f7dce055d0 1256 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
MikamiUitOpen 6:38f7dce055d0 1257 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
MikamiUitOpen 6:38f7dce055d0 1258
MikamiUitOpen 6:38f7dce055d0 1259 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
MikamiUitOpen 6:38f7dce055d0 1260 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
MikamiUitOpen 6:38f7dce055d0 1261
MikamiUitOpen 6:38f7dce055d0 1262 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
MikamiUitOpen 6:38f7dce055d0 1263 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
MikamiUitOpen 6:38f7dce055d0 1264
MikamiUitOpen 6:38f7dce055d0 1265 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
MikamiUitOpen 6:38f7dce055d0 1266 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
MikamiUitOpen 6:38f7dce055d0 1267
MikamiUitOpen 6:38f7dce055d0 1268 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
MikamiUitOpen 6:38f7dce055d0 1269 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
MikamiUitOpen 6:38f7dce055d0 1270
MikamiUitOpen 6:38f7dce055d0 1271 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
MikamiUitOpen 6:38f7dce055d0 1272 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
MikamiUitOpen 6:38f7dce055d0 1273
MikamiUitOpen 6:38f7dce055d0 1274 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
MikamiUitOpen 6:38f7dce055d0 1275 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
MikamiUitOpen 6:38f7dce055d0 1276
MikamiUitOpen 6:38f7dce055d0 1277 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
MikamiUitOpen 6:38f7dce055d0 1278 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
MikamiUitOpen 6:38f7dce055d0 1279
MikamiUitOpen 6:38f7dce055d0 1280 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
MikamiUitOpen 6:38f7dce055d0 1281 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
MikamiUitOpen 6:38f7dce055d0 1282
MikamiUitOpen 6:38f7dce055d0 1283 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 6:38f7dce055d0 1284
MikamiUitOpen 6:38f7dce055d0 1285
MikamiUitOpen 6:38f7dce055d0 1286 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 1287 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 6:38f7dce055d0 1288 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 6:38f7dce055d0 1289 @{
MikamiUitOpen 6:38f7dce055d0 1290 */
MikamiUitOpen 6:38f7dce055d0 1291
MikamiUitOpen 6:38f7dce055d0 1292 /* Memory mapping of Cortex-M3 Hardware */
MikamiUitOpen 6:38f7dce055d0 1293 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 6:38f7dce055d0 1294 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
MikamiUitOpen 6:38f7dce055d0 1295 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
MikamiUitOpen 6:38f7dce055d0 1296 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
MikamiUitOpen 6:38f7dce055d0 1297 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
MikamiUitOpen 6:38f7dce055d0 1298 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 6:38f7dce055d0 1299 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 6:38f7dce055d0 1300 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 6:38f7dce055d0 1301
MikamiUitOpen 6:38f7dce055d0 1302 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
MikamiUitOpen 6:38f7dce055d0 1303 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 6:38f7dce055d0 1304 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 6:38f7dce055d0 1305 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 6:38f7dce055d0 1306 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
MikamiUitOpen 6:38f7dce055d0 1307 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
MikamiUitOpen 6:38f7dce055d0 1308 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
MikamiUitOpen 6:38f7dce055d0 1309 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
MikamiUitOpen 6:38f7dce055d0 1310
MikamiUitOpen 6:38f7dce055d0 1311 #if (__MPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 1312 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
MikamiUitOpen 6:38f7dce055d0 1313 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
MikamiUitOpen 6:38f7dce055d0 1314 #endif
MikamiUitOpen 6:38f7dce055d0 1315
MikamiUitOpen 6:38f7dce055d0 1316 /*@} */
MikamiUitOpen 6:38f7dce055d0 1317
MikamiUitOpen 6:38f7dce055d0 1318
MikamiUitOpen 6:38f7dce055d0 1319
MikamiUitOpen 6:38f7dce055d0 1320 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 1321 * Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 1322 Core Function Interface contains:
MikamiUitOpen 6:38f7dce055d0 1323 - Core NVIC Functions
MikamiUitOpen 6:38f7dce055d0 1324 - Core SysTick Functions
MikamiUitOpen 6:38f7dce055d0 1325 - Core Debug Functions
MikamiUitOpen 6:38f7dce055d0 1326 - Core Register Access Functions
MikamiUitOpen 6:38f7dce055d0 1327 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 1328 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 6:38f7dce055d0 1329 */
MikamiUitOpen 6:38f7dce055d0 1330
MikamiUitOpen 6:38f7dce055d0 1331
MikamiUitOpen 6:38f7dce055d0 1332
MikamiUitOpen 6:38f7dce055d0 1333 /* ########################## NVIC functions #################################### */
MikamiUitOpen 6:38f7dce055d0 1334 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 1335 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 6:38f7dce055d0 1336 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 6:38f7dce055d0 1337 @{
MikamiUitOpen 6:38f7dce055d0 1338 */
MikamiUitOpen 6:38f7dce055d0 1339
MikamiUitOpen 6:38f7dce055d0 1340 /** \brief Set Priority Grouping
MikamiUitOpen 6:38f7dce055d0 1341
MikamiUitOpen 6:38f7dce055d0 1342 The function sets the priority grouping field using the required unlock sequence.
MikamiUitOpen 6:38f7dce055d0 1343 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MikamiUitOpen 6:38f7dce055d0 1344 Only values from 0..7 are used.
MikamiUitOpen 6:38f7dce055d0 1345 In case of a conflict between priority grouping and available
MikamiUitOpen 6:38f7dce055d0 1346 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen 6:38f7dce055d0 1347
MikamiUitOpen 6:38f7dce055d0 1348 \param [in] PriorityGroup Priority grouping field.
MikamiUitOpen 6:38f7dce055d0 1349 */
MikamiUitOpen 6:38f7dce055d0 1350 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
MikamiUitOpen 6:38f7dce055d0 1351 {
MikamiUitOpen 6:38f7dce055d0 1352 uint32_t reg_value;
MikamiUitOpen 6:38f7dce055d0 1353 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 6:38f7dce055d0 1354
MikamiUitOpen 6:38f7dce055d0 1355 reg_value = SCB->AIRCR; /* read old register configuration */
MikamiUitOpen 6:38f7dce055d0 1356 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MikamiUitOpen 6:38f7dce055d0 1357 reg_value = (reg_value |
MikamiUitOpen 6:38f7dce055d0 1358 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 6:38f7dce055d0 1359 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
MikamiUitOpen 6:38f7dce055d0 1360 SCB->AIRCR = reg_value;
MikamiUitOpen 6:38f7dce055d0 1361 }
MikamiUitOpen 6:38f7dce055d0 1362
MikamiUitOpen 6:38f7dce055d0 1363
MikamiUitOpen 6:38f7dce055d0 1364 /** \brief Get Priority Grouping
MikamiUitOpen 6:38f7dce055d0 1365
MikamiUitOpen 6:38f7dce055d0 1366 The function reads the priority grouping field from the NVIC Interrupt Controller.
MikamiUitOpen 6:38f7dce055d0 1367
MikamiUitOpen 6:38f7dce055d0 1368 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MikamiUitOpen 6:38f7dce055d0 1369 */
MikamiUitOpen 6:38f7dce055d0 1370 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
MikamiUitOpen 6:38f7dce055d0 1371 {
MikamiUitOpen 6:38f7dce055d0 1372 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MikamiUitOpen 6:38f7dce055d0 1373 }
MikamiUitOpen 6:38f7dce055d0 1374
MikamiUitOpen 6:38f7dce055d0 1375
MikamiUitOpen 6:38f7dce055d0 1376 /** \brief Enable External Interrupt
MikamiUitOpen 6:38f7dce055d0 1377
MikamiUitOpen 6:38f7dce055d0 1378 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 6:38f7dce055d0 1379
MikamiUitOpen 6:38f7dce055d0 1380 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 1381 */
MikamiUitOpen 6:38f7dce055d0 1382 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1383 {
MikamiUitOpen 6:38f7dce055d0 1384 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 1385 }
MikamiUitOpen 6:38f7dce055d0 1386
MikamiUitOpen 6:38f7dce055d0 1387
MikamiUitOpen 6:38f7dce055d0 1388 /** \brief Disable External Interrupt
MikamiUitOpen 6:38f7dce055d0 1389
MikamiUitOpen 6:38f7dce055d0 1390 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 6:38f7dce055d0 1391
MikamiUitOpen 6:38f7dce055d0 1392 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 1393 */
MikamiUitOpen 6:38f7dce055d0 1394 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1395 {
MikamiUitOpen 6:38f7dce055d0 1396 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 1397 }
MikamiUitOpen 6:38f7dce055d0 1398
MikamiUitOpen 6:38f7dce055d0 1399
MikamiUitOpen 6:38f7dce055d0 1400 /** \brief Get Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 1401
MikamiUitOpen 6:38f7dce055d0 1402 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 6:38f7dce055d0 1403 for the specified interrupt.
MikamiUitOpen 6:38f7dce055d0 1404
MikamiUitOpen 6:38f7dce055d0 1405 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 1406
MikamiUitOpen 6:38f7dce055d0 1407 \return 0 Interrupt status is not pending.
MikamiUitOpen 6:38f7dce055d0 1408 \return 1 Interrupt status is pending.
MikamiUitOpen 6:38f7dce055d0 1409 */
MikamiUitOpen 6:38f7dce055d0 1410 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1411 {
MikamiUitOpen 6:38f7dce055d0 1412 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 6:38f7dce055d0 1413 }
MikamiUitOpen 6:38f7dce055d0 1414
MikamiUitOpen 6:38f7dce055d0 1415
MikamiUitOpen 6:38f7dce055d0 1416 /** \brief Set Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 1417
MikamiUitOpen 6:38f7dce055d0 1418 The function sets the pending bit of an external interrupt.
MikamiUitOpen 6:38f7dce055d0 1419
MikamiUitOpen 6:38f7dce055d0 1420 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 1421 */
MikamiUitOpen 6:38f7dce055d0 1422 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1423 {
MikamiUitOpen 6:38f7dce055d0 1424 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 1425 }
MikamiUitOpen 6:38f7dce055d0 1426
MikamiUitOpen 6:38f7dce055d0 1427
MikamiUitOpen 6:38f7dce055d0 1428 /** \brief Clear Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 1429
MikamiUitOpen 6:38f7dce055d0 1430 The function clears the pending bit of an external interrupt.
MikamiUitOpen 6:38f7dce055d0 1431
MikamiUitOpen 6:38f7dce055d0 1432 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 1433 */
MikamiUitOpen 6:38f7dce055d0 1434 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1435 {
MikamiUitOpen 6:38f7dce055d0 1436 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 1437 }
MikamiUitOpen 6:38f7dce055d0 1438
MikamiUitOpen 6:38f7dce055d0 1439
MikamiUitOpen 6:38f7dce055d0 1440 /** \brief Get Active Interrupt
MikamiUitOpen 6:38f7dce055d0 1441
MikamiUitOpen 6:38f7dce055d0 1442 The function reads the active register in NVIC and returns the active bit.
MikamiUitOpen 6:38f7dce055d0 1443
MikamiUitOpen 6:38f7dce055d0 1444 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 1445
MikamiUitOpen 6:38f7dce055d0 1446 \return 0 Interrupt status is not active.
MikamiUitOpen 6:38f7dce055d0 1447 \return 1 Interrupt status is active.
MikamiUitOpen 6:38f7dce055d0 1448 */
MikamiUitOpen 6:38f7dce055d0 1449 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1450 {
MikamiUitOpen 6:38f7dce055d0 1451 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 6:38f7dce055d0 1452 }
MikamiUitOpen 6:38f7dce055d0 1453
MikamiUitOpen 6:38f7dce055d0 1454
MikamiUitOpen 6:38f7dce055d0 1455 /** \brief Set Interrupt Priority
MikamiUitOpen 6:38f7dce055d0 1456
MikamiUitOpen 6:38f7dce055d0 1457 The function sets the priority of an interrupt.
MikamiUitOpen 6:38f7dce055d0 1458
MikamiUitOpen 6:38f7dce055d0 1459 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 6:38f7dce055d0 1460
MikamiUitOpen 6:38f7dce055d0 1461 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 1462 \param [in] priority Priority to set.
MikamiUitOpen 6:38f7dce055d0 1463 */
MikamiUitOpen 6:38f7dce055d0 1464 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 6:38f7dce055d0 1465 {
MikamiUitOpen 6:38f7dce055d0 1466 if((int32_t)IRQn < 0) {
MikamiUitOpen 6:38f7dce055d0 1467 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen 6:38f7dce055d0 1468 }
MikamiUitOpen 6:38f7dce055d0 1469 else {
MikamiUitOpen 6:38f7dce055d0 1470 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MikamiUitOpen 6:38f7dce055d0 1471 }
MikamiUitOpen 6:38f7dce055d0 1472 }
MikamiUitOpen 6:38f7dce055d0 1473
MikamiUitOpen 6:38f7dce055d0 1474
MikamiUitOpen 6:38f7dce055d0 1475 /** \brief Get Interrupt Priority
MikamiUitOpen 6:38f7dce055d0 1476
MikamiUitOpen 6:38f7dce055d0 1477 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 6:38f7dce055d0 1478 number can be positive to specify an external (device specific)
MikamiUitOpen 6:38f7dce055d0 1479 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 6:38f7dce055d0 1480
MikamiUitOpen 6:38f7dce055d0 1481
MikamiUitOpen 6:38f7dce055d0 1482 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 1483 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 6:38f7dce055d0 1484 priority bits of the microcontroller.
MikamiUitOpen 6:38f7dce055d0 1485 */
MikamiUitOpen 6:38f7dce055d0 1486 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 1487 {
MikamiUitOpen 6:38f7dce055d0 1488
MikamiUitOpen 6:38f7dce055d0 1489 if((int32_t)IRQn < 0) {
MikamiUitOpen 6:38f7dce055d0 1490 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 6:38f7dce055d0 1491 }
MikamiUitOpen 6:38f7dce055d0 1492 else {
MikamiUitOpen 6:38f7dce055d0 1493 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 6:38f7dce055d0 1494 }
MikamiUitOpen 6:38f7dce055d0 1495 }
MikamiUitOpen 6:38f7dce055d0 1496
MikamiUitOpen 6:38f7dce055d0 1497
MikamiUitOpen 6:38f7dce055d0 1498 /** \brief Encode Priority
MikamiUitOpen 6:38f7dce055d0 1499
MikamiUitOpen 6:38f7dce055d0 1500 The function encodes the priority for an interrupt with the given priority group,
MikamiUitOpen 6:38f7dce055d0 1501 preemptive priority value, and subpriority value.
MikamiUitOpen 6:38f7dce055d0 1502 In case of a conflict between priority grouping and available
MikamiUitOpen 6:38f7dce055d0 1503 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MikamiUitOpen 6:38f7dce055d0 1504
MikamiUitOpen 6:38f7dce055d0 1505 \param [in] PriorityGroup Used priority group.
MikamiUitOpen 6:38f7dce055d0 1506 \param [in] PreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen 6:38f7dce055d0 1507 \param [in] SubPriority Subpriority value (starting from 0).
MikamiUitOpen 6:38f7dce055d0 1508 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
MikamiUitOpen 6:38f7dce055d0 1509 */
MikamiUitOpen 6:38f7dce055d0 1510 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
MikamiUitOpen 6:38f7dce055d0 1511 {
MikamiUitOpen 6:38f7dce055d0 1512 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 6:38f7dce055d0 1513 uint32_t PreemptPriorityBits;
MikamiUitOpen 6:38f7dce055d0 1514 uint32_t SubPriorityBits;
MikamiUitOpen 6:38f7dce055d0 1515
MikamiUitOpen 6:38f7dce055d0 1516 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen 6:38f7dce055d0 1517 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen 6:38f7dce055d0 1518
MikamiUitOpen 6:38f7dce055d0 1519 return (
MikamiUitOpen 6:38f7dce055d0 1520 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
MikamiUitOpen 6:38f7dce055d0 1521 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
MikamiUitOpen 6:38f7dce055d0 1522 );
MikamiUitOpen 6:38f7dce055d0 1523 }
MikamiUitOpen 6:38f7dce055d0 1524
MikamiUitOpen 6:38f7dce055d0 1525
MikamiUitOpen 6:38f7dce055d0 1526 /** \brief Decode Priority
MikamiUitOpen 6:38f7dce055d0 1527
MikamiUitOpen 6:38f7dce055d0 1528 The function decodes an interrupt priority value with a given priority group to
MikamiUitOpen 6:38f7dce055d0 1529 preemptive priority value and subpriority value.
MikamiUitOpen 6:38f7dce055d0 1530 In case of a conflict between priority grouping and available
MikamiUitOpen 6:38f7dce055d0 1531 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
MikamiUitOpen 6:38f7dce055d0 1532
MikamiUitOpen 6:38f7dce055d0 1533 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
MikamiUitOpen 6:38f7dce055d0 1534 \param [in] PriorityGroup Used priority group.
MikamiUitOpen 6:38f7dce055d0 1535 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
MikamiUitOpen 6:38f7dce055d0 1536 \param [out] pSubPriority Subpriority value (starting from 0).
MikamiUitOpen 6:38f7dce055d0 1537 */
MikamiUitOpen 6:38f7dce055d0 1538 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
MikamiUitOpen 6:38f7dce055d0 1539 {
MikamiUitOpen 6:38f7dce055d0 1540 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MikamiUitOpen 6:38f7dce055d0 1541 uint32_t PreemptPriorityBits;
MikamiUitOpen 6:38f7dce055d0 1542 uint32_t SubPriorityBits;
MikamiUitOpen 6:38f7dce055d0 1543
MikamiUitOpen 6:38f7dce055d0 1544 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MikamiUitOpen 6:38f7dce055d0 1545 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MikamiUitOpen 6:38f7dce055d0 1546
MikamiUitOpen 6:38f7dce055d0 1547 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
MikamiUitOpen 6:38f7dce055d0 1548 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
MikamiUitOpen 6:38f7dce055d0 1549 }
MikamiUitOpen 6:38f7dce055d0 1550
MikamiUitOpen 6:38f7dce055d0 1551
MikamiUitOpen 6:38f7dce055d0 1552 /** \brief System Reset
MikamiUitOpen 6:38f7dce055d0 1553
MikamiUitOpen 6:38f7dce055d0 1554 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 6:38f7dce055d0 1555 */
MikamiUitOpen 6:38f7dce055d0 1556 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 6:38f7dce055d0 1557 {
MikamiUitOpen 6:38f7dce055d0 1558 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 6:38f7dce055d0 1559 buffered write are completed before reset */
MikamiUitOpen 6:38f7dce055d0 1560 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 6:38f7dce055d0 1561 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
MikamiUitOpen 6:38f7dce055d0 1562 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
MikamiUitOpen 6:38f7dce055d0 1563 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 6:38f7dce055d0 1564 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 6:38f7dce055d0 1565 }
MikamiUitOpen 6:38f7dce055d0 1566
MikamiUitOpen 6:38f7dce055d0 1567 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 6:38f7dce055d0 1568
MikamiUitOpen 6:38f7dce055d0 1569
MikamiUitOpen 6:38f7dce055d0 1570
MikamiUitOpen 6:38f7dce055d0 1571 /* ################################## SysTick function ############################################ */
MikamiUitOpen 6:38f7dce055d0 1572 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 1573 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 6:38f7dce055d0 1574 \brief Functions that configure the System.
MikamiUitOpen 6:38f7dce055d0 1575 @{
MikamiUitOpen 6:38f7dce055d0 1576 */
MikamiUitOpen 6:38f7dce055d0 1577
MikamiUitOpen 6:38f7dce055d0 1578 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 6:38f7dce055d0 1579
MikamiUitOpen 6:38f7dce055d0 1580 /** \brief System Tick Configuration
MikamiUitOpen 6:38f7dce055d0 1581
MikamiUitOpen 6:38f7dce055d0 1582 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 6:38f7dce055d0 1583 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 6:38f7dce055d0 1584
MikamiUitOpen 6:38f7dce055d0 1585 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 6:38f7dce055d0 1586
MikamiUitOpen 6:38f7dce055d0 1587 \return 0 Function succeeded.
MikamiUitOpen 6:38f7dce055d0 1588 \return 1 Function failed.
MikamiUitOpen 6:38f7dce055d0 1589
MikamiUitOpen 6:38f7dce055d0 1590 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 6:38f7dce055d0 1591 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 6:38f7dce055d0 1592 must contain a vendor-specific implementation of this function.
MikamiUitOpen 6:38f7dce055d0 1593
MikamiUitOpen 6:38f7dce055d0 1594 */
MikamiUitOpen 6:38f7dce055d0 1595 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 6:38f7dce055d0 1596 {
MikamiUitOpen 6:38f7dce055d0 1597 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
MikamiUitOpen 6:38f7dce055d0 1598
MikamiUitOpen 6:38f7dce055d0 1599 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 6:38f7dce055d0 1600 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 6:38f7dce055d0 1601 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 6:38f7dce055d0 1602 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 6:38f7dce055d0 1603 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 6:38f7dce055d0 1604 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 6:38f7dce055d0 1605 return (0UL); /* Function successful */
MikamiUitOpen 6:38f7dce055d0 1606 }
MikamiUitOpen 6:38f7dce055d0 1607
MikamiUitOpen 6:38f7dce055d0 1608 #endif
MikamiUitOpen 6:38f7dce055d0 1609
MikamiUitOpen 6:38f7dce055d0 1610 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 6:38f7dce055d0 1611
MikamiUitOpen 6:38f7dce055d0 1612
MikamiUitOpen 6:38f7dce055d0 1613
MikamiUitOpen 6:38f7dce055d0 1614 /* ##################################### Debug In/Output function ########################################### */
MikamiUitOpen 6:38f7dce055d0 1615 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 1616 \defgroup CMSIS_core_DebugFunctions ITM Functions
MikamiUitOpen 6:38f7dce055d0 1617 \brief Functions that access the ITM debug interface.
MikamiUitOpen 6:38f7dce055d0 1618 @{
MikamiUitOpen 6:38f7dce055d0 1619 */
MikamiUitOpen 6:38f7dce055d0 1620
MikamiUitOpen 6:38f7dce055d0 1621 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
MikamiUitOpen 6:38f7dce055d0 1622 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
MikamiUitOpen 6:38f7dce055d0 1623
MikamiUitOpen 6:38f7dce055d0 1624
MikamiUitOpen 6:38f7dce055d0 1625 /** \brief ITM Send Character
MikamiUitOpen 6:38f7dce055d0 1626
MikamiUitOpen 6:38f7dce055d0 1627 The function transmits a character via the ITM channel 0, and
MikamiUitOpen 6:38f7dce055d0 1628 \li Just returns when no debugger is connected that has booked the output.
MikamiUitOpen 6:38f7dce055d0 1629 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
MikamiUitOpen 6:38f7dce055d0 1630
MikamiUitOpen 6:38f7dce055d0 1631 \param [in] ch Character to transmit.
MikamiUitOpen 6:38f7dce055d0 1632
MikamiUitOpen 6:38f7dce055d0 1633 \returns Character to transmit.
MikamiUitOpen 6:38f7dce055d0 1634 */
MikamiUitOpen 6:38f7dce055d0 1635 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
MikamiUitOpen 6:38f7dce055d0 1636 {
MikamiUitOpen 6:38f7dce055d0 1637 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
MikamiUitOpen 6:38f7dce055d0 1638 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
MikamiUitOpen 6:38f7dce055d0 1639 {
MikamiUitOpen 6:38f7dce055d0 1640 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
MikamiUitOpen 6:38f7dce055d0 1641 ITM->PORT[0].u8 = (uint8_t)ch;
MikamiUitOpen 6:38f7dce055d0 1642 }
MikamiUitOpen 6:38f7dce055d0 1643 return (ch);
MikamiUitOpen 6:38f7dce055d0 1644 }
MikamiUitOpen 6:38f7dce055d0 1645
MikamiUitOpen 6:38f7dce055d0 1646
MikamiUitOpen 6:38f7dce055d0 1647 /** \brief ITM Receive Character
MikamiUitOpen 6:38f7dce055d0 1648
MikamiUitOpen 6:38f7dce055d0 1649 The function inputs a character via the external variable \ref ITM_RxBuffer.
MikamiUitOpen 6:38f7dce055d0 1650
MikamiUitOpen 6:38f7dce055d0 1651 \return Received character.
MikamiUitOpen 6:38f7dce055d0 1652 \return -1 No character pending.
MikamiUitOpen 6:38f7dce055d0 1653 */
MikamiUitOpen 6:38f7dce055d0 1654 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
MikamiUitOpen 6:38f7dce055d0 1655 int32_t ch = -1; /* no character available */
MikamiUitOpen 6:38f7dce055d0 1656
MikamiUitOpen 6:38f7dce055d0 1657 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
MikamiUitOpen 6:38f7dce055d0 1658 ch = ITM_RxBuffer;
MikamiUitOpen 6:38f7dce055d0 1659 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
MikamiUitOpen 6:38f7dce055d0 1660 }
MikamiUitOpen 6:38f7dce055d0 1661
MikamiUitOpen 6:38f7dce055d0 1662 return (ch);
MikamiUitOpen 6:38f7dce055d0 1663 }
MikamiUitOpen 6:38f7dce055d0 1664
MikamiUitOpen 6:38f7dce055d0 1665
MikamiUitOpen 6:38f7dce055d0 1666 /** \brief ITM Check Character
MikamiUitOpen 6:38f7dce055d0 1667
MikamiUitOpen 6:38f7dce055d0 1668 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
MikamiUitOpen 6:38f7dce055d0 1669
MikamiUitOpen 6:38f7dce055d0 1670 \return 0 No character available.
MikamiUitOpen 6:38f7dce055d0 1671 \return 1 Character available.
MikamiUitOpen 6:38f7dce055d0 1672 */
MikamiUitOpen 6:38f7dce055d0 1673 __STATIC_INLINE int32_t ITM_CheckChar (void) {
MikamiUitOpen 6:38f7dce055d0 1674
MikamiUitOpen 6:38f7dce055d0 1675 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
MikamiUitOpen 6:38f7dce055d0 1676 return (0); /* no character available */
MikamiUitOpen 6:38f7dce055d0 1677 } else {
MikamiUitOpen 6:38f7dce055d0 1678 return (1); /* character available */
MikamiUitOpen 6:38f7dce055d0 1679 }
MikamiUitOpen 6:38f7dce055d0 1680 }
MikamiUitOpen 6:38f7dce055d0 1681
MikamiUitOpen 6:38f7dce055d0 1682 /*@} end of CMSIS_core_DebugFunctions */
MikamiUitOpen 6:38f7dce055d0 1683
MikamiUitOpen 6:38f7dce055d0 1684
MikamiUitOpen 6:38f7dce055d0 1685
MikamiUitOpen 6:38f7dce055d0 1686
MikamiUitOpen 6:38f7dce055d0 1687 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 1688 }
MikamiUitOpen 6:38f7dce055d0 1689 #endif
MikamiUitOpen 6:38f7dce055d0 1690
MikamiUitOpen 6:38f7dce055d0 1691 #endif /* __CORE_CM3_H_DEPENDANT */
MikamiUitOpen 6:38f7dce055d0 1692
MikamiUitOpen 6:38f7dce055d0 1693 #endif /* __CMSIS_GENERIC */