不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_cm0plus.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_cm0plus.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version V4.10
MikamiUitOpen 6:38f7dce055d0 5 * @date 18. March 2015
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #if defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 6:38f7dce055d0 40 #endif
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 #ifndef __CORE_CM0PLUS_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 43 #define __CORE_CM0PLUS_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 44
MikamiUitOpen 6:38f7dce055d0 45 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 46 extern "C" {
MikamiUitOpen 6:38f7dce055d0 47 #endif
MikamiUitOpen 6:38f7dce055d0 48
MikamiUitOpen 6:38f7dce055d0 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 6:38f7dce055d0 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 6:38f7dce055d0 51
MikamiUitOpen 6:38f7dce055d0 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 6:38f7dce055d0 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 6:38f7dce055d0 54
MikamiUitOpen 6:38f7dce055d0 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 6:38f7dce055d0 56 Unions are used for effective representation of core registers.
MikamiUitOpen 6:38f7dce055d0 57
MikamiUitOpen 6:38f7dce055d0 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 6:38f7dce055d0 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 6:38f7dce055d0 60 */
MikamiUitOpen 6:38f7dce055d0 61
MikamiUitOpen 6:38f7dce055d0 62
MikamiUitOpen 6:38f7dce055d0 63 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 64 * CMSIS definitions
MikamiUitOpen 6:38f7dce055d0 65 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 66 /** \ingroup Cortex-M0+
MikamiUitOpen 6:38f7dce055d0 67 @{
MikamiUitOpen 6:38f7dce055d0 68 */
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70 /* CMSIS CM0P definitions */
MikamiUitOpen 6:38f7dce055d0 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 6:38f7dce055d0 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 6:38f7dce055d0 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 6:38f7dce055d0 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
MikamiUitOpen 6:38f7dce055d0 75
MikamiUitOpen 6:38f7dce055d0 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
MikamiUitOpen 6:38f7dce055d0 77
MikamiUitOpen 6:38f7dce055d0 78
MikamiUitOpen 6:38f7dce055d0 79 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 6:38f7dce055d0 83
MikamiUitOpen 6:38f7dce055d0 84 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 87 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 88
MikamiUitOpen 6:38f7dce055d0 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 6:38f7dce055d0 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 6:38f7dce055d0 92 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 93
MikamiUitOpen 6:38f7dce055d0 94 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 6:38f7dce055d0 96 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 97
MikamiUitOpen 6:38f7dce055d0 98 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 101 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 102
MikamiUitOpen 6:38f7dce055d0 103 #elif defined ( __CSMC__ )
MikamiUitOpen 6:38f7dce055d0 104 #define __packed
MikamiUitOpen 6:38f7dce055d0 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 6:38f7dce055d0 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 6:38f7dce055d0 107 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 108
MikamiUitOpen 6:38f7dce055d0 109 #endif
MikamiUitOpen 6:38f7dce055d0 110
MikamiUitOpen 6:38f7dce055d0 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 6:38f7dce055d0 112 This core does not support an FPU at all
MikamiUitOpen 6:38f7dce055d0 113 */
MikamiUitOpen 6:38f7dce055d0 114 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 115
MikamiUitOpen 6:38f7dce055d0 116 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 6:38f7dce055d0 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 119 #endif
MikamiUitOpen 6:38f7dce055d0 120
MikamiUitOpen 6:38f7dce055d0 121 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 6:38f7dce055d0 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 124 #endif
MikamiUitOpen 6:38f7dce055d0 125
MikamiUitOpen 6:38f7dce055d0 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 127 #if defined __ARMVFP__
MikamiUitOpen 6:38f7dce055d0 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 129 #endif
MikamiUitOpen 6:38f7dce055d0 130
MikamiUitOpen 6:38f7dce055d0 131 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 6:38f7dce055d0 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 134 #endif
MikamiUitOpen 6:38f7dce055d0 135
MikamiUitOpen 6:38f7dce055d0 136 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 137 #if defined __FPU_VFP__
MikamiUitOpen 6:38f7dce055d0 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 139 #endif
MikamiUitOpen 6:38f7dce055d0 140
MikamiUitOpen 6:38f7dce055d0 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 6:38f7dce055d0 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 6:38f7dce055d0 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 144 #endif
MikamiUitOpen 6:38f7dce055d0 145 #endif
MikamiUitOpen 6:38f7dce055d0 146
MikamiUitOpen 6:38f7dce055d0 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 6:38f7dce055d0 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 6:38f7dce055d0 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 6:38f7dce055d0 150
MikamiUitOpen 6:38f7dce055d0 151 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 152 }
MikamiUitOpen 6:38f7dce055d0 153 #endif
MikamiUitOpen 6:38f7dce055d0 154
MikamiUitOpen 6:38f7dce055d0 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
MikamiUitOpen 6:38f7dce055d0 156
MikamiUitOpen 6:38f7dce055d0 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 6:38f7dce055d0 158
MikamiUitOpen 6:38f7dce055d0 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 160 #define __CORE_CM0PLUS_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 161
MikamiUitOpen 6:38f7dce055d0 162 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 163 extern "C" {
MikamiUitOpen 6:38f7dce055d0 164 #endif
MikamiUitOpen 6:38f7dce055d0 165
MikamiUitOpen 6:38f7dce055d0 166 /* check device defines and use defaults */
MikamiUitOpen 6:38f7dce055d0 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 6:38f7dce055d0 168 #ifndef __CM0PLUS_REV
MikamiUitOpen 6:38f7dce055d0 169 #define __CM0PLUS_REV 0x0000
MikamiUitOpen 6:38f7dce055d0 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 171 #endif
MikamiUitOpen 6:38f7dce055d0 172
MikamiUitOpen 6:38f7dce055d0 173 #ifndef __MPU_PRESENT
MikamiUitOpen 6:38f7dce055d0 174 #define __MPU_PRESENT 0
MikamiUitOpen 6:38f7dce055d0 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 176 #endif
MikamiUitOpen 6:38f7dce055d0 177
MikamiUitOpen 6:38f7dce055d0 178 #ifndef __VTOR_PRESENT
MikamiUitOpen 6:38f7dce055d0 179 #define __VTOR_PRESENT 0
MikamiUitOpen 6:38f7dce055d0 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 181 #endif
MikamiUitOpen 6:38f7dce055d0 182
MikamiUitOpen 6:38f7dce055d0 183 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 6:38f7dce055d0 184 #define __NVIC_PRIO_BITS 2
MikamiUitOpen 6:38f7dce055d0 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 186 #endif
MikamiUitOpen 6:38f7dce055d0 187
MikamiUitOpen 6:38f7dce055d0 188 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 6:38f7dce055d0 189 #define __Vendor_SysTickConfig 0
MikamiUitOpen 6:38f7dce055d0 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 191 #endif
MikamiUitOpen 6:38f7dce055d0 192 #endif
MikamiUitOpen 6:38f7dce055d0 193
MikamiUitOpen 6:38f7dce055d0 194 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 6:38f7dce055d0 195 /**
MikamiUitOpen 6:38f7dce055d0 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 6:38f7dce055d0 197
MikamiUitOpen 6:38f7dce055d0 198 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 6:38f7dce055d0 199 \li to specify the access to peripheral variables.
MikamiUitOpen 6:38f7dce055d0 200 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 6:38f7dce055d0 201 */
MikamiUitOpen 6:38f7dce055d0 202 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 203 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 204 #else
MikamiUitOpen 6:38f7dce055d0 205 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 206 #endif
MikamiUitOpen 6:38f7dce055d0 207 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 6:38f7dce055d0 208 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 6:38f7dce055d0 209
MikamiUitOpen 6:38f7dce055d0 210 /*@} end of group Cortex-M0+ */
MikamiUitOpen 6:38f7dce055d0 211
MikamiUitOpen 6:38f7dce055d0 212
MikamiUitOpen 6:38f7dce055d0 213
MikamiUitOpen 6:38f7dce055d0 214 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 215 * Register Abstraction
MikamiUitOpen 6:38f7dce055d0 216 Core Register contain:
MikamiUitOpen 6:38f7dce055d0 217 - Core Register
MikamiUitOpen 6:38f7dce055d0 218 - Core NVIC Register
MikamiUitOpen 6:38f7dce055d0 219 - Core SCB Register
MikamiUitOpen 6:38f7dce055d0 220 - Core SysTick Register
MikamiUitOpen 6:38f7dce055d0 221 - Core MPU Register
MikamiUitOpen 6:38f7dce055d0 222 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 6:38f7dce055d0 224 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 6:38f7dce055d0 225 */
MikamiUitOpen 6:38f7dce055d0 226
MikamiUitOpen 6:38f7dce055d0 227 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 228 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 6:38f7dce055d0 229 \brief Core Register type definitions.
MikamiUitOpen 6:38f7dce055d0 230 @{
MikamiUitOpen 6:38f7dce055d0 231 */
MikamiUitOpen 6:38f7dce055d0 232
MikamiUitOpen 6:38f7dce055d0 233 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 6:38f7dce055d0 234 */
MikamiUitOpen 6:38f7dce055d0 235 typedef union
MikamiUitOpen 6:38f7dce055d0 236 {
MikamiUitOpen 6:38f7dce055d0 237 struct
MikamiUitOpen 6:38f7dce055d0 238 {
MikamiUitOpen 6:38f7dce055d0 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
MikamiUitOpen 6:38f7dce055d0 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 6:38f7dce055d0 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 6:38f7dce055d0 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 6:38f7dce055d0 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 6:38f7dce055d0 244 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 245 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 246 } APSR_Type;
MikamiUitOpen 6:38f7dce055d0 247
MikamiUitOpen 6:38f7dce055d0 248 /* APSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 6:38f7dce055d0 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 6:38f7dce055d0 251
MikamiUitOpen 6:38f7dce055d0 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 6:38f7dce055d0 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 6:38f7dce055d0 254
MikamiUitOpen 6:38f7dce055d0 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 6:38f7dce055d0 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 6:38f7dce055d0 257
MikamiUitOpen 6:38f7dce055d0 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 6:38f7dce055d0 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 6:38f7dce055d0 260
MikamiUitOpen 6:38f7dce055d0 261
MikamiUitOpen 6:38f7dce055d0 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 6:38f7dce055d0 263 */
MikamiUitOpen 6:38f7dce055d0 264 typedef union
MikamiUitOpen 6:38f7dce055d0 265 {
MikamiUitOpen 6:38f7dce055d0 266 struct
MikamiUitOpen 6:38f7dce055d0 267 {
MikamiUitOpen 6:38f7dce055d0 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 6:38f7dce055d0 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 6:38f7dce055d0 270 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 271 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 272 } IPSR_Type;
MikamiUitOpen 6:38f7dce055d0 273
MikamiUitOpen 6:38f7dce055d0 274 /* IPSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 6:38f7dce055d0 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 6:38f7dce055d0 277
MikamiUitOpen 6:38f7dce055d0 278
MikamiUitOpen 6:38f7dce055d0 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 6:38f7dce055d0 280 */
MikamiUitOpen 6:38f7dce055d0 281 typedef union
MikamiUitOpen 6:38f7dce055d0 282 {
MikamiUitOpen 6:38f7dce055d0 283 struct
MikamiUitOpen 6:38f7dce055d0 284 {
MikamiUitOpen 6:38f7dce055d0 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 6:38f7dce055d0 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 6:38f7dce055d0 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 6:38f7dce055d0 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
MikamiUitOpen 6:38f7dce055d0 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 6:38f7dce055d0 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 6:38f7dce055d0 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 6:38f7dce055d0 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 6:38f7dce055d0 293 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 294 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 295 } xPSR_Type;
MikamiUitOpen 6:38f7dce055d0 296
MikamiUitOpen 6:38f7dce055d0 297 /* xPSR Register Definitions */
MikamiUitOpen 6:38f7dce055d0 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 6:38f7dce055d0 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 6:38f7dce055d0 300
MikamiUitOpen 6:38f7dce055d0 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 6:38f7dce055d0 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 6:38f7dce055d0 303
MikamiUitOpen 6:38f7dce055d0 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 6:38f7dce055d0 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 6:38f7dce055d0 306
MikamiUitOpen 6:38f7dce055d0 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 6:38f7dce055d0 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 6:38f7dce055d0 309
MikamiUitOpen 6:38f7dce055d0 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 6:38f7dce055d0 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 6:38f7dce055d0 312
MikamiUitOpen 6:38f7dce055d0 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 6:38f7dce055d0 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 6:38f7dce055d0 315
MikamiUitOpen 6:38f7dce055d0 316
MikamiUitOpen 6:38f7dce055d0 317 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 6:38f7dce055d0 318 */
MikamiUitOpen 6:38f7dce055d0 319 typedef union
MikamiUitOpen 6:38f7dce055d0 320 {
MikamiUitOpen 6:38f7dce055d0 321 struct
MikamiUitOpen 6:38f7dce055d0 322 {
MikamiUitOpen 6:38f7dce055d0 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
MikamiUitOpen 6:38f7dce055d0 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 6:38f7dce055d0 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 6:38f7dce055d0 326 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 327 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 328 } CONTROL_Type;
MikamiUitOpen 6:38f7dce055d0 329
MikamiUitOpen 6:38f7dce055d0 330 /* CONTROL Register Definitions */
MikamiUitOpen 6:38f7dce055d0 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 6:38f7dce055d0 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 6:38f7dce055d0 333
MikamiUitOpen 6:38f7dce055d0 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
MikamiUitOpen 6:38f7dce055d0 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
MikamiUitOpen 6:38f7dce055d0 336
MikamiUitOpen 6:38f7dce055d0 337 /*@} end of group CMSIS_CORE */
MikamiUitOpen 6:38f7dce055d0 338
MikamiUitOpen 6:38f7dce055d0 339
MikamiUitOpen 6:38f7dce055d0 340 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 6:38f7dce055d0 342 \brief Type definitions for the NVIC Registers
MikamiUitOpen 6:38f7dce055d0 343 @{
MikamiUitOpen 6:38f7dce055d0 344 */
MikamiUitOpen 6:38f7dce055d0 345
MikamiUitOpen 6:38f7dce055d0 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 6:38f7dce055d0 347 */
MikamiUitOpen 6:38f7dce055d0 348 typedef struct
MikamiUitOpen 6:38f7dce055d0 349 {
MikamiUitOpen 6:38f7dce055d0 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 6:38f7dce055d0 351 uint32_t RESERVED0[31];
MikamiUitOpen 6:38f7dce055d0 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 6:38f7dce055d0 353 uint32_t RSERVED1[31];
MikamiUitOpen 6:38f7dce055d0 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 6:38f7dce055d0 355 uint32_t RESERVED2[31];
MikamiUitOpen 6:38f7dce055d0 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 6:38f7dce055d0 357 uint32_t RESERVED3[31];
MikamiUitOpen 6:38f7dce055d0 358 uint32_t RESERVED4[64];
MikamiUitOpen 6:38f7dce055d0 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
MikamiUitOpen 6:38f7dce055d0 360 } NVIC_Type;
MikamiUitOpen 6:38f7dce055d0 361
MikamiUitOpen 6:38f7dce055d0 362 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 6:38f7dce055d0 363
MikamiUitOpen 6:38f7dce055d0 364
MikamiUitOpen 6:38f7dce055d0 365 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 366 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 6:38f7dce055d0 367 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 6:38f7dce055d0 368 @{
MikamiUitOpen 6:38f7dce055d0 369 */
MikamiUitOpen 6:38f7dce055d0 370
MikamiUitOpen 6:38f7dce055d0 371 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 6:38f7dce055d0 372 */
MikamiUitOpen 6:38f7dce055d0 373 typedef struct
MikamiUitOpen 6:38f7dce055d0 374 {
MikamiUitOpen 6:38f7dce055d0 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 6:38f7dce055d0 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 6:38f7dce055d0 377 #if (__VTOR_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
MikamiUitOpen 6:38f7dce055d0 379 #else
MikamiUitOpen 6:38f7dce055d0 380 uint32_t RESERVED0;
MikamiUitOpen 6:38f7dce055d0 381 #endif
MikamiUitOpen 6:38f7dce055d0 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 6:38f7dce055d0 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 6:38f7dce055d0 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 6:38f7dce055d0 385 uint32_t RESERVED1;
MikamiUitOpen 6:38f7dce055d0 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
MikamiUitOpen 6:38f7dce055d0 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 6:38f7dce055d0 388 } SCB_Type;
MikamiUitOpen 6:38f7dce055d0 389
MikamiUitOpen 6:38f7dce055d0 390 /* SCB CPUID Register Definitions */
MikamiUitOpen 6:38f7dce055d0 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 6:38f7dce055d0 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 6:38f7dce055d0 393
MikamiUitOpen 6:38f7dce055d0 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 6:38f7dce055d0 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 6:38f7dce055d0 396
MikamiUitOpen 6:38f7dce055d0 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 6:38f7dce055d0 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 6:38f7dce055d0 399
MikamiUitOpen 6:38f7dce055d0 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 6:38f7dce055d0 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 6:38f7dce055d0 402
MikamiUitOpen 6:38f7dce055d0 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 6:38f7dce055d0 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 6:38f7dce055d0 405
MikamiUitOpen 6:38f7dce055d0 406 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 6:38f7dce055d0 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 6:38f7dce055d0 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 6:38f7dce055d0 409
MikamiUitOpen 6:38f7dce055d0 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 6:38f7dce055d0 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 6:38f7dce055d0 412
MikamiUitOpen 6:38f7dce055d0 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 6:38f7dce055d0 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 6:38f7dce055d0 415
MikamiUitOpen 6:38f7dce055d0 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 6:38f7dce055d0 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 6:38f7dce055d0 418
MikamiUitOpen 6:38f7dce055d0 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 6:38f7dce055d0 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 6:38f7dce055d0 421
MikamiUitOpen 6:38f7dce055d0 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 6:38f7dce055d0 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 6:38f7dce055d0 424
MikamiUitOpen 6:38f7dce055d0 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 6:38f7dce055d0 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 6:38f7dce055d0 427
MikamiUitOpen 6:38f7dce055d0 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 6:38f7dce055d0 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 6:38f7dce055d0 430
MikamiUitOpen 6:38f7dce055d0 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 6:38f7dce055d0 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 6:38f7dce055d0 433
MikamiUitOpen 6:38f7dce055d0 434 #if (__VTOR_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 435 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 6:38f7dce055d0 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 6:38f7dce055d0 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 6:38f7dce055d0 438 #endif
MikamiUitOpen 6:38f7dce055d0 439
MikamiUitOpen 6:38f7dce055d0 440 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 6:38f7dce055d0 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 6:38f7dce055d0 443
MikamiUitOpen 6:38f7dce055d0 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 6:38f7dce055d0 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 6:38f7dce055d0 446
MikamiUitOpen 6:38f7dce055d0 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 6:38f7dce055d0 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 6:38f7dce055d0 449
MikamiUitOpen 6:38f7dce055d0 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 6:38f7dce055d0 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 6:38f7dce055d0 452
MikamiUitOpen 6:38f7dce055d0 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 6:38f7dce055d0 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 6:38f7dce055d0 455
MikamiUitOpen 6:38f7dce055d0 456 /* SCB System Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 6:38f7dce055d0 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 6:38f7dce055d0 459
MikamiUitOpen 6:38f7dce055d0 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 6:38f7dce055d0 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 6:38f7dce055d0 462
MikamiUitOpen 6:38f7dce055d0 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 6:38f7dce055d0 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 6:38f7dce055d0 465
MikamiUitOpen 6:38f7dce055d0 466 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 6:38f7dce055d0 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 6:38f7dce055d0 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 6:38f7dce055d0 469
MikamiUitOpen 6:38f7dce055d0 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 6:38f7dce055d0 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 6:38f7dce055d0 472
MikamiUitOpen 6:38f7dce055d0 473 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 6:38f7dce055d0 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 6:38f7dce055d0 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 6:38f7dce055d0 476
MikamiUitOpen 6:38f7dce055d0 477 /*@} end of group CMSIS_SCB */
MikamiUitOpen 6:38f7dce055d0 478
MikamiUitOpen 6:38f7dce055d0 479
MikamiUitOpen 6:38f7dce055d0 480 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 6:38f7dce055d0 482 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 6:38f7dce055d0 483 @{
MikamiUitOpen 6:38f7dce055d0 484 */
MikamiUitOpen 6:38f7dce055d0 485
MikamiUitOpen 6:38f7dce055d0 486 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 6:38f7dce055d0 487 */
MikamiUitOpen 6:38f7dce055d0 488 typedef struct
MikamiUitOpen 6:38f7dce055d0 489 {
MikamiUitOpen 6:38f7dce055d0 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 6:38f7dce055d0 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 6:38f7dce055d0 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 6:38f7dce055d0 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 6:38f7dce055d0 494 } SysTick_Type;
MikamiUitOpen 6:38f7dce055d0 495
MikamiUitOpen 6:38f7dce055d0 496 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 6:38f7dce055d0 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 6:38f7dce055d0 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 6:38f7dce055d0 499
MikamiUitOpen 6:38f7dce055d0 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 6:38f7dce055d0 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 6:38f7dce055d0 502
MikamiUitOpen 6:38f7dce055d0 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 6:38f7dce055d0 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 6:38f7dce055d0 505
MikamiUitOpen 6:38f7dce055d0 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 6:38f7dce055d0 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 6:38f7dce055d0 508
MikamiUitOpen 6:38f7dce055d0 509 /* SysTick Reload Register Definitions */
MikamiUitOpen 6:38f7dce055d0 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 6:38f7dce055d0 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 6:38f7dce055d0 512
MikamiUitOpen 6:38f7dce055d0 513 /* SysTick Current Register Definitions */
MikamiUitOpen 6:38f7dce055d0 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 6:38f7dce055d0 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 6:38f7dce055d0 516
MikamiUitOpen 6:38f7dce055d0 517 /* SysTick Calibration Register Definitions */
MikamiUitOpen 6:38f7dce055d0 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 6:38f7dce055d0 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 6:38f7dce055d0 520
MikamiUitOpen 6:38f7dce055d0 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 6:38f7dce055d0 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 6:38f7dce055d0 523
MikamiUitOpen 6:38f7dce055d0 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 6:38f7dce055d0 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 6:38f7dce055d0 526
MikamiUitOpen 6:38f7dce055d0 527 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 6:38f7dce055d0 528
MikamiUitOpen 6:38f7dce055d0 529 #if (__MPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 530 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen 6:38f7dce055d0 532 \brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen 6:38f7dce055d0 533 @{
MikamiUitOpen 6:38f7dce055d0 534 */
MikamiUitOpen 6:38f7dce055d0 535
MikamiUitOpen 6:38f7dce055d0 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen 6:38f7dce055d0 537 */
MikamiUitOpen 6:38f7dce055d0 538 typedef struct
MikamiUitOpen 6:38f7dce055d0 539 {
MikamiUitOpen 6:38f7dce055d0 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
MikamiUitOpen 6:38f7dce055d0 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
MikamiUitOpen 6:38f7dce055d0 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
MikamiUitOpen 6:38f7dce055d0 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 545 } MPU_Type;
MikamiUitOpen 6:38f7dce055d0 546
MikamiUitOpen 6:38f7dce055d0 547 /* MPU Type Register */
MikamiUitOpen 6:38f7dce055d0 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
MikamiUitOpen 6:38f7dce055d0 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
MikamiUitOpen 6:38f7dce055d0 550
MikamiUitOpen 6:38f7dce055d0 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
MikamiUitOpen 6:38f7dce055d0 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
MikamiUitOpen 6:38f7dce055d0 553
MikamiUitOpen 6:38f7dce055d0 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
MikamiUitOpen 6:38f7dce055d0 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
MikamiUitOpen 6:38f7dce055d0 556
MikamiUitOpen 6:38f7dce055d0 557 /* MPU Control Register */
MikamiUitOpen 6:38f7dce055d0 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
MikamiUitOpen 6:38f7dce055d0 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
MikamiUitOpen 6:38f7dce055d0 560
MikamiUitOpen 6:38f7dce055d0 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
MikamiUitOpen 6:38f7dce055d0 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
MikamiUitOpen 6:38f7dce055d0 563
MikamiUitOpen 6:38f7dce055d0 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
MikamiUitOpen 6:38f7dce055d0 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
MikamiUitOpen 6:38f7dce055d0 566
MikamiUitOpen 6:38f7dce055d0 567 /* MPU Region Number Register */
MikamiUitOpen 6:38f7dce055d0 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
MikamiUitOpen 6:38f7dce055d0 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
MikamiUitOpen 6:38f7dce055d0 570
MikamiUitOpen 6:38f7dce055d0 571 /* MPU Region Base Address Register */
MikamiUitOpen 6:38f7dce055d0 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
MikamiUitOpen 6:38f7dce055d0 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
MikamiUitOpen 6:38f7dce055d0 574
MikamiUitOpen 6:38f7dce055d0 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
MikamiUitOpen 6:38f7dce055d0 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
MikamiUitOpen 6:38f7dce055d0 577
MikamiUitOpen 6:38f7dce055d0 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
MikamiUitOpen 6:38f7dce055d0 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
MikamiUitOpen 6:38f7dce055d0 580
MikamiUitOpen 6:38f7dce055d0 581 /* MPU Region Attribute and Size Register */
MikamiUitOpen 6:38f7dce055d0 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
MikamiUitOpen 6:38f7dce055d0 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
MikamiUitOpen 6:38f7dce055d0 584
MikamiUitOpen 6:38f7dce055d0 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
MikamiUitOpen 6:38f7dce055d0 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
MikamiUitOpen 6:38f7dce055d0 587
MikamiUitOpen 6:38f7dce055d0 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
MikamiUitOpen 6:38f7dce055d0 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
MikamiUitOpen 6:38f7dce055d0 590
MikamiUitOpen 6:38f7dce055d0 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
MikamiUitOpen 6:38f7dce055d0 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
MikamiUitOpen 6:38f7dce055d0 593
MikamiUitOpen 6:38f7dce055d0 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
MikamiUitOpen 6:38f7dce055d0 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
MikamiUitOpen 6:38f7dce055d0 596
MikamiUitOpen 6:38f7dce055d0 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
MikamiUitOpen 6:38f7dce055d0 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
MikamiUitOpen 6:38f7dce055d0 599
MikamiUitOpen 6:38f7dce055d0 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
MikamiUitOpen 6:38f7dce055d0 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
MikamiUitOpen 6:38f7dce055d0 602
MikamiUitOpen 6:38f7dce055d0 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
MikamiUitOpen 6:38f7dce055d0 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
MikamiUitOpen 6:38f7dce055d0 605
MikamiUitOpen 6:38f7dce055d0 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
MikamiUitOpen 6:38f7dce055d0 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
MikamiUitOpen 6:38f7dce055d0 608
MikamiUitOpen 6:38f7dce055d0 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
MikamiUitOpen 6:38f7dce055d0 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
MikamiUitOpen 6:38f7dce055d0 611
MikamiUitOpen 6:38f7dce055d0 612 /*@} end of group CMSIS_MPU */
MikamiUitOpen 6:38f7dce055d0 613 #endif
MikamiUitOpen 6:38f7dce055d0 614
MikamiUitOpen 6:38f7dce055d0 615
MikamiUitOpen 6:38f7dce055d0 616 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 6:38f7dce055d0 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
MikamiUitOpen 6:38f7dce055d0 619 are only accessible over DAP and not via processor. Therefore
MikamiUitOpen 6:38f7dce055d0 620 they are not covered by the Cortex-M0 header file.
MikamiUitOpen 6:38f7dce055d0 621 @{
MikamiUitOpen 6:38f7dce055d0 622 */
MikamiUitOpen 6:38f7dce055d0 623 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 6:38f7dce055d0 624
MikamiUitOpen 6:38f7dce055d0 625
MikamiUitOpen 6:38f7dce055d0 626 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 627 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 6:38f7dce055d0 628 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 6:38f7dce055d0 629 @{
MikamiUitOpen 6:38f7dce055d0 630 */
MikamiUitOpen 6:38f7dce055d0 631
MikamiUitOpen 6:38f7dce055d0 632 /* Memory mapping of Cortex-M0+ Hardware */
MikamiUitOpen 6:38f7dce055d0 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 6:38f7dce055d0 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 6:38f7dce055d0 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 6:38f7dce055d0 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 6:38f7dce055d0 637
MikamiUitOpen 6:38f7dce055d0 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 6:38f7dce055d0 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 6:38f7dce055d0 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 6:38f7dce055d0 641
MikamiUitOpen 6:38f7dce055d0 642 #if (__MPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
MikamiUitOpen 6:38f7dce055d0 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
MikamiUitOpen 6:38f7dce055d0 645 #endif
MikamiUitOpen 6:38f7dce055d0 646
MikamiUitOpen 6:38f7dce055d0 647 /*@} */
MikamiUitOpen 6:38f7dce055d0 648
MikamiUitOpen 6:38f7dce055d0 649
MikamiUitOpen 6:38f7dce055d0 650
MikamiUitOpen 6:38f7dce055d0 651 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 652 * Hardware Abstraction Layer
MikamiUitOpen 6:38f7dce055d0 653 Core Function Interface contains:
MikamiUitOpen 6:38f7dce055d0 654 - Core NVIC Functions
MikamiUitOpen 6:38f7dce055d0 655 - Core SysTick Functions
MikamiUitOpen 6:38f7dce055d0 656 - Core Register Access Functions
MikamiUitOpen 6:38f7dce055d0 657 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 6:38f7dce055d0 659 */
MikamiUitOpen 6:38f7dce055d0 660
MikamiUitOpen 6:38f7dce055d0 661
MikamiUitOpen 6:38f7dce055d0 662
MikamiUitOpen 6:38f7dce055d0 663 /* ########################## NVIC functions #################################### */
MikamiUitOpen 6:38f7dce055d0 664 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 6:38f7dce055d0 666 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 6:38f7dce055d0 667 @{
MikamiUitOpen 6:38f7dce055d0 668 */
MikamiUitOpen 6:38f7dce055d0 669
MikamiUitOpen 6:38f7dce055d0 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
MikamiUitOpen 6:38f7dce055d0 671 /* The following MACROS handle generation of the register offset and byte masks */
MikamiUitOpen 6:38f7dce055d0 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
MikamiUitOpen 6:38f7dce055d0 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
MikamiUitOpen 6:38f7dce055d0 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
MikamiUitOpen 6:38f7dce055d0 675
MikamiUitOpen 6:38f7dce055d0 676
MikamiUitOpen 6:38f7dce055d0 677 /** \brief Enable External Interrupt
MikamiUitOpen 6:38f7dce055d0 678
MikamiUitOpen 6:38f7dce055d0 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 6:38f7dce055d0 680
MikamiUitOpen 6:38f7dce055d0 681 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 682 */
MikamiUitOpen 6:38f7dce055d0 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 684 {
MikamiUitOpen 6:38f7dce055d0 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 686 }
MikamiUitOpen 6:38f7dce055d0 687
MikamiUitOpen 6:38f7dce055d0 688
MikamiUitOpen 6:38f7dce055d0 689 /** \brief Disable External Interrupt
MikamiUitOpen 6:38f7dce055d0 690
MikamiUitOpen 6:38f7dce055d0 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 6:38f7dce055d0 692
MikamiUitOpen 6:38f7dce055d0 693 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 694 */
MikamiUitOpen 6:38f7dce055d0 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 696 {
MikamiUitOpen 6:38f7dce055d0 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 698 }
MikamiUitOpen 6:38f7dce055d0 699
MikamiUitOpen 6:38f7dce055d0 700
MikamiUitOpen 6:38f7dce055d0 701 /** \brief Get Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 702
MikamiUitOpen 6:38f7dce055d0 703 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 6:38f7dce055d0 704 for the specified interrupt.
MikamiUitOpen 6:38f7dce055d0 705
MikamiUitOpen 6:38f7dce055d0 706 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 707
MikamiUitOpen 6:38f7dce055d0 708 \return 0 Interrupt status is not pending.
MikamiUitOpen 6:38f7dce055d0 709 \return 1 Interrupt status is pending.
MikamiUitOpen 6:38f7dce055d0 710 */
MikamiUitOpen 6:38f7dce055d0 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 712 {
MikamiUitOpen 6:38f7dce055d0 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 6:38f7dce055d0 714 }
MikamiUitOpen 6:38f7dce055d0 715
MikamiUitOpen 6:38f7dce055d0 716
MikamiUitOpen 6:38f7dce055d0 717 /** \brief Set Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 718
MikamiUitOpen 6:38f7dce055d0 719 The function sets the pending bit of an external interrupt.
MikamiUitOpen 6:38f7dce055d0 720
MikamiUitOpen 6:38f7dce055d0 721 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 722 */
MikamiUitOpen 6:38f7dce055d0 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 724 {
MikamiUitOpen 6:38f7dce055d0 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 726 }
MikamiUitOpen 6:38f7dce055d0 727
MikamiUitOpen 6:38f7dce055d0 728
MikamiUitOpen 6:38f7dce055d0 729 /** \brief Clear Pending Interrupt
MikamiUitOpen 6:38f7dce055d0 730
MikamiUitOpen 6:38f7dce055d0 731 The function clears the pending bit of an external interrupt.
MikamiUitOpen 6:38f7dce055d0 732
MikamiUitOpen 6:38f7dce055d0 733 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 6:38f7dce055d0 734 */
MikamiUitOpen 6:38f7dce055d0 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 736 {
MikamiUitOpen 6:38f7dce055d0 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 6:38f7dce055d0 738 }
MikamiUitOpen 6:38f7dce055d0 739
MikamiUitOpen 6:38f7dce055d0 740
MikamiUitOpen 6:38f7dce055d0 741 /** \brief Set Interrupt Priority
MikamiUitOpen 6:38f7dce055d0 742
MikamiUitOpen 6:38f7dce055d0 743 The function sets the priority of an interrupt.
MikamiUitOpen 6:38f7dce055d0 744
MikamiUitOpen 6:38f7dce055d0 745 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 6:38f7dce055d0 746
MikamiUitOpen 6:38f7dce055d0 747 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 748 \param [in] priority Priority to set.
MikamiUitOpen 6:38f7dce055d0 749 */
MikamiUitOpen 6:38f7dce055d0 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 6:38f7dce055d0 751 {
MikamiUitOpen 6:38f7dce055d0 752 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 6:38f7dce055d0 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 6:38f7dce055d0 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 6:38f7dce055d0 755 }
MikamiUitOpen 6:38f7dce055d0 756 else {
MikamiUitOpen 6:38f7dce055d0 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 6:38f7dce055d0 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 6:38f7dce055d0 759 }
MikamiUitOpen 6:38f7dce055d0 760 }
MikamiUitOpen 6:38f7dce055d0 761
MikamiUitOpen 6:38f7dce055d0 762
MikamiUitOpen 6:38f7dce055d0 763 /** \brief Get Interrupt Priority
MikamiUitOpen 6:38f7dce055d0 764
MikamiUitOpen 6:38f7dce055d0 765 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 6:38f7dce055d0 766 number can be positive to specify an external (device specific)
MikamiUitOpen 6:38f7dce055d0 767 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 6:38f7dce055d0 768
MikamiUitOpen 6:38f7dce055d0 769
MikamiUitOpen 6:38f7dce055d0 770 \param [in] IRQn Interrupt number.
MikamiUitOpen 6:38f7dce055d0 771 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 6:38f7dce055d0 772 priority bits of the microcontroller.
MikamiUitOpen 6:38f7dce055d0 773 */
MikamiUitOpen 6:38f7dce055d0 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 6:38f7dce055d0 775 {
MikamiUitOpen 6:38f7dce055d0 776
MikamiUitOpen 6:38f7dce055d0 777 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 6:38f7dce055d0 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 6:38f7dce055d0 779 }
MikamiUitOpen 6:38f7dce055d0 780 else {
MikamiUitOpen 6:38f7dce055d0 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 6:38f7dce055d0 782 }
MikamiUitOpen 6:38f7dce055d0 783 }
MikamiUitOpen 6:38f7dce055d0 784
MikamiUitOpen 6:38f7dce055d0 785
MikamiUitOpen 6:38f7dce055d0 786 /** \brief System Reset
MikamiUitOpen 6:38f7dce055d0 787
MikamiUitOpen 6:38f7dce055d0 788 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 6:38f7dce055d0 789 */
MikamiUitOpen 6:38f7dce055d0 790 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 6:38f7dce055d0 791 {
MikamiUitOpen 6:38f7dce055d0 792 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 6:38f7dce055d0 793 buffered write are completed before reset */
MikamiUitOpen 6:38f7dce055d0 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 6:38f7dce055d0 795 SCB_AIRCR_SYSRESETREQ_Msk);
MikamiUitOpen 6:38f7dce055d0 796 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 6:38f7dce055d0 797 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 6:38f7dce055d0 798 }
MikamiUitOpen 6:38f7dce055d0 799
MikamiUitOpen 6:38f7dce055d0 800 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 6:38f7dce055d0 801
MikamiUitOpen 6:38f7dce055d0 802
MikamiUitOpen 6:38f7dce055d0 803
MikamiUitOpen 6:38f7dce055d0 804 /* ################################## SysTick function ############################################ */
MikamiUitOpen 6:38f7dce055d0 805 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 6:38f7dce055d0 807 \brief Functions that configure the System.
MikamiUitOpen 6:38f7dce055d0 808 @{
MikamiUitOpen 6:38f7dce055d0 809 */
MikamiUitOpen 6:38f7dce055d0 810
MikamiUitOpen 6:38f7dce055d0 811 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 6:38f7dce055d0 812
MikamiUitOpen 6:38f7dce055d0 813 /** \brief System Tick Configuration
MikamiUitOpen 6:38f7dce055d0 814
MikamiUitOpen 6:38f7dce055d0 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 6:38f7dce055d0 816 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 6:38f7dce055d0 817
MikamiUitOpen 6:38f7dce055d0 818 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 6:38f7dce055d0 819
MikamiUitOpen 6:38f7dce055d0 820 \return 0 Function succeeded.
MikamiUitOpen 6:38f7dce055d0 821 \return 1 Function failed.
MikamiUitOpen 6:38f7dce055d0 822
MikamiUitOpen 6:38f7dce055d0 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 6:38f7dce055d0 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 6:38f7dce055d0 825 must contain a vendor-specific implementation of this function.
MikamiUitOpen 6:38f7dce055d0 826
MikamiUitOpen 6:38f7dce055d0 827 */
MikamiUitOpen 6:38f7dce055d0 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 6:38f7dce055d0 829 {
MikamiUitOpen 6:38f7dce055d0 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
MikamiUitOpen 6:38f7dce055d0 831
MikamiUitOpen 6:38f7dce055d0 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 6:38f7dce055d0 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 6:38f7dce055d0 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 6:38f7dce055d0 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 6:38f7dce055d0 836 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 6:38f7dce055d0 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 6:38f7dce055d0 838 return (0UL); /* Function successful */
MikamiUitOpen 6:38f7dce055d0 839 }
MikamiUitOpen 6:38f7dce055d0 840
MikamiUitOpen 6:38f7dce055d0 841 #endif
MikamiUitOpen 6:38f7dce055d0 842
MikamiUitOpen 6:38f7dce055d0 843 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 6:38f7dce055d0 844
MikamiUitOpen 6:38f7dce055d0 845
MikamiUitOpen 6:38f7dce055d0 846
MikamiUitOpen 6:38f7dce055d0 847
MikamiUitOpen 6:38f7dce055d0 848 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 849 }
MikamiUitOpen 6:38f7dce055d0 850 #endif
MikamiUitOpen 6:38f7dce055d0 851
MikamiUitOpen 6:38f7dce055d0 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
MikamiUitOpen 6:38f7dce055d0 853
MikamiUitOpen 6:38f7dce055d0 854 #endif /* __CMSIS_GENERIC */