不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_ca_mmu.h@10:56f2f01df983, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:44:13 2017 +0000
Revision:
10:56f2f01df983
Parent:
6:38f7dce055d0 
11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 ;/**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 ; * @file core_ca_mmu.h
MikamiUitOpen 6:38f7dce055d0 3 ; * @brief MMU Startup File for A9_MP Device Series
MikamiUitOpen 6:38f7dce055d0 4 ; * @version V1.01
MikamiUitOpen 6:38f7dce055d0 5 ; * @date 10 Sept 2014
MikamiUitOpen 6:38f7dce055d0 6 ; *
MikamiUitOpen 6:38f7dce055d0 7 ; * @note
MikamiUitOpen 6:38f7dce055d0 8 ; *
MikamiUitOpen 6:38f7dce055d0 9 ; ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11 ;
MikamiUitOpen 6:38f7dce055d0 12 ; All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 ; Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 ; modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 ; - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 ; notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 ; - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 ; notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 ; documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 ; - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 ; to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 ; specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 ; *
MikamiUitOpen 6:38f7dce055d0 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 ; POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ; ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 38 extern "C" {
MikamiUitOpen 6:38f7dce055d0 39 #endif
MikamiUitOpen 6:38f7dce055d0 40
MikamiUitOpen 6:38f7dce055d0 41 #ifndef _MMU_FUNC_H
MikamiUitOpen 6:38f7dce055d0 42 #define _MMU_FUNC_H
MikamiUitOpen 6:38f7dce055d0 43
MikamiUitOpen 6:38f7dce055d0 44 #define SECTION_DESCRIPTOR (0x2)
MikamiUitOpen 6:38f7dce055d0 45 #define SECTION_MASK (0xFFFFFFFC)
MikamiUitOpen 6:38f7dce055d0 46
MikamiUitOpen 6:38f7dce055d0 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 6:38f7dce055d0 48 #define SECTION_B_SHIFT (2)
MikamiUitOpen 6:38f7dce055d0 49 #define SECTION_C_SHIFT (3)
MikamiUitOpen 6:38f7dce055d0 50 #define SECTION_TEX0_SHIFT (12)
MikamiUitOpen 6:38f7dce055d0 51 #define SECTION_TEX1_SHIFT (13)
MikamiUitOpen 6:38f7dce055d0 52 #define SECTION_TEX2_SHIFT (14)
MikamiUitOpen 6:38f7dce055d0 53
MikamiUitOpen 6:38f7dce055d0 54 #define SECTION_XN_MASK (0xFFFFFFEF)
MikamiUitOpen 6:38f7dce055d0 55 #define SECTION_XN_SHIFT (4)
MikamiUitOpen 6:38f7dce055d0 56
MikamiUitOpen 6:38f7dce055d0 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
MikamiUitOpen 6:38f7dce055d0 58 #define SECTION_DOMAIN_SHIFT (5)
MikamiUitOpen 6:38f7dce055d0 59
MikamiUitOpen 6:38f7dce055d0 60 #define SECTION_P_MASK (0xFFFFFDFF)
MikamiUitOpen 6:38f7dce055d0 61 #define SECTION_P_SHIFT (9)
MikamiUitOpen 6:38f7dce055d0 62
MikamiUitOpen 6:38f7dce055d0 63 #define SECTION_AP_MASK (0xFFFF73FF)
MikamiUitOpen 6:38f7dce055d0 64 #define SECTION_AP_SHIFT (10)
MikamiUitOpen 6:38f7dce055d0 65 #define SECTION_AP2_SHIFT (15)
MikamiUitOpen 6:38f7dce055d0 66
MikamiUitOpen 6:38f7dce055d0 67 #define SECTION_S_MASK (0xFFFEFFFF)
MikamiUitOpen 6:38f7dce055d0 68 #define SECTION_S_SHIFT (16)
MikamiUitOpen 6:38f7dce055d0 69
MikamiUitOpen 6:38f7dce055d0 70 #define SECTION_NG_MASK (0xFFFDFFFF)
MikamiUitOpen 6:38f7dce055d0 71 #define SECTION_NG_SHIFT (17)
MikamiUitOpen 6:38f7dce055d0 72
MikamiUitOpen 6:38f7dce055d0 73 #define SECTION_NS_MASK (0xFFF7FFFF)
MikamiUitOpen 6:38f7dce055d0 74 #define SECTION_NS_SHIFT (19)
MikamiUitOpen 6:38f7dce055d0 75
MikamiUitOpen 6:38f7dce055d0 76
MikamiUitOpen 6:38f7dce055d0 77 #define PAGE_L1_DESCRIPTOR (0x1)
MikamiUitOpen 6:38f7dce055d0 78 #define PAGE_L1_MASK (0xFFFFFFFC)
MikamiUitOpen 6:38f7dce055d0 79
MikamiUitOpen 6:38f7dce055d0 80 #define PAGE_L2_4K_DESC (0x2)
MikamiUitOpen 6:38f7dce055d0 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
MikamiUitOpen 6:38f7dce055d0 82
MikamiUitOpen 6:38f7dce055d0 83 #define PAGE_L2_64K_DESC (0x1)
MikamiUitOpen 6:38f7dce055d0 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
MikamiUitOpen 6:38f7dce055d0 85
MikamiUitOpen 6:38f7dce055d0 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
MikamiUitOpen 6:38f7dce055d0 87 #define PAGE_4K_B_SHIFT (2)
MikamiUitOpen 6:38f7dce055d0 88 #define PAGE_4K_C_SHIFT (3)
MikamiUitOpen 6:38f7dce055d0 89 #define PAGE_4K_TEX0_SHIFT (6)
MikamiUitOpen 6:38f7dce055d0 90 #define PAGE_4K_TEX1_SHIFT (7)
MikamiUitOpen 6:38f7dce055d0 91 #define PAGE_4K_TEX2_SHIFT (8)
MikamiUitOpen 6:38f7dce055d0 92
MikamiUitOpen 6:38f7dce055d0 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 6:38f7dce055d0 94 #define PAGE_64K_B_SHIFT (2)
MikamiUitOpen 6:38f7dce055d0 95 #define PAGE_64K_C_SHIFT (3)
MikamiUitOpen 6:38f7dce055d0 96 #define PAGE_64K_TEX0_SHIFT (12)
MikamiUitOpen 6:38f7dce055d0 97 #define PAGE_64K_TEX1_SHIFT (13)
MikamiUitOpen 6:38f7dce055d0 98 #define PAGE_64K_TEX2_SHIFT (14)
MikamiUitOpen 6:38f7dce055d0 99
MikamiUitOpen 6:38f7dce055d0 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
MikamiUitOpen 6:38f7dce055d0 101 #define PAGE_B_SHIFT (2)
MikamiUitOpen 6:38f7dce055d0 102 #define PAGE_C_SHIFT (3)
MikamiUitOpen 6:38f7dce055d0 103 #define PAGE_TEX_SHIFT (12)
MikamiUitOpen 6:38f7dce055d0 104
MikamiUitOpen 6:38f7dce055d0 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
MikamiUitOpen 6:38f7dce055d0 106 #define PAGE_XN_4K_SHIFT (0)
MikamiUitOpen 6:38f7dce055d0 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
MikamiUitOpen 6:38f7dce055d0 108 #define PAGE_XN_64K_SHIFT (15)
MikamiUitOpen 6:38f7dce055d0 109
MikamiUitOpen 6:38f7dce055d0 110
MikamiUitOpen 6:38f7dce055d0 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
MikamiUitOpen 6:38f7dce055d0 112 #define PAGE_DOMAIN_SHIFT (5)
MikamiUitOpen 6:38f7dce055d0 113
MikamiUitOpen 6:38f7dce055d0 114 #define PAGE_P_MASK (0xFFFFFDFF)
MikamiUitOpen 6:38f7dce055d0 115 #define PAGE_P_SHIFT (9)
MikamiUitOpen 6:38f7dce055d0 116
MikamiUitOpen 6:38f7dce055d0 117 #define PAGE_AP_MASK (0xFFFFFDCF)
MikamiUitOpen 6:38f7dce055d0 118 #define PAGE_AP_SHIFT (4)
MikamiUitOpen 6:38f7dce055d0 119 #define PAGE_AP2_SHIFT (9)
MikamiUitOpen 6:38f7dce055d0 120
MikamiUitOpen 6:38f7dce055d0 121 #define PAGE_S_MASK (0xFFFFFBFF)
MikamiUitOpen 6:38f7dce055d0 122 #define PAGE_S_SHIFT (10)
MikamiUitOpen 6:38f7dce055d0 123
MikamiUitOpen 6:38f7dce055d0 124 #define PAGE_NG_MASK (0xFFFFF7FF)
MikamiUitOpen 6:38f7dce055d0 125 #define PAGE_NG_SHIFT (11)
MikamiUitOpen 6:38f7dce055d0 126
MikamiUitOpen 6:38f7dce055d0 127 #define PAGE_NS_MASK (0xFFFFFFF7)
MikamiUitOpen 6:38f7dce055d0 128 #define PAGE_NS_SHIFT (3)
MikamiUitOpen 6:38f7dce055d0 129
MikamiUitOpen 6:38f7dce055d0 130 #define OFFSET_1M (0x00100000)
MikamiUitOpen 6:38f7dce055d0 131 #define OFFSET_64K (0x00010000)
MikamiUitOpen 6:38f7dce055d0 132 #define OFFSET_4K (0x00001000)
MikamiUitOpen 6:38f7dce055d0 133
MikamiUitOpen 6:38f7dce055d0 134 #define DESCRIPTOR_FAULT (0x00000000)
MikamiUitOpen 6:38f7dce055d0 135
MikamiUitOpen 6:38f7dce055d0 136 /* ########################### MMU Function Access ########################### */
MikamiUitOpen 6:38f7dce055d0 137 /** \ingroup MMU_FunctionInterface
MikamiUitOpen 6:38f7dce055d0 138 \defgroup MMU_Functions MMU Functions Interface
MikamiUitOpen 6:38f7dce055d0 139 @{
MikamiUitOpen 6:38f7dce055d0 140 */
MikamiUitOpen 6:38f7dce055d0 141
MikamiUitOpen 6:38f7dce055d0 142 /* Attributes enumerations */
MikamiUitOpen 6:38f7dce055d0 143
MikamiUitOpen 6:38f7dce055d0 144 /* Region size attributes */
MikamiUitOpen 6:38f7dce055d0 145 typedef enum
MikamiUitOpen 6:38f7dce055d0 146 {
MikamiUitOpen 6:38f7dce055d0 147 SECTION,
MikamiUitOpen 6:38f7dce055d0 148 PAGE_4k,
MikamiUitOpen 6:38f7dce055d0 149 PAGE_64k,
MikamiUitOpen 6:38f7dce055d0 150 } mmu_region_size_Type;
MikamiUitOpen 6:38f7dce055d0 151
MikamiUitOpen 6:38f7dce055d0 152 /* Region type attributes */
MikamiUitOpen 6:38f7dce055d0 153 typedef enum
MikamiUitOpen 6:38f7dce055d0 154 {
MikamiUitOpen 6:38f7dce055d0 155 NORMAL,
MikamiUitOpen 6:38f7dce055d0 156 DEVICE,
MikamiUitOpen 6:38f7dce055d0 157 SHARED_DEVICE,
MikamiUitOpen 6:38f7dce055d0 158 NON_SHARED_DEVICE,
MikamiUitOpen 6:38f7dce055d0 159 STRONGLY_ORDERED
MikamiUitOpen 6:38f7dce055d0 160 } mmu_memory_Type;
MikamiUitOpen 6:38f7dce055d0 161
MikamiUitOpen 6:38f7dce055d0 162 /* Region cacheability attributes */
MikamiUitOpen 6:38f7dce055d0 163 typedef enum
MikamiUitOpen 6:38f7dce055d0 164 {
MikamiUitOpen 6:38f7dce055d0 165 NON_CACHEABLE,
MikamiUitOpen 6:38f7dce055d0 166 WB_WA,
MikamiUitOpen 6:38f7dce055d0 167 WT,
MikamiUitOpen 6:38f7dce055d0 168 WB_NO_WA,
MikamiUitOpen 6:38f7dce055d0 169 } mmu_cacheability_Type;
MikamiUitOpen 6:38f7dce055d0 170
MikamiUitOpen 6:38f7dce055d0 171 /* Region parity check attributes */
MikamiUitOpen 6:38f7dce055d0 172 typedef enum
MikamiUitOpen 6:38f7dce055d0 173 {
MikamiUitOpen 6:38f7dce055d0 174 ECC_DISABLED,
MikamiUitOpen 6:38f7dce055d0 175 ECC_ENABLED,
MikamiUitOpen 6:38f7dce055d0 176 } mmu_ecc_check_Type;
MikamiUitOpen 6:38f7dce055d0 177
MikamiUitOpen 6:38f7dce055d0 178 /* Region execution attributes */
MikamiUitOpen 6:38f7dce055d0 179 typedef enum
MikamiUitOpen 6:38f7dce055d0 180 {
MikamiUitOpen 6:38f7dce055d0 181 EXECUTE,
MikamiUitOpen 6:38f7dce055d0 182 NON_EXECUTE,
MikamiUitOpen 6:38f7dce055d0 183 } mmu_execute_Type;
MikamiUitOpen 6:38f7dce055d0 184
MikamiUitOpen 6:38f7dce055d0 185 /* Region global attributes */
MikamiUitOpen 6:38f7dce055d0 186 typedef enum
MikamiUitOpen 6:38f7dce055d0 187 {
MikamiUitOpen 6:38f7dce055d0 188 GLOBAL,
MikamiUitOpen 6:38f7dce055d0 189 NON_GLOBAL,
MikamiUitOpen 6:38f7dce055d0 190 } mmu_global_Type;
MikamiUitOpen 6:38f7dce055d0 191
MikamiUitOpen 6:38f7dce055d0 192 /* Region shareability attributes */
MikamiUitOpen 6:38f7dce055d0 193 typedef enum
MikamiUitOpen 6:38f7dce055d0 194 {
MikamiUitOpen 6:38f7dce055d0 195 NON_SHARED,
MikamiUitOpen 6:38f7dce055d0 196 SHARED,
MikamiUitOpen 6:38f7dce055d0 197 } mmu_shared_Type;
MikamiUitOpen 6:38f7dce055d0 198
MikamiUitOpen 6:38f7dce055d0 199 /* Region security attributes */
MikamiUitOpen 6:38f7dce055d0 200 typedef enum
MikamiUitOpen 6:38f7dce055d0 201 {
MikamiUitOpen 6:38f7dce055d0 202 SECURE,
MikamiUitOpen 6:38f7dce055d0 203 NON_SECURE,
MikamiUitOpen 6:38f7dce055d0 204 } mmu_secure_Type;
MikamiUitOpen 6:38f7dce055d0 205
MikamiUitOpen 6:38f7dce055d0 206 /* Region access attributes */
MikamiUitOpen 6:38f7dce055d0 207 typedef enum
MikamiUitOpen 6:38f7dce055d0 208 {
MikamiUitOpen 6:38f7dce055d0 209 NO_ACCESS,
MikamiUitOpen 6:38f7dce055d0 210 RW,
MikamiUitOpen 6:38f7dce055d0 211 READ,
MikamiUitOpen 6:38f7dce055d0 212 } mmu_access_Type;
MikamiUitOpen 6:38f7dce055d0 213
MikamiUitOpen 6:38f7dce055d0 214 /* Memory Region definition */
MikamiUitOpen 6:38f7dce055d0 215 typedef struct RegionStruct {
MikamiUitOpen 6:38f7dce055d0 216 mmu_region_size_Type rg_t;
MikamiUitOpen 6:38f7dce055d0 217 mmu_memory_Type mem_t;
MikamiUitOpen 6:38f7dce055d0 218 uint8_t domain;
MikamiUitOpen 6:38f7dce055d0 219 mmu_cacheability_Type inner_norm_t;
MikamiUitOpen 6:38f7dce055d0 220 mmu_cacheability_Type outer_norm_t;
MikamiUitOpen 6:38f7dce055d0 221 mmu_ecc_check_Type e_t;
MikamiUitOpen 6:38f7dce055d0 222 mmu_execute_Type xn_t;
MikamiUitOpen 6:38f7dce055d0 223 mmu_global_Type g_t;
MikamiUitOpen 6:38f7dce055d0 224 mmu_secure_Type sec_t;
MikamiUitOpen 6:38f7dce055d0 225 mmu_access_Type priv_t;
MikamiUitOpen 6:38f7dce055d0 226 mmu_access_Type user_t;
MikamiUitOpen 6:38f7dce055d0 227 mmu_shared_Type sh_t;
MikamiUitOpen 6:38f7dce055d0 228
MikamiUitOpen 6:38f7dce055d0 229 } mmu_region_attributes_Type;
MikamiUitOpen 6:38f7dce055d0 230
MikamiUitOpen 6:38f7dce055d0 231 /** \brief Set section execution-never attribute
MikamiUitOpen 6:38f7dce055d0 232
MikamiUitOpen 6:38f7dce055d0 233 The function sets section execution-never attribute
MikamiUitOpen 6:38f7dce055d0 234
MikamiUitOpen 6:38f7dce055d0 235 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
MikamiUitOpen 6:38f7dce055d0 237
MikamiUitOpen 6:38f7dce055d0 238 \return 0
MikamiUitOpen 6:38f7dce055d0 239 */
MikamiUitOpen 6:38f7dce055d0 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
MikamiUitOpen 6:38f7dce055d0 241 {
MikamiUitOpen 6:38f7dce055d0 242 *descriptor_l1 &= SECTION_XN_MASK;
MikamiUitOpen 6:38f7dce055d0 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
MikamiUitOpen 6:38f7dce055d0 244 return 0;
MikamiUitOpen 6:38f7dce055d0 245 }
MikamiUitOpen 6:38f7dce055d0 246
MikamiUitOpen 6:38f7dce055d0 247 /** \brief Set section domain
MikamiUitOpen 6:38f7dce055d0 248
MikamiUitOpen 6:38f7dce055d0 249 The function sets section domain
MikamiUitOpen 6:38f7dce055d0 250
MikamiUitOpen 6:38f7dce055d0 251 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 252 \param [in] domain Section domain
MikamiUitOpen 6:38f7dce055d0 253
MikamiUitOpen 6:38f7dce055d0 254 \return 0
MikamiUitOpen 6:38f7dce055d0 255 */
MikamiUitOpen 6:38f7dce055d0 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
MikamiUitOpen 6:38f7dce055d0 257 {
MikamiUitOpen 6:38f7dce055d0 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
MikamiUitOpen 6:38f7dce055d0 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
MikamiUitOpen 6:38f7dce055d0 260 return 0;
MikamiUitOpen 6:38f7dce055d0 261 }
MikamiUitOpen 6:38f7dce055d0 262
MikamiUitOpen 6:38f7dce055d0 263 /** \brief Set section parity check
MikamiUitOpen 6:38f7dce055d0 264
MikamiUitOpen 6:38f7dce055d0 265 The function sets section parity check
MikamiUitOpen 6:38f7dce055d0 266
MikamiUitOpen 6:38f7dce055d0 267 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
MikamiUitOpen 6:38f7dce055d0 269
MikamiUitOpen 6:38f7dce055d0 270 \return 0
MikamiUitOpen 6:38f7dce055d0 271 */
MikamiUitOpen 6:38f7dce055d0 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
MikamiUitOpen 6:38f7dce055d0 273 {
MikamiUitOpen 6:38f7dce055d0 274 *descriptor_l1 &= SECTION_P_MASK;
MikamiUitOpen 6:38f7dce055d0 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
MikamiUitOpen 6:38f7dce055d0 276 return 0;
MikamiUitOpen 6:38f7dce055d0 277 }
MikamiUitOpen 6:38f7dce055d0 278
MikamiUitOpen 6:38f7dce055d0 279 /** \brief Set section access privileges
MikamiUitOpen 6:38f7dce055d0 280
MikamiUitOpen 6:38f7dce055d0 281 The function sets section access privileges
MikamiUitOpen 6:38f7dce055d0 282
MikamiUitOpen 6:38f7dce055d0 283 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 6:38f7dce055d0 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 6:38f7dce055d0 286 \param [in] afe Access flag enable
MikamiUitOpen 6:38f7dce055d0 287
MikamiUitOpen 6:38f7dce055d0 288 \return 0
MikamiUitOpen 6:38f7dce055d0 289 */
MikamiUitOpen 6:38f7dce055d0 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
MikamiUitOpen 6:38f7dce055d0 291 {
MikamiUitOpen 6:38f7dce055d0 292 uint32_t ap = 0;
MikamiUitOpen 6:38f7dce055d0 293
MikamiUitOpen 6:38f7dce055d0 294 if (afe == 0) { //full access
MikamiUitOpen 6:38f7dce055d0 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
MikamiUitOpen 6:38f7dce055d0 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 6:38f7dce055d0 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
MikamiUitOpen 6:38f7dce055d0 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 6:38f7dce055d0 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 6:38f7dce055d0 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 6:38f7dce055d0 301 }
MikamiUitOpen 6:38f7dce055d0 302
MikamiUitOpen 6:38f7dce055d0 303 else { //Simplified access
MikamiUitOpen 6:38f7dce055d0 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 6:38f7dce055d0 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 6:38f7dce055d0 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 6:38f7dce055d0 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 6:38f7dce055d0 308 }
MikamiUitOpen 6:38f7dce055d0 309
MikamiUitOpen 6:38f7dce055d0 310 *descriptor_l1 &= SECTION_AP_MASK;
MikamiUitOpen 6:38f7dce055d0 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
MikamiUitOpen 6:38f7dce055d0 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
MikamiUitOpen 6:38f7dce055d0 313
MikamiUitOpen 6:38f7dce055d0 314 return 0;
MikamiUitOpen 6:38f7dce055d0 315 }
MikamiUitOpen 6:38f7dce055d0 316
MikamiUitOpen 6:38f7dce055d0 317 /** \brief Set section shareability
MikamiUitOpen 6:38f7dce055d0 318
MikamiUitOpen 6:38f7dce055d0 319 The function sets section shareability
MikamiUitOpen 6:38f7dce055d0 320
MikamiUitOpen 6:38f7dce055d0 321 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
MikamiUitOpen 6:38f7dce055d0 323
MikamiUitOpen 6:38f7dce055d0 324 \return 0
MikamiUitOpen 6:38f7dce055d0 325 */
MikamiUitOpen 6:38f7dce055d0 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
MikamiUitOpen 6:38f7dce055d0 327 {
MikamiUitOpen 6:38f7dce055d0 328 *descriptor_l1 &= SECTION_S_MASK;
MikamiUitOpen 6:38f7dce055d0 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
MikamiUitOpen 6:38f7dce055d0 330 return 0;
MikamiUitOpen 6:38f7dce055d0 331 }
MikamiUitOpen 6:38f7dce055d0 332
MikamiUitOpen 6:38f7dce055d0 333 /** \brief Set section Global attribute
MikamiUitOpen 6:38f7dce055d0 334
MikamiUitOpen 6:38f7dce055d0 335 The function sets section Global attribute
MikamiUitOpen 6:38f7dce055d0 336
MikamiUitOpen 6:38f7dce055d0 337 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
MikamiUitOpen 6:38f7dce055d0 339
MikamiUitOpen 6:38f7dce055d0 340 \return 0
MikamiUitOpen 6:38f7dce055d0 341 */
MikamiUitOpen 6:38f7dce055d0 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
MikamiUitOpen 6:38f7dce055d0 343 {
MikamiUitOpen 6:38f7dce055d0 344 *descriptor_l1 &= SECTION_NG_MASK;
MikamiUitOpen 6:38f7dce055d0 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
MikamiUitOpen 6:38f7dce055d0 346 return 0;
MikamiUitOpen 6:38f7dce055d0 347 }
MikamiUitOpen 6:38f7dce055d0 348
MikamiUitOpen 6:38f7dce055d0 349 /** \brief Set section Security attribute
MikamiUitOpen 6:38f7dce055d0 350
MikamiUitOpen 6:38f7dce055d0 351 The function sets section Global attribute
MikamiUitOpen 6:38f7dce055d0 352
MikamiUitOpen 6:38f7dce055d0 353 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
MikamiUitOpen 6:38f7dce055d0 355
MikamiUitOpen 6:38f7dce055d0 356 \return 0
MikamiUitOpen 6:38f7dce055d0 357 */
MikamiUitOpen 6:38f7dce055d0 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
MikamiUitOpen 6:38f7dce055d0 359 {
MikamiUitOpen 6:38f7dce055d0 360 *descriptor_l1 &= SECTION_NS_MASK;
MikamiUitOpen 6:38f7dce055d0 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
MikamiUitOpen 6:38f7dce055d0 362 return 0;
MikamiUitOpen 6:38f7dce055d0 363 }
MikamiUitOpen 6:38f7dce055d0 364
MikamiUitOpen 6:38f7dce055d0 365 /* Page 4k or 64k */
MikamiUitOpen 6:38f7dce055d0 366 /** \brief Set 4k/64k page execution-never attribute
MikamiUitOpen 6:38f7dce055d0 367
MikamiUitOpen 6:38f7dce055d0 368 The function sets 4k/64k page execution-never attribute
MikamiUitOpen 6:38f7dce055d0 369
MikamiUitOpen 6:38f7dce055d0 370 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 6:38f7dce055d0 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
MikamiUitOpen 6:38f7dce055d0 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
MikamiUitOpen 6:38f7dce055d0 373
MikamiUitOpen 6:38f7dce055d0 374 \return 0
MikamiUitOpen 6:38f7dce055d0 375 */
MikamiUitOpen 6:38f7dce055d0 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
MikamiUitOpen 6:38f7dce055d0 377 {
MikamiUitOpen 6:38f7dce055d0 378 if (page == PAGE_4k)
MikamiUitOpen 6:38f7dce055d0 379 {
MikamiUitOpen 6:38f7dce055d0 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
MikamiUitOpen 6:38f7dce055d0 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
MikamiUitOpen 6:38f7dce055d0 382 }
MikamiUitOpen 6:38f7dce055d0 383 else
MikamiUitOpen 6:38f7dce055d0 384 {
MikamiUitOpen 6:38f7dce055d0 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
MikamiUitOpen 6:38f7dce055d0 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
MikamiUitOpen 6:38f7dce055d0 387 }
MikamiUitOpen 6:38f7dce055d0 388 return 0;
MikamiUitOpen 6:38f7dce055d0 389 }
MikamiUitOpen 6:38f7dce055d0 390
MikamiUitOpen 6:38f7dce055d0 391 /** \brief Set 4k/64k page domain
MikamiUitOpen 6:38f7dce055d0 392
MikamiUitOpen 6:38f7dce055d0 393 The function sets 4k/64k page domain
MikamiUitOpen 6:38f7dce055d0 394
MikamiUitOpen 6:38f7dce055d0 395 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 396 \param [in] domain Page domain
MikamiUitOpen 6:38f7dce055d0 397
MikamiUitOpen 6:38f7dce055d0 398 \return 0
MikamiUitOpen 6:38f7dce055d0 399 */
MikamiUitOpen 6:38f7dce055d0 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
MikamiUitOpen 6:38f7dce055d0 401 {
MikamiUitOpen 6:38f7dce055d0 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
MikamiUitOpen 6:38f7dce055d0 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
MikamiUitOpen 6:38f7dce055d0 404 return 0;
MikamiUitOpen 6:38f7dce055d0 405 }
MikamiUitOpen 6:38f7dce055d0 406
MikamiUitOpen 6:38f7dce055d0 407 /** \brief Set 4k/64k page parity check
MikamiUitOpen 6:38f7dce055d0 408
MikamiUitOpen 6:38f7dce055d0 409 The function sets 4k/64k page parity check
MikamiUitOpen 6:38f7dce055d0 410
MikamiUitOpen 6:38f7dce055d0 411 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
MikamiUitOpen 6:38f7dce055d0 413
MikamiUitOpen 6:38f7dce055d0 414 \return 0
MikamiUitOpen 6:38f7dce055d0 415 */
MikamiUitOpen 6:38f7dce055d0 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
MikamiUitOpen 6:38f7dce055d0 417 {
MikamiUitOpen 6:38f7dce055d0 418 *descriptor_l1 &= SECTION_P_MASK;
MikamiUitOpen 6:38f7dce055d0 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
MikamiUitOpen 6:38f7dce055d0 420 return 0;
MikamiUitOpen 6:38f7dce055d0 421 }
MikamiUitOpen 6:38f7dce055d0 422
MikamiUitOpen 6:38f7dce055d0 423 /** \brief Set 4k/64k page access privileges
MikamiUitOpen 6:38f7dce055d0 424
MikamiUitOpen 6:38f7dce055d0 425 The function sets 4k/64k page access privileges
MikamiUitOpen 6:38f7dce055d0 426
MikamiUitOpen 6:38f7dce055d0 427 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 6:38f7dce055d0 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 6:38f7dce055d0 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
MikamiUitOpen 6:38f7dce055d0 430 \param [in] afe Access flag enable
MikamiUitOpen 6:38f7dce055d0 431
MikamiUitOpen 6:38f7dce055d0 432 \return 0
MikamiUitOpen 6:38f7dce055d0 433 */
MikamiUitOpen 6:38f7dce055d0 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
MikamiUitOpen 6:38f7dce055d0 435 {
MikamiUitOpen 6:38f7dce055d0 436 uint32_t ap = 0;
MikamiUitOpen 6:38f7dce055d0 437
MikamiUitOpen 6:38f7dce055d0 438 if (afe == 0) { //full access
MikamiUitOpen 6:38f7dce055d0 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
MikamiUitOpen 6:38f7dce055d0 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 6:38f7dce055d0 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
MikamiUitOpen 6:38f7dce055d0 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 6:38f7dce055d0 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 6:38f7dce055d0 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
MikamiUitOpen 6:38f7dce055d0 445 }
MikamiUitOpen 6:38f7dce055d0 446
MikamiUitOpen 6:38f7dce055d0 447 else { //Simplified access
MikamiUitOpen 6:38f7dce055d0 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
MikamiUitOpen 6:38f7dce055d0 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
MikamiUitOpen 6:38f7dce055d0 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
MikamiUitOpen 6:38f7dce055d0 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
MikamiUitOpen 6:38f7dce055d0 452 }
MikamiUitOpen 6:38f7dce055d0 453
MikamiUitOpen 6:38f7dce055d0 454 *descriptor_l2 &= PAGE_AP_MASK;
MikamiUitOpen 6:38f7dce055d0 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
MikamiUitOpen 6:38f7dce055d0 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
MikamiUitOpen 6:38f7dce055d0 457
MikamiUitOpen 6:38f7dce055d0 458 return 0;
MikamiUitOpen 6:38f7dce055d0 459 }
MikamiUitOpen 6:38f7dce055d0 460
MikamiUitOpen 6:38f7dce055d0 461 /** \brief Set 4k/64k page shareability
MikamiUitOpen 6:38f7dce055d0 462
MikamiUitOpen 6:38f7dce055d0 463 The function sets 4k/64k page shareability
MikamiUitOpen 6:38f7dce055d0 464
MikamiUitOpen 6:38f7dce055d0 465 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 6:38f7dce055d0 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
MikamiUitOpen 6:38f7dce055d0 467
MikamiUitOpen 6:38f7dce055d0 468 \return 0
MikamiUitOpen 6:38f7dce055d0 469 */
MikamiUitOpen 6:38f7dce055d0 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
MikamiUitOpen 6:38f7dce055d0 471 {
MikamiUitOpen 6:38f7dce055d0 472 *descriptor_l2 &= PAGE_S_MASK;
MikamiUitOpen 6:38f7dce055d0 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
MikamiUitOpen 6:38f7dce055d0 474 return 0;
MikamiUitOpen 6:38f7dce055d0 475 }
MikamiUitOpen 6:38f7dce055d0 476
MikamiUitOpen 6:38f7dce055d0 477 /** \brief Set 4k/64k page Global attribute
MikamiUitOpen 6:38f7dce055d0 478
MikamiUitOpen 6:38f7dce055d0 479 The function sets 4k/64k page Global attribute
MikamiUitOpen 6:38f7dce055d0 480
MikamiUitOpen 6:38f7dce055d0 481 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 6:38f7dce055d0 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
MikamiUitOpen 6:38f7dce055d0 483
MikamiUitOpen 6:38f7dce055d0 484 \return 0
MikamiUitOpen 6:38f7dce055d0 485 */
MikamiUitOpen 6:38f7dce055d0 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
MikamiUitOpen 6:38f7dce055d0 487 {
MikamiUitOpen 6:38f7dce055d0 488 *descriptor_l2 &= PAGE_NG_MASK;
MikamiUitOpen 6:38f7dce055d0 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
MikamiUitOpen 6:38f7dce055d0 490 return 0;
MikamiUitOpen 6:38f7dce055d0 491 }
MikamiUitOpen 6:38f7dce055d0 492
MikamiUitOpen 6:38f7dce055d0 493 /** \brief Set 4k/64k page Security attribute
MikamiUitOpen 6:38f7dce055d0 494
MikamiUitOpen 6:38f7dce055d0 495 The function sets 4k/64k page Global attribute
MikamiUitOpen 6:38f7dce055d0 496
MikamiUitOpen 6:38f7dce055d0 497 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
MikamiUitOpen 6:38f7dce055d0 499
MikamiUitOpen 6:38f7dce055d0 500 \return 0
MikamiUitOpen 6:38f7dce055d0 501 */
MikamiUitOpen 6:38f7dce055d0 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
MikamiUitOpen 6:38f7dce055d0 503 {
MikamiUitOpen 6:38f7dce055d0 504 *descriptor_l1 &= PAGE_NS_MASK;
MikamiUitOpen 6:38f7dce055d0 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
MikamiUitOpen 6:38f7dce055d0 506 return 0;
MikamiUitOpen 6:38f7dce055d0 507 }
MikamiUitOpen 6:38f7dce055d0 508
MikamiUitOpen 6:38f7dce055d0 509
MikamiUitOpen 6:38f7dce055d0 510 /** \brief Set Section memory attributes
MikamiUitOpen 6:38f7dce055d0 511
MikamiUitOpen 6:38f7dce055d0 512 The function sets section memory attributes
MikamiUitOpen 6:38f7dce055d0 513
MikamiUitOpen 6:38f7dce055d0 514 \param [out] descriptor_l1 L1 descriptor.
MikamiUitOpen 6:38f7dce055d0 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
MikamiUitOpen 6:38f7dce055d0 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 6:38f7dce055d0 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 6:38f7dce055d0 518
MikamiUitOpen 6:38f7dce055d0 519 \return 0
MikamiUitOpen 6:38f7dce055d0 520 */
MikamiUitOpen 6:38f7dce055d0 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
MikamiUitOpen 6:38f7dce055d0 522 {
MikamiUitOpen 6:38f7dce055d0 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
MikamiUitOpen 6:38f7dce055d0 524
MikamiUitOpen 6:38f7dce055d0 525 if (STRONGLY_ORDERED == mem)
MikamiUitOpen 6:38f7dce055d0 526 {
MikamiUitOpen 6:38f7dce055d0 527 return 0;
MikamiUitOpen 6:38f7dce055d0 528 }
MikamiUitOpen 6:38f7dce055d0 529 else if (SHARED_DEVICE == mem)
MikamiUitOpen 6:38f7dce055d0 530 {
MikamiUitOpen 6:38f7dce055d0 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
MikamiUitOpen 6:38f7dce055d0 532 }
MikamiUitOpen 6:38f7dce055d0 533 else if (NON_SHARED_DEVICE == mem)
MikamiUitOpen 6:38f7dce055d0 534 {
MikamiUitOpen 6:38f7dce055d0 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
MikamiUitOpen 6:38f7dce055d0 536 }
MikamiUitOpen 6:38f7dce055d0 537 else if (NORMAL == mem)
MikamiUitOpen 6:38f7dce055d0 538 {
MikamiUitOpen 6:38f7dce055d0 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
MikamiUitOpen 6:38f7dce055d0 540 switch(inner)
MikamiUitOpen 6:38f7dce055d0 541 {
MikamiUitOpen 6:38f7dce055d0 542 case NON_CACHEABLE:
MikamiUitOpen 6:38f7dce055d0 543 break;
MikamiUitOpen 6:38f7dce055d0 544 case WB_WA:
MikamiUitOpen 6:38f7dce055d0 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
MikamiUitOpen 6:38f7dce055d0 546 break;
MikamiUitOpen 6:38f7dce055d0 547 case WT:
MikamiUitOpen 6:38f7dce055d0 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
MikamiUitOpen 6:38f7dce055d0 549 break;
MikamiUitOpen 6:38f7dce055d0 550 case WB_NO_WA:
MikamiUitOpen 6:38f7dce055d0 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
MikamiUitOpen 6:38f7dce055d0 552 break;
MikamiUitOpen 6:38f7dce055d0 553 }
MikamiUitOpen 6:38f7dce055d0 554 switch(outer)
MikamiUitOpen 6:38f7dce055d0 555 {
MikamiUitOpen 6:38f7dce055d0 556 case NON_CACHEABLE:
MikamiUitOpen 6:38f7dce055d0 557 break;
MikamiUitOpen 6:38f7dce055d0 558 case WB_WA:
MikamiUitOpen 6:38f7dce055d0 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
MikamiUitOpen 6:38f7dce055d0 560 break;
MikamiUitOpen 6:38f7dce055d0 561 case WT:
MikamiUitOpen 6:38f7dce055d0 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
MikamiUitOpen 6:38f7dce055d0 563 break;
MikamiUitOpen 6:38f7dce055d0 564 case WB_NO_WA:
MikamiUitOpen 6:38f7dce055d0 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
MikamiUitOpen 6:38f7dce055d0 566 break;
MikamiUitOpen 6:38f7dce055d0 567 }
MikamiUitOpen 6:38f7dce055d0 568 }
MikamiUitOpen 6:38f7dce055d0 569
MikamiUitOpen 6:38f7dce055d0 570 return 0;
MikamiUitOpen 6:38f7dce055d0 571 }
MikamiUitOpen 6:38f7dce055d0 572
MikamiUitOpen 6:38f7dce055d0 573 /** \brief Set 4k/64k page memory attributes
MikamiUitOpen 6:38f7dce055d0 574
MikamiUitOpen 6:38f7dce055d0 575 The function sets 4k/64k page memory attributes
MikamiUitOpen 6:38f7dce055d0 576
MikamiUitOpen 6:38f7dce055d0 577 \param [out] descriptor_l2 L2 descriptor.
MikamiUitOpen 6:38f7dce055d0 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
MikamiUitOpen 6:38f7dce055d0 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 6:38f7dce055d0 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
MikamiUitOpen 6:38f7dce055d0 581
MikamiUitOpen 6:38f7dce055d0 582 \return 0
MikamiUitOpen 6:38f7dce055d0 583 */
MikamiUitOpen 6:38f7dce055d0 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
MikamiUitOpen 6:38f7dce055d0 585 {
MikamiUitOpen 6:38f7dce055d0 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
MikamiUitOpen 6:38f7dce055d0 587
MikamiUitOpen 6:38f7dce055d0 588 if (page == PAGE_64k)
MikamiUitOpen 6:38f7dce055d0 589 {
MikamiUitOpen 6:38f7dce055d0 590 //same as section
MikamiUitOpen 6:38f7dce055d0 591 __memory_section(descriptor_l2, mem, outer, inner);
MikamiUitOpen 6:38f7dce055d0 592 }
MikamiUitOpen 6:38f7dce055d0 593 else
MikamiUitOpen 6:38f7dce055d0 594 {
MikamiUitOpen 6:38f7dce055d0 595 if (STRONGLY_ORDERED == mem)
MikamiUitOpen 6:38f7dce055d0 596 {
MikamiUitOpen 6:38f7dce055d0 597 return 0;
MikamiUitOpen 6:38f7dce055d0 598 }
MikamiUitOpen 6:38f7dce055d0 599 else if (SHARED_DEVICE == mem)
MikamiUitOpen 6:38f7dce055d0 600 {
MikamiUitOpen 6:38f7dce055d0 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
MikamiUitOpen 6:38f7dce055d0 602 }
MikamiUitOpen 6:38f7dce055d0 603 else if (NON_SHARED_DEVICE == mem)
MikamiUitOpen 6:38f7dce055d0 604 {
MikamiUitOpen 6:38f7dce055d0 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
MikamiUitOpen 6:38f7dce055d0 606 }
MikamiUitOpen 6:38f7dce055d0 607 else if (NORMAL == mem)
MikamiUitOpen 6:38f7dce055d0 608 {
MikamiUitOpen 6:38f7dce055d0 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
MikamiUitOpen 6:38f7dce055d0 610 switch(inner)
MikamiUitOpen 6:38f7dce055d0 611 {
MikamiUitOpen 6:38f7dce055d0 612 case NON_CACHEABLE:
MikamiUitOpen 6:38f7dce055d0 613 break;
MikamiUitOpen 6:38f7dce055d0 614 case WB_WA:
MikamiUitOpen 6:38f7dce055d0 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
MikamiUitOpen 6:38f7dce055d0 616 break;
MikamiUitOpen 6:38f7dce055d0 617 case WT:
MikamiUitOpen 6:38f7dce055d0 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
MikamiUitOpen 6:38f7dce055d0 619 break;
MikamiUitOpen 6:38f7dce055d0 620 case WB_NO_WA:
MikamiUitOpen 6:38f7dce055d0 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
MikamiUitOpen 6:38f7dce055d0 622 break;
MikamiUitOpen 6:38f7dce055d0 623 }
MikamiUitOpen 6:38f7dce055d0 624 switch(outer)
MikamiUitOpen 6:38f7dce055d0 625 {
MikamiUitOpen 6:38f7dce055d0 626 case NON_CACHEABLE:
MikamiUitOpen 6:38f7dce055d0 627 break;
MikamiUitOpen 6:38f7dce055d0 628 case WB_WA:
MikamiUitOpen 6:38f7dce055d0 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
MikamiUitOpen 6:38f7dce055d0 630 break;
MikamiUitOpen 6:38f7dce055d0 631 case WT:
MikamiUitOpen 6:38f7dce055d0 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
MikamiUitOpen 6:38f7dce055d0 633 break;
MikamiUitOpen 6:38f7dce055d0 634 case WB_NO_WA:
MikamiUitOpen 6:38f7dce055d0 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
MikamiUitOpen 6:38f7dce055d0 636 break;
MikamiUitOpen 6:38f7dce055d0 637 }
MikamiUitOpen 6:38f7dce055d0 638 }
MikamiUitOpen 6:38f7dce055d0 639 }
MikamiUitOpen 6:38f7dce055d0 640
MikamiUitOpen 6:38f7dce055d0 641 return 0;
MikamiUitOpen 6:38f7dce055d0 642 }
MikamiUitOpen 6:38f7dce055d0 643
MikamiUitOpen 6:38f7dce055d0 644 /** \brief Create a L1 section descriptor
MikamiUitOpen 6:38f7dce055d0 645
MikamiUitOpen 6:38f7dce055d0 646 The function creates a section descriptor.
MikamiUitOpen 6:38f7dce055d0 647
MikamiUitOpen 6:38f7dce055d0 648 Assumptions:
MikamiUitOpen 6:38f7dce055d0 649 - 16MB super sections not supported
MikamiUitOpen 6:38f7dce055d0 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
MikamiUitOpen 6:38f7dce055d0 651 - Functions always return 0
MikamiUitOpen 6:38f7dce055d0 652
MikamiUitOpen 6:38f7dce055d0 653 \param [out] descriptor L1 descriptor
MikamiUitOpen 6:38f7dce055d0 654 \param [out] descriptor2 L2 descriptor
MikamiUitOpen 6:38f7dce055d0 655 \param [in] reg Section attributes
MikamiUitOpen 6:38f7dce055d0 656
MikamiUitOpen 6:38f7dce055d0 657 \return 0
MikamiUitOpen 6:38f7dce055d0 658 */
MikamiUitOpen 6:38f7dce055d0 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
MikamiUitOpen 6:38f7dce055d0 660 {
MikamiUitOpen 6:38f7dce055d0 661 *descriptor = 0;
MikamiUitOpen 6:38f7dce055d0 662
MikamiUitOpen 6:38f7dce055d0 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
MikamiUitOpen 6:38f7dce055d0 664 __xn_section(descriptor,reg.xn_t);
MikamiUitOpen 6:38f7dce055d0 665 __domain_section(descriptor, reg.domain);
MikamiUitOpen 6:38f7dce055d0 666 __p_section(descriptor, reg.e_t);
MikamiUitOpen 6:38f7dce055d0 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 6:38f7dce055d0 668 __shared_section(descriptor,reg.sh_t);
MikamiUitOpen 6:38f7dce055d0 669 __global_section(descriptor,reg.g_t);
MikamiUitOpen 6:38f7dce055d0 670 __secure_section(descriptor,reg.sec_t);
MikamiUitOpen 6:38f7dce055d0 671 *descriptor &= SECTION_MASK;
MikamiUitOpen 6:38f7dce055d0 672 *descriptor |= SECTION_DESCRIPTOR;
MikamiUitOpen 6:38f7dce055d0 673
MikamiUitOpen 6:38f7dce055d0 674 return 0;
MikamiUitOpen 6:38f7dce055d0 675
MikamiUitOpen 6:38f7dce055d0 676 }
MikamiUitOpen 6:38f7dce055d0 677
MikamiUitOpen 6:38f7dce055d0 678
MikamiUitOpen 6:38f7dce055d0 679 /** \brief Create a L1 and L2 4k/64k page descriptor
MikamiUitOpen 6:38f7dce055d0 680
MikamiUitOpen 6:38f7dce055d0 681 The function creates a 4k/64k page descriptor.
MikamiUitOpen 6:38f7dce055d0 682 Assumptions:
MikamiUitOpen 6:38f7dce055d0 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
MikamiUitOpen 6:38f7dce055d0 684 - Functions always return 0
MikamiUitOpen 6:38f7dce055d0 685
MikamiUitOpen 6:38f7dce055d0 686 \param [out] descriptor L1 descriptor
MikamiUitOpen 6:38f7dce055d0 687 \param [out] descriptor2 L2 descriptor
MikamiUitOpen 6:38f7dce055d0 688 \param [in] reg 4k/64k page attributes
MikamiUitOpen 6:38f7dce055d0 689
MikamiUitOpen 6:38f7dce055d0 690 \return 0
MikamiUitOpen 6:38f7dce055d0 691 */
MikamiUitOpen 6:38f7dce055d0 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
MikamiUitOpen 6:38f7dce055d0 693 {
MikamiUitOpen 6:38f7dce055d0 694 *descriptor = 0;
MikamiUitOpen 6:38f7dce055d0 695 *descriptor2 = 0;
MikamiUitOpen 6:38f7dce055d0 696
MikamiUitOpen 6:38f7dce055d0 697 switch (reg.rg_t)
MikamiUitOpen 6:38f7dce055d0 698 {
MikamiUitOpen 6:38f7dce055d0 699 case PAGE_4k:
MikamiUitOpen 6:38f7dce055d0 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
MikamiUitOpen 6:38f7dce055d0 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
MikamiUitOpen 6:38f7dce055d0 702 __domain_page(descriptor, reg.domain);
MikamiUitOpen 6:38f7dce055d0 703 __p_page(descriptor, reg.e_t);
MikamiUitOpen 6:38f7dce055d0 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 6:38f7dce055d0 705 __shared_page(descriptor2,reg.sh_t);
MikamiUitOpen 6:38f7dce055d0 706 __global_page(descriptor2,reg.g_t);
MikamiUitOpen 6:38f7dce055d0 707 __secure_page(descriptor,reg.sec_t);
MikamiUitOpen 6:38f7dce055d0 708 *descriptor &= PAGE_L1_MASK;
MikamiUitOpen 6:38f7dce055d0 709 *descriptor |= PAGE_L1_DESCRIPTOR;
MikamiUitOpen 6:38f7dce055d0 710 *descriptor2 &= PAGE_L2_4K_MASK;
MikamiUitOpen 6:38f7dce055d0 711 *descriptor2 |= PAGE_L2_4K_DESC;
MikamiUitOpen 6:38f7dce055d0 712 break;
MikamiUitOpen 6:38f7dce055d0 713
MikamiUitOpen 6:38f7dce055d0 714 case PAGE_64k:
MikamiUitOpen 6:38f7dce055d0 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
MikamiUitOpen 6:38f7dce055d0 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
MikamiUitOpen 6:38f7dce055d0 717 __domain_page(descriptor, reg.domain);
MikamiUitOpen 6:38f7dce055d0 718 __p_page(descriptor, reg.e_t);
MikamiUitOpen 6:38f7dce055d0 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
MikamiUitOpen 6:38f7dce055d0 720 __shared_page(descriptor2,reg.sh_t);
MikamiUitOpen 6:38f7dce055d0 721 __global_page(descriptor2,reg.g_t);
MikamiUitOpen 6:38f7dce055d0 722 __secure_page(descriptor,reg.sec_t);
MikamiUitOpen 6:38f7dce055d0 723 *descriptor &= PAGE_L1_MASK;
MikamiUitOpen 6:38f7dce055d0 724 *descriptor |= PAGE_L1_DESCRIPTOR;
MikamiUitOpen 6:38f7dce055d0 725 *descriptor2 &= PAGE_L2_64K_MASK;
MikamiUitOpen 6:38f7dce055d0 726 *descriptor2 |= PAGE_L2_64K_DESC;
MikamiUitOpen 6:38f7dce055d0 727 break;
MikamiUitOpen 6:38f7dce055d0 728
MikamiUitOpen 6:38f7dce055d0 729 case SECTION:
MikamiUitOpen 6:38f7dce055d0 730 //error
MikamiUitOpen 6:38f7dce055d0 731 break;
MikamiUitOpen 6:38f7dce055d0 732
MikamiUitOpen 6:38f7dce055d0 733 }
MikamiUitOpen 6:38f7dce055d0 734
MikamiUitOpen 6:38f7dce055d0 735 return 0;
MikamiUitOpen 6:38f7dce055d0 736
MikamiUitOpen 6:38f7dce055d0 737 }
MikamiUitOpen 6:38f7dce055d0 738
MikamiUitOpen 6:38f7dce055d0 739 /** \brief Create a 1MB Section
MikamiUitOpen 6:38f7dce055d0 740
MikamiUitOpen 6:38f7dce055d0 741 \param [in] ttb Translation table base address
MikamiUitOpen 6:38f7dce055d0 742 \param [in] base_address Section base address
MikamiUitOpen 6:38f7dce055d0 743 \param [in] count Number of sections to create
MikamiUitOpen 6:38f7dce055d0 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 6:38f7dce055d0 745
MikamiUitOpen 6:38f7dce055d0 746 */
MikamiUitOpen 6:38f7dce055d0 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
MikamiUitOpen 6:38f7dce055d0 748 {
MikamiUitOpen 6:38f7dce055d0 749 uint32_t offset;
MikamiUitOpen 6:38f7dce055d0 750 uint32_t entry;
MikamiUitOpen 6:38f7dce055d0 751 uint32_t i;
MikamiUitOpen 6:38f7dce055d0 752
MikamiUitOpen 6:38f7dce055d0 753 offset = base_address >> 20;
MikamiUitOpen 6:38f7dce055d0 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
MikamiUitOpen 6:38f7dce055d0 755
MikamiUitOpen 6:38f7dce055d0 756 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 757 ttb = ttb + offset;
MikamiUitOpen 6:38f7dce055d0 758
MikamiUitOpen 6:38f7dce055d0 759 for (i = 0; i < count; i++ )
MikamiUitOpen 6:38f7dce055d0 760 {
MikamiUitOpen 6:38f7dce055d0 761 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 762 *ttb++ = entry;
MikamiUitOpen 6:38f7dce055d0 763 entry += OFFSET_1M;
MikamiUitOpen 6:38f7dce055d0 764 }
MikamiUitOpen 6:38f7dce055d0 765 }
MikamiUitOpen 6:38f7dce055d0 766
MikamiUitOpen 6:38f7dce055d0 767 /** \brief Create a 4k page entry
MikamiUitOpen 6:38f7dce055d0 768
MikamiUitOpen 6:38f7dce055d0 769 \param [in] ttb L1 table base address
MikamiUitOpen 6:38f7dce055d0 770 \param [in] base_address 4k base address
MikamiUitOpen 6:38f7dce055d0 771 \param [in] count Number of 4k pages to create
MikamiUitOpen 6:38f7dce055d0 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 6:38f7dce055d0 773 \param [in] ttb_l2 L2 table base address
MikamiUitOpen 6:38f7dce055d0 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
MikamiUitOpen 6:38f7dce055d0 775
MikamiUitOpen 6:38f7dce055d0 776 */
MikamiUitOpen 6:38f7dce055d0 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
MikamiUitOpen 6:38f7dce055d0 778 {
MikamiUitOpen 6:38f7dce055d0 779
MikamiUitOpen 6:38f7dce055d0 780 uint32_t offset, offset2;
MikamiUitOpen 6:38f7dce055d0 781 uint32_t entry, entry2;
MikamiUitOpen 6:38f7dce055d0 782 uint32_t i;
MikamiUitOpen 6:38f7dce055d0 783
MikamiUitOpen 6:38f7dce055d0 784
MikamiUitOpen 6:38f7dce055d0 785 offset = base_address >> 20;
MikamiUitOpen 6:38f7dce055d0 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
MikamiUitOpen 6:38f7dce055d0 787
MikamiUitOpen 6:38f7dce055d0 788 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 789 ttb += offset;
MikamiUitOpen 6:38f7dce055d0 790 //create l1_entry
MikamiUitOpen 6:38f7dce055d0 791 *ttb = entry;
MikamiUitOpen 6:38f7dce055d0 792
MikamiUitOpen 6:38f7dce055d0 793 offset2 = (base_address & 0xff000) >> 12;
MikamiUitOpen 6:38f7dce055d0 794 ttb_l2 += offset2;
MikamiUitOpen 6:38f7dce055d0 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
MikamiUitOpen 6:38f7dce055d0 796 for (i = 0; i < count; i++ )
MikamiUitOpen 6:38f7dce055d0 797 {
MikamiUitOpen 6:38f7dce055d0 798 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 799 *ttb_l2++ = entry2;
MikamiUitOpen 6:38f7dce055d0 800 entry2 += OFFSET_4K;
MikamiUitOpen 6:38f7dce055d0 801 }
MikamiUitOpen 6:38f7dce055d0 802 }
MikamiUitOpen 6:38f7dce055d0 803
MikamiUitOpen 6:38f7dce055d0 804 /** \brief Create a 64k page entry
MikamiUitOpen 6:38f7dce055d0 805
MikamiUitOpen 6:38f7dce055d0 806 \param [in] ttb L1 table base address
MikamiUitOpen 6:38f7dce055d0 807 \param [in] base_address 64k base address
MikamiUitOpen 6:38f7dce055d0 808 \param [in] count Number of 64k pages to create
MikamiUitOpen 6:38f7dce055d0 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
MikamiUitOpen 6:38f7dce055d0 810 \param [in] ttb_l2 L2 table base address
MikamiUitOpen 6:38f7dce055d0 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
MikamiUitOpen 6:38f7dce055d0 812
MikamiUitOpen 6:38f7dce055d0 813 */
MikamiUitOpen 6:38f7dce055d0 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
MikamiUitOpen 6:38f7dce055d0 815 {
MikamiUitOpen 6:38f7dce055d0 816 uint32_t offset, offset2;
MikamiUitOpen 6:38f7dce055d0 817 uint32_t entry, entry2;
MikamiUitOpen 6:38f7dce055d0 818 uint32_t i,j;
MikamiUitOpen 6:38f7dce055d0 819
MikamiUitOpen 6:38f7dce055d0 820
MikamiUitOpen 6:38f7dce055d0 821 offset = base_address >> 20;
MikamiUitOpen 6:38f7dce055d0 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
MikamiUitOpen 6:38f7dce055d0 823
MikamiUitOpen 6:38f7dce055d0 824 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 825 ttb += offset;
MikamiUitOpen 6:38f7dce055d0 826 //create l1_entry
MikamiUitOpen 6:38f7dce055d0 827 *ttb = entry;
MikamiUitOpen 6:38f7dce055d0 828
MikamiUitOpen 6:38f7dce055d0 829 offset2 = (base_address & 0xff000) >> 12;
MikamiUitOpen 6:38f7dce055d0 830 ttb_l2 += offset2;
MikamiUitOpen 6:38f7dce055d0 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
MikamiUitOpen 6:38f7dce055d0 832 for (i = 0; i < count; i++ )
MikamiUitOpen 6:38f7dce055d0 833 {
MikamiUitOpen 6:38f7dce055d0 834 //create 16 entries
MikamiUitOpen 6:38f7dce055d0 835 for (j = 0; j < 16; j++)
MikamiUitOpen 6:38f7dce055d0 836 //4 bytes aligned
MikamiUitOpen 6:38f7dce055d0 837 *ttb_l2++ = entry2;
MikamiUitOpen 6:38f7dce055d0 838 entry2 += OFFSET_64K;
MikamiUitOpen 6:38f7dce055d0 839 }
MikamiUitOpen 6:38f7dce055d0 840 }
MikamiUitOpen 6:38f7dce055d0 841
MikamiUitOpen 6:38f7dce055d0 842 /*@} end of MMU_Functions */
MikamiUitOpen 6:38f7dce055d0 843 #endif
MikamiUitOpen 6:38f7dce055d0 844
MikamiUitOpen 6:38f7dce055d0 845 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 846 }
MikamiUitOpen 6:38f7dce055d0 847 #endif