不韋 呂 / F746_AcousticEffector_MIC

Audio singal input and output example for DISCO-F746. Input: MEMS mic, Output: CN10 OUT, Acoustic effect: echo and frequency shift. DISCO-F746 によるオーディオ信号入出力．入力：MEMS マイク，出力：CN10 OUT，音響効果：エコー，周波数変換．

Dependencies:   F746_GUI F746_SAI_IO

mbed_src_STM32F7/targets/cmsis/core_ca9.h@6:38f7dce055d0, 2016-10-02 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Oct 02 10:44:58 2016 +0000
Revision:
6:38f7dce055d0
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 6:38f7dce055d0 1 /**************************************************************************//**
MikamiUitOpen 6:38f7dce055d0 2 * @file core_ca9.h
MikamiUitOpen 6:38f7dce055d0 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
MikamiUitOpen 6:38f7dce055d0 4 * @version
MikamiUitOpen 6:38f7dce055d0 5 * @date 25 March 2013
MikamiUitOpen 6:38f7dce055d0 6 *
MikamiUitOpen 6:38f7dce055d0 7 * @note
MikamiUitOpen 6:38f7dce055d0 8 *
MikamiUitOpen 6:38f7dce055d0 9 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
MikamiUitOpen 6:38f7dce055d0 11
MikamiUitOpen 6:38f7dce055d0 12 All rights reserved.
MikamiUitOpen 6:38f7dce055d0 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 6:38f7dce055d0 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 6:38f7dce055d0 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 6:38f7dce055d0 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 6:38f7dce055d0 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 6:38f7dce055d0 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 6:38f7dce055d0 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 6:38f7dce055d0 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 6:38f7dce055d0 21 to endorse or promote products derived from this software without
MikamiUitOpen 6:38f7dce055d0 22 specific prior written permission.
MikamiUitOpen 6:38f7dce055d0 23 *
MikamiUitOpen 6:38f7dce055d0 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 6:38f7dce055d0 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 6:38f7dce055d0 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 6:38f7dce055d0 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 6:38f7dce055d0 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 6:38f7dce055d0 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 6:38f7dce055d0 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 6:38f7dce055d0 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 6:38f7dce055d0 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 6:38f7dce055d0 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 6:38f7dce055d0 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 6:38f7dce055d0 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 6:38f7dce055d0 36
MikamiUitOpen 6:38f7dce055d0 37
MikamiUitOpen 6:38f7dce055d0 38 #if defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 6:38f7dce055d0 40 #endif
MikamiUitOpen 6:38f7dce055d0 41
MikamiUitOpen 6:38f7dce055d0 42 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 43 extern "C" {
MikamiUitOpen 6:38f7dce055d0 44 #endif
MikamiUitOpen 6:38f7dce055d0 45
MikamiUitOpen 6:38f7dce055d0 46 #ifndef __CORE_CA9_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 47 #define __CORE_CA9_H_GENERIC
MikamiUitOpen 6:38f7dce055d0 48
MikamiUitOpen 6:38f7dce055d0 49
MikamiUitOpen 6:38f7dce055d0 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 6:38f7dce055d0 51 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 6:38f7dce055d0 52
MikamiUitOpen 6:38f7dce055d0 53 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 6:38f7dce055d0 54 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 6:38f7dce055d0 55
MikamiUitOpen 6:38f7dce055d0 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 6:38f7dce055d0 57 Unions are used for effective representation of core registers.
MikamiUitOpen 6:38f7dce055d0 58
MikamiUitOpen 6:38f7dce055d0 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 6:38f7dce055d0 60 Function-like macros are used to allow more efficient code.
MikamiUitOpen 6:38f7dce055d0 61 */
MikamiUitOpen 6:38f7dce055d0 62
MikamiUitOpen 6:38f7dce055d0 63
MikamiUitOpen 6:38f7dce055d0 64 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 65 * CMSIS definitions
MikamiUitOpen 6:38f7dce055d0 66 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 67 /** \ingroup Cortex_A9
MikamiUitOpen 6:38f7dce055d0 68 @{
MikamiUitOpen 6:38f7dce055d0 69 */
MikamiUitOpen 6:38f7dce055d0 70
MikamiUitOpen 6:38f7dce055d0 71 /* CMSIS CA9 definitions */
MikamiUitOpen 6:38f7dce055d0 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 6:38f7dce055d0 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 6:38f7dce055d0 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 6:38f7dce055d0 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 6:38f7dce055d0 76
MikamiUitOpen 6:38f7dce055d0 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
MikamiUitOpen 6:38f7dce055d0 78
MikamiUitOpen 6:38f7dce055d0 79
MikamiUitOpen 6:38f7dce055d0 80 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 6:38f7dce055d0 83 #define __STATIC_INLINE static __inline
MikamiUitOpen 6:38f7dce055d0 84 #define __STATIC_ASM static __asm
MikamiUitOpen 6:38f7dce055d0 85
MikamiUitOpen 6:38f7dce055d0 86 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 6:38f7dce055d0 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 6:38f7dce055d0 89 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 90 #define __STATIC_ASM static __asm
MikamiUitOpen 6:38f7dce055d0 91
MikamiUitOpen 6:38f7dce055d0 92 #include <stdint.h>
MikamiUitOpen 6:38f7dce055d0 93 inline uint32_t __get_PSR(void) {
MikamiUitOpen 6:38f7dce055d0 94 __ASM("mrs r0, cpsr");
MikamiUitOpen 6:38f7dce055d0 95 }
MikamiUitOpen 6:38f7dce055d0 96
MikamiUitOpen 6:38f7dce055d0 97 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 6:38f7dce055d0 99 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 100 #define __STATIC_ASM static __asm
MikamiUitOpen 6:38f7dce055d0 101
MikamiUitOpen 6:38f7dce055d0 102 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 6:38f7dce055d0 105 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 106 #define __STATIC_ASM static __asm
MikamiUitOpen 6:38f7dce055d0 107
MikamiUitOpen 6:38f7dce055d0 108 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 6:38f7dce055d0 111 #define __STATIC_INLINE static inline
MikamiUitOpen 6:38f7dce055d0 112 #define __STATIC_ASM static __asm
MikamiUitOpen 6:38f7dce055d0 113
MikamiUitOpen 6:38f7dce055d0 114 #endif
MikamiUitOpen 6:38f7dce055d0 115
MikamiUitOpen 6:38f7dce055d0 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MikamiUitOpen 6:38f7dce055d0 117 */
MikamiUitOpen 6:38f7dce055d0 118 #if defined ( __CC_ARM )
MikamiUitOpen 6:38f7dce055d0 119 #if defined __TARGET_FPU_VFP
MikamiUitOpen 6:38f7dce055d0 120 #if (__FPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 121 #define __FPU_USED 1
MikamiUitOpen 6:38f7dce055d0 122 #else
MikamiUitOpen 6:38f7dce055d0 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 124 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 125 #endif
MikamiUitOpen 6:38f7dce055d0 126 #else
MikamiUitOpen 6:38f7dce055d0 127 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 128 #endif
MikamiUitOpen 6:38f7dce055d0 129
MikamiUitOpen 6:38f7dce055d0 130 #elif defined ( __ICCARM__ )
MikamiUitOpen 6:38f7dce055d0 131 #if defined __ARMVFP__
MikamiUitOpen 6:38f7dce055d0 132 #if (__FPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 133 #define __FPU_USED 1
MikamiUitOpen 6:38f7dce055d0 134 #else
MikamiUitOpen 6:38f7dce055d0 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 136 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 137 #endif
MikamiUitOpen 6:38f7dce055d0 138 #else
MikamiUitOpen 6:38f7dce055d0 139 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 140 #endif
MikamiUitOpen 6:38f7dce055d0 141
MikamiUitOpen 6:38f7dce055d0 142 #elif defined ( __TMS470__ )
MikamiUitOpen 6:38f7dce055d0 143 #if defined __TI_VFP_SUPPORT__
MikamiUitOpen 6:38f7dce055d0 144 #if (__FPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 145 #define __FPU_USED 1
MikamiUitOpen 6:38f7dce055d0 146 #else
MikamiUitOpen 6:38f7dce055d0 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 148 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 149 #endif
MikamiUitOpen 6:38f7dce055d0 150 #else
MikamiUitOpen 6:38f7dce055d0 151 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 152 #endif
MikamiUitOpen 6:38f7dce055d0 153
MikamiUitOpen 6:38f7dce055d0 154 #elif defined ( __GNUC__ )
MikamiUitOpen 6:38f7dce055d0 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 6:38f7dce055d0 156 #if (__FPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 157 #define __FPU_USED 1
MikamiUitOpen 6:38f7dce055d0 158 #else
MikamiUitOpen 6:38f7dce055d0 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 160 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 161 #endif
MikamiUitOpen 6:38f7dce055d0 162 #else
MikamiUitOpen 6:38f7dce055d0 163 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 164 #endif
MikamiUitOpen 6:38f7dce055d0 165
MikamiUitOpen 6:38f7dce055d0 166 #elif defined ( __TASKING__ )
MikamiUitOpen 6:38f7dce055d0 167 #if defined __FPU_VFP__
MikamiUitOpen 6:38f7dce055d0 168 #if (__FPU_PRESENT == 1)
MikamiUitOpen 6:38f7dce055d0 169 #define __FPU_USED 1
MikamiUitOpen 6:38f7dce055d0 170 #else
MikamiUitOpen 6:38f7dce055d0 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 6:38f7dce055d0 172 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 173 #endif
MikamiUitOpen 6:38f7dce055d0 174 #else
MikamiUitOpen 6:38f7dce055d0 175 #define __FPU_USED 0
MikamiUitOpen 6:38f7dce055d0 176 #endif
MikamiUitOpen 6:38f7dce055d0 177 #endif
MikamiUitOpen 6:38f7dce055d0 178
MikamiUitOpen 6:38f7dce055d0 179 #include <stdint.h> /*!< standard types definitions */
MikamiUitOpen 6:38f7dce055d0 180 #include "core_caInstr.h" /*!< Core Instruction Access */
MikamiUitOpen 6:38f7dce055d0 181 #include "core_caFunc.h" /*!< Core Function Access */
MikamiUitOpen 6:38f7dce055d0 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
MikamiUitOpen 6:38f7dce055d0 183
MikamiUitOpen 6:38f7dce055d0 184 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 6:38f7dce055d0 185
MikamiUitOpen 6:38f7dce055d0 186 #ifndef __CMSIS_GENERIC
MikamiUitOpen 6:38f7dce055d0 187
MikamiUitOpen 6:38f7dce055d0 188 #ifndef __CORE_CA9_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 189 #define __CORE_CA9_H_DEPENDANT
MikamiUitOpen 6:38f7dce055d0 190
MikamiUitOpen 6:38f7dce055d0 191 /* check device defines and use defaults */
MikamiUitOpen 6:38f7dce055d0 192 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 6:38f7dce055d0 193 #ifndef __CA9_REV
MikamiUitOpen 6:38f7dce055d0 194 #define __CA9_REV 0x0000
MikamiUitOpen 6:38f7dce055d0 195 #warning "__CA9_REV not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 196 #endif
MikamiUitOpen 6:38f7dce055d0 197
MikamiUitOpen 6:38f7dce055d0 198 #ifndef __FPU_PRESENT
MikamiUitOpen 6:38f7dce055d0 199 #define __FPU_PRESENT 1
MikamiUitOpen 6:38f7dce055d0 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 6:38f7dce055d0 201 #endif
MikamiUitOpen 6:38f7dce055d0 202
MikamiUitOpen 6:38f7dce055d0 203 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 6:38f7dce055d0 204 #define __Vendor_SysTickConfig 1
MikamiUitOpen 6:38f7dce055d0 205 #endif
MikamiUitOpen 6:38f7dce055d0 206
MikamiUitOpen 6:38f7dce055d0 207 #if __Vendor_SysTickConfig == 0
MikamiUitOpen 6:38f7dce055d0 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
MikamiUitOpen 6:38f7dce055d0 209 #endif
MikamiUitOpen 6:38f7dce055d0 210 #endif
MikamiUitOpen 6:38f7dce055d0 211
MikamiUitOpen 6:38f7dce055d0 212 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 6:38f7dce055d0 213 /**
MikamiUitOpen 6:38f7dce055d0 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 6:38f7dce055d0 215
MikamiUitOpen 6:38f7dce055d0 216 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 6:38f7dce055d0 217 \li to specify the access to peripheral variables.
MikamiUitOpen 6:38f7dce055d0 218 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 6:38f7dce055d0 219 */
MikamiUitOpen 6:38f7dce055d0 220 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 221 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 222 #else
MikamiUitOpen 6:38f7dce055d0 223 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 6:38f7dce055d0 224 #endif
MikamiUitOpen 6:38f7dce055d0 225 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 6:38f7dce055d0 226 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 6:38f7dce055d0 227
MikamiUitOpen 6:38f7dce055d0 228 /*@} end of group Cortex_A9 */
MikamiUitOpen 6:38f7dce055d0 229
MikamiUitOpen 6:38f7dce055d0 230
MikamiUitOpen 6:38f7dce055d0 231 /*******************************************************************************
MikamiUitOpen 6:38f7dce055d0 232 * Register Abstraction
MikamiUitOpen 6:38f7dce055d0 233 ******************************************************************************/
MikamiUitOpen 6:38f7dce055d0 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 6:38f7dce055d0 235 \brief Type definitions and defines for Cortex-A processor based devices.
MikamiUitOpen 6:38f7dce055d0 236 */
MikamiUitOpen 6:38f7dce055d0 237
MikamiUitOpen 6:38f7dce055d0 238 /** \ingroup CMSIS_core_register
MikamiUitOpen 6:38f7dce055d0 239 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 6:38f7dce055d0 240 \brief Core Register type definitions.
MikamiUitOpen 6:38f7dce055d0 241 @{
MikamiUitOpen 6:38f7dce055d0 242 */
MikamiUitOpen 6:38f7dce055d0 243
MikamiUitOpen 6:38f7dce055d0 244 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 6:38f7dce055d0 245 */
MikamiUitOpen 6:38f7dce055d0 246 typedef union
MikamiUitOpen 6:38f7dce055d0 247 {
MikamiUitOpen 6:38f7dce055d0 248 struct
MikamiUitOpen 6:38f7dce055d0 249 {
MikamiUitOpen 6:38f7dce055d0 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
MikamiUitOpen 6:38f7dce055d0 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
MikamiUitOpen 6:38f7dce055d0 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
MikamiUitOpen 6:38f7dce055d0 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
MikamiUitOpen 6:38f7dce055d0 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 6:38f7dce055d0 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 6:38f7dce055d0 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 6:38f7dce055d0 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 6:38f7dce055d0 258 } b; /*!< Structure used for bit access */
MikamiUitOpen 6:38f7dce055d0 259 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 6:38f7dce055d0 260 } APSR_Type;
MikamiUitOpen 6:38f7dce055d0 261
MikamiUitOpen 6:38f7dce055d0 262
MikamiUitOpen 6:38f7dce055d0 263 /*@} end of group CMSIS_CORE */
MikamiUitOpen 6:38f7dce055d0 264
MikamiUitOpen 6:38f7dce055d0 265 /*@} end of CMSIS_Core_FPUFunctions */
MikamiUitOpen 6:38f7dce055d0 266
MikamiUitOpen 6:38f7dce055d0 267
MikamiUitOpen 6:38f7dce055d0 268 #endif /* __CORE_CA9_H_GENERIC */
MikamiUitOpen 6:38f7dce055d0 269
MikamiUitOpen 6:38f7dce055d0 270 #endif /* __CMSIS_GENERIC */
MikamiUitOpen 6:38f7dce055d0 271
MikamiUitOpen 6:38f7dce055d0 272 #ifdef __cplusplus
MikamiUitOpen 6:38f7dce055d0 273 }
MikamiUitOpen 6:38f7dce055d0 274
MikamiUitOpen 6:38f7dce055d0 275
MikamiUitOpen 6:38f7dce055d0 276 #endif