stm32f30x_tim.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the TIM peripheral:
00009   *            + TimeBase management
00010   *            + Output Compare management
00011   *            + Input Capture management
00012   *            + Advanced-control timers (TIM1 and TIM8) specific features  
00013   *            + Interrupts, DMA and flags management
00014   *            + Clocks management
00015   *            + Synchronization management
00016   *            + Specific interface management
00017   *            + Specific remapping management      
00018   *              
00019   @verbatim
00020     
00021   ==============================================================================
00022                        ##### How to use this driver #####
00023   ==============================================================================
00024    [..] This driver provides functions to configure and program the TIM 
00025         of all stm32f30x devices.
00026         These functions are split in 9 groups: 
00027      
00028         (#) TIM TimeBase management: this group includes all needed functions 
00029             to configure the TM Timebase unit:
00030                  (++) Set/Get Prescaler
00031                  (++) Set/Get Autoreload  
00032                  (++) Counter modes configuration
00033                  (++) Set Clock division  
00034                  (++) Select the One Pulse mode
00035                  (++) Update Request Configuration
00036                  (++) Update Disable Configuration
00037                  (++) Auto-Preload Configuration 
00038                  (++) Enable/Disable the counter     
00039                    
00040        (#) TIM Output Compare management: this group includes all needed 
00041            functions to configure the Capture/Compare unit used in Output 
00042            compare mode: 
00043                  (++) Configure each channel, independently, in Output Compare mode
00044                  (++) Select the output compare modes
00045                  (++) Select the Polarities of each channel
00046                  (++) Set/Get the Capture/Compare register values
00047                  (++) Select the Output Compare Fast mode 
00048                  (++) Select the Output Compare Forced mode  
00049                  (++) Output Compare-Preload Configuration 
00050                  (++) Clear Output Compare Reference
00051                  (++) Select the OCREF Clear signal
00052                  (++) Enable/Disable the Capture/Compare Channels    
00053                     
00054         (#) TIM Input Capture management: this group includes all needed 
00055             functions to configure the Capture/Compare unit used in 
00056             Input Capture mode:
00057                  (++) Configure each channel in input capture mode
00058                  (++) Configure Channel1/2 in PWM Input mode
00059                  (++) Set the Input Capture Prescaler
00060                  (++) Get the Capture/Compare values      
00061                      
00062         (#) Advanced-control timers (TIM1 and TIM8) specific features
00063                  (++) Configures the Break input, dead time, Lock level, the OSSI,
00064                       the OSSR State and the AOE(automatic output enable)
00065                  (++) Enable/Disable the TIM peripheral Main Outputs
00066                  (++) Select the Commutation event
00067                  (++) Set/Reset the Capture Compare Preload Control bit
00068                                
00069         (#) TIM interrupts, DMA and flags management
00070                  (++) Enable/Disable interrupt sources
00071                  (++) Get flags status
00072                  (++) Clear flags/ Pending bits
00073                  (++) Enable/Disable DMA requests 
00074                  (++) Configure DMA burst mode
00075                  (++) Select CaptureCompare DMA request  
00076                 
00077         (#) TIM clocks management: this group includes all needed functions 
00078             to configure the clock controller unit:
00079                  (++) Select internal/External clock
00080                  (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
00081          
00082         (#) TIM synchronization management: this group includes all needed 
00083             functions to configure the Synchronization unit:
00084                  (++) Select Input Trigger  
00085                  (++) Select Output Trigger  
00086                  (++) Select Master Slave Mode 
00087                  (++) ETR Configuration when used as external trigger   
00088        
00089         (#) TIM specific interface management, this group includes all 
00090             needed functions to use the specific TIM interface:
00091                  (++) Encoder Interface Configuration
00092                  (++) Select Hall Sensor   
00093            
00094         (#) TIM specific remapping management includes the Remapping 
00095             configuration of specific timers               
00096      
00097   @endverbatim
00098       
00099   ******************************************************************************
00100   * @attention
00101   *
00102   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00103   *
00104   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00105   * You may not use this file except in compliance with the License.
00106   * You may obtain a copy of the License at:
00107   *
00108   *        http://www.st.com/software_license_agreement_liberty_v2
00109   *
00110   * Unless required by applicable law or agreed to in writing, software 
00111   * distributed under the License is distributed on an "AS IS" BASIS, 
00112   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00113   * See the License for the specific language governing permissions and
00114   * limitations under the License.
00115   *
00116   ******************************************************************************
00117   */
00118 
00119 /* Includes ------------------------------------------------------------------*/
00120 #include "stm32f30x_tim.h"
00121 #include "stm32f30x_rcc.h"
00122 
00123 /** @addtogroup STM32F30x_StdPeriph_Driver
00124   * @{
00125   */
00126 
00127 /** @defgroup TIM 
00128   * @brief TIM driver modules
00129   * @{
00130   */
00131 
00132 /* Private typedef -----------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134 
00135 /* ---------------------- TIM registers bit mask ------------------------ */
00136 #define SMCR_ETR_MASK      ((uint16_t)0x00FF) 
00137 #define CCMR_OFFSET        ((uint16_t)0x0018)
00138 #define CCER_CCE_SET       ((uint16_t)0x0001)  
00139 #define CCER_CCNE_SET      ((uint16_t)0x0004) 
00140 #define CCMR_OC13M_MASK    ((uint32_t)0xFFFEFF8F)
00141 #define CCMR_OC24M_MASK    ((uint32_t)0xFEFF8FFF) 
00142 
00143 /* Private macro -------------------------------------------------------------*/
00144 /* Private variables ---------------------------------------------------------*/
00145 /* Private function prototypes -----------------------------------------------*/
00146 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00147                        uint16_t TIM_ICFilter);
00148 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00149                        uint16_t TIM_ICFilter);
00150 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00151                        uint16_t TIM_ICFilter);
00152 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00153                        uint16_t TIM_ICFilter);
00154 
00155 /* Private functions ---------------------------------------------------------*/
00156 
00157 /** @defgroup TIM_Private_Functions
00158   * @{
00159   */
00160 
00161 /** @defgroup TIM_Group1 TimeBase management functions
00162  *  @brief   TimeBase management functions 
00163  *
00164 @verbatim   
00165  ===============================================================================
00166                    ##### TimeBase management functions #####
00167  ===============================================================================  
00168   
00169              
00170     *** TIM Driver: how to use it in Timing(Time base) Mode ***
00171     ============================================================ 
00172     [..]
00173     To use the Timer in Timing(Time base) mode, the following steps are mandatory:
00174        
00175     (#) Enable TIM clock using 
00176         RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function               
00177     (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.   
00178     (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure 
00179         the Time Base unit
00180         with the corresponding configuration        
00181     (#) Enable the NVIC if you need to generate the update interrupt.        
00182     (#) Enable the corresponding interrupt using the function 
00183         TIM_ITConfig(TIMx, TIM_IT_Update)      
00184     (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
00185     [..]                  
00186     (@) All other functions can be used separately to modify, if needed,
00187         a specific feature of the Timer. 
00188 
00189 @endverbatim
00190   * @{
00191   */
00192   
00193 /**
00194   * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
00195   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16,17 or 20 to select the TIM peripheral.
00196   * @retval None
00197 
00198   */
00199 void TIM_DeInit(TIM_TypeDef* TIMx)
00200 {
00201   /* Check the parameters */
00202   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00203  
00204   if (TIMx == TIM1)
00205   {
00206     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00207     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
00208   } 
00209   else if (TIMx == TIM2) 
00210   {     
00211     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
00212     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00213   }  
00214   else if (TIMx == TIM3)
00215   { 
00216     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00217     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
00218   }  
00219   else if (TIMx == TIM4)
00220   { 
00221     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
00222     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00223   }   
00224   else if (TIMx == TIM6)  
00225   {    
00226     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
00227     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00228   }  
00229   else if (TIMx == TIM7)
00230   {      
00231     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00232     RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
00233   }  
00234   else if (TIMx == TIM8)
00235   {      
00236     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
00237     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
00238   }    
00239   else if (TIMx == TIM15)
00240   {      
00241     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
00242     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);  
00243   }  
00244   else if (TIMx == TIM16) 
00245   {       
00246     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
00247     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);  
00248   } 
00249   else if (TIMx == TIM17) 
00250   {     
00251     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
00252     RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); 
00253   }    
00254   else
00255   { 
00256     if (TIMx == TIM20) 
00257     {     
00258       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM20, ENABLE);
00259       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM20, DISABLE); 
00260     }   
00261   }
00262 }
00263 
00264 /**
00265   * @brief  Initializes the TIMx Time Base Unit peripheral according to 
00266   *         the specified parameters in the TIM_TimeBaseInitStruct.
00267   * @param  TIMx: where x can be  1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00268   * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
00269   *         that contains the configuration information for the specified TIM peripheral.
00270   * @retval None
00271   */
00272 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00273 {
00274   uint16_t tmpcr1 = 0;
00275 
00276   /* Check the parameters */
00277   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00278   assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
00279   assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
00280 
00281   tmpcr1 = TIMx->CR1;  
00282 
00283   if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || 
00284      (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM20)) 
00285   {
00286     /* Select the Counter Mode */
00287     tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
00288     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
00289   }
00290  
00291   if((TIMx != TIM6) && (TIMx != TIM7))
00292   {
00293     /* Set the clock division */
00294     tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
00295     tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
00296   }
00297 
00298   TIMx->CR1 = tmpcr1;
00299 
00300   /* Set the Autoreload value */
00301   TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
00302  
00303   /* Set the Prescaler value */
00304   TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
00305     
00306   if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) || 
00307       (TIMx == TIM16) || (TIMx == TIM17)|| (TIMx == TIM20))  
00308   {
00309     /* Set the Repetition Counter value */
00310     TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
00311   }
00312 
00313   /* Generate an update event to reload the Prescaler 
00314      and the repetition counter(only for TIM1 and TIM8) value immediately */
00315   TIMx->EGR = TIM_PSCReloadMode_Immediate;          
00316 }
00317 
00318 /**
00319   * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
00320   * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
00321   *         structure which will be initialized.
00322   * @retval None
00323   */
00324 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
00325 {
00326   /* Set the default configuration */
00327   TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
00328   TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
00329   TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
00330   TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
00331   TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
00332 }
00333 
00334 /**
00335   * @brief  Configures the TIMx Prescaler.
00336   * @param  TIMx: where x can be  1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral.
00337   * @param  Prescaler: specifies the Prescaler Register value
00338   * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
00339   *          This parameter can be one of the following values:
00340   *            @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
00341   *            @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
00342   * @retval None
00343   */
00344 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
00345 {
00346   /* Check the parameters */
00347   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00348   assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
00349   /* Set the Prescaler value */
00350   TIMx->PSC = Prescaler;
00351   /* Set or reset the UG Bit */
00352   TIMx->EGR = TIM_PSCReloadMode;
00353 }
00354 
00355 /**
00356   * @brief  Specifies the TIMx Counter Mode to be used.
00357   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
00358   * @param  TIM_CounterMode: specifies the Counter Mode to be used
00359   *          This parameter can be one of the following values:
00360   *            @arg TIM_CounterMode_Up: TIM Up Counting Mode
00361   *            @arg TIM_CounterMode_Down: TIM Down Counting Mode
00362   *            @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
00363   *            @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
00364   *            @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
00365   * @retval None
00366   */
00367 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
00368 {
00369   uint16_t tmpcr1 = 0;
00370 
00371   /* Check the parameters */
00372   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
00373   assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
00374 
00375   tmpcr1 = TIMx->CR1;
00376 
00377   /* Reset the CMS and DIR Bits */
00378   tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
00379 
00380   /* Set the Counter Mode */
00381   tmpcr1 |= TIM_CounterMode;
00382 
00383   /* Write to TIMx CR1 register */
00384   TIMx->CR1 = tmpcr1;
00385 }
00386 
00387 /**
00388   * @brief  Sets the TIMx Counter Register value
00389   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00390   * @param  Counter: specifies the Counter register new value.
00391   * @retval None
00392   */
00393 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
00394 {
00395   /* Check the parameters */
00396    assert_param(IS_TIM_ALL_PERIPH(TIMx));
00397 
00398   /* Set the Counter Register value */
00399   TIMx->CNT = Counter;
00400 }
00401 
00402 /**
00403   * @brief  Sets the TIMx Autoreload Register value
00404   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00405   * @param  Autoreload: specifies the Autoreload register new value.
00406   * @retval None
00407   */
00408 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
00409 {
00410   /* Check the parameters */
00411   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00412   
00413   /* Set the Autoreload Register value */
00414   TIMx->ARR = Autoreload;
00415 }
00416 
00417 /**
00418   * @brief  Gets the TIMx Counter value.
00419   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00420   * @retval Counter Register value
00421   */
00422 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
00423 {
00424   /* Check the parameters */
00425   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00426 
00427   /* Get the Counter Register value */
00428   return TIMx->CNT;
00429 }
00430 
00431 /**
00432   * @brief  Gets the TIMx Prescaler value.
00433   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00434   * @retval Prescaler Register value.
00435   */
00436 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
00437 {
00438   /* Check the parameters */
00439   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00440 
00441   /* Get the Prescaler Register value */
00442   return TIMx->PSC;
00443 }
00444 
00445 /**
00446   * @brief  Enables or Disables the TIMx Update event.
00447   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00448   * @param  NewState: new state of the TIMx UDIS bit
00449   *          This parameter can be: ENABLE or DISABLE.
00450   * @retval None
00451   */
00452 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
00453 {
00454   /* Check the parameters */
00455   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00456   assert_param(IS_FUNCTIONAL_STATE(NewState));
00457 
00458   if (NewState != DISABLE)
00459   {
00460     /* Set the Update Disable Bit */
00461     TIMx->CR1 |= TIM_CR1_UDIS;
00462   }
00463   else
00464   {
00465     /* Reset the Update Disable Bit */
00466     TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
00467   }
00468 }
00469 
00470 /**
00471   * @brief  Configures the TIMx Update Request Interrupt source.
00472   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00473   * @param  TIM_UpdateSource: specifies the Update source.
00474   *          This parameter can be one of the following values:
00475   *            @arg TIM_UpdateSource_Regular: Source of update is the counter
00476   *                 overflow/underflow or the setting of UG bit, or an update
00477   *                 generation through the slave mode controller.
00478   *            @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
00479   * @retval None
00480   */
00481 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00485   assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
00486 
00487   if (TIM_UpdateSource != TIM_UpdateSource_Global)
00488   {
00489     /* Set the URS Bit */
00490     TIMx->CR1 |= TIM_CR1_URS;
00491   }
00492   else
00493   {
00494     /* Reset the URS Bit */
00495     TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
00496   }
00497 }
00498 
00499 /**
00500   * @brief  Sets or resets the update interrupt flag (UIF)status bit Remapping.
00501   *         when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]  
00502   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00503   * @param  NewState: new state of the UIFREMAP bit.
00504   *          This parameter can be: ENABLE or DISABLE.
00505   * @retval None
00506   */
00507 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState)
00508 {
00509   /* Check the parameters */
00510   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00511   assert_param(IS_FUNCTIONAL_STATE(NewState));
00512   
00513   if (NewState != DISABLE)
00514   {
00515     /* Enable the TIM Counter */
00516     TIMx->CR1 |= TIM_CR1_UIFREMAP;
00517   }
00518   else
00519   {
00520     /* Disable the TIM Counter */
00521     TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP;
00522   }  
00523 }
00524 
00525 /**
00526   * @brief  Enables or disables TIMx peripheral Preload register on ARR.
00527   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00528   * @param  NewState: new state of the TIMx peripheral Preload register
00529   *          This parameter can be: ENABLE or DISABLE.
00530   * @retval None
00531   */
00532 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
00533 {
00534   /* Check the parameters */
00535   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00536   assert_param(IS_FUNCTIONAL_STATE(NewState));
00537 
00538   if (NewState != DISABLE)
00539   {
00540     /* Set the ARR Preload Bit */
00541     TIMx->CR1 |= TIM_CR1_ARPE;
00542   }
00543   else
00544   {
00545     /* Reset the ARR Preload Bit */
00546     TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
00547   }
00548 }
00549 
00550 /**
00551   * @brief  Selects the TIMx's One Pulse Mode.
00552   * @param  TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16, 17 or 20 to select the TIM peripheral.
00553   * @param  TIM_OPMode: specifies the OPM Mode to be used.
00554   *          This parameter can be one of the following values:
00555   *            @arg TIM_OPMode_Single
00556   *            @arg TIM_OPMode_Repetitive
00557   * @retval None
00558   */
00559 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
00560 {
00561   /* Check the parameters */
00562   assert_param(IS_TIM_ALL_PERIPH(TIMx));
00563   assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
00564 
00565   /* Reset the OPM Bit */
00566   TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
00567 
00568   /* Configure the OPM Mode */
00569   TIMx->CR1 |= TIM_OPMode;
00570 }
00571 
00572 /**
00573   * @brief  Sets the TIMx Clock Division value.
00574   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral.
00575   * @param  TIM_CKD: specifies the clock division value.
00576   *          This parameter can be one of the following value:
00577   *            @arg TIM_CKD_DIV1: TDTS = Tck_tim
00578   *            @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
00579   *            @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
00580   * @retval None
00581   */
00582 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
00583 {
00584   /* Check the parameters */
00585   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
00586   assert_param(IS_TIM_CKD_DIV(TIM_CKD));
00587 
00588   /* Reset the CKD Bits */
00589   TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
00590 
00591   /* Set the CKD value */
00592   TIMx->CR1 |= TIM_CKD;
00593 }
00594 
00595 /**
00596   * @brief  Enables or disables the specified TIM peripheral.
00597   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 17 and 20 to select 
00598   *        the TIMx peripheral.
00599   * @param  NewState: new state of the TIMx peripheral.
00600   *          This parameter can be: ENABLE or DISABLE.
00601   * @retval None
00602   */
00603 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
00604 {
00605   /* Check the parameters */
00606   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
00607   assert_param(IS_FUNCTIONAL_STATE(NewState));
00608   
00609   if (NewState != DISABLE)
00610   {
00611     /* Enable the TIM Counter */
00612     TIMx->CR1 |= TIM_CR1_CEN;
00613   }
00614   else
00615   {
00616     /* Disable the TIM Counter */
00617     TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
00618   }
00619 }
00620 /**
00621   * @}
00622   */
00623 
00624 /** @defgroup TIM_Group2 Output Compare management functions
00625  *  @brief    Output Compare management functions 
00626  *
00627 @verbatim   
00628  ===============================================================================
00629                 ##### Output Compare management functions #####
00630  ===============================================================================  
00631        
00632   *** TIM Driver: how to use it in Output Compare Mode ***
00633   ======================================================== 
00634   [..] 
00635   To use the Timer in Output Compare mode, the following steps are mandatory:
00636        
00637        (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
00638        
00639        (#) Configure the TIM pins by configuring the corresponding GPIO pins
00640        
00641        (#) Configure the Time base unit as described in the first part of this driver, 
00642            if needed, else the Timer will run with the default configuration:
00643            (++) Autoreload value = 0xFFFF
00644            (++) Prescaler value = 0x0000
00645            (++) Counter mode = Up counting
00646            (++) Clock Division = TIM_CKD_DIV1   
00647        (#) Fill the TIM_OCInitStruct with the desired parameters including:
00648            (++) The TIM Output Compare mode: TIM_OCMode
00649            (++) TIM Output State: TIM_OutputState
00650            (++) TIM Pulse value: TIM_Pulse
00651            (++) TIM Output Compare Polarity : TIM_OCPolarity
00652        
00653        (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the 
00654            corresponding configuration
00655        
00656        (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
00657  [..]      
00658        (@) All other functions can be used separately to modify, if needed,
00659            a specific feature of the Timer. 
00660           
00661        (@) In case of PWM mode, this function is mandatory:
00662            TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 
00663               
00664        (@) If the corresponding interrupt or DMA request are needed, the user should:
00665                 (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 
00666                 (#@) Enable the corresponding interrupt (or DMA request) using the function 
00667                      TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))   
00668 
00669 @endverbatim
00670   * @{
00671   */
00672 
00673 /**
00674   * @brief  Initializes the TIMx Channel1 according to the specified parameters in
00675   *         the TIM_OCInitStruct.
00676   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17, to select the TIM peripheral.
00677   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
00678   *         the configuration information for the specified TIM peripheral.
00679   * @retval None
00680   */
00681 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00682 {
00683   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00684    
00685   /* Check the parameters */
00686   assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
00687   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00688   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00689   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00690 
00691   /* Disable the Channel 1: Reset the CC1E Bit */
00692   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
00693   
00694   /* Get the TIMx CCER register value */
00695   tmpccer = TIMx->CCER;
00696   /* Get the TIMx CR2 register value */
00697   tmpcr2 =  TIMx->CR2;
00698   
00699   /* Get the TIMx CCMR1 register value */
00700   tmpccmrx = TIMx->CCMR1;
00701     
00702   /* Reset the Output Compare Mode Bits */
00703   tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M;
00704   tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S;
00705   /* Select the Output Compare Mode */
00706   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00707   
00708   /* Reset the Output Polarity level */
00709   tmpccer &= (uint32_t)~TIM_CCER_CC1P;
00710   /* Set the Output Compare Polarity */
00711   tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00712   
00713   /* Set the Output State */
00714   tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00715     
00716   if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
00717   {
00718     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00719     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00720     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00721     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00722     
00723     /* Reset the Output N Polarity level */
00724     tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
00725     /* Set the Output N Polarity */
00726     tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
00727     /* Reset the Output N State */
00728     tmpccer &= (uint32_t)~TIM_CCER_CC1NE;
00729     
00730     /* Set the Output N State */
00731     tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
00732     /* Reset the Output Compare and Output Compare N IDLE State */
00733     tmpcr2 &= (uint32_t)~TIM_CR2_OIS1;
00734     tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N;
00735     /* Set the Output Idle state */
00736     tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
00737     /* Set the Output N Idle state */
00738     tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
00739   }
00740   /* Write to TIMx CR2 */
00741   TIMx->CR2 = tmpcr2;
00742   
00743   /* Write to TIMx CCMR1 */
00744   TIMx->CCMR1 = tmpccmrx;
00745   
00746   /* Set the Capture Compare Register value */
00747   TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
00748   
00749   /* Write to TIMx CCER */
00750   TIMx->CCER = tmpccer;
00751 }
00752 
00753 /**
00754   * @brief  Initializes the TIMx Channel2 according to the specified parameters 
00755   *         in the TIM_OCInitStruct.
00756   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM peripheral.
00757   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
00758   *         the configuration information for the specified TIM peripheral.
00759   * @retval None
00760   */
00761 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00762 {
00763   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00764    
00765   /* Check the parameters */
00766   assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
00767   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00768   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00769   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00770 
00771   /* Disable the Channel 2: Reset the CC2E Bit */
00772   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
00773   
00774   /* Get the TIMx CCER register value */  
00775   tmpccer = TIMx->CCER;
00776   /* Get the TIMx CR2 register value */
00777   tmpcr2 =  TIMx->CR2;
00778   
00779   /* Get the TIMx CCMR1 register value */
00780   tmpccmrx = TIMx->CCMR1;
00781     
00782   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00783   tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M;
00784   tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S;
00785   
00786   /* Select the Output Compare Mode */
00787   tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00788   
00789   /* Reset the Output Polarity level */
00790   tmpccer &= (uint32_t)~TIM_CCER_CC2P;
00791   /* Set the Output Compare Polarity */
00792   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4);
00793   
00794   /* Set the Output State */
00795   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4);
00796     
00797   if((TIMx == TIM1) || (TIMx == TIM8))
00798   {
00799     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00800     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00801     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00802     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00803     
00804     /* Reset the Output N Polarity level */
00805     tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
00806     /* Set the Output N Polarity */
00807     tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4);
00808     /* Reset the Output N State */
00809     tmpccer &= (uint32_t)~TIM_CCER_CC2NE;
00810     
00811     /* Set the Output N State */
00812     tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4);
00813     /* Reset the Output Compare and Output Compare N IDLE State */
00814     tmpcr2 &= (uint32_t)~TIM_CR2_OIS2;
00815     tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N;
00816     /* Set the Output Idle state */
00817     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2);
00818     /* Set the Output N Idle state */
00819     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2);
00820   }
00821   /* Write to TIMx CR2 */
00822   TIMx->CR2 = tmpcr2;
00823   
00824   /* Write to TIMx CCMR1 */
00825   TIMx->CCMR1 = tmpccmrx;
00826   
00827   /* Set the Capture Compare Register value */
00828   TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
00829   
00830   /* Write to TIMx CCER */
00831   TIMx->CCER = tmpccer;
00832 }
00833 
00834 /**
00835   * @brief  Initializes the TIMx Channel3 according to the specified parameters
00836   *         in the TIM_OCInitStruct.
00837   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
00838   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
00839   *         the configuration information for the specified TIM peripheral.
00840   * @retval None
00841   */
00842 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00843 {
00844   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00845    
00846   /* Check the parameters */
00847   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
00848   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00849   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00850   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00851 
00852   /* Disable the Channel 3: Reset the CC2E Bit */
00853   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
00854   
00855   /* Get the TIMx CCER register value */
00856   tmpccer = TIMx->CCER;
00857   /* Get the TIMx CR2 register value */
00858   tmpcr2 =  TIMx->CR2;
00859   
00860   /* Get the TIMx CCMR2 register value */
00861   tmpccmrx = TIMx->CCMR2;
00862     
00863   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00864   tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M;
00865   tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S;  
00866   /* Select the Output Compare Mode */
00867   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00868   
00869   /* Reset the Output Polarity level */
00870   tmpccer &= (uint32_t)~TIM_CCER_CC3P;
00871   /* Set the Output Compare Polarity */
00872   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8);
00873   
00874   /* Set the Output State */
00875   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8);
00876     
00877   if((TIMx == TIM1) || (TIMx == TIM8))
00878   {
00879     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
00880     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
00881     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
00882     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00883     
00884     /* Reset the Output N Polarity level */
00885     tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
00886     /* Set the Output N Polarity */
00887     tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8);
00888     /* Reset the Output N State */
00889     tmpccer &= (uint32_t)~TIM_CCER_CC3NE;
00890     
00891     /* Set the Output N State */
00892     tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8);
00893     /* Reset the Output Compare and Output Compare N IDLE State */
00894     tmpcr2 &= (uint32_t)~TIM_CR2_OIS3;
00895     tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N;
00896     /* Set the Output Idle state */
00897     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4);
00898     /* Set the Output N Idle state */
00899     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4);
00900   }
00901   /* Write to TIMx CR2 */
00902   TIMx->CR2 = tmpcr2;
00903   
00904   /* Write to TIMx CCMR2 */
00905   TIMx->CCMR2 = tmpccmrx;
00906   
00907   /* Set the Capture Compare Register value */
00908   TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
00909   
00910   /* Write to TIMx CCER */
00911   TIMx->CCER = tmpccer;
00912 }
00913 
00914 /**
00915   * @brief  Initializes the TIMx Channel4 according to the specified parameters
00916   *         in the TIM_OCInitStruct.
00917   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
00918   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
00919   *         the configuration information for the specified TIM peripheral.
00920   * @retval None
00921   */
00922 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00923 {
00924   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00925    
00926   /* Check the parameters */
00927   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
00928   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00929   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00930   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00931 
00932   /* Disable the Channel 4: Reset the CC4E Bit */
00933   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
00934   
00935   /* Get the TIMx CCER register value */
00936   tmpccer = TIMx->CCER;
00937   /* Get the TIMx CR2 register value */
00938   tmpcr2 =  TIMx->CR2;
00939   
00940   /* Get the TIMx CCMR2 register value */
00941   tmpccmrx = TIMx->CCMR2;
00942     
00943   /* Reset the Output Compare mode and Capture/Compare selection Bits */
00944   tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M;
00945   tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S;
00946   
00947   /* Select the Output Compare Mode */
00948   tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
00949   
00950   /* Reset the Output Polarity level */
00951   tmpccer &= (uint32_t)~TIM_CCER_CC4P;
00952   /* Set the Output Compare Polarity */
00953   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12);
00954   
00955   /* Set the Output State */
00956   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12);
00957   
00958   if((TIMx == TIM1) || (TIMx == TIM8))
00959   {
00960     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
00961     /* Reset the Output Compare IDLE State */
00962     tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4;
00963     /* Set the Output Idle state */
00964     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6);
00965   }
00966   /* Write to TIMx CR2 */
00967   TIMx->CR2 = tmpcr2;
00968   
00969   /* Write to TIMx CCMR2 */  
00970   TIMx->CCMR2 = tmpccmrx;
00971     
00972   /* Set the Capture Compare Register value */
00973   TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
00974   
00975   /* Write to TIMx CCER */
00976   TIMx->CCER = tmpccer;
00977 }
00978 
00979 /**
00980   * @brief  Initializes the TIMx Channel5 according to the specified parameters
00981   *         in the TIM_OCInitStruct.
00982   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
00983   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
00984   *         the configuration information for the specified TIM peripheral.
00985   * @retval None
00986   */
00987 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
00988 {
00989   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00990    
00991   /* Check the parameters */
00992   assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
00993   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
00994   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
00995   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
00996 
00997   /* Disable the Channel 5: Reset the CC5E Bit */
00998   TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/
00999   
01000   /* Get the TIMx CCER register value */
01001   tmpccer = TIMx->CCER;
01002   /* Get the TIMx CR2 register value */
01003   tmpcr2 =  TIMx->CR2;
01004   
01005   /* Get the TIMx CCMR3 register value */
01006   tmpccmrx = TIMx->CCMR3;
01007   
01008   /* Reset the Output Compare mode and Capture/Compare selection Bits */
01009   tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M;
01010   
01011   /* Select the Output Compare Mode */
01012   tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode);
01013   
01014   /* Reset the Output Polarity level */
01015   tmpccer &= (uint32_t)~TIM_CCER_CC5P;
01016   /* Set the Output Compare Polarity */
01017   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16);
01018 
01019   /* Set the Output State */
01020   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16);
01021   
01022   if((TIMx == TIM1) || (TIMx == TIM8))
01023   {
01024     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
01025     /* Reset the Output Compare IDLE State */
01026     tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5;
01027     /* Set the Output Idle state */
01028     tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16);
01029   }
01030   /* Write to TIMx CR2 */
01031   TIMx->CR2 = tmpcr2;
01032   
01033   /* Write to TIMx CCMR2 */  
01034   TIMx->CCMR3 = tmpccmrx;
01035     
01036   /* Set the Capture Compare Register value */
01037   TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse;
01038   
01039   /* Write to TIMx CCER */
01040   TIMx->CCER = tmpccer;
01041 }
01042 
01043 /**
01044   * @brief  Initializes the TIMx Channel6 according to the specified parameters
01045   *         in the TIM_OCInitStruct.
01046   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
01047   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
01048   *         the configuration information for the specified TIM peripheral.
01049   * @retval None
01050   */
01051 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
01052 {
01053   uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
01054    
01055   /* Check the parameters */
01056   assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
01057   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
01058   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
01059   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
01060 
01061   /* Disable the Channel 5: Reset the CC5E Bit */
01062   TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/
01063   
01064   /* Get the TIMx CCER register value */
01065   tmpccer = TIMx->CCER;
01066   /* Get the TIMx CR2 register value */
01067   tmpcr2 =  TIMx->CR2;
01068   
01069   /* Get the TIMx CCMR3 register value */
01070   tmpccmrx = TIMx->CCMR3;
01071   
01072   /* Reset the Output Compare mode and Capture/Compare selection Bits */
01073   tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M;
01074   
01075   /* Select the Output Compare Mode */
01076   tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8);
01077   
01078   /* Reset the Output Polarity level */
01079   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
01080   /* Set the Output Compare Polarity */
01081   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20);
01082 
01083   /* Set the Output State */
01084   tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20);
01085   
01086   if((TIMx == TIM1) || (TIMx == TIM8))
01087   {
01088     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
01089     /* Reset the Output Compare IDLE State */
01090     tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6;
01091     /* Set the Output Idle state */
01092     tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18);
01093   }
01094   /* Write to TIMx CR2 */
01095   TIMx->CR2 = tmpcr2;
01096   
01097   /* Write to TIMx CCMR2 */  
01098   TIMx->CCMR3 = tmpccmrx;
01099     
01100   /* Set the Capture Compare Register value */
01101   TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse;
01102   
01103   /* Write to TIMx CCER */
01104   TIMx->CCER = tmpccer;
01105 }
01106 
01107 /**
01108   * @brief  Selects the TIM Group Channel 5 and Channel 1, 
01109             OC1REFC is the logical AND of OC1REFC and OC5REF.
01110   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIMx peripheral
01111   * @param  NewState: new state of the Commutation event.
01112   *          This parameter can be: ENABLE or DISABLE.
01113   * @retval None
01114   */
01115 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState)
01116 {
01117   /* Check the parameters */
01118   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01119   assert_param(IS_FUNCTIONAL_STATE(NewState));
01120 
01121   if (NewState != DISABLE)
01122   {
01123     /* Set the GC5C1 Bit */
01124     TIMx->CCR5 |= TIM_CCR5_GC5C1;
01125   }
01126   else
01127   {
01128     /* Reset the GC5C1 Bit */
01129     TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1;
01130   }
01131 }
01132 
01133 /**
01134   * @brief  Selects the TIM Group Channel 5 and Channel 2, 
01135             OC2REFC is the logical AND of OC2REFC and OC5REF.
01136   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIMx peripheral
01137   * @param  NewState: new state of the Commutation event.
01138   *          This parameter can be: ENABLE or DISABLE.
01139   * @retval None
01140   */
01141 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState)
01142 {
01143   /* Check the parameters */
01144   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01145   assert_param(IS_FUNCTIONAL_STATE(NewState));
01146 
01147   if (NewState != DISABLE)
01148   {
01149     /* Set the GC5C2 Bit */
01150     TIMx->CCR5 |= TIM_CCR5_GC5C2;
01151   }
01152   else
01153   {
01154     /* Reset the GC5C2 Bit */
01155     TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2;
01156   }
01157 }
01158 
01159 
01160 /**
01161   * @brief  Selects the TIM Group Channel 5 and Channel 3, 
01162             OC3REFC is the logical AND of OC3REFC and OC5REF.
01163   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIMx peripheral
01164   * @param  NewState: new state of the Commutation event.
01165   *          This parameter can be: ENABLE or DISABLE.
01166   * @retval None
01167   */
01168 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState)
01169 {
01170   /* Check the parameters */
01171   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01172   assert_param(IS_FUNCTIONAL_STATE(NewState));
01173 
01174   if (NewState != DISABLE)
01175   {
01176     /* Set the GC5C3 Bit */
01177     TIMx->CCR5 |= TIM_CCR5_GC5C3;
01178   }
01179   else
01180   {
01181     /* Reset the GC5C3 Bit */
01182     TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3;
01183   }
01184 }
01185 
01186 /**
01187   * @brief  Fills each TIM_OCInitStruct member with its default value.
01188   * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
01189   *         be initialized.
01190   * @retval None
01191   */
01192 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
01193 {
01194   /* Set the default configuration */
01195   TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
01196   TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
01197   TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
01198   TIM_OCInitStruct->TIM_Pulse = 0x00000000;
01199   TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
01200   TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
01201   TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
01202   TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
01203 }
01204 
01205 /**
01206   * @brief  Selects the TIM Output Compare Mode.
01207   * @note   This function disables the selected channel before changing the Output
01208   *         Compare Mode. If needed, user has to enable this channel using
01209   *         TIM_CCxCmd() and TIM_CCxNCmd() functions.
01210   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01211   * @param  TIM_Channel: specifies the TIM Channel
01212   *          This parameter can be one of the following values:
01213   *            @arg TIM_Channel_1: TIM Channel 1
01214   *            @arg TIM_Channel_2: TIM Channel 2
01215   *            @arg TIM_Channel_3: TIM Channel 3
01216   *            @arg TIM_Channel_4: TIM Channel 4
01217   * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
01218   *           This parameter can be one of the following values:
01219   *            @arg TIM_OCMode_Timing
01220   *            @arg TIM_OCMode_Active
01221   *            @arg TIM_OCMode_Toggle
01222   *            @arg TIM_OCMode_PWM1
01223   *            @arg TIM_OCMode_PWM2
01224   *            @arg TIM_ForcedAction_Active
01225   *            @arg TIM_ForcedAction_InActive
01226   *            @arg TIM_OCMode_Retrigerrable_OPM1
01227   *            @arg TIM_OCMode_Retrigerrable_OPM2
01228   *            @arg TIM_OCMode_Combined_PWM1
01229   *            @arg TIM_OCMode_Combined_PWM2
01230   *            @arg TIM_OCMode_Asymmetric_PWM1
01231   *            @arg TIM_OCMode_Asymmetric_PWM2            
01232   * @retval None
01233   */
01234 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode)
01235 {
01236   uint32_t tmp = 0;
01237   uint16_t tmp1 = 0;
01238 
01239   /* Check the parameters */
01240   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01241   assert_param(IS_TIM_CHANNEL(TIM_Channel));
01242   assert_param(IS_TIM_OCM(TIM_OCMode));
01243 
01244   tmp = (uint32_t) TIMx;
01245   tmp += CCMR_OFFSET;
01246 
01247   tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
01248 
01249   /* Disable the Channel: Reset the CCxE Bit */
01250   TIMx->CCER &= (uint16_t) ~tmp1;
01251 
01252   if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
01253   {
01254     tmp += (TIM_Channel>>1);
01255 
01256     /* Reset the OCxM bits in the CCMRx register */
01257     *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
01258    
01259     /* Configure the OCxM bits in the CCMRx register */
01260     *(__IO uint32_t *) tmp |= TIM_OCMode;
01261   }
01262   else
01263   {
01264     tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1;
01265 
01266     /* Reset the OCxM bits in the CCMRx register */
01267     *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
01268     
01269     /* Configure the OCxM bits in the CCMRx register */
01270     *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8);
01271   }
01272 }
01273 
01274 /**
01275   * @brief  Sets the TIMx Capture Compare1 Register value
01276   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01277   * @param  Compare1: specifies the Capture Compare1 register new value.
01278   * @retval None
01279   */
01280 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
01281 {
01282   /* Check the parameters */
01283   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01284 
01285   /* Set the Capture Compare1 Register value */
01286   TIMx->CCR1 = Compare1;
01287 }
01288 
01289 /**
01290   * @brief  Sets the TIMx Capture Compare2 Register value
01291   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
01292   *         peripheral.
01293   * @param  Compare2: specifies the Capture Compare2 register new value.
01294   * @retval None
01295   */
01296 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
01297 {
01298   /* Check the parameters */
01299   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01300 
01301   /* Set the Capture Compare2 Register value */
01302   TIMx->CCR2 = Compare2;
01303 }
01304 
01305 /**
01306   * @brief  Sets the TIMx Capture Compare3 Register value
01307   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 20 or 8 to select the TIM peripheral.
01308   * @param  Compare3: specifies the Capture Compare3 register new value.
01309   * @retval None
01310   */
01311 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
01312 {
01313   /* Check the parameters */
01314   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01315 
01316   /* Set the Capture Compare3 Register value */
01317   TIMx->CCR3 = Compare3;
01318 }
01319 
01320 /**
01321   * @brief  Sets the TIMx Capture Compare4 Register value
01322   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 20 or 8 to select the TIM peripheral.
01323   * @param  Compare4: specifies the Capture Compare4 register new value.
01324   * @retval None
01325   */
01326 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
01327 {
01328   /* Check the parameters */
01329   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01330 
01331   /* Set the Capture Compare4 Register value */
01332   TIMx->CCR4 = Compare4;
01333 }
01334 
01335 /**
01336   * @brief  Sets the TIMx Capture Compare5 Register value
01337   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
01338   * @param  Compare5: specifies the Capture Compare5 register new value.
01339   * @retval None
01340   */
01341 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5)
01342 {
01343   /* Check the parameters */
01344   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01345 
01346   /* Set the Capture Compare5 Register value */
01347   TIMx->CCR5 = Compare5;
01348 }
01349 
01350 /**
01351   * @brief  Sets the TIMx Capture Compare6 Register value
01352   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
01353   * @param  Compare6: specifies the Capture Compare5 register new value.
01354   * @retval None
01355   */
01356 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6)
01357 {
01358   /* Check the parameters */
01359   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01360 
01361   /* Set the Capture Compare6 Register value */
01362   TIMx->CCR6 = Compare6;
01363 }
01364 
01365 /**
01366   * @brief  Forces the TIMx output 1 waveform to active or inactive level.
01367   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01368   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01369   *          This parameter can be one of the following values:
01370   *            @arg TIM_ForcedAction_Active: Force active level on OC1REF
01371   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
01372   * @retval None
01373   */
01374 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01375 {
01376   uint32_t tmpccmr1 = 0;
01377 
01378   /* Check the parameters */
01379   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01380   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01381   tmpccmr1 = TIMx->CCMR1;
01382 
01383   /* Reset the OC1M Bits */
01384   tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M;
01385 
01386   /* Configure The Forced output Mode */
01387   tmpccmr1 |= TIM_ForcedAction;
01388 
01389   /* Write to TIMx CCMR1 register */
01390   TIMx->CCMR1 = tmpccmr1;
01391 }
01392 
01393 /**
01394   * @brief  Forces the TIMx output 2 waveform to active or inactive level.
01395   * @param  TIMx: where x can be   1, 2, 3, 4, 8, 20 or 15 to select the TIM 
01396   *         peripheral.
01397   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01398   *          This parameter can be one of the following values:
01399   *            @arg TIM_ForcedAction_Active: Force active level on OC2REF
01400   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
01401   * @retval None
01402   */
01403 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01404 {
01405   uint32_t tmpccmr1 = 0;
01406 
01407   /* Check the parameters */
01408   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01409   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01410   tmpccmr1 = TIMx->CCMR1;
01411 
01412   /* Reset the OC2M Bits */
01413   tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M;
01414 
01415   /* Configure The Forced output Mode */
01416   tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8);
01417 
01418   /* Write to TIMx CCMR1 register */
01419   TIMx->CCMR1 = tmpccmr1;
01420 }
01421 
01422 /**
01423   * @brief  Forces the TIMx output 3 waveform to active or inactive level.
01424   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01425   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01426   *          This parameter can be one of the following values:
01427   *            @arg TIM_ForcedAction_Active: Force active level on OC3REF
01428   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
01429   * @retval None
01430   */
01431 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01432 {
01433   uint32_t tmpccmr2 = 0;
01434 
01435   /* Check the parameters */
01436   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01437   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01438 
01439   tmpccmr2 = TIMx->CCMR2;
01440 
01441   /* Reset the OC1M Bits */
01442   tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M;
01443 
01444   /* Configure The Forced output Mode */
01445   tmpccmr2 |= TIM_ForcedAction;
01446 
01447   /* Write to TIMx CCMR2 register */
01448   TIMx->CCMR2 = tmpccmr2;
01449 }
01450 
01451 /**
01452   * @brief  Forces the TIMx output 4 waveform to active or inactive level.
01453   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01454   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01455   *          This parameter can be one of the following values:
01456   *            @arg TIM_ForcedAction_Active: Force active level on OC4REF
01457   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
01458   * @retval None
01459   */
01460 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01461 {
01462   uint32_t tmpccmr2 = 0;
01463 
01464   /* Check the parameters */
01465   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01466   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01467   tmpccmr2 = TIMx->CCMR2;
01468 
01469   /* Reset the OC2M Bits */
01470   tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M;
01471 
01472   /* Configure The Forced output Mode */
01473   tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8);
01474 
01475   /* Write to TIMx CCMR2 register */
01476   TIMx->CCMR2 = tmpccmr2;
01477 }
01478 
01479 /**
01480   * @brief  Forces the TIMx output 5 waveform to active or inactive level.
01481   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM peripheral.
01482   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01483   *          This parameter can be one of the following values:
01484   *            @arg TIM_ForcedAction_Active: Force active level on OC5REF
01485   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
01486   * @retval None
01487   */
01488 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01489 {
01490   uint32_t tmpccmr3 = 0;
01491 
01492   /* Check the parameters */
01493   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01494   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01495   tmpccmr3 = TIMx->CCMR3;
01496 
01497   /* Reset the OC5M Bits */
01498   tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M;
01499 
01500   /* Configure The Forced output Mode */
01501   tmpccmr3 |= (uint32_t)(TIM_ForcedAction);
01502 
01503   /* Write to TIMx CCMR3 register */
01504   TIMx->CCMR3 = tmpccmr3;
01505 }
01506 
01507 /**
01508   * @brief  Forces the TIMx output 6 waveform to active or inactive level.
01509   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
01510   * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
01511   *          This parameter can be one of the following values:
01512   *            @arg TIM_ForcedAction_Active: Force active level on OC5REF
01513   *            @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF.
01514   * @retval None
01515   */
01516 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
01517 {
01518   uint32_t tmpccmr3 = 0;
01519 
01520   /* Check the parameters */
01521   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01522   assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
01523   tmpccmr3 = TIMx->CCMR3;
01524 
01525   /* Reset the OC6M Bits */
01526   tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M;
01527 
01528   /* Configure The Forced output Mode */
01529   tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8);
01530 
01531   /* Write to TIMx CCMR3 register */
01532   TIMx->CCMR3 = tmpccmr3;
01533 }
01534 
01535 /**
01536   * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
01537   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01538   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01539   *          This parameter can be one of the following values:
01540   *            @arg TIM_OCPreload_Enable
01541   *            @arg TIM_OCPreload_Disable
01542   * @retval None
01543   */
01544 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01545 {
01546   uint32_t tmpccmr1 = 0;
01547 
01548   /* Check the parameters */
01549   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01550   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01551 
01552   tmpccmr1 = TIMx->CCMR1;
01553 
01554   /* Reset the OC1PE Bit */
01555   tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE);
01556 
01557   /* Enable or Disable the Output Compare Preload feature */
01558   tmpccmr1 |= TIM_OCPreload;
01559 
01560   /* Write to TIMx CCMR1 register */
01561   TIMx->CCMR1 = tmpccmr1;
01562 }
01563 
01564 /**
01565   * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
01566   * @param  TIMx: where x can be  1, 2, 3, 4, 8, 20 or 15 to select the TIM 
01567   *         peripheral.
01568   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01569   *          This parameter can be one of the following values:
01570   *            @arg TIM_OCPreload_Enable
01571   *            @arg TIM_OCPreload_Disable
01572   * @retval None
01573   */
01574 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01575 {
01576   uint32_t tmpccmr1 = 0;
01577 
01578   /* Check the parameters */
01579   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01580   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01581 
01582   tmpccmr1 = TIMx->CCMR1;
01583 
01584   /* Reset the OC2PE Bit */
01585   tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE);
01586 
01587   /* Enable or Disable the Output Compare Preload feature */
01588   tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8);
01589 
01590   /* Write to TIMx CCMR1 register */
01591   TIMx->CCMR1 = tmpccmr1;
01592 }
01593 
01594 /**
01595   * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
01596   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01597   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01598   *          This parameter can be one of the following values:
01599   *            @arg TIM_OCPreload_Enable
01600   *            @arg TIM_OCPreload_Disable
01601   * @retval None
01602   */
01603 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01604 {
01605   uint32_t tmpccmr2 = 0;
01606 
01607   /* Check the parameters */
01608   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01609   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01610 
01611   tmpccmr2 = TIMx->CCMR2;
01612 
01613   /* Reset the OC3PE Bit */
01614   tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE);
01615 
01616   /* Enable or Disable the Output Compare Preload feature */
01617   tmpccmr2 |= TIM_OCPreload;
01618 
01619   /* Write to TIMx CCMR2 register */
01620   TIMx->CCMR2 = tmpccmr2;
01621 }
01622 
01623 /**
01624   * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
01625   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01626   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01627   *          This parameter can be one of the following values:
01628   *            @arg TIM_OCPreload_Enable
01629   *            @arg TIM_OCPreload_Disable
01630   * @retval None
01631   */
01632 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01633 {
01634   uint32_t tmpccmr2 = 0;
01635 
01636   /* Check the parameters */
01637   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01638   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01639 
01640   tmpccmr2 = TIMx->CCMR2;
01641 
01642   /* Reset the OC4PE Bit */
01643   tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE);
01644 
01645   /* Enable or Disable the Output Compare Preload feature */
01646   tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8);
01647 
01648   /* Write to TIMx CCMR2 register */
01649   TIMx->CCMR2 = tmpccmr2;
01650 }
01651 
01652 /**
01653   * @brief  Enables or disables the TIMx peripheral Preload register on CCR5.
01654   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM peripheral.
01655   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01656   *          This parameter can be one of the following values:
01657   *            @arg TIM_OCPreload_Enable
01658   *            @arg TIM_OCPreload_Disable
01659   * @retval None
01660   */
01661 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01662 {
01663   uint32_t tmpccmr3 = 0;
01664 
01665   /* Check the parameters */
01666   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01667   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01668 
01669   tmpccmr3 = TIMx->CCMR3;
01670 
01671   /* Reset the OC5PE Bit */
01672   tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE);
01673 
01674   /* Enable or Disable the Output Compare Preload feature */
01675   tmpccmr3 |= (uint32_t)(TIM_OCPreload);
01676 
01677   /* Write to TIMx CCMR3 register */
01678   TIMx->CCMR3 = tmpccmr3;
01679 }
01680 
01681 /**
01682   * @brief  Enables or disables the TIMx peripheral Preload register on CCR6.
01683   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM peripheral.
01684   * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
01685   *          This parameter can be one of the following values:
01686   *            @arg TIM_OCPreload_Enable
01687   *            @arg TIM_OCPreload_Disable
01688   * @retval None
01689   */
01690 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
01691 {
01692   uint32_t tmpccmr3 = 0;
01693 
01694   /* Check the parameters */
01695   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01696   assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
01697 
01698   tmpccmr3 = TIMx->CCMR3;
01699 
01700   /* Reset the OC5PE Bit */
01701   tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE);
01702 
01703   /* Enable or Disable the Output Compare Preload feature */
01704   tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8);
01705 
01706   /* Write to TIMx CCMR3 register */
01707   TIMx->CCMR3 = tmpccmr3;
01708 }
01709 
01710 /**
01711   * @brief  Configures the TIMx Output Compare 1 Fast feature.
01712   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01713   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01714   *          This parameter can be one of the following values:
01715   *            @arg TIM_OCFast_Enable: TIM output compare fast enable
01716   *            @arg TIM_OCFast_Disable: TIM output compare fast disable
01717   * @retval None
01718   */
01719 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01720 {
01721   uint32_t tmpccmr1 = 0;
01722 
01723   /* Check the parameters */
01724   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01725   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01726 
01727   /* Get the TIMx CCMR1 register value */
01728   tmpccmr1 = TIMx->CCMR1;
01729 
01730   /* Reset the OC1FE Bit */
01731   tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE;
01732 
01733   /* Enable or Disable the Output Compare Fast Bit */
01734   tmpccmr1 |= TIM_OCFast;
01735 
01736   /* Write to TIMx CCMR1 */
01737   TIMx->CCMR1 = tmpccmr1;
01738 }
01739 
01740 /**
01741   * @brief  Configures the TIMx Output Compare 2 Fast feature.
01742   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
01743   *         peripheral.
01744   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01745   *          This parameter can be one of the following values:
01746   *            @arg TIM_OCFast_Enable: TIM output compare fast enable
01747   *            @arg TIM_OCFast_Disable: TIM output compare fast disable
01748   * @retval None
01749   */
01750 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01751 {
01752   uint32_t tmpccmr1 = 0;
01753 
01754   /* Check the parameters */
01755   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01756   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01757 
01758   /* Get the TIMx CCMR1 register value */
01759   tmpccmr1 = TIMx->CCMR1;
01760 
01761   /* Reset the OC2FE Bit */
01762   tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE);
01763 
01764   /* Enable or Disable the Output Compare Fast Bit */
01765   tmpccmr1 |= ((uint32_t)TIM_OCFast << 8);
01766 
01767   /* Write to TIMx CCMR1 */
01768   TIMx->CCMR1 = tmpccmr1;
01769 }
01770 
01771 /**
01772   * @brief  Configures the TIMx Output Compare 3 Fast feature.
01773   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01774   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01775   *          This parameter can be one of the following values:
01776   *            @arg TIM_OCFast_Enable: TIM output compare fast enable
01777   *            @arg TIM_OCFast_Disable: TIM output compare fast disable
01778   * @retval None
01779   */
01780 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01781 {
01782   uint32_t tmpccmr2 = 0;
01783   
01784   /* Check the parameters */
01785   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01786   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01787 
01788   /* Get the TIMx CCMR2 register value */
01789   tmpccmr2 = TIMx->CCMR2;
01790 
01791   /* Reset the OC3FE Bit */
01792   tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE;
01793 
01794   /* Enable or Disable the Output Compare Fast Bit */
01795   tmpccmr2 |= TIM_OCFast;
01796 
01797   /* Write to TIMx CCMR2 */
01798   TIMx->CCMR2 = tmpccmr2;
01799 }
01800 
01801 /**
01802   * @brief  Configures the TIMx Output Compare 4 Fast feature.
01803   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01804   * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
01805   *          This parameter can be one of the following values:
01806   *            @arg TIM_OCFast_Enable: TIM output compare fast enable
01807   *            @arg TIM_OCFast_Disable: TIM output compare fast disable
01808   * @retval None
01809   */
01810 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
01811 {
01812   uint32_t tmpccmr2 = 0;
01813 
01814   /* Check the parameters */
01815   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01816   assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
01817 
01818   /* Get the TIMx CCMR2 register value */
01819   tmpccmr2 = TIMx->CCMR2;
01820 
01821   /* Reset the OC4FE Bit */
01822   tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE);
01823 
01824   /* Enable or Disable the Output Compare Fast Bit */
01825   tmpccmr2 |= ((uint32_t)TIM_OCFast << 8);
01826 
01827   /* Write to TIMx CCMR2 */
01828   TIMx->CCMR2 = tmpccmr2;
01829 }
01830 
01831 /**
01832   * @brief  Clears or safeguards the OCREF1 signal on an external event
01833   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
01834   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01835   *          This parameter can be one of the following values:
01836   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01837   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01838   * @retval None
01839   */
01840 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01841 {
01842   uint32_t tmpccmr1 = 0;
01843 
01844   /* Check the parameters */
01845   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
01846   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01847 
01848   tmpccmr1 = TIMx->CCMR1;
01849 
01850   /* Reset the OC1CE Bit */
01851   tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE;
01852 
01853   /* Enable or Disable the Output Compare Clear Bit */
01854   tmpccmr1 |= TIM_OCClear;
01855 
01856   /* Write to TIMx CCMR1 register */
01857   TIMx->CCMR1 = tmpccmr1;
01858 }
01859 
01860 /**
01861   * @brief  Clears or safeguards the OCREF2 signal on an external event
01862   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
01863   *         peripheral.
01864   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01865   *          This parameter can be one of the following values:
01866   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01867   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01868   * @retval None
01869   */
01870 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01871 {
01872   uint32_t tmpccmr1 = 0;
01873 
01874   /* Check the parameters */
01875   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
01876   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01877 
01878   tmpccmr1 = TIMx->CCMR1;
01879 
01880   /* Reset the OC2CE Bit */
01881   tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE;
01882 
01883   /* Enable or Disable the Output Compare Clear Bit */
01884   tmpccmr1 |= ((uint32_t)TIM_OCClear << 8);
01885 
01886   /* Write to TIMx CCMR1 register */
01887   TIMx->CCMR1 = tmpccmr1;
01888 }
01889 
01890 /**
01891   * @brief  Clears or safeguards the OCREF3 signal on an external event
01892   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01893   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01894   *          This parameter can be one of the following values:
01895   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01896   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01897   * @retval None
01898   */
01899 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01900 {
01901   uint32_t tmpccmr2 = 0;
01902 
01903   /* Check the parameters */
01904   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01905   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01906 
01907   tmpccmr2 = TIMx->CCMR2;
01908 
01909   /* Reset the OC3CE Bit */
01910   tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE;
01911 
01912   /* Enable or Disable the Output Compare Clear Bit */
01913   tmpccmr2 |= TIM_OCClear;
01914 
01915   /* Write to TIMx CCMR2 register */
01916   TIMx->CCMR2 = tmpccmr2;
01917 }
01918 
01919 /**
01920   * @brief  Clears or safeguards the OCREF4 signal on an external event
01921   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
01922   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01923   *          This parameter can be one of the following values:
01924   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01925   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01926   * @retval None
01927   */
01928 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01929 {
01930   uint32_t tmpccmr2 = 0;
01931 
01932   /* Check the parameters */
01933   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
01934   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01935 
01936   tmpccmr2 = TIMx->CCMR2;
01937 
01938   /* Reset the OC4CE Bit */
01939   tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE;
01940 
01941   /* Enable or Disable the Output Compare Clear Bit */
01942   tmpccmr2 |= ((uint32_t)TIM_OCClear << 8);
01943 
01944   /* Write to TIMx CCMR2 register */
01945   TIMx->CCMR2 = tmpccmr2;
01946 }
01947 
01948 /**
01949   * @brief  Clears or safeguards the OCREF5 signal on an external event
01950   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM peripheral.
01951   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01952   *          This parameter can be one of the following values:
01953   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01954   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01955   * @retval None
01956   */
01957 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01958 {
01959   uint32_t tmpccmr3 = 0;
01960 
01961   /* Check the parameters */
01962   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01963   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01964 
01965   tmpccmr3 = TIMx->CCMR3;
01966 
01967   /* Reset the OC5CE Bit */
01968   tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE;
01969 
01970   /* Enable or Disable the Output Compare Clear Bit */
01971   tmpccmr3 |= (uint32_t)(TIM_OCClear);
01972 
01973   /* Write to TIMx CCMR3 register */
01974   TIMx->CCMR3 = tmpccmr3;
01975 }
01976 
01977 /**
01978   * @brief  Clears or safeguards the OCREF6 signal on an external event
01979   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM peripheral.
01980   * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
01981   *          This parameter can be one of the following values:
01982   *            @arg TIM_OCClear_Enable: TIM Output clear enable
01983   *            @arg TIM_OCClear_Disable: TIM Output clear disable
01984   * @retval None
01985   */
01986 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
01987 {
01988   uint32_t tmpccmr3 = 0;
01989 
01990   /* Check the parameters */
01991   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
01992   assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
01993 
01994   tmpccmr3 = TIMx->CCMR3;
01995 
01996   /* Reset the OC5CE Bit */
01997   tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE;
01998 
01999   /* Enable or Disable the Output Compare Clear Bit */
02000   tmpccmr3 |= ((uint32_t)TIM_OCClear << 8);
02001 
02002   /* Write to TIMx CCMR3 register */
02003   TIMx->CCMR3 = tmpccmr3;
02004 }
02005 
02006 /**
02007   * @brief  Selects the OCReference Clear source.
02008   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02009   * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.
02010   *   This parameter can be one of the following values:
02011   *     @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
02012   *     @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.  
02013   * @retval None
02014   */
02015 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
02016 {
02017   /* Check the parameters */
02018   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02019   assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
02020 
02021   /* Set the TIM_OCReferenceClear source */
02022   TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
02023   TIMx->SMCR |=  TIM_OCReferenceClear;
02024 }
02025 
02026 /**
02027   * @brief  Configures the TIMx channel 1 polarity.
02028   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02029   * @param  TIM_OCPolarity: specifies the OC1 Polarity
02030   *          This parameter can be one of the following values:
02031   *            @arg TIM_OCPolarity_High: Output Compare active high
02032   *            @arg TIM_OCPolarity_Low: Output Compare active low
02033   * @retval None
02034   */
02035 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02036 {
02037   uint32_t tmpccer = 0;
02038 
02039   /* Check the parameters */
02040   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02041   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02042 
02043   tmpccer = TIMx->CCER;
02044 
02045   /* Set or Reset the CC1P Bit */
02046   tmpccer &= (uint32_t)(~TIM_CCER_CC1P);
02047   tmpccer |= TIM_OCPolarity;
02048 
02049   /* Write to TIMx CCER register */
02050   TIMx->CCER = tmpccer;
02051 }
02052 
02053 /**
02054   * @brief  Configures the TIMx Channel 1N polarity.
02055   * @param  TIMx: where x can be 1, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02056   * @param  TIM_OCNPolarity: specifies the OC1N Polarity
02057   *          This parameter can be one of the following values:
02058   *            @arg TIM_OCNPolarity_High: Output Compare active high
02059   *            @arg TIM_OCNPolarity_Low: Output Compare active low
02060   * @retval None
02061   */
02062 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
02063 {
02064   uint32_t tmpccer = 0;
02065   /* Check the parameters */
02066   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02067   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
02068    
02069   tmpccer = TIMx->CCER;
02070 
02071   /* Set or Reset the CC1NP Bit */
02072   tmpccer &= (uint32_t)~TIM_CCER_CC1NP;
02073   tmpccer |= TIM_OCNPolarity;
02074 
02075   /* Write to TIMx CCER register */
02076   TIMx->CCER = tmpccer;
02077 }
02078 
02079 /**
02080   * @brief  Configures the TIMx channel 2 polarity.
02081   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
02082   *         peripheral.
02083   * @param  TIM_OCPolarity: specifies the OC2 Polarity
02084   *          This parameter can be one of the following values:
02085   *            @arg TIM_OCPolarity_High: Output Compare active high
02086   *            @arg TIM_OCPolarity_Low: Output Compare active low
02087   * @retval None
02088   */
02089 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02090 {
02091   uint32_t tmpccer = 0;
02092 
02093   /* Check the parameters */
02094   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02095   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02096 
02097   tmpccer = TIMx->CCER;
02098 
02099   /* Set or Reset the CC2P Bit */
02100   tmpccer &= (uint32_t)(~TIM_CCER_CC2P);
02101   tmpccer |= ((uint32_t)TIM_OCPolarity << 4);
02102 
02103   /* Write to TIMx CCER register */
02104   TIMx->CCER = tmpccer;
02105 }
02106 
02107 /**
02108   * @brief  Configures the TIMx Channel 2N polarity.
02109   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
02110   * @param  TIM_OCNPolarity: specifies the OC2N Polarity
02111   *          This parameter can be one of the following values:
02112   *            @arg TIM_OCNPolarity_High: Output Compare active high
02113   *            @arg TIM_OCNPolarity_Low: Output Compare active low
02114   * @retval None
02115   */
02116 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
02117 {
02118   uint32_t tmpccer = 0;
02119 
02120   /* Check the parameters */
02121   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02122   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
02123   
02124   tmpccer = TIMx->CCER;
02125 
02126   /* Set or Reset the CC2NP Bit */
02127   tmpccer &= (uint32_t)~TIM_CCER_CC2NP;
02128   tmpccer |= ((uint32_t)TIM_OCNPolarity << 4);
02129 
02130   /* Write to TIMx CCER register */
02131   TIMx->CCER = tmpccer;
02132 }
02133 
02134 /**
02135   * @brief  Configures the TIMx channel 3 polarity.
02136   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02137   * @param  TIM_OCPolarity: specifies the OC3 Polarity
02138   *          This parameter can be one of the following values:
02139   *            @arg TIM_OCPolarity_High: Output Compare active high
02140   *            @arg TIM_OCPolarity_Low: Output Compare active low
02141   * @retval None
02142   */
02143 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02144 {
02145   uint32_t tmpccer = 0;
02146 
02147   /* Check the parameters */
02148   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02149   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02150 
02151   tmpccer = TIMx->CCER;
02152 
02153   /* Set or Reset the CC3P Bit */
02154   tmpccer &= (uint32_t)~TIM_CCER_CC3P;
02155   tmpccer |= ((uint32_t)TIM_OCPolarity << 8);
02156 
02157   /* Write to TIMx CCER register */
02158   TIMx->CCER = tmpccer;
02159 }
02160 
02161 /**
02162   * @brief  Configures the TIMx Channel 3N polarity.
02163   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
02164   * @param  TIM_OCNPolarity: specifies the OC3N Polarity
02165   *          This parameter can be one of the following values:
02166   *            @arg TIM_OCNPolarity_High: Output Compare active high
02167   *            @arg TIM_OCNPolarity_Low: Output Compare active low
02168   * @retval None
02169   */
02170 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
02171 {
02172   uint32_t tmpccer = 0;
02173  
02174   /* Check the parameters */
02175   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02176   assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
02177     
02178   tmpccer = TIMx->CCER;
02179 
02180   /* Set or Reset the CC3NP Bit */
02181   tmpccer &= (uint32_t)~TIM_CCER_CC3NP;
02182   tmpccer |= ((uint32_t)TIM_OCNPolarity << 8);
02183 
02184   /* Write to TIMx CCER register */
02185   TIMx->CCER = tmpccer;
02186 }
02187 
02188 /**
02189   * @brief  Configures the TIMx channel 4 polarity.
02190   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02191   * @param  TIM_OCPolarity: specifies the OC4 Polarity
02192   *          This parameter can be one of the following values:
02193   *            @arg TIM_OCPolarity_High: Output Compare active high
02194   *            @arg TIM_OCPolarity_Low: Output Compare active low
02195   * @retval None
02196   */
02197 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02198 {
02199   uint32_t tmpccer = 0;
02200 
02201   /* Check the parameters */
02202   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02203   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02204 
02205   tmpccer = TIMx->CCER;
02206 
02207   /* Set or Reset the CC4P Bit */
02208   tmpccer &= (uint32_t)~TIM_CCER_CC4P;
02209   tmpccer |= ((uint32_t)TIM_OCPolarity << 12);
02210 
02211   /* Write to TIMx CCER register */
02212   TIMx->CCER = tmpccer;
02213 }
02214 
02215 /**
02216   * @brief  Configures the TIMx channel 5 polarity.
02217   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
02218   * @param  TIM_OCPolarity: specifies the OC5 Polarity
02219   *          This parameter can be one of the following values:
02220   *            @arg TIM_OCPolarity_High: Output Compare active high
02221   *            @arg TIM_OCPolarity_Low: Output Compare active low
02222   * @retval None
02223   */
02224 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02225 {
02226   uint32_t tmpccer = 0;
02227 
02228   /* Check the parameters */
02229   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02230   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02231 
02232   tmpccer = TIMx->CCER;
02233 
02234   /* Set or Reset the CC5P Bit */
02235   tmpccer &= (uint32_t)~TIM_CCER_CC5P;
02236   tmpccer |= ((uint32_t)TIM_OCPolarity << 16);
02237 
02238   /* Write to TIMx CCER register */
02239   TIMx->CCER = tmpccer;
02240 }
02241 
02242 /**
02243   * @brief  Configures the TIMx channel 6 polarity.
02244   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
02245   * @param  TIM_OCPolarity: specifies the OC6 Polarity
02246   *          This parameter can be one of the following values:
02247   *            @arg TIM_OCPolarity_High: Output Compare active high
02248   *            @arg TIM_OCPolarity_Low: Output Compare active low
02249   * @retval None
02250   */
02251 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
02252 {
02253   uint32_t tmpccer = 0;
02254 
02255   /* Check the parameters */
02256   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02257   assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
02258 
02259   tmpccer = TIMx->CCER;
02260 
02261   /* Set or Reset the CC6P Bit */
02262   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
02263   tmpccer |= ((uint32_t)TIM_OCPolarity << 20);
02264 
02265   /* Write to TIMx CCER register */
02266   TIMx->CCER = tmpccer;
02267 }
02268 
02269 /**
02270   * @brief  Enables or disables the TIM Capture Compare Channel x.
02271   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02272   * @param  TIM_Channel: specifies the TIM Channel
02273   *          This parameter can be one of the following values:
02274   *            @arg TIM_Channel_1: TIM Channel 1
02275   *            @arg TIM_Channel_2: TIM Channel 2
02276   *            @arg TIM_Channel_3: TIM Channel 3
02277   *            @arg TIM_Channel_4: TIM Channel 4
02278   *            @arg TIM_Channel_5: TIM Channel 5
02279   *            @arg TIM_Channel_6: TIM Channel 6    
02280   * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
02281   *          This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
02282   * @retval None
02283   */
02284 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
02285 {
02286   uint32_t tmp = 0;
02287 
02288   /* Check the parameters */
02289   assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
02290   assert_param(IS_TIM_CHANNEL(TIM_Channel));
02291   assert_param(IS_TIM_CCX(TIM_CCx));
02292 
02293   tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel;
02294 
02295   /* Reset the CCxE Bit */
02296   TIMx->CCER &= (uint32_t)(~tmp);
02297 
02298   /* Set or reset the CCxE Bit */ 
02299   TIMx->CCER |=  ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel);
02300 }
02301 
02302 /**
02303   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02304   * @param  TIMx: where x can be 1, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02305   * @param  TIM_Channel: specifies the TIM Channel
02306   *          This parameter can be one of the following values:
02307   *            @arg TIM_Channel_1: TIM Channel 1
02308   *            @arg TIM_Channel_2: TIM Channel 2
02309   *            @arg TIM_Channel_3: TIM Channel 3
02310   * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
02311   *          This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
02312   * @retval None
02313   */
02314 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
02315 {
02316   uint32_t tmp = 0;
02317 
02318   /* Check the parameters */
02319   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02320   assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
02321   assert_param(IS_TIM_CCXN(TIM_CCxN));
02322 
02323   tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel;
02324 
02325   /* Reset the CCxNE Bit */
02326   TIMx->CCER &= (uint32_t) ~tmp;
02327 
02328   /* Set or reset the CCxNE Bit */ 
02329   TIMx->CCER |=  ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel);
02330 }
02331 /**
02332   * @}
02333   */
02334 
02335 /** @defgroup TIM_Group3 Input Capture management functions
02336  *  @brief    Input Capture management functions 
02337  *
02338 @verbatim   
02339  ===============================================================================
02340                ##### Input Capture management functions #####
02341  ===============================================================================  
02342          
02343   *** TIM Driver: how to use it in Input Capture Mode ***
02344   =======================================================
02345   [..] 
02346   To use the Timer in Input Capture mode, the following steps are mandatory:
02347        
02348       (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
02349        
02350       (#) Configure the TIM pins by configuring the corresponding GPIO pins
02351        
02352       (#) Configure the Time base unit as described in the first part of this driver,
02353           if needed, else the Timer will run with the default configuration:
02354           (++) Autoreload value = 0xFFFF
02355           (++) Prescaler value = 0x0000
02356           (++) Counter mode = Up counting
02357           (++) Clock Division = TIM_CKD_DIV1
02358           
02359       (#) Fill the TIM_ICInitStruct with the desired parameters including:
02360           (++) TIM Channel: TIM_Channel
02361           (++) TIM Input Capture polarity: TIM_ICPolarity
02362           (++) TIM Input Capture selection: TIM_ICSelection
02363           (++) TIM Input Capture Prescaler: TIM_ICPrescaler
02364           (++) TIM Input CApture filter value: TIM_ICFilter
02365        
02366       (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the 
02367           corresponding configuration and to measure only frequency or duty cycle of the input signal,
02368           or,
02369           Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the 
02370           corresponding configuration and to measure the frequency and the duty cycle of the input signal
02371           
02372       (#) Enable the NVIC or the DMA to read the measured frequency. 
02373           
02374       (#) Enable the corresponding interrupt (or DMA request) to read the Captured value,
02375           using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 
02376        
02377       (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
02378        
02379       (#) Use TIM_GetCapturex(TIMx); to read the captured value.
02380   [..]        
02381       (@) All other functions can be used separately to modify, if needed,
02382           a specific feature of the Timer. 
02383 
02384 @endverbatim
02385   * @{
02386   */
02387 
02388 /**
02389   * @brief  Initializes the TIM peripheral according to the specified parameters
02390   *         in the TIM_ICInitStruct.
02391   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02392   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
02393   *         the configuration information for the specified TIM peripheral.
02394   * @retval None
02395   */
02396 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
02397 {
02398   /* Check the parameters */
02399   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02400   assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
02401   assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
02402   assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
02403   assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
02404   
02405   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
02406   {
02407     /* TI1 Configuration */
02408     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
02409                TIM_ICInitStruct->TIM_ICSelection,
02410                TIM_ICInitStruct->TIM_ICFilter);
02411     /* Set the Input Capture Prescaler value */
02412     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02413   }
02414   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
02415   {
02416     /* TI2 Configuration */
02417     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
02418                TIM_ICInitStruct->TIM_ICSelection,
02419                TIM_ICInitStruct->TIM_ICFilter);
02420     /* Set the Input Capture Prescaler value */
02421     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02422   }
02423   else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
02424   {
02425     /* TI3 Configuration */
02426     TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
02427                TIM_ICInitStruct->TIM_ICSelection,
02428                TIM_ICInitStruct->TIM_ICFilter);
02429     /* Set the Input Capture Prescaler value */
02430     TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02431   }
02432   else
02433   {
02434     /* TI4 Configuration */
02435     TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
02436                TIM_ICInitStruct->TIM_ICSelection,
02437                TIM_ICInitStruct->TIM_ICFilter);
02438     /* Set the Input Capture Prescaler value */
02439     TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02440   }
02441 }
02442 
02443 /**
02444   * @brief  Fills each TIM_ICInitStruct member with its default value.
02445   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
02446   *         be initialized.
02447   * @retval None
02448   */
02449 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
02450 {
02451   /* Set the default configuration */
02452   TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
02453   TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
02454   TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
02455   TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
02456   TIM_ICInitStruct->TIM_ICFilter = 0x00;
02457 }
02458 
02459 /**
02460   * @brief  Configures the TIM peripheral according to the specified parameters
02461   *         in the TIM_ICInitStruct to measure an external PWM signal.
02462   * @param  TIMx: where x can be  1, 2, 3, 4, 8, 20 or 15 to select the TIM 
02463   *         peripheral.
02464   * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
02465   *         the configuration information for the specified TIM peripheral.
02466   * @retval None
02467   */
02468 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
02469 {
02470   uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
02471   uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
02472 
02473   /* Check the parameters */
02474   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02475 
02476   /* Select the Opposite Input Polarity */
02477   if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
02478   {
02479     icoppositepolarity = TIM_ICPolarity_Falling;
02480   }
02481   else
02482   {
02483     icoppositepolarity = TIM_ICPolarity_Rising;
02484   }
02485   /* Select the Opposite Input */
02486   if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
02487   {
02488     icoppositeselection = TIM_ICSelection_IndirectTI;
02489   }
02490   else
02491   {
02492     icoppositeselection = TIM_ICSelection_DirectTI;
02493   }
02494   if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
02495   {
02496     /* TI1 Configuration */
02497     TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
02498                TIM_ICInitStruct->TIM_ICFilter);
02499     /* Set the Input Capture Prescaler value */
02500     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02501     /* TI2 Configuration */
02502     TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
02503     /* Set the Input Capture Prescaler value */
02504     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02505   }
02506   else
02507   { 
02508     /* TI2 Configuration */
02509     TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
02510                TIM_ICInitStruct->TIM_ICFilter);
02511     /* Set the Input Capture Prescaler value */
02512     TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02513     /* TI1 Configuration */
02514     TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
02515     /* Set the Input Capture Prescaler value */
02516     TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
02517   }
02518 }
02519 
02520 /**
02521   * @brief  Gets the TIMx Input Capture 1 value.
02522   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02523   * @retval Capture Compare 1 Register value.
02524   */
02525 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
02526 {
02527   /* Check the parameters */
02528   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02529 
02530   /* Get the Capture 1 Register value */
02531   return TIMx->CCR1;
02532 }
02533 
02534 /**
02535   * @brief  Gets the TIMx Input Capture 2 value.
02536   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
02537   *         peripheral.
02538   * @retval Capture Compare 2 Register value.
02539   */
02540 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
02541 {
02542   /* Check the parameters */
02543   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02544 
02545   /* Get the Capture 2 Register value */
02546   return TIMx->CCR2;
02547 }
02548 
02549 /**
02550   * @brief  Gets the TIMx Input Capture 3 value.
02551   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02552   * @retval Capture Compare 3 Register value.
02553   */
02554 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
02555 {
02556   /* Check the parameters */
02557   assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
02558 
02559   /* Get the Capture 3 Register value */
02560   return TIMx->CCR3;
02561 }
02562 
02563 /**
02564   * @brief  Gets the TIMx Input Capture 4 value.
02565   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02566   * @retval Capture Compare 4 Register value.
02567   */
02568 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
02569 {
02570   /* Check the parameters */
02571   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02572 
02573   /* Get the Capture 4 Register value */
02574   return TIMx->CCR4;
02575 }
02576 
02577 /**
02578   * @brief  Sets the TIMx Input Capture 1 prescaler.
02579   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02580   * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
02581   *          This parameter can be one of the following values:
02582   *            @arg TIM_ICPSC_DIV1: no prescaler
02583   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02584   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02585   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02586   * @retval None
02587   */
02588 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02589 {
02590   /* Check the parameters */
02591   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
02592   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02593 
02594   /* Reset the IC1PSC Bits */
02595   TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC;
02596 
02597   /* Set the IC1PSC value */
02598   TIMx->CCMR1 |= TIM_ICPSC;
02599 }
02600 
02601 /**
02602   * @brief  Sets the TIMx Input Capture 2 prescaler.
02603   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
02604   *         peripheral.
02605   * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
02606   *          This parameter can be one of the following values:
02607   *            @arg TIM_ICPSC_DIV1: no prescaler
02608   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02609   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02610   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02611   * @retval None
02612   */
02613 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02614 {
02615   /* Check the parameters */
02616   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
02617   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02618 
02619   /* Reset the IC2PSC Bits */
02620   TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC;
02621 
02622   /* Set the IC2PSC value */
02623   TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8);
02624 }
02625 
02626 /**
02627   * @brief  Sets the TIMx Input Capture 3 prescaler.
02628   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02629   * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
02630   *          This parameter can be one of the following values:
02631   *            @arg TIM_ICPSC_DIV1: no prescaler
02632   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02633   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02634   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02635   * @retval None
02636   */
02637 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02638 {
02639   /* Check the parameters */
02640   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02641   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02642 
02643   /* Reset the IC3PSC Bits */
02644   TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
02645 
02646   /* Set the IC3PSC value */
02647   TIMx->CCMR2 |= TIM_ICPSC;
02648 }
02649 
02650 /**
02651   * @brief  Sets the TIMx Input Capture 4 prescaler.
02652   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
02653   * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
02654   *          This parameter can be one of the following values:
02655   *            @arg TIM_ICPSC_DIV1: no prescaler
02656   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
02657   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
02658   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
02659   * @retval None
02660   */
02661 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
02662 {  
02663   /* Check the parameters */
02664   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
02665   assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
02666 
02667   /* Reset the IC4PSC Bits */
02668   TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
02669 
02670   /* Set the IC4PSC value */
02671   TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
02672 }
02673 /**
02674   * @}
02675   */
02676 
02677 /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
02678  *  @brief   Advanced-control timers (TIM1 and TIM8) specific features
02679  *
02680 @verbatim   
02681  ===============================================================================
02682      ##### Advanced-control timers (TIM1 and TIM8) specific features #####
02683  ===============================================================================  
02684        
02685   *** TIM Driver: how to use the Break feature ***
02686   ================================================ 
02687   [..]
02688   After configuring the Timer channel(s) in the appropriate Output Compare mode: 
02689                          
02690        (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
02691            Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
02692            AOE(automatic output enable).
02693                
02694        (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
02695           
02696        (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
02697           
02698        (#) Once the break even occurs, the Timer's output signals are put in reset
02699            state or in a known state (according to the configuration made in
02700            TIM_BDTRConfig() function).
02701 
02702 @endverbatim
02703   * @{
02704   */
02705 
02706 /**
02707   * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
02708   *         and the AOE(automatic output enable).
02709   * @param  TIMx: where x can be  1, 8, 15, 16, 20 or 17 to select the TIM 
02710   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
02711   *         contains the BDTR Register configuration  information for the TIM peripheral.
02712   * @retval None
02713   */
02714 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
02715 {
02716   /* Check the parameters */
02717   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02718   assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
02719   assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
02720   assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
02721   assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
02722   assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
02723   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
02724 
02725   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
02726      the OSSI State, the dead time value and the Automatic Output Enable Bit */
02727   TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
02728              TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
02729              TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
02730              TIM_BDTRInitStruct->TIM_AutomaticOutput;
02731 }
02732 
02733 /**
02734   * @brief  Configures the Break1 feature.
02735   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM 
02736   * @param  TIM_Break1Polarity: specifies the Break1 polarity.
02737   *          This parameter can be one of the following values:
02738   *            @arg TIM_Break1Polarity_Low: Break1 input is active low
02739   *            @arg TIM_Break1Polarity_High: Break1 input is active high
02740   * @param  TIM_Break1Filter: specifies the Break1 filter value.
02741   *          This parameter must be a value between 0x00 and 0x0F
02742   * @retval None
02743   */
02744 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter)
02745 {   /* Check the parameters */
02746   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02747   assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter));
02748 
02749   /* Reset the BKP and BKF Bits */
02750   TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF);
02751   /* Configure the Break1 polarity and filter */
02752   TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16);
02753 }
02754 
02755 /**
02756   * @brief  Configures the Break2 feature.
02757   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIM 
02758   * @param  TIM_Break2Polarity: specifies the Break2 polarity.
02759   *          This parameter can be one of the following values:
02760   *            @arg TIM_Break2Polarity_Low: Break2 input is active low
02761   *            @arg TIM_Break2Polarity_High: Break2 input is active high
02762   * @param  TIM_Break2Filter: specifies the Break2 filter value.
02763   *          This parameter must be a value between 0x00 and 0x0F
02764   * @retval None
02765   */
02766 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter)
02767 {
02768   /* Check the parameters */
02769   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02770   assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter));
02771 
02772   /* Reset the BKP and BKF Bits */
02773   TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F);
02774 
02775   /* Configure the Break1 polarity and filter */
02776   TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20);
02777 }
02778 
02779 /**
02780   * @brief  Enables or disables the TIM Break1 input.
02781   * @param  TIMx: where x can be 1, 8, 20, 16 or 17 to select the TIMx peripheral.
02782   * @param  NewState: new state of the TIM Break1 input.
02783   *          This parameter can be: ENABLE or DISABLE.
02784   * @retval None
02785   */
02786 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
02787 {
02788   /* Check the parameters */
02789   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02790   assert_param(IS_FUNCTIONAL_STATE(NewState));
02791 
02792   if (NewState != DISABLE)
02793   {
02794     /* Enable the Break1 */
02795     TIMx->BDTR |= TIM_BDTR_BKE;
02796   }
02797   else
02798   {
02799     /* Disable the Break1 */
02800     TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE;
02801   } 
02802 }
02803 
02804 /**
02805   * @brief  Enables or disables the TIM Break2 input.
02806   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIMx peripheral.
02807   * @param  NewState: new state of the TIM Break2 input.
02808   *          This parameter can be: ENABLE or DISABLE.
02809   * @retval None
02810   */
02811 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
02812 {
02813   /* Check the parameters */
02814   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
02815   assert_param(IS_FUNCTIONAL_STATE(NewState));
02816 
02817   if (NewState != DISABLE)
02818   {
02819     /* Enable the Break1 */
02820     TIMx->BDTR |= TIM_BDTR_BK2E;
02821   }
02822   else
02823   {
02824     /* Disable the Break1 */
02825     TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E;
02826   }
02827 }
02828 
02829 /**
02830   * @brief  Fills each TIM_BDTRInitStruct member with its default value.
02831   * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
02832   *         will be initialized.
02833   * @retval None
02834   */
02835 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
02836 {
02837   /* Set the default configuration */
02838   TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
02839   TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
02840   TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
02841   TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
02842   TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
02843   TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
02844   TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
02845 }
02846 
02847 /**
02848   * @brief  Enables or disables the TIM peripheral Main Outputs.
02849   * @param  TIMx: where x can be 1, 8, 15, 16, 20 or 17 to select the TIMx peripheral.
02850   * @param  NewState: new state of the TIM peripheral Main Outputs.
02851   *          This parameter can be: ENABLE or DISABLE.
02852   * @retval None
02853   */
02854 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
02855 {
02856   /* Check the parameters */
02857   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02858   assert_param(IS_FUNCTIONAL_STATE(NewState));
02859 
02860   if (NewState != DISABLE)
02861   {
02862     /* Enable the TIM Main Output */
02863     TIMx->BDTR |= TIM_BDTR_MOE;
02864   }
02865   else
02866   {
02867     /* Disable the TIM Main Output */
02868     TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
02869   }  
02870 }
02871 
02872 /**
02873   * @brief  Selects the TIM peripheral Commutation event.
02874   * @param  TIMx: where x can be  1, 8, 15, 16, 20 or 17 to select the TIMx peripheral
02875   * @param  NewState: new state of the Commutation event.
02876   *          This parameter can be: ENABLE or DISABLE.
02877   * @retval None
02878   */
02879 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
02880 {
02881   /* Check the parameters */
02882   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02883   assert_param(IS_FUNCTIONAL_STATE(NewState));
02884 
02885   if (NewState != DISABLE)
02886   {
02887     /* Set the COM Bit */
02888     TIMx->CR2 |= TIM_CR2_CCUS;
02889   }
02890   else
02891   {
02892     /* Reset the COM Bit */
02893     TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
02894   }
02895 }
02896 
02897 /**
02898   * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
02899   * @param  TIMx: where x can be  1 or 8 or 20 to select the TIMx peripheral
02900   * @param  NewState: new state of the Capture Compare Preload Control bit
02901   *          This parameter can be: ENABLE or DISABLE.
02902   * @retval None
02903   */
02904 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
02905 { 
02906   /* Check the parameters */
02907   assert_param(IS_TIM_LIST6_PERIPH(TIMx));
02908   assert_param(IS_FUNCTIONAL_STATE(NewState));
02909   if (NewState != DISABLE)
02910   {
02911     /* Set the CCPC Bit */
02912     TIMx->CR2 |= TIM_CR2_CCPC;
02913   }
02914   else
02915   {
02916     /* Reset the CCPC Bit */
02917     TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
02918   }
02919 }
02920 /**
02921   * @}
02922   */
02923 
02924 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions
02925  *  @brief    Interrupts, DMA and flags management functions 
02926  *
02927 @verbatim   
02928  ===============================================================================
02929          ##### Interrupts, DMA and flags management functions #####
02930  ===============================================================================  
02931 
02932 @endverbatim
02933   * @{
02934   */
02935 
02936 /**
02937   * @brief  Enables or disables the specified TIM interrupts.
02938   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIMx peripheral.
02939   * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
02940   *          This parameter can be any combination of the following values:
02941   *            @arg TIM_IT_Update: TIM update Interrupt source
02942   *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
02943   *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
02944   *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
02945   *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
02946   *            @arg TIM_IT_COM: TIM Commutation Interrupt source
02947   *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
02948   *            @arg TIM_IT_Break: TIM Break Interrupt source
02949   *  
02950   * @note   For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
02951   * @note   For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
02952   *          TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
02953   * @note   For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
02954   *          be used: TIM_IT_Update or TIM_IT_CC1   
02955   * @note   TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 
02956   *        
02957   * @param  NewState: new state of the TIM interrupts.
02958   *          This parameter can be: ENABLE or DISABLE.
02959   * @retval None
02960   */
02961 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
02962 {  
02963   /* Check the parameters */
02964   assert_param(IS_TIM_ALL_PERIPH(TIMx));
02965   assert_param(IS_TIM_IT(TIM_IT));
02966   assert_param(IS_FUNCTIONAL_STATE(NewState));
02967   
02968   if (NewState != DISABLE)
02969   {
02970     /* Enable the Interrupt sources */
02971     TIMx->DIER |= TIM_IT;
02972   }
02973   else
02974   {
02975     /* Disable the Interrupt sources */
02976     TIMx->DIER &= (uint16_t)~TIM_IT;
02977   }
02978 }
02979 
02980 /**
02981   * @brief  Configures the TIMx event to be generate by software.
02982   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
02983   * @param  TIM_EventSource: specifies the event source.
02984   *          This parameter can be one or more of the following values:    
02985   *            @arg TIM_EventSource_Update: Timer update Event source
02986   *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
02987   *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
02988   *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
02989   *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
02990   *            @arg TIM_EventSource_COM: Timer COM event source  
02991   *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
02992   *            @arg TIM_EventSource_Break: Timer Break event source
02993   * 
02994   * @note   TIM6 and TIM7 can only generate an update event. 
02995   * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
02996   *        
02997   * @retval None
02998   */
02999 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
03000 { 
03001   /* Check the parameters */
03002   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03003   assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
03004  
03005   /* Set the event sources */
03006   TIMx->EGR = TIM_EventSource;
03007 }
03008 
03009 /**
03010   * @brief  Checks whether the specified TIM flag is set or not.
03011   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03012   * @param  TIM_FLAG: specifies the flag to check.
03013   *          This parameter can be one of the following values:
03014   *            @arg TIM_FLAG_Update: TIM update Flag
03015   *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
03016   *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
03017   *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
03018   *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
03019   *            @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
03020   *            @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag  
03021   *            @arg TIM_FLAG_COM: TIM Commutation Flag
03022   *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
03023   *            @arg TIM_FLAG_Break: TIM Break Flag
03024   *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
03025   *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
03026   *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
03027   *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
03028   *
03029   * @note   TIM6 and TIM7 can have only one update flag. 
03030   * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.    
03031   *
03032   * @retval The new state of TIM_FLAG (SET or RESET).
03033   */
03034 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG)
03035 { 
03036   ITStatus bitstatus = RESET;  
03037   /* Check the parameters */
03038   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03039   assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
03040 
03041   
03042   if ((TIMx->SR & TIM_FLAG) != RESET)
03043   {
03044     bitstatus = SET;
03045   }
03046   else
03047   {
03048     bitstatus = RESET;
03049   }
03050   return bitstatus;
03051 }
03052 
03053 /**
03054   * @brief  Clears the TIMx's pending flags.
03055   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03056   * @param  TIM_FLAG: specifies the flag bit to clear.
03057   *          This parameter can be any combination of the following values:
03058   *            @arg TIM_FLAG_Update: TIM update Flag
03059   *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
03060   *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
03061   *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
03062   *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
03063   *            @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag
03064   *            @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag               
03065   *            @arg TIM_FLAG_COM: TIM Commutation Flag
03066   *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
03067   *            @arg TIM_FLAG_Break: TIM Break Flag
03068   *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
03069   *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
03070   *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
03071   *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
03072   *
03073   * @note   TIM6 and TIM7 can have only one update flag. 
03074   * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
03075   *    
03076   * @retval None
03077   */
03078 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
03079 {  
03080   /* Check the parameters */
03081   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03082    
03083   /* Clear the flags */
03084   TIMx->SR = (uint16_t)~TIM_FLAG;
03085 }
03086 
03087 /**
03088   * @brief  Checks whether the TIM interrupt has occurred or not.
03089   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03090   * @param  TIM_IT: specifies the TIM interrupt source to check.
03091   *          This parameter can be one of the following values:
03092   *            @arg TIM_IT_Update: TIM update Interrupt source
03093   *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
03094   *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
03095   *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
03096   *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
03097   *            @arg TIM_IT_COM: TIM Commutation Interrupt source
03098   *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
03099   *            @arg TIM_IT_Break: TIM Break Interrupt source
03100   *
03101   * @note   TIM6 and TIM7 can generate only an update interrupt.
03102   * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
03103   *     
03104   * @retval The new state of the TIM_IT(SET or RESET).
03105   */
03106 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
03107 {
03108   ITStatus bitstatus = RESET;  
03109   uint16_t itstatus = 0x0, itenable = 0x0;
03110   /* Check the parameters */
03111   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03112   assert_param(IS_TIM_GET_IT(TIM_IT));
03113    
03114   itstatus = TIMx->SR & TIM_IT;
03115   
03116   itenable = TIMx->DIER & TIM_IT;
03117   if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
03118   {
03119     bitstatus = SET;
03120   }
03121   else
03122   {
03123     bitstatus = RESET;
03124   }
03125   return bitstatus;
03126 }
03127 
03128 /**
03129   * @brief  Clears the TIMx's interrupt pending bits.
03130   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03131   * @param  TIM_IT: specifies the pending bit to clear.
03132   *          This parameter can be any combination of the following values:
03133   *            @arg TIM_IT_Update: TIM1 update Interrupt source
03134   *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
03135   *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
03136   *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
03137   *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
03138   *            @arg TIM_IT_COM: TIM Commutation Interrupt source
03139   *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
03140   *            @arg TIM_IT_Break: TIM Break Interrupt source
03141   *
03142   * @note   TIM6 and TIM7 can generate only an update interrupt.
03143   * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
03144   *      
03145   * @retval None
03146   */
03147 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
03148 {
03149   /* Check the parameters */
03150   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03151 
03152   /* Clear the IT pending Bit */
03153   TIMx->SR = (uint16_t)~TIM_IT;
03154 }
03155 
03156 /**
03157   * @brief  Configures the TIMx's DMA interface.
03158   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
03159   * @param  TIM_DMABase: DMA Base address.
03160   *          This parameter can be one of the following values:
03161   *            @arg TIM_DMABase_CR1  
03162   *            @arg TIM_DMABase_CR2
03163   *            @arg TIM_DMABase_SMCR
03164   *            @arg TIM_DMABase_DIER
03165   *            @arg TIM1_DMABase_SR
03166   *            @arg TIM_DMABase_EGR
03167   *            @arg TIM_DMABase_CCMR1
03168   *            @arg TIM_DMABase_CCMR2
03169   *            @arg TIM_DMABase_CCER
03170   *            @arg TIM_DMABase_CNT   
03171   *            @arg TIM_DMABase_PSC   
03172   *            @arg TIM_DMABase_ARR
03173   *            @arg TIM_DMABase_RCR
03174   *            @arg TIM_DMABase_CCR1
03175   *            @arg TIM_DMABase_CCR2
03176   *            @arg TIM_DMABase_CCR3  
03177   *            @arg TIM_DMABase_CCR4
03178   *            @arg TIM_DMABase_BDTR
03179   *            @arg TIM_DMABase_DCR
03180   * @param  TIM_DMABurstLength: DMA Burst length. This parameter can be one value
03181   *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
03182   * @retval None
03183   */
03184 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
03185 {
03186   /* Check the parameters */
03187   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
03188   assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
03189   assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
03190 
03191   /* Set the DMA Base and the DMA Burst Length */
03192   TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
03193 }
03194 
03195 /**
03196   * @brief  Enables or disables the TIMx's DMA Requests.
03197   * @param  TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03198   * @param  TIM_DMASource: specifies the DMA Request sources.
03199   *          This parameter can be any combination of the following values:
03200   *            @arg TIM_DMA_Update: TIM update Interrupt source
03201   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03202   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03203   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03204   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03205   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03206   *            @arg TIM_DMA_Trigger: TIM Trigger DMA source
03207   * @param  NewState: new state of the DMA Request sources.
03208   *          This parameter can be: ENABLE or DISABLE.
03209   * @retval None
03210   */
03211 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
03212 { 
03213   /* Check the parameters */
03214   assert_param(IS_TIM_ALL_PERIPH(TIMx));
03215   assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
03216   assert_param(IS_FUNCTIONAL_STATE(NewState));
03217   
03218   if (NewState != DISABLE)
03219   {
03220     /* Enable the DMA sources */
03221     TIMx->DIER |= TIM_DMASource; 
03222   }
03223   else
03224   {
03225     /* Disable the DMA sources */
03226     TIMx->DIER &= (uint16_t)~TIM_DMASource;
03227   }
03228 }
03229 
03230 /**
03231   * @brief  Selects the TIMx peripheral Capture Compare DMA source.
03232   * @param  TIMx: where x can be  1, 2, 3, 4, 8, 15, 16, 20 or 17 to select the TIM peripheral.
03233   * @param  NewState: new state of the Capture Compare DMA source
03234   *          This parameter can be: ENABLE or DISABLE.
03235   * @retval None
03236   */
03237 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
03238 {
03239   /* Check the parameters */
03240   assert_param(IS_TIM_LIST1_PERIPH(TIMx));
03241   assert_param(IS_FUNCTIONAL_STATE(NewState));
03242 
03243   if (NewState != DISABLE)
03244   {
03245     /* Set the CCDS Bit */
03246     TIMx->CR2 |= TIM_CR2_CCDS;
03247   }
03248   else
03249   {
03250     /* Reset the CCDS Bit */
03251     TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
03252   }
03253 }
03254 /**
03255   * @}
03256   */
03257 
03258 /** @defgroup TIM_Group6 Clocks management functions
03259  *  @brief    Clocks management functions
03260  *
03261 @verbatim   
03262  ===============================================================================
03263                    ##### Clocks management functions #####
03264  ===============================================================================  
03265 
03266 @endverbatim
03267   * @{
03268   */
03269 
03270 /**
03271   * @brief  Configures the TIMx internal Clock
03272   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
03273   *         peripheral.
03274   * @retval None
03275   */
03276 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
03277 {
03278   /* Check the parameters */
03279   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03280 
03281   /* Disable slave mode to clock the prescaler directly with the internal clock */
03282   TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
03283 }
03284 
03285 /**
03286   * @brief  Configures the TIMx Internal Trigger as External Clock
03287   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
03288   *         peripheral.
03289   * @param  TIM_InputTriggerSource: Trigger source.
03290   *          This parameter can be one of the following values:
03291   *            @arg TIM_TS_ITR0: Internal Trigger 0
03292   *            @arg TIM_TS_ITR1: Internal Trigger 1
03293   *            @arg TIM_TS_ITR2: Internal Trigger 2
03294   *            @arg TIM_TS_ITR3: Internal Trigger 3
03295   * @retval None
03296   */
03297 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
03298 {
03299   /* Check the parameters */
03300   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03301   assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
03302 
03303   /* Select the Internal Trigger */
03304   TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
03305 
03306   /* Select the External clock mode1 */
03307   TIMx->SMCR |= TIM_SlaveMode_External1;
03308 }
03309 
03310 /**
03311   * @brief  Configures the TIMx Trigger as External Clock
03312   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15  
03313   *         to select the TIM peripheral.
03314   * @param  TIM_TIxExternalCLKSource: Trigger source.
03315   *          This parameter can be one of the following values:
03316   *            @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
03317   *            @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
03318   *            @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
03319   * @param  TIM_ICPolarity: specifies the TIx Polarity.
03320   *          This parameter can be one of the following values:
03321   *            @arg TIM_ICPolarity_Rising
03322   *            @arg TIM_ICPolarity_Falling
03323   * @param  ICFilter: specifies the filter value.
03324   *          This parameter must be a value between 0x0 and 0xF.
03325   * @retval None
03326   */
03327 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
03328                                 uint16_t TIM_ICPolarity, uint16_t ICFilter)
03329 {
03330   /* Check the parameters */
03331   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03332   assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
03333   assert_param(IS_TIM_IC_FILTER(ICFilter));
03334 
03335   /* Configure the Timer Input Clock Source */
03336   if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
03337   {
03338     TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
03339   }
03340   else
03341   {
03342     TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
03343   }
03344   /* Select the Trigger source */
03345   TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
03346   /* Select the External clock mode1 */
03347   TIMx->SMCR |= TIM_SlaveMode_External1;
03348 }
03349 
03350 /**
03351   * @brief  Configures the External clock Mode1
03352   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
03353   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
03354   *          This parameter can be one of the following values:
03355   *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
03356   *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
03357   *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
03358   *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
03359   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
03360   *          This parameter can be one of the following values:
03361   *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
03362   *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
03363   * @param  ExtTRGFilter: External Trigger Filter.
03364   *          This parameter must be a value between 0x00 and 0x0F
03365   * @retval None
03366   */
03367 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
03368                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
03369 {
03370   uint16_t tmpsmcr = 0;
03371 
03372   /* Check the parameters */
03373   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
03374   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
03375   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
03376   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
03377   /* Configure the ETR Clock source */
03378   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
03379   
03380   /* Get the TIMx SMCR register value */
03381   tmpsmcr = TIMx->SMCR;
03382 
03383   /* Reset the SMS Bits */
03384   tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
03385 
03386   /* Select the External clock mode1 */
03387   tmpsmcr |= TIM_SlaveMode_External1;
03388 
03389   /* Select the Trigger selection : ETRF */
03390   tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
03391   tmpsmcr |= TIM_TS_ETRF;
03392 
03393   /* Write to TIMx SMCR */
03394   TIMx->SMCR = tmpsmcr;
03395 }
03396 
03397 /**
03398   * @brief  Configures the External clock Mode2
03399   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
03400   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
03401   *          This parameter can be one of the following values:
03402   *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
03403   *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
03404   *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
03405   *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
03406   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
03407   *          This parameter can be one of the following values:
03408   *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
03409   *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
03410   * @param  ExtTRGFilter: External Trigger Filter.
03411   *          This parameter must be a value between 0x00 and 0x0F
03412   * @retval None
03413   */
03414 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
03415                              uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
03416 {
03417   /* Check the parameters */
03418   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
03419   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
03420   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
03421   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
03422 
03423   /* Configure the ETR Clock source */
03424   TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
03425 
03426   /* Enable the External clock mode2 */
03427   TIMx->SMCR |= TIM_SMCR_ECE;
03428 }
03429 /**
03430   * @}
03431   */
03432 
03433 /** @defgroup TIM_Group7 Synchronization management functions
03434  *  @brief    Synchronization management functions 
03435  *
03436 @verbatim   
03437  ===============================================================================
03438                  ##### Synchronization management functions #####
03439  ===============================================================================  
03440                          
03441   *** TIM Driver: how to use it in synchronization Mode ***
03442   ========================================================= 
03443   [..] Case of two/several Timers
03444        
03445        (#) Configure the Master Timers using the following functions:
03446            (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 
03447            (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);  
03448        (#) Configure the Slave Timers using the following functions: 
03449            (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
03450            (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
03451           
03452   [..] Case of Timers and external trigger(ETR pin)
03453            
03454        (#) Configure the External trigger using this function:
03455            (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
03456                                    uint16_t ExtTRGFilter);
03457        (#) Configure the Slave Timers using the following functions: 
03458            (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
03459            (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
03460 
03461 @endverbatim
03462   * @{
03463   */
03464 
03465 /**
03466   * @brief  Selects the Input Trigger source
03467   * @param  TIMx: where x can be  1, 2, 3, 4, 8, 20 or 15  
03468   *         to select the TIM peripheral.
03469   * @param  TIM_InputTriggerSource: The Input Trigger source.
03470   *          This parameter can be one of the following values:
03471   *            @arg TIM_TS_ITR0: Internal Trigger 0
03472   *            @arg TIM_TS_ITR1: Internal Trigger 1
03473   *            @arg TIM_TS_ITR2: Internal Trigger 2
03474   *            @arg TIM_TS_ITR3: Internal Trigger 3
03475   *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
03476   *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
03477   *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
03478   *            @arg TIM_TS_ETRF: External Trigger input
03479   * @retval None
03480   */
03481 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
03482 {
03483   uint16_t tmpsmcr = 0;
03484 
03485   /* Check the parameters */
03486   assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
03487   assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
03488 
03489   /* Get the TIMx SMCR register value */
03490   tmpsmcr = TIMx->SMCR;
03491 
03492   /* Reset the TS Bits */
03493   tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
03494 
03495   /* Set the Input Trigger source */
03496   tmpsmcr |= TIM_InputTriggerSource;
03497 
03498   /* Write to TIMx SMCR */
03499   TIMx->SMCR = tmpsmcr;
03500 }
03501 
03502 /**
03503   * @brief  Selects the TIMx Trigger Output Mode.
03504   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral.
03505   *     
03506   * @param  TIM_TRGOSource: specifies the Trigger Output source.
03507   *   This parameter can be one of the following values:
03508   *
03509   *  - For all TIMx
03510   *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
03511   *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
03512   *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
03513   *
03514   *  - For all TIMx except TIM6 and TIM7
03515   *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
03516   *                                     is to be set, as soon as a capture or compare match occurs(TRGO)
03517   *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
03518   *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
03519   *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
03520   *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
03521   *
03522   * @retval None
03523   */
03524 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
03525 {
03526   /* Check the parameters */
03527   assert_param(IS_TIM_LIST7_PERIPH(TIMx));
03528   assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
03529 
03530   /* Reset the MMS Bits */
03531   TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
03532   /* Select the TRGO source */
03533   TIMx->CR2 |=  TIM_TRGOSource;
03534 }
03535 
03536 /**
03537   * @brief  Selects the TIMx Trigger Output Mode2 (TRGO2).
03538   * @param  TIMx: where x can be 1 or 8 or 20 to select the TIM peripheral.
03539   *     
03540   * @param  TIM_TRGO2Source: specifies the Trigger Output source.
03541   *   This parameter can be one of the following values:
03542   *
03543   *  - For all TIMx
03544   *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO2)
03545   *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2)
03546   *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2)
03547   *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
03548   *                                     is to be set, as soon as a capture or compare match occurs(TRGO2)
03549   *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2)
03550   *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2)
03551   *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2)
03552   *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2)
03553   *            @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2)
03554   *            @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2)
03555   *            @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising  are used as the trigger output(TRGO2)
03556   *            @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
03557   *            @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2)
03558   *            @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2)
03559   *
03560   * @retval None
03561   */
03562 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source)
03563 {
03564   /* Check the parameters */
03565   assert_param(IS_TIM_LIST4_PERIPH(TIMx));
03566   assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source));
03567 
03568   /* Reset the MMS Bits */
03569   TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2;
03570   /* Select the TRGO source */
03571   TIMx->CR2 |=  TIM_TRGO2Source;
03572 }
03573 
03574 /**
03575   * @brief  Selects the TIMx Slave Mode.
03576   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM peripheral.
03577   * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
03578   *          This parameter can be one of the following values:
03579   *            @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize 
03580   *                                      the counter and triggers an update of the registers
03581   *            @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high
03582   *            @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI
03583   *            @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
03584   *            @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI)
03585   *                                                      reinitializes the counter, generates an update 
03586   *                                                      of the registers and starts the counter.
03587   * @retval None
03588   */
03589 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode)
03590 {
03591   /* Check the parameters */
03592   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03593   assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
03594 
03595   /* Reset the SMS Bits */
03596   TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS;
03597 
03598   /* Select the Slave Mode */
03599   TIMx->SMCR |= (uint32_t)TIM_SlaveMode;
03600 }
03601 
03602 /**
03603   * @brief  Sets or Resets the TIMx Master/Slave Mode.
03604   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM peripheral.
03605   * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
03606   *          This parameter can be one of the following values:
03607   *            @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
03608   *                                             and its slaves (through TRGO)
03609   *            @arg TIM_MasterSlaveMode_Disable: No action
03610   * @retval None
03611   */
03612 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
03613 {
03614   /* Check the parameters */
03615   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03616   assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
03617 
03618   /* Reset the MSM Bit */
03619   TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
03620   
03621   /* Set or Reset the MSM Bit */
03622   TIMx->SMCR |= TIM_MasterSlaveMode;
03623 }
03624 
03625 /**
03626   * @brief  Configures the TIMx External Trigger (ETR).
03627   * @param  TIMx: where x can be  1, 2, 3, 4, 20 or 8 to select the TIM peripheral.
03628   * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
03629   *          This parameter can be one of the following values:
03630   *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
03631   *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
03632   *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
03633   *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
03634   * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
03635   *          This parameter can be one of the following values:
03636   *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
03637   *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
03638   * @param  ExtTRGFilter: External Trigger Filter.
03639   *          This parameter must be a value between 0x00 and 0x0F
03640   * @retval None
03641   */
03642 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
03643                    uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
03644 {
03645   uint16_t tmpsmcr = 0;
03646 
03647   /* Check the parameters */
03648   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
03649   assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
03650   assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
03651   assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
03652 
03653   tmpsmcr = TIMx->SMCR;
03654 
03655   /* Reset the ETR Bits */
03656   tmpsmcr &= SMCR_ETR_MASK;
03657 
03658   /* Set the Prescaler, the Filter value and the Polarity */
03659   tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
03660 
03661   /* Write to TIMx SMCR */
03662   TIMx->SMCR = tmpsmcr;
03663 }
03664 /**
03665   * @}
03666   */
03667 
03668 /** @defgroup TIM_Group8 Specific interface management functions
03669  *  @brief    Specific interface management functions 
03670  *
03671 @verbatim   
03672  ===============================================================================
03673               ##### Specific interface management functions #####
03674  ===============================================================================  
03675 
03676 @endverbatim
03677   * @{
03678   */
03679 
03680 /**
03681   * @brief  Configures the TIMx Encoder Interface.
03682   * @param  TIMx: where x can be 1, 2, 3, 4, 20 or 8 to select the TIM 
03683   *         peripheral.
03684   * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
03685   *          This parameter can be one of the following values:
03686   *            @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
03687   *            @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
03688   *            @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
03689   *                                       on the level of the other input.
03690   * @param  TIM_IC1Polarity: specifies the IC1 Polarity
03691   *          This parameter can be one of the following values:
03692   *            @arg TIM_ICPolarity_Falling: IC Falling edge.
03693   *            @arg TIM_ICPolarity_Rising: IC Rising edge.
03694   * @param  TIM_IC2Polarity: specifies the IC2 Polarity
03695   *          This parameter can be one of the following values:
03696   *            @arg TIM_ICPolarity_Falling: IC Falling edge.
03697   *            @arg TIM_ICPolarity_Rising: IC Rising edge.
03698   * @retval None
03699   */
03700 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
03701                                 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
03702 {
03703   uint16_t tmpsmcr = 0;
03704   uint16_t tmpccmr1 = 0;
03705   uint16_t tmpccer = 0;
03706     
03707   /* Check the parameters */
03708   assert_param(IS_TIM_LIST3_PERIPH(TIMx));
03709   assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
03710   assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
03711   assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
03712 
03713   /* Get the TIMx SMCR register value */
03714   tmpsmcr = TIMx->SMCR;
03715 
03716   /* Get the TIMx CCMR1 register value */
03717   tmpccmr1 = TIMx->CCMR1;
03718 
03719   /* Get the TIMx CCER register value */
03720   tmpccer = TIMx->CCER;
03721 
03722   /* Set the encoder Mode */
03723   tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
03724   tmpsmcr |= TIM_EncoderMode;
03725 
03726   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
03727   tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
03728   tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
03729 
03730   /* Set the TI1 and the TI2 Polarities */
03731   tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
03732   tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
03733 
03734   /* Write to TIMx SMCR */
03735   TIMx->SMCR = tmpsmcr;
03736 
03737   /* Write to TIMx CCMR1 */
03738   TIMx->CCMR1 = tmpccmr1;
03739 
03740   /* Write to TIMx CCER */
03741   TIMx->CCER = tmpccer;
03742 }
03743 
03744 /**
03745   * @brief  Enables or disables the TIMx's Hall sensor interface.
03746   * @param  TIMx: where x can be 1, 2, 3, 4, 8, 20 or 15 to select the TIM 
03747   *         peripheral.
03748   * @param  NewState: new state of the TIMx Hall sensor interface.
03749   *          This parameter can be: ENABLE or DISABLE.
03750   * @retval None
03751   */
03752 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
03753 {
03754   /* Check the parameters */
03755   assert_param(IS_TIM_LIST2_PERIPH(TIMx));
03756   assert_param(IS_FUNCTIONAL_STATE(NewState));
03757 
03758   if (NewState != DISABLE)
03759   {
03760     /* Set the TI1S Bit */
03761     TIMx->CR2 |= TIM_CR2_TI1S;
03762   }
03763   else
03764   {
03765     /* Reset the TI1S Bit */
03766     TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
03767   }
03768 }
03769 /**
03770   * @}
03771   */
03772 
03773 /** @defgroup TIM_Group9 Specific remapping management function
03774  *  @brief   Specific remapping management function
03775  *
03776 @verbatim   
03777  ===============================================================================
03778                ##### Specific remapping management function #####
03779  ===============================================================================  
03780 
03781 @endverbatim
03782   * @{
03783   */
03784 
03785 /**
03786   * @brief  Configures the TIM16 Remapping input Capabilities.
03787   * @param TIMx: where x can be 1, 8, 20 or 16 to select the TIM peripheral.
03788   * @param TIM_Remap: specifies the TIM input remapping source.
03789   *   This parameter can be one of the following values:
03790   *            @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO.
03791   *            @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock.
03792   *            @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock.  
03793   *            @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock. 
03794   *            @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1.
03795   *            @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2.
03796   *            @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3.  
03797   *            @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1.
03798   *            @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2.
03799   *            @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3. 
03800   *            @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1.
03801   *            @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2.
03802   *            @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3.
03803   *            @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1.
03804   *            @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2.
03805   *            @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3.  
03806   *            @arg TIM20_ADC3_AWDG1: TIM20 ETR is connected to ADC3 AWDG1.
03807   *            @arg TIM20_ADC3_AWDG2: TIM20 ETR is connected to ADC3 AWDG2.
03808   *            @arg TIM20_ADC3_AWDG3: TIM20 ETR is connected to ADC3 AWDG3.
03809   *            @arg TIM20_ADC4_AWDG1: TIM20 ETR is connected to ADC4 AWDG1.
03810   *            @arg TIM20_ADC4_AWDG2: TIM20 ETR is connected to ADC4 AWDG2.
03811   *            @arg TIM20_ADC4_AWDG3: TIM20 ETR is connected to ADC4 AWDG3.   
03812   * @retval : None
03813   */
03814 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
03815 {
03816  /* Check the parameters */
03817   assert_param(IS_TIM_LIST8_PERIPH(TIMx));
03818   assert_param(IS_TIM_REMAP(TIM_Remap));
03819 
03820   /* Set the Timer remapping configuration */
03821   TIMx->OR =  TIM_Remap;
03822 }
03823 /**
03824   * @}
03825   */
03826 
03827 /**
03828   * @brief  Configure the TI1 as Input.
03829   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 
03830   *         to select the TIM peripheral.
03831   * @param  TIM_ICPolarity : The Input Polarity.
03832   *          This parameter can be one of the following values:
03833   *            @arg TIM_ICPolarity_Rising
03834   *            @arg TIM_ICPolarity_Falling
03835   *            @arg TIM_ICPolarity_BothEdge  
03836   * @param  TIM_ICSelection: specifies the input to be used.
03837   *          This parameter can be one of the following values:
03838   *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
03839   *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
03840   *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
03841   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
03842   *          This parameter must be a value between 0x00 and 0x0F.
03843   * @retval None
03844   */
03845 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
03846                        uint16_t TIM_ICFilter)
03847 {
03848   uint32_t tmpccmr1 = 0, tmpccer = 0;
03849 
03850   /* Disable the Channel 1: Reset the CC1E Bit */
03851   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
03852   tmpccmr1 = TIMx->CCMR1;
03853   tmpccer = TIMx->CCER;
03854 
03855   /* Select the Input and set the filter */
03856   tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F);
03857   tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4));
03858 
03859   /* Select the Polarity and set the CC1E Bit */
03860   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
03861   tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E);
03862 
03863   /* Write to TIMx CCMR1 and CCER registers */
03864   TIMx->CCMR1 = tmpccmr1;
03865   TIMx->CCER = tmpccer;
03866 }
03867 
03868 /**
03869   * @brief  Configure the TI2 as Input.
03870   * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
03871   *         peripheral.
03872   * @param  TIM_ICPolarity : The Input Polarity.
03873   *          This parameter can be one of the following values:
03874   *            @arg TIM_ICPolarity_Rising
03875   *            @arg TIM_ICPolarity_Falling
03876   *            @arg TIM_ICPolarity_BothEdge   
03877   * @param  TIM_ICSelection: specifies the input to be used.
03878   *          This parameter can be one of the following values:
03879   *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
03880   *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
03881   *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
03882   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
03883   *          This parameter must be a value between 0x00 and 0x0F.
03884   * @retval None
03885   */
03886 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
03887                        uint16_t TIM_ICFilter)
03888 {
03889   uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
03890 
03891   /* Disable the Channel 2: Reset the CC2E Bit */
03892   TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
03893   tmpccmr1 = TIMx->CCMR1;
03894   tmpccer = TIMx->CCER;
03895   tmp = (uint16_t)(TIM_ICPolarity << 4);
03896 
03897   /* Select the Input and set the filter */
03898   tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F);
03899   tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12);
03900   tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8);
03901 
03902   /* Select the Polarity and set the CC2E Bit */
03903   tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
03904   tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
03905 
03906   /* Write to TIMx CCMR1 and CCER registers */
03907   TIMx->CCMR1 = tmpccmr1 ;
03908   TIMx->CCER = tmpccer;
03909 }
03910 
03911 /**
03912   * @brief  Configure the TI3 as Input.
03913   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
03914   * @param  TIM_ICPolarity : The Input Polarity.
03915   *          This parameter can be one of the following values:
03916   *            @arg TIM_ICPolarity_Rising
03917   *            @arg TIM_ICPolarity_Falling
03918   *            @arg TIM_ICPolarity_BothEdge         
03919   * @param  TIM_ICSelection: specifies the input to be used.
03920   *          This parameter can be one of the following values:
03921   *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
03922   *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
03923   *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
03924   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
03925   *          This parameter must be a value between 0x00 and 0x0F.
03926   * @retval None
03927   */
03928 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
03929                        uint16_t TIM_ICFilter)
03930 {
03931   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
03932 
03933   /* Disable the Channel 3: Reset the CC3E Bit */
03934   TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
03935   tmpccmr2 = TIMx->CCMR2;
03936   tmpccer = TIMx->CCER;
03937   tmp = (uint16_t)(TIM_ICPolarity << 8);
03938 
03939   /* Select the Input and set the filter */
03940   tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
03941   tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
03942 
03943   /* Select the Polarity and set the CC3E Bit */
03944   tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
03945   tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
03946 
03947   /* Write to TIMx CCMR2 and CCER registers */
03948   TIMx->CCMR2 = tmpccmr2;
03949   TIMx->CCER = tmpccer;
03950 }
03951 
03952 /**
03953   * @brief  Configure the TI4 as Input.
03954   * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
03955   * @param  TIM_ICPolarity : The Input Polarity.
03956   *          This parameter can be one of the following values:
03957   *            @arg TIM_ICPolarity_Rising
03958   *            @arg TIM_ICPolarity_Falling
03959   *            @arg TIM_ICPolarity_BothEdge     
03960   * @param  TIM_ICSelection: specifies the input to be used.
03961   *          This parameter can be one of the following values:
03962   *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
03963   *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
03964   *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
03965   * @param  TIM_ICFilter: Specifies the Input Capture Filter.
03966   *          This parameter must be a value between 0x00 and 0x0F.
03967   * @retval None
03968   */
03969 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
03970                        uint16_t TIM_ICFilter)
03971 {
03972   uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
03973 
03974   /* Disable the Channel 4: Reset the CC4E Bit */
03975   TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
03976   tmpccmr2 = TIMx->CCMR2;
03977   tmpccer = TIMx->CCER;
03978   tmp = (uint16_t)(TIM_ICPolarity << 12);
03979 
03980   /* Select the Input and set the filter */
03981   tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
03982   tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
03983   tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
03984 
03985   /* Select the Polarity and set the CC4E Bit */
03986   tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
03987   tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
03988 
03989   /* Write to TIMx CCMR2 and CCER registers */
03990   TIMx->CCMR2 = tmpccmr2;
03991   TIMx->CCER = tmpccer ;
03992 }
03993 
03994 /**
03995   * @}
03996   */
03997 
03998 /**
03999   * @}
04000   */
04001 
04002 /**
04003   * @}
04004   */
04005 
04006 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/