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STM32F3-Discovery
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stm32f30x_spi.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_spi.h 00004 * @author MCD Application Team 00005 * @version V1.2.3 00006 * @date 10-July-2015 00007 * @brief This file contains all the functions prototypes for the SPI 00008 * firmware library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F30x_SPI_H 00031 #define __STM32F30x_SPI_H 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f30x.h" 00039 00040 /** @addtogroup STM32F30x_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup SPI 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 00050 /** 00051 * @brief SPI Init structure definition 00052 */ 00053 00054 typedef struct 00055 { 00056 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 00057 This parameter can be a value of @ref SPI_data_direction */ 00058 00059 uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). 00060 This parameter can be a value of @ref SPI_mode */ 00061 00062 uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 00063 This parameter can be a value of @ref SPI_data_size */ 00064 00065 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 00066 This parameter can be a value of @ref SPI_Clock_Polarity */ 00067 00068 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 00069 This parameter can be a value of @ref SPI_Clock_Phase */ 00070 00071 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 00072 hardware (NSS pin) or by software using the SSI bit. 00073 This parameter can be a value of @ref SPI_Slave_Select_management */ 00074 00075 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 00076 used to configure the transmit and receive SCK clock. 00077 This parameter can be a value of @ref SPI_BaudRate_Prescaler. 00078 @note The communication clock is derived from the master 00079 clock. The slave clock does not need to be set. */ 00080 00081 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 00082 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 00083 00084 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 00085 }SPI_InitTypeDef; 00086 00087 00088 /** 00089 * @brief I2S Init structure definition 00090 */ 00091 00092 typedef struct 00093 { 00094 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 00095 This parameter can be a value of @ref I2S_Mode */ 00096 00097 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 00098 This parameter can be a value of @ref I2S_Standard */ 00099 00100 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 00101 This parameter can be a value of @ref I2S_Data_Format */ 00102 00103 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 00104 This parameter can be a value of @ref I2S_MCLK_Output */ 00105 00106 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 00107 This parameter can be a value of @ref I2S_Audio_Frequency */ 00108 00109 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 00110 This parameter can be a value of @ref I2S_Clock_Polarity */ 00111 }I2S_InitTypeDef; 00112 00113 /* Exported constants --------------------------------------------------------*/ 00114 00115 /** @defgroup SPI_Exported_Constants 00116 * @{ 00117 */ 00118 00119 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 00120 ((PERIPH) == SPI2) || \ 00121 ((PERIPH) == SPI3) || \ 00122 ((PERIPH) == SPI4)) 00123 00124 #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ 00125 ((PERIPH) == SPI2) || \ 00126 ((PERIPH) == SPI3) || \ 00127 ((PERIPH) == SPI4) || \ 00128 ((PERIPH) == I2S2ext) || \ 00129 ((PERIPH) == I2S3ext)) 00130 00131 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ 00132 ((PERIPH) == SPI3)) 00133 00134 #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ 00135 ((PERIPH) == SPI3) || \ 00136 ((PERIPH) == I2S2ext) || \ 00137 ((PERIPH) == I2S3ext)) 00138 00139 #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ 00140 ((PERIPH) == I2S3ext)) 00141 00142 /** @defgroup SPI_data_direction 00143 * @{ 00144 */ 00145 00146 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 00147 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 00148 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 00149 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 00150 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 00151 ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 00152 ((MODE) == SPI_Direction_1Line_Rx) || \ 00153 ((MODE) == SPI_Direction_1Line_Tx)) 00154 /** 00155 * @} 00156 */ 00157 00158 /** @defgroup SPI_mode 00159 * @{ 00160 */ 00161 00162 #define SPI_Mode_Master ((uint16_t)0x0104) 00163 #define SPI_Mode_Slave ((uint16_t)0x0000) 00164 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 00165 ((MODE) == SPI_Mode_Slave)) 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup SPI_data_size 00171 * @{ 00172 */ 00173 00174 #define SPI_DataSize_4b ((uint16_t)0x0300) 00175 #define SPI_DataSize_5b ((uint16_t)0x0400) 00176 #define SPI_DataSize_6b ((uint16_t)0x0500) 00177 #define SPI_DataSize_7b ((uint16_t)0x0600) 00178 #define SPI_DataSize_8b ((uint16_t)0x0700) 00179 #define SPI_DataSize_9b ((uint16_t)0x0800) 00180 #define SPI_DataSize_10b ((uint16_t)0x0900) 00181 #define SPI_DataSize_11b ((uint16_t)0x0A00) 00182 #define SPI_DataSize_12b ((uint16_t)0x0B00) 00183 #define SPI_DataSize_13b ((uint16_t)0x0C00) 00184 #define SPI_DataSize_14b ((uint16_t)0x0D00) 00185 #define SPI_DataSize_15b ((uint16_t)0x0E00) 00186 #define SPI_DataSize_16b ((uint16_t)0x0F00) 00187 #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ 00188 ((SIZE) == SPI_DataSize_5b) || \ 00189 ((SIZE) == SPI_DataSize_6b) || \ 00190 ((SIZE) == SPI_DataSize_7b) || \ 00191 ((SIZE) == SPI_DataSize_8b) || \ 00192 ((SIZE) == SPI_DataSize_9b) || \ 00193 ((SIZE) == SPI_DataSize_10b) || \ 00194 ((SIZE) == SPI_DataSize_11b) || \ 00195 ((SIZE) == SPI_DataSize_12b) || \ 00196 ((SIZE) == SPI_DataSize_13b) || \ 00197 ((SIZE) == SPI_DataSize_14b) || \ 00198 ((SIZE) == SPI_DataSize_15b) || \ 00199 ((SIZE) == SPI_DataSize_16b)) 00200 /** 00201 * @} 00202 */ 00203 00204 /** @defgroup SPI_CRC_length 00205 * @{ 00206 */ 00207 00208 #define SPI_CRCLength_8b ((uint16_t)0x0000) 00209 #define SPI_CRCLength_16b ((uint16_t)0x0800) 00210 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ 00211 ((LENGTH) == SPI_CRCLength_16b)) 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup SPI_Clock_Polarity 00217 * @{ 00218 */ 00219 00220 #define SPI_CPOL_Low ((uint16_t)0x0000) 00221 #define SPI_CPOL_High ((uint16_t)0x0002) 00222 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 00223 ((CPOL) == SPI_CPOL_High)) 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup SPI_Clock_Phase 00229 * @{ 00230 */ 00231 00232 #define SPI_CPHA_1Edge ((uint16_t)0x0000) 00233 #define SPI_CPHA_2Edge ((uint16_t)0x0001) 00234 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 00235 ((CPHA) == SPI_CPHA_2Edge)) 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup SPI_Slave_Select_management 00241 * @{ 00242 */ 00243 00244 #define SPI_NSS_Soft ((uint16_t)0x0200) 00245 #define SPI_NSS_Hard ((uint16_t)0x0000) 00246 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 00247 ((NSS) == SPI_NSS_Hard)) 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup SPI_BaudRate_Prescaler 00253 * @{ 00254 */ 00255 00256 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 00257 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 00258 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 00259 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 00260 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 00261 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 00262 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 00263 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 00264 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 00265 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 00266 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 00267 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 00268 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 00269 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 00270 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 00271 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup SPI_MSB_LSB_transmission 00277 * @{ 00278 */ 00279 00280 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 00281 #define SPI_FirstBit_LSB ((uint16_t)0x0080) 00282 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 00283 ((BIT) == SPI_FirstBit_LSB)) 00284 /** 00285 * @} 00286 */ 00287 00288 /** @defgroup I2S_Mode 00289 * @{ 00290 */ 00291 00292 #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 00293 #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 00294 #define I2S_Mode_MasterTx ((uint16_t)0x0200) 00295 #define I2S_Mode_MasterRx ((uint16_t)0x0300) 00296 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 00297 ((MODE) == I2S_Mode_SlaveRx) || \ 00298 ((MODE) == I2S_Mode_MasterTx)|| \ 00299 ((MODE) == I2S_Mode_MasterRx)) 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup I2S_Standard 00305 * @{ 00306 */ 00307 00308 #define I2S_Standard_Phillips ((uint16_t)0x0000) 00309 #define I2S_Standard_MSB ((uint16_t)0x0010) 00310 #define I2S_Standard_LSB ((uint16_t)0x0020) 00311 #define I2S_Standard_PCMShort ((uint16_t)0x0030) 00312 #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 00313 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 00314 ((STANDARD) == I2S_Standard_MSB) || \ 00315 ((STANDARD) == I2S_Standard_LSB) || \ 00316 ((STANDARD) == I2S_Standard_PCMShort) || \ 00317 ((STANDARD) == I2S_Standard_PCMLong)) 00318 /** 00319 * @} 00320 */ 00321 00322 /** @defgroup I2S_Data_Format 00323 * @{ 00324 */ 00325 00326 #define I2S_DataFormat_16b ((uint16_t)0x0000) 00327 #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 00328 #define I2S_DataFormat_24b ((uint16_t)0x0003) 00329 #define I2S_DataFormat_32b ((uint16_t)0x0005) 00330 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 00331 ((FORMAT) == I2S_DataFormat_16bextended) || \ 00332 ((FORMAT) == I2S_DataFormat_24b) || \ 00333 ((FORMAT) == I2S_DataFormat_32b)) 00334 /** 00335 * @} 00336 */ 00337 00338 /** @defgroup I2S_MCLK_Output 00339 * @{ 00340 */ 00341 00342 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 00343 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 00344 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 00345 ((OUTPUT) == I2S_MCLKOutput_Disable)) 00346 /** 00347 * @} 00348 */ 00349 00350 /** @defgroup I2S_Audio_Frequency 00351 * @{ 00352 */ 00353 00354 #define I2S_AudioFreq_192k ((uint32_t)192000) 00355 #define I2S_AudioFreq_96k ((uint32_t)96000) 00356 #define I2S_AudioFreq_48k ((uint32_t)48000) 00357 #define I2S_AudioFreq_44k ((uint32_t)44100) 00358 #define I2S_AudioFreq_32k ((uint32_t)32000) 00359 #define I2S_AudioFreq_22k ((uint32_t)22050) 00360 #define I2S_AudioFreq_16k ((uint32_t)16000) 00361 #define I2S_AudioFreq_11k ((uint32_t)11025) 00362 #define I2S_AudioFreq_8k ((uint32_t)8000) 00363 #define I2S_AudioFreq_Default ((uint32_t)2) 00364 00365 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 00366 ((FREQ) <= I2S_AudioFreq_192k)) || \ 00367 ((FREQ) == I2S_AudioFreq_Default)) 00368 /** 00369 * @} 00370 */ 00371 00372 /** @defgroup I2S_Clock_Polarity 00373 * @{ 00374 */ 00375 00376 #define I2S_CPOL_Low ((uint16_t)0x0000) 00377 #define I2S_CPOL_High ((uint16_t)0x0008) 00378 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 00379 ((CPOL) == I2S_CPOL_High)) 00380 /** 00381 * @} 00382 */ 00383 00384 /** @defgroup SPI_FIFO_reception_threshold 00385 * @{ 00386 */ 00387 00388 #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) 00389 #define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000) 00390 #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ 00391 ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup SPI_I2S_DMA_transfer_requests 00397 * @{ 00398 */ 00399 00400 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 00401 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 00402 #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) 00403 /** 00404 * @} 00405 */ 00406 00407 /** @defgroup SPI_last_DMA_transfers 00408 * @{ 00409 */ 00410 00411 #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) 00412 #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) 00413 #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) 00414 #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) 00415 #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ 00416 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ 00417 ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ 00418 ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) 00419 /** 00420 * @} 00421 */ 00422 /** @defgroup SPI_NSS_internal_software_management 00423 * @{ 00424 */ 00425 00426 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 00427 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 00428 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 00429 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 00430 /** 00431 * @} 00432 */ 00433 00434 /** @defgroup SPI_CRC_Transmit_Receive 00435 * @{ 00436 */ 00437 00438 #define SPI_CRC_Tx ((uint8_t)0x00) 00439 #define SPI_CRC_Rx ((uint8_t)0x01) 00440 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 00441 /** 00442 * @} 00443 */ 00444 00445 /** @defgroup SPI_direction_transmit_receive 00446 * @{ 00447 */ 00448 00449 #define SPI_Direction_Rx ((uint16_t)0xBFFF) 00450 #define SPI_Direction_Tx ((uint16_t)0x4000) 00451 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 00452 ((DIRECTION) == SPI_Direction_Tx)) 00453 /** 00454 * @} 00455 */ 00456 00457 /** @defgroup SPI_I2S_interrupts_definition 00458 * @{ 00459 */ 00460 00461 #define SPI_I2S_IT_TXE ((uint8_t)0x71) 00462 #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 00463 #define SPI_I2S_IT_ERR ((uint8_t)0x50) 00464 00465 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 00466 ((IT) == SPI_I2S_IT_RXNE) || \ 00467 ((IT) == SPI_I2S_IT_ERR)) 00468 00469 #define I2S_IT_UDR ((uint8_t)0x53) 00470 #define SPI_IT_MODF ((uint8_t)0x55) 00471 #define SPI_I2S_IT_OVR ((uint8_t)0x56) 00472 #define SPI_I2S_IT_FRE ((uint8_t)0x58) 00473 00474 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 00475 ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ 00476 ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) 00477 /** 00478 * @} 00479 */ 00480 00481 00482 /** @defgroup SPI_transmission_fifo_status_level 00483 * @{ 00484 */ 00485 00486 #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) 00487 #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) 00488 #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) 00489 #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) 00490 00491 /** 00492 * @} 00493 */ 00494 00495 /** @defgroup SPI_reception_fifo_status_level 00496 * @{ 00497 */ 00498 #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) 00499 #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) 00500 #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) 00501 #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) 00502 00503 /** 00504 * @} 00505 */ 00506 00507 00508 /** @defgroup SPI_I2S_flags_definition 00509 * @{ 00510 */ 00511 00512 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 00513 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 00514 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 00515 #define I2S_FLAG_UDR ((uint16_t)0x0008) 00516 #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 00517 #define SPI_FLAG_MODF ((uint16_t)0x0020) 00518 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 00519 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 00520 #define SPI_I2S_FLAG_FRE ((uint16_t)0x0100) 00521 00522 00523 00524 #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 00525 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 00526 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 00527 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ 00528 ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ 00529 ((FLAG) == I2S_FLAG_UDR)) 00530 /** 00531 * @} 00532 */ 00533 00534 /** @defgroup SPI_CRC_polynomial 00535 * @{ 00536 */ 00537 00538 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 00539 /** 00540 * @} 00541 */ 00542 00543 /** 00544 * @} 00545 */ 00546 00547 /* Exported macro ------------------------------------------------------------*/ 00548 /* Exported functions ------------------------------------------------------- */ 00549 00550 /* Function used to set the SPI configuration to the default reset state*******/ 00551 void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 00552 00553 /* Initialization and Configuration functions *********************************/ 00554 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 00555 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 00556 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 00557 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 00558 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00559 void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00560 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00561 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00562 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 00563 void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); 00564 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 00565 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 00566 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 00567 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); 00568 00569 /* Data transfers functions ***************************************************/ 00570 void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); 00571 void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); 00572 uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); 00573 uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); 00574 00575 /* Hardware CRC Calculation functions *****************************************/ 00576 void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); 00577 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 00578 void SPI_TransmitCRC(SPI_TypeDef* SPIx); 00579 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 00580 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 00581 00582 /* DMA transfers management functions *****************************************/ 00583 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 00584 void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); 00585 00586 /* Interrupts and flags management functions **********************************/ 00587 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 00588 uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); 00589 uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); 00590 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 00591 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 00592 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 00593 00594 #ifdef __cplusplus 00595 } 00596 #endif 00597 00598 #endif /*__STM32F30x_SPI_H */ 00599 00600 /** 00601 * @} 00602 */ 00603 00604 /** 00605 * @} 00606 */ 00607 00608 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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