stm32f30x_rcc.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file contains all the functions prototypes for the RCC 
00008   *          firmware library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00013   *
00014   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00015   * You may not use this file except in compliance with the License.
00016   * You may obtain a copy of the License at:
00017   *
00018   *        http://www.st.com/software_license_agreement_liberty_v2
00019   *
00020   * Unless required by applicable law or agreed to in writing, software 
00021   * distributed under the License is distributed on an "AS IS" BASIS, 
00022   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00023   * See the License for the specific language governing permissions and
00024   * limitations under the License.
00025   *
00026   ******************************************************************************
00027   */
00028 
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM32F30x_RCC_H
00031 #define __STM32F30x_RCC_H
00032 
00033 #ifdef __cplusplus
00034  extern "C" {
00035 #endif
00036 
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f30x.h"
00039 
00040 /** @addtogroup STM32F30x_StdPeriph_Driver
00041   * @{
00042   */
00043 
00044 /** @addtogroup RCC
00045   * @{
00046   */
00047 
00048 /* Exported types ------------------------------------------------------------*/
00049 
00050 typedef struct
00051 {
00052   uint32_t SYSCLK_Frequency;
00053   uint32_t HCLK_Frequency;
00054   uint32_t PCLK1_Frequency;
00055   uint32_t PCLK2_Frequency;
00056   uint32_t ADC12CLK_Frequency;
00057   uint32_t ADC34CLK_Frequency;
00058   uint32_t I2C1CLK_Frequency;
00059   uint32_t I2C2CLK_Frequency;
00060   uint32_t I2C3CLK_Frequency;
00061   uint32_t TIM1CLK_Frequency;
00062   uint32_t HRTIM1CLK_Frequency;
00063   uint32_t TIM8CLK_Frequency;
00064   uint32_t TIM2CLK_Frequency;
00065   uint32_t TIM3CLK_Frequency;
00066   uint32_t USART1CLK_Frequency;
00067   uint32_t USART2CLK_Frequency;
00068   uint32_t USART3CLK_Frequency;
00069   uint32_t UART4CLK_Frequency;
00070   uint32_t UART5CLK_Frequency;
00071   uint32_t TIM15CLK_Frequency;
00072   uint32_t TIM16CLK_Frequency;
00073   uint32_t TIM17CLK_Frequency;  
00074   uint32_t TIM20CLK_Frequency; 
00075 }RCC_ClocksTypeDef;
00076 
00077 /* Exported constants --------------------------------------------------------*/
00078 
00079 /** @defgroup RCC_Exported_Constants
00080   * @{
00081   */
00082 
00083 /** @defgroup RCC_HSE_configuration 
00084   * @{
00085   */
00086 
00087 #define RCC_HSE_OFF                      ((uint8_t)0x00)
00088 #define RCC_HSE_ON                       ((uint8_t)0x01)
00089 #define RCC_HSE_Bypass                   ((uint8_t)0x05)
00090 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
00091                          ((HSE) == RCC_HSE_Bypass))
00092 
00093 /**
00094   * @}
00095   */ 
00096  
00097 /** @defgroup RCC_PLL_Clock_Source 
00098   * @{
00099   */
00100 #define RCC_PLLSource_HSI                RCC_CFGR_PLLSRC_HSI_PREDIV     /*!< Only applicable for STM32F303xE devices */
00101 #define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
00102 #define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_PREDIV1
00103  
00104 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
00105                                    ((SOURCE) == RCC_PLLSource_PREDIV1)|| \
00106                                    ((SOURCE) == RCC_PLLSource_HSI))
00107                                    
00108 /**
00109   * @}
00110   */ 
00111 
00112 /** @defgroup RCC_PLL_Multiplication_Factor 
00113   * @{
00114   */
00115 
00116 #define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
00117 #define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
00118 #define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
00119 #define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
00120 #define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
00121 #define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
00122 #define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
00123 #define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
00124 #define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
00125 #define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
00126 #define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
00127 #define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
00128 #define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
00129 #define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
00130 #define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
00131 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
00132                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
00133                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
00134                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
00135                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
00136                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
00137                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
00138                              ((MUL) == RCC_PLLMul_16))
00139 /**
00140   * @}
00141   */
00142 
00143 /** @defgroup RCC_PREDIV1_division_factor
00144   * @{
00145   */
00146 #define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
00147 #define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
00148 #define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
00149 #define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
00150 #define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
00151 #define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
00152 #define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
00153 #define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
00154 #define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
00155 #define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
00156 #define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
00157 #define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
00158 #define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
00159 #define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
00160 #define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
00161 #define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
00162 
00163 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
00164                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
00165                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
00166                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
00167                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
00168                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
00169                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
00170                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
00171 /**
00172   * @}
00173   */ 
00174  
00175 /** @defgroup RCC_System_Clock_Source 
00176   * @{
00177   */
00178 
00179 #define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
00180 #define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
00181 #define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
00182 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
00183                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \
00184                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
00185 /**
00186   * @}
00187   */
00188 
00189 /** @defgroup RCC_AHB_Clock_Source
00190   * @{
00191   */
00192 
00193 #define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
00194 #define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
00195 #define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
00196 #define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
00197 #define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
00198 #define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
00199 #define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
00200 #define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
00201 #define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
00202 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
00203                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
00204                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
00205                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
00206                            ((HCLK) == RCC_SYSCLK_Div512))
00207 /**
00208   * @}
00209   */ 
00210 
00211 /** @defgroup RCC_APB1_APB2_clock_source 
00212   * @{
00213   */
00214 
00215 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
00216 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
00217 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
00218 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
00219 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
00220 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
00221                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
00222                            ((PCLK) == RCC_HCLK_Div16))
00223 /**
00224   * @}
00225   */
00226   
00227 /** @defgroup RCC_ADC_clock_source 
00228   * @{
00229   */
00230   
00231 /* ADC1 & ADC2 */
00232 #define RCC_ADC12PLLCLK_OFF                    ((uint32_t)0x00000000)
00233 #define RCC_ADC12PLLCLK_Div1                   ((uint32_t)0x00000100)
00234 #define RCC_ADC12PLLCLK_Div2                   ((uint32_t)0x00000110)
00235 #define RCC_ADC12PLLCLK_Div4                   ((uint32_t)0x00000120)
00236 #define RCC_ADC12PLLCLK_Div6                   ((uint32_t)0x00000130)
00237 #define RCC_ADC12PLLCLK_Div8                   ((uint32_t)0x00000140)
00238 #define RCC_ADC12PLLCLK_Div10                  ((uint32_t)0x00000150)
00239 #define RCC_ADC12PLLCLK_Div12                  ((uint32_t)0x00000160)
00240 #define RCC_ADC12PLLCLK_Div16                  ((uint32_t)0x00000170)
00241 #define RCC_ADC12PLLCLK_Div32                  ((uint32_t)0x00000180)
00242 #define RCC_ADC12PLLCLK_Div64                  ((uint32_t)0x00000190)
00243 #define RCC_ADC12PLLCLK_Div128                 ((uint32_t)0x000001A0)
00244 #define RCC_ADC12PLLCLK_Div256                 ((uint32_t)0x000001B0)
00245 
00246 /* ADC3 & ADC4 */
00247 #define RCC_ADC34PLLCLK_OFF                    ((uint32_t)0x10000000)
00248 #define RCC_ADC34PLLCLK_Div1                   ((uint32_t)0x10002000)
00249 #define RCC_ADC34PLLCLK_Div2                   ((uint32_t)0x10002200)
00250 #define RCC_ADC34PLLCLK_Div4                   ((uint32_t)0x10002400)
00251 #define RCC_ADC34PLLCLK_Div6                   ((uint32_t)0x10002600)
00252 #define RCC_ADC34PLLCLK_Div8                   ((uint32_t)0x10002800)
00253 #define RCC_ADC34PLLCLK_Div10                  ((uint32_t)0x10002A00)
00254 #define RCC_ADC34PLLCLK_Div12                  ((uint32_t)0x10002C00)
00255 #define RCC_ADC34PLLCLK_Div16                  ((uint32_t)0x10002E00)
00256 #define RCC_ADC34PLLCLK_Div32                  ((uint32_t)0x10003000)
00257 #define RCC_ADC34PLLCLK_Div64                  ((uint32_t)0x10003200)
00258 #define RCC_ADC34PLLCLK_Div128                 ((uint32_t)0x10003400)
00259 #define RCC_ADC34PLLCLK_Div256                 ((uint32_t)0x10003600)
00260 
00261 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
00262                                ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
00263                                ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
00264                                ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
00265                                ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
00266                                ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
00267                                ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
00268                                ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
00269                                ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
00270                                ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
00271                                ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
00272                                ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
00273                                ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
00274 
00275 /**
00276   * @}
00277   */
00278 
00279 /** @defgroup RCC_TIM_clock_source 
00280   * @{
00281   */
00282 
00283 #define RCC_TIM1CLK_PCLK                  ((uint32_t)0x00000000)
00284 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW
00285 
00286 #define RCC_TIM8CLK_PCLK                  ((uint32_t)0x10000000)
00287 #define RCC_TIM8CLK_PLLCLK                ((uint32_t)0x10000200)
00288 
00289 #define RCC_TIM15CLK_PCLK                 ((uint32_t)0x20000000)
00290 #define RCC_TIM15CLK_PLLCLK               ((uint32_t)0x20000400)
00291 
00292 #define RCC_TIM16CLK_PCLK                 ((uint32_t)0x30000000)
00293 #define RCC_TIM16CLK_PLLCLK               ((uint32_t)0x30000800)
00294 
00295 #define RCC_TIM17CLK_PCLK                 ((uint32_t)0x40000000)
00296 #define RCC_TIM17CLK_PLLCLK               ((uint32_t)0x40002000)
00297 
00298 #define RCC_TIM20CLK_PCLK                 ((uint32_t)0x50000000)
00299 #define RCC_TIM20CLK_PLLCLK               ((uint32_t)0x50008000)
00300 
00301 #define RCC_TIM2CLK_PCLK                  ((uint32_t)0x60000000)
00302 #define RCC_TIM2CLK_PLLCLK                ((uint32_t)0x61000000)
00303 
00304 #define RCC_TIM3TIM4CLK_PCLK              ((uint32_t)0x70000000)
00305 #define RCC_TIM3TIM4CLK_PLLCLK            ((uint32_t)0x72000000)
00306 
00307 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_PCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
00308                                ((TIMCLK) == RCC_TIM8CLK_PCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
00309                                ((TIMCLK) == RCC_TIM15CLK_PCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
00310                                ((TIMCLK) == RCC_TIM16CLK_PCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
00311                                ((TIMCLK) == RCC_TIM17CLK_PCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK)|| \
00312                                ((TIMCLK) == RCC_TIM20CLK_PCLK) || ((TIMCLK) == RCC_TIM20CLK_PLLCLK)|| \
00313                                ((TIMCLK) == RCC_TIM2CLK_PCLK) || ((TIMCLK) == RCC_TIM2CLK_PLLCLK)|| \
00314                                ((TIMCLK) == RCC_TIM3TIM4CLK_PCLK) || ((TIMCLK) == RCC_TIM3TIM4CLK_PLLCLK))
00315 /* legacy RCC_TIM_clock_source*/                              
00316 #define RCC_TIM1CLK_HCLK   RCC_TIM1CLK_PCLK                           
00317 #define RCC_TIM8CLK_HCLK   RCC_TIM8CLK_PCLK
00318 #define RCC_TIM15CLK_HCLK  RCC_TIM15CLK_PCLK                               
00319 #define RCC_TIM16CLK_HCLK  RCC_TIM16CLK_PCLK
00320 #define RCC_TIM17CLK_HCLK  RCC_TIM17CLK_PCLK
00321 #define RCC_TIM20CLK_HCLK  RCC_TIM20CLK_PCLK
00322 #define RCC_TIM2CLK_HCLK   RCC_TIM2CLK_PCLK
00323 #define RCC_TIM3CLK_HCLK   RCC_TIM3TIM4CLK_PCLK
00324 #define RCC_TIM3CLK_PLLCLK RCC_TIM3TIM4CLK_PLLCLK
00325 /**
00326   * @}
00327   */
00328 
00329 /** @defgroup RCC_HRTIM_clock_source 
00330   * @{
00331   */
00332 
00333 #define RCC_HRTIM1CLK_HCLK                  ((uint32_t)0x00000000)
00334 #define RCC_HRTIM1CLK_PLLCLK                RCC_CFGR3_HRTIM1SW
00335 
00336 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
00337 
00338 /**
00339   * @}
00340   */
00341   
00342 /** @defgroup RCC_I2C_clock_source 
00343   * @{
00344   */
00345 
00346 #define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
00347 #define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
00348 
00349 #define RCC_I2C2CLK_HSI                   ((uint32_t)0x10000000)
00350 #define RCC_I2C2CLK_SYSCLK                ((uint32_t)0x10000020)
00351 
00352 #define RCC_I2C3CLK_HSI                   ((uint32_t)0x20000000)
00353 #define RCC_I2C3CLK_SYSCLK                ((uint32_t)0x20000040)
00354 
00355 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
00356                                ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
00357                                ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
00358 
00359 /**
00360   * @}
00361   */
00362 
00363 /** @defgroup RCC_USART_clock_source 
00364   * @{
00365   */
00366 
00367 #define RCC_USART1CLK_PCLK                  ((uint32_t)0x10000000)
00368 #define RCC_USART1CLK_SYSCLK                ((uint32_t)0x10000001)
00369 #define RCC_USART1CLK_LSE                   ((uint32_t)0x10000002)
00370 #define RCC_USART1CLK_HSI                   ((uint32_t)0x10000003)
00371 
00372 #define RCC_USART2CLK_PCLK                  ((uint32_t)0x20000000)
00373 #define RCC_USART2CLK_SYSCLK                ((uint32_t)0x20010000)
00374 #define RCC_USART2CLK_LSE                   ((uint32_t)0x20020000)
00375 #define RCC_USART2CLK_HSI                   ((uint32_t)0x20030000)
00376 
00377 #define RCC_USART3CLK_PCLK                  ((uint32_t)0x30000000)
00378 #define RCC_USART3CLK_SYSCLK                ((uint32_t)0x30040000)
00379 #define RCC_USART3CLK_LSE                   ((uint32_t)0x30080000)
00380 #define RCC_USART3CLK_HSI                   ((uint32_t)0x300C0000)
00381 
00382 #define RCC_UART4CLK_PCLK                   ((uint32_t)0x40000000)
00383 #define RCC_UART4CLK_SYSCLK                 ((uint32_t)0x40100000)
00384 #define RCC_UART4CLK_LSE                    ((uint32_t)0x40200000)
00385 #define RCC_UART4CLK_HSI                    ((uint32_t)0x40300000)
00386 
00387 #define RCC_UART5CLK_PCLK                   ((uint32_t)0x50000000)
00388 #define RCC_UART5CLK_SYSCLK                 ((uint32_t)0x50400000)
00389 #define RCC_UART5CLK_LSE                    ((uint32_t)0x50800000)
00390 #define RCC_UART5CLK_HSI                    ((uint32_t)0x50C00000)
00391 
00392 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
00393                                    ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
00394                                    ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
00395                                    ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
00396                                    ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
00397                                    ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
00398                                    ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
00399                                    ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
00400                                    ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
00401                                    ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
00402 
00403 /**
00404   * @}
00405   */
00406        
00407 /** @defgroup RCC_Interrupt_Source 
00408   * @{
00409   */
00410 
00411 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
00412 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
00413 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
00414 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
00415 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
00416 #define RCC_IT_CSS                       ((uint8_t)0x80)
00417 
00418 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
00419 
00420 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
00421                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
00422                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
00423                            
00424 
00425 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
00426 
00427 /**
00428   * @}
00429   */
00430   
00431 /** @defgroup RCC_LSE_configuration 
00432   * @{
00433   */
00434 
00435 #define RCC_LSE_OFF                      ((uint32_t)0x00000000)
00436 #define RCC_LSE_ON                       RCC_BDCR_LSEON
00437 #define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
00438 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
00439                          ((LSE) == RCC_LSE_Bypass))
00440 /**
00441   * @}
00442   */
00443 
00444 /** @defgroup RCC_RTC_Clock_Source
00445   * @{
00446   */
00447 
00448 #define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
00449 #define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
00450 #define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
00451 
00452 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
00453                                       ((SOURCE) == RCC_RTCCLKSource_LSI) || \
00454                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
00455 /**
00456   * @}
00457   */
00458 
00459 /** @defgroup RCC_I2S_Clock_Source
00460   * @{
00461   */
00462 #define RCC_I2S2CLKSource_SYSCLK             ((uint8_t)0x00)
00463 #define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
00464 
00465 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 
00466 
00467 /** @defgroup RCC_LSE_Drive_Configuration 
00468   * @{
00469   */
00470 
00471 #define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
00472 #define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
00473 #define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
00474 #define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
00475 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
00476                                  ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
00477 /**
00478   * @}
00479   */
00480   
00481 /** @defgroup RCC_AHB_Peripherals 
00482   * @{
00483   */
00484 
00485 #define RCC_AHBPeriph_ADC34               RCC_AHBENR_ADC34EN
00486 #define RCC_AHBPeriph_ADC12               RCC_AHBENR_ADC12EN
00487 #define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
00488 #define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
00489 #define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
00490 #define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
00491 #define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
00492 #define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
00493 #define RCC_AHBPeriph_GPIOG               RCC_AHBENR_GPIOGEN
00494 #define RCC_AHBPeriph_GPIOH               RCC_AHBENR_GPIOHEN
00495 #define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
00496 #define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
00497 #define RCC_AHBPeriph_FMC                 RCC_AHBENR_FMCEN
00498 #define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
00499 #define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
00500 #define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
00501 #define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
00502 
00503 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FF88) == 0x00) && ((PERIPH) != 0x00))
00504 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FFDF) == 0x00) && ((PERIPH) != 0x00))
00505 
00506 /**
00507   * @}
00508   */
00509 
00510 /** @defgroup RCC_APB2_Peripherals 
00511   * @{
00512   */
00513 
00514 #define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
00515 #define RCC_APB2Periph_TIM1              RCC_APB2ENR_TIM1EN
00516 #define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
00517 #define RCC_APB2Periph_TIM8              RCC_APB2ENR_TIM8EN
00518 #define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
00519 #define RCC_APB2Periph_SPI4              RCC_APB2ENR_SPI4EN
00520 #define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
00521 #define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
00522 #define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
00523 #define RCC_APB2Periph_TIM20             RCC_APB2ENR_TIM20EN
00524 #define RCC_APB2Periph_HRTIM1            RCC_APB2ENR_HRTIM1
00525 
00526 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFE807FE) == 0x00) && ((PERIPH) != 0x00))
00527 
00528 /**
00529   * @}
00530   */ 
00531 
00532 /** @defgroup RCC_APB1_Peripherals 
00533   * @{
00534   */
00535 #define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
00536 #define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
00537 #define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN
00538 #define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
00539 #define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
00540 #define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
00541 #define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
00542 #define RCC_APB1Periph_SPI3              RCC_APB1ENR_SPI3EN
00543 #define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
00544 #define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
00545 #define RCC_APB1Periph_UART4             RCC_APB1ENR_UART4EN
00546 #define RCC_APB1Periph_UART5             RCC_APB1ENR_UART5EN
00547 #define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
00548 #define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
00549 #define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
00550 #define RCC_APB1Periph_CAN1              RCC_APB1ENR_CAN1EN
00551 #define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
00552 #define RCC_APB1Periph_DAC1              RCC_APB1ENR_DAC1EN
00553 #define RCC_APB1Periph_I2C3              RCC_APB1ENR_I2C3EN
00554 #define RCC_APB1Periph_DAC2              RCC_APB1ENR_DAC2EN
00555 #define RCC_APB1Periph_DAC               RCC_APB1Periph_DAC1
00556 
00557 
00558 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
00559 /**
00560   * @}
00561   */
00562 
00563 /** @defgroup RCC_MCO_Clock_Source
00564   * @{
00565   */
00566 
00567 #define RCC_MCOSource_NoClock            ((uint8_t)0x00)
00568 #define RCC_MCOSource_LSI                ((uint8_t)0x02)
00569 #define RCC_MCOSource_LSE                ((uint8_t)0x03)
00570 #define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
00571 #define RCC_MCOSource_HSI                ((uint8_t)0x05)
00572 #define RCC_MCOSource_HSE                ((uint8_t)0x06)
00573 #define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
00574 #define RCC_MCOSource_PLLCLK             ((uint8_t)0x87)
00575 
00576 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
00577                                    ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_HSE) || \
00578                                    ((SOURCE) == RCC_MCOSource_LSI)  || ((SOURCE) == RCC_MCOSource_LSE) || \
00579                                    ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| ((SOURCE) == RCC_MCOSource_PLLCLK))
00580 /**
00581   * @}
00582   */ 
00583 
00584 /** @defgroup RCC_MCOPrescaler
00585   * @{
00586   */
00587 
00588 #define RCC_MCOPrescaler_1            RCC_CFGR_MCO_PRE_1
00589 #define RCC_MCOPrescaler_2            RCC_CFGR_MCO_PRE_2
00590 #define RCC_MCOPrescaler_4            RCC_CFGR_MCO_PRE_4
00591 #define RCC_MCOPrescaler_8            RCC_CFGR_MCO_PRE_8
00592 #define RCC_MCOPrescaler_16           RCC_CFGR_MCO_PRE_16
00593 #define RCC_MCOPrescaler_32           RCC_CFGR_MCO_PRE_32
00594 #define RCC_MCOPrescaler_64           RCC_CFGR_MCO_PRE_64
00595 #define RCC_MCOPrescaler_128          RCC_CFGR_MCO_PRE_128
00596 
00597 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
00598                                          ((PRESCALER) == RCC_MCOPrescaler_2)  || \
00599                                          ((PRESCALER) == RCC_MCOPrescaler_4)  || \
00600                                          ((PRESCALER) == RCC_MCOPrescaler_8)  || \
00601                                          ((PRESCALER) == RCC_MCOPrescaler_16) || \
00602                                          ((PRESCALER) == RCC_MCOPrescaler_32) || \
00603                                          ((PRESCALER) == RCC_MCOPrescaler_64) || \
00604                                          ((PRESCALER) == RCC_MCOPrescaler_128))
00605 /**
00606   * @}
00607   */ 
00608 
00609 /** @defgroup RCC_USB_Device_clock_source 
00610   * @{
00611   */
00612 
00613 #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
00614 #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
00615 
00616 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
00617                                       ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
00618 /**
00619   * @}
00620   */
00621 
00622 /** @defgroup RCC_Flag 
00623   * @{
00624   */
00625 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
00626 #define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
00627 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
00628 #define RCC_FLAG_MCOF                    ((uint8_t)0x9C)
00629 #define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
00630 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
00631 #define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
00632 #define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
00633 #define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
00634 #define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
00635 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
00636 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
00637 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
00638 
00639 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
00640                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
00641                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
00642                            ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
00643                            ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
00644                            ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
00645                            ((FLAG) == RCC_FLAG_MCOF))
00646 
00647 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
00648 
00649 /**
00650   * @}
00651   */
00652 
00653 /**
00654   * @}
00655   */
00656 
00657 /* Exported macro ------------------------------------------------------------*/
00658 /* Exported functions ------------------------------------------------------- */
00659 
00660 /* Function used to set the RCC clock configuration to the default reset state */
00661 void RCC_DeInit(void);
00662 
00663 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
00664 void RCC_HSEConfig(uint8_t RCC_HSE);
00665 ErrorStatus RCC_WaitForHSEStartUp(void);
00666 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
00667 void RCC_HSICmd(FunctionalState NewState);
00668 void RCC_LSEConfig(uint32_t RCC_LSE);
00669 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
00670 void RCC_LSICmd(FunctionalState NewState);
00671 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
00672 void RCC_PLLCmd(FunctionalState NewState);
00673 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
00674 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
00675 #ifdef STM32F303xC
00676  void RCC_MCOConfig(uint8_t RCC_MCOSource);
00677 #else
00678  void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
00679 #endif /* STM32F303xC */
00680 
00681 /* System, AHB and APB busses clocks configuration functions ******************/
00682 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
00683 uint8_t RCC_GetSYSCLKSource(void);
00684 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
00685 void RCC_PCLK1Config(uint32_t RCC_HCLK);
00686 void RCC_PCLK2Config(uint32_t RCC_HCLK);
00687 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
00688 
00689 /* Peripheral clocks configuration functions **********************************/
00690 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
00691 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
00692 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
00693 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
00694 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 
00695 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
00696 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
00697 
00698 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
00699 void RCC_RTCCLKCmd(FunctionalState NewState);
00700 void RCC_BackupResetCmd(FunctionalState NewState);
00701 
00702 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00703 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00704 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00705 
00706 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
00707 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
00708 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
00709 
00710 /* Interrupts and flags management functions **********************************/
00711 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
00712 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
00713 void RCC_ClearFlag(void);
00714 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
00715 void RCC_ClearITPendingBit(uint8_t RCC_IT);
00716 
00717 #ifdef __cplusplus
00718 }
00719 #endif
00720 
00721 #endif /* __STM32F30x_RCC_H */
00722 
00723 /**
00724   * @}
00725   */
00726 
00727 /**
00728   * @}
00729   */ 
00730 
00731 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/