Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependents: Space_Invaders_Demo neopixels gpio_test_stm32f3_discovery gpio_test_systimer ... more
stm32f30x_hrtim.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_hrtim.c 00004 * @author MCD Application Team 00005 * @version V1.2.3 00006 * @date 10-July-2015 00007 * @brief HRTIMx module driver. 00008 * 00009 * This file provides firmware functions to manage the following 00010 * functionalities of the HRTIMx peripheral: 00011 * + Initialization/de-initialization methods 00012 * + I/O operation methods 00013 * + Peripheral Control methods 00014 * 00015 @verbatim 00016 ================================================================================ 00017 ##### <HRTIM specific features> ##### 00018 ================================================================================ 00019 00020 [..] < HRTIM introduction: 00021 (#) The high-resolution timer can generate up to 10 digital signals with 00022 highly accurate timings. 00023 It is primarily intended to drive power conversion systems such as 00024 switch mode power supplies or lighting systems, 00025 but can be of general purpose usage, whenever a very fine timing 00026 resolution is expected. 00027 00028 (#) Its modular architecture allows to generate either independent or 00029 coupled waveforms. 00030 The wave-shape is defined by self-contained timings 00031 (using counters and compare units) and a broad range of external events, 00032 such as analog or digital feedbacks and synchronisation signals. 00033 This allows to produce a large variety of control signal (PWM, phase-shifted, 00034 constant Ton,...) and address most of conversion topologies. 00035 00036 (#) For control and monitoring purposes, the timer has also timing measure 00037 capabilities and links to built-in ADC and DAC converters. 00038 Last, it features light-load management mode and is able to handle 00039 various fault schemes for safe shut-down purposes. 00040 00041 00042 ##### How to use this driver ##### 00043 ================================================================================ 00044 [..] This driver provides functions to configure and program the HRTIM 00045 of all stm32f33x devices. 00046 These functions are split in 9 groups: 00047 00048 (#) HRTIM Simple TimeBase management: this group includes all needed functions 00049 to configure the HRTIM Timebase unit: 00050 (++) Initializes the HRTIMx timer in simple time base mode 00051 (++) Start/Stop the time base generation 00052 (++) Deinitialize the HRTIM peripheral 00053 00054 00055 (#) HRTIM simple Output Compare management: this group includes all needed 00056 functions to configure the Compare unit used in Output compare mode: 00057 (++) Initializes the HRTIMx timer time base unit 00058 (++) Configure the compare unit in simple Output Compare mode 00059 (++) Start/Stop the Output compare generation 00060 00061 (#) HRTIM simple PWM management: this group includes all needed 00062 functions to configure the Compare unit used in PWM mode: 00063 (++) Initializes the HRTIMx timer time base unit 00064 (++) Configure the compare unit in simple PWM mode 00065 (++) Start/Stop the PWM generation 00066 00067 (#) HRTIM simple Capture management: this group includes all needed 00068 functions to configure the Capture unit used in Capture mode: 00069 (++) Initializes the HRTIMx timer time base unit 00070 (++) Configure the compare unit in simple Capture mode 00071 (++) Start/Stop the Capture mode 00072 00073 (#) HRTIM simple One Pulse management: this group includes all needed 00074 functions to configure the Capture unit and Compare unit used in One Pulse mode: 00075 (++) Initializes the HRTIMx timer time base unit 00076 (++) Configure the compare unit and the capture unit in simple One Pulse mode 00077 (++) Start/Stop the One Pulse mode generation 00078 00079 (#) HRTIM Waveform management: this group includes all needed 00080 functions to configure the HRTIM possible waveform mode: 00081 (++) Initializes the HRTIMx timer Master time base unit 00082 (++) Initializes the HRTIMx timer Slaves time base unit 00083 (++) Configures the HRTIMx timer Compare unit 00084 (++) Configures the HRTIMx Slave timer Capture unit 00085 (++) Configures the HRTIMx timer Output unit 00086 (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features 00087 (++) Configures the HRTIMx timer Fault / External event features 00088 (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,... 00089 (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers 00090 (++) HRTIMx timer Outputs Start/Stop 00091 (++) Start/Stop the HRTIMx Timer counters 00092 00093 (#) HRTIM interrupts, DMA and flags management 00094 (++) Enable/Disable interrupt sources 00095 (++) Get flags status 00096 (++) Clear flags/ Pending bits 00097 (++) Enable/Disable DMA requests 00098 (++) Configure DMA burst mode 00099 00100 (#) TIM specific interface management, this group includes all 00101 needed functions to use the specific TIM interface: 00102 (++) HRTIMx timer DLL calibration 00103 00104 @endverbatim 00105 ****************************************************************************** 00106 * @attention 00107 * 00108 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00109 * 00110 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00111 * You may not use this file except in compliance with the License. 00112 * You may obtain a copy of the License at: 00113 * 00114 * http://www.st.com/software_license_agreement_liberty_v2 00115 * 00116 * Unless required by applicable law or agreed to in writing, software 00117 * distributed under the License is distributed on an "AS IS" BASIS, 00118 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00119 * See the License for the specific language governing permissions and 00120 * limitations under the License. 00121 * 00122 ****************************************************************************** 00123 */ 00124 /* Includes ------------------------------------------------------------------*/ 00125 #include "stm32f30x_hrtim.h" 00126 00127 /** @addtogroup STM32F30x_StdPeriph_Driver 00128 * @{ 00129 */ 00130 00131 /** @defgroup HRTIM 00132 * @brief HRTIM driver module 00133 * @{ 00134 */ 00135 00136 /* Private typedef -----------------------------------------------------------*/ 00137 /* Private define ------------------------------------------------------------*/ 00138 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\ 00139 HRTIM_FLTR_FLT2EN |\ 00140 HRTIM_FLTR_FLT3EN |\ 00141 HRTIM_FLTR_FLT4EN | \ 00142 HRTIM_FLTR_FLT5EN) 00143 00144 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\ 00145 HRTIM_TIMUPDATETRIGGER_TIMER_A |\ 00146 HRTIM_TIMUPDATETRIGGER_TIMER_B |\ 00147 HRTIM_TIMUPDATETRIGGER_TIMER_C |\ 00148 HRTIM_TIMUPDATETRIGGER_TIMER_D |\ 00149 HRTIM_TIMUPDATETRIGGER_TIMER_E) 00150 00151 #define HRTIM_TIM_OFFSET (uint32_t)0x00000080 00152 /* Private macro -------------------------------------------------------------*/ 00153 /* Private variables ---------------------------------------------------------*/ 00154 static uint32_t TimerIdxToTimerId[] = 00155 { 00156 HRTIM_TIMERID_TIMER_A, 00157 HRTIM_TIMERID_TIMER_B, 00158 HRTIM_TIMERID_TIMER_C, 00159 HRTIM_TIMERID_TIMER_D, 00160 HRTIM_TIMERID_TIMER_E, 00161 HRTIM_TIMERID_MASTER, 00162 }; 00163 00164 /* Private function prototypes -----------------------------------------------*/ 00165 /* Private functions ---------------------------------------------------------*/ 00166 static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc); 00167 static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct); 00168 static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit); 00169 static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx, 00170 uint32_t TimerIdx, 00171 HRTIM_TimerInitTypeDef * TimerInit); 00172 static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx, 00173 uint32_t TimerIdx, 00174 uint32_t CompareUnit, 00175 HRTIM_CompareCfgTypeDef * CompareCfg); 00176 static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx, 00177 uint32_t TimerIdx, 00178 uint32_t CaptureUnit, 00179 uint32_t Event); 00180 static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx, 00181 uint32_t TimerIdx, 00182 uint32_t Output, 00183 HRTIM_OutputCfgTypeDef * OutputCfg); 00184 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx, 00185 uint32_t Event, 00186 HRTIM_EventCfgTypeDef * EventCfg); 00187 static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx, 00188 uint32_t TimerIdx, 00189 uint32_t Event); 00190 /** @defgroup HRTIM_Private_Functions 00191 * @{ 00192 */ 00193 00194 /** @defgroup HRTIM_Group1 Initialization/de-initialization methods 00195 * @brief Initialization and Configuration functions 00196 * 00197 @verbatim 00198 =============================================================================== 00199 ##### Initialization/de-initialization methods ##### 00200 =============================================================================== 00201 [..] This section provides functions allowing to: 00202 (+)Initializes timer in basic time base mode 00203 (+)Initializes timer in basic OC mode 00204 (+)Initializes timer in basic PWM mode 00205 (+)Initializes timer in basic Capture mode 00206 (+)Initializes timer in One Pulse mode 00207 (+)Initializes a timer operating in waveform mode 00208 (+)De-initializes the HRTIMx timer 00209 00210 @endverbatim 00211 * @{ 00212 */ 00213 00214 /** 00215 * @brief Initializes the HRTIMx timer in basic time base mode 00216 * @param HRTIMx: pointer to HRTIMx peripheral 00217 * @param TimerIdx: Timer index 00218 * This parameter can be one of the following values: 00219 * @arg 0x0 for master timer 00220 * @arg 0x1 to 0x5 for timers A to E 00221 * @note The time-base unit initialization parameters specify: 00222 * The timer counter operating mode (continuous, one shot) 00223 * The timer clock prescaler 00224 * The timer period 00225 * The timer repetition counter. 00226 * @retval None 00227 */ 00228 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 00229 { 00230 /* Check the parameters */ 00231 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00232 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); 00233 00234 if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 00235 { 00236 /* Configure master timer */ 00237 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct); 00238 } 00239 else 00240 { 00241 /* Configure timing unit */ 00242 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00243 } 00244 } 00245 00246 /** 00247 * @brief De-initializes a timer operating in all mode 00248 * @param HRTIMx: pointer to HRTIMx peripheral 00249 * @retval None 00250 */ 00251 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx) 00252 { 00253 /* Check the parameters */ 00254 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE); 00255 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE); 00256 } 00257 00258 /** 00259 * @brief Initializes the HRTIMx timer in basic output compare mode 00260 * @param HRTIMx: pointer to HRTIMx peripheral 00261 * @param TimerIdx: Timer index 00262 * This parameter can be one of the following values: 00263 * @arg 0x1 to 0x5 for timers A to E 00264 * @note Initializes the time-base unit of the timer and prepare it to 00265 * operate in output compare mode 00266 * @retval None 00267 */ 00268 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 00269 { 00270 /* Check the parameters */ 00271 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00272 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); 00273 00274 /* Configure timing unit */ 00275 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00276 } 00277 00278 /** 00279 * @brief Initializes the HRTIMx timer in basic PWM mode 00280 * @param HRTIMx: pointer to HRTIMx peripheral 00281 * @param TimerIdx: Timer index 00282 * This parameter can be one of the following values: 00283 * @arg 0x1 to 0x5 for timers A to E 00284 * @note Initializes the time-base unit of the timer and prepare it to 00285 * operate in capture mode 00286 * @retval None 00287 */ 00288 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 00289 { 00290 /* Check the parameters */ 00291 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00292 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); 00293 00294 /* Configure timing unit */ 00295 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00296 } 00297 00298 /** 00299 * @brief Initializes a timer operating in basic capture mode 00300 * @param HRTIMx: pointer to HRTIMx peripheral 00301 * @param TimerIdx: Timer index 00302 * This parameter can be one of the following values: 00303 * @arg 0x1 to 0x5 for timers A to E 00304 * @retval None 00305 */ 00306 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 00307 { 00308 /* Check the parameters */ 00309 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00310 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); 00311 00312 /* Configure timing unit */ 00313 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00314 } 00315 00316 /** 00317 * @brief Initializes the HRTIMx timer in basic one pulse mode 00318 * @param HRTIMx: pointer to HRTIMx peripheral 00319 * @param TimerIdx: Timer index 00320 * This parameter can be one of the following values: 00321 * @arg 0x1 to 0x5 for timers A to E 00322 * @note Initializes the time-base unit of the timer and prepare it to 00323 * operate in one pulse mode. In this mode the counter operates 00324 * in single shot mode (retriggerable or not) 00325 * @retval None 00326 */ 00327 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 00328 { 00329 /* Check the parameters */ 00330 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00331 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode)); 00332 00333 /* Configure timing unit */ 00334 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00335 } 00336 00337 /** 00338 * @brief Initializes a timer operating in waveform mode 00339 * @param HRTIMx: pointer to HRTIMx peripheral 00340 * @param TimerIdx: Timer index 00341 * This parameter can be one of the following values: 00342 * @arg 0x0 for master timer 00343 * @arg 0x1 to 0x5 for timers A to E 00344 * @param pTimerInit: pointer to the timer initialization data structure 00345 * @retval None 00346 */ 00347 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx, 00348 uint32_t TimerIdx, 00349 HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct, 00350 HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct) 00351 { 00352 /* Check the parameters */ 00353 assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable)); 00354 assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync)); 00355 assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync)); 00356 assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro)); 00357 assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable)); 00358 assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode)); 00359 assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate)); 00360 00361 if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 00362 { 00363 /* Check parameters */ 00364 assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating)); 00365 00366 /* Configure master timer */ 00367 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct); 00368 HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct); 00369 } 00370 else 00371 { 00372 /* Check parameters */ 00373 assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating)); 00374 00375 /* Configure timing unit */ 00376 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct); 00377 HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct); 00378 } 00379 } 00380 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup HRTIM_Group2 I/O operation methods 00386 * @brief Data transfers functions 00387 * 00388 @verbatim 00389 =============================================================================== 00390 ##### IO operation methods ##### 00391 =============================================================================== 00392 [..] 00393 This subsection provides a set of functions allowing to manage the HRTIMx data 00394 transfers. 00395 (+) Starts the DLL calibration. 00396 (+) Starts / stops the counter of a timer operating in basic time base mode 00397 (+) Starts / stops the output compare signal generation on the designed timer output 00398 (+) Starts / stops the PWM output signal generation on the designed timer output 00399 (+) Enables / disables a basic capture on the designed capture unit 00400 00401 @endverbatim 00402 * @{ 00403 */ 00404 00405 /** 00406 * @brief Starts the DLL calibration 00407 * @param HRTIMx: pointer to HRTIMx peripheral 00408 * @param CalibrationRate: DLL calibration period 00409 * This parameter can be one of the following values: 00410 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration 00411 * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms 00412 * @arg HRTIM_CALIBRATIONRATE_910: 910 us 00413 * @arg HRTIM_CALIBRATIONRATE_114: 114 us 00414 * @arg HRTIM_CALIBRATIONRATE_14: 14 us 00415 * @retval None 00416 */ 00417 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate) 00418 { 00419 uint32_t HRTIM_dllcr; 00420 00421 /* Check the parameters */ 00422 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate)); 00423 00424 /* Configure DLL Calibration */ 00425 HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR; 00426 00427 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION) 00428 { 00429 /* One shot DLL calibration */ 00430 HRTIM_dllcr &= ~(HRTIM_DLLCR_CALEN); 00431 HRTIM_dllcr |= HRTIM_DLLCR_CAL; 00432 } 00433 else 00434 { 00435 /* Periodic DLL calibration */ 00436 HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL); 00437 HRTIM_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN); 00438 } 00439 00440 /* Update HRTIMx register */ 00441 HRTIMx->HRTIM_COMMON.DLLCR = HRTIM_dllcr; 00442 00443 } 00444 /** 00445 * @brief Starts the counter of a timer operating in basic time base mode 00446 * @param HRTIMx: pointer to HRTIM peripheral 00447 * @param TimerIdx: Timer index 00448 * This parameter can be one of the following values: 00449 * @arg 0x5 for master timer 00450 * @arg 0x0 to 0x4 for timers A to E 00451 * @retval None 00452 */ 00453 void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx) 00454 { 00455 /* Check the parameters */ 00456 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00457 00458 /* Enable the timer counter */ 00459 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00460 } 00461 00462 /** 00463 * @brief Stops the counter of a timer operating in basic time base mode 00464 * @param HRTIMx: pointer to HRTIM peripheral 00465 * @param TimerIdx: Timer index 00466 * This parameter can be one of the following values: 00467 * @arg 0x5 for master timer 00468 * @arg 0x0 to 0x4 for timers A to E 00469 * @retval None 00470 */ 00471 void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx) 00472 { 00473 /* Check the parameters */ 00474 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00475 00476 /* Disable the timer counter */ 00477 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00478 } 00479 00480 /** 00481 * @brief Starts the output compare signal generation on the designed timer output 00482 * @param HRTIMx: pointer to HRTIM peripheral 00483 * @param TimerIdx: Timer index 00484 * This parameter can be one of the following values: 00485 * @arg 0x0 to 0x4 for timers A to E 00486 * @param OCChannel: Timer output 00487 * This parameter can be one of the following values: 00488 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00489 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00490 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00491 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00492 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00493 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00494 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00495 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00496 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00497 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00498 * @retval None 00499 */ 00500 void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx, 00501 uint32_t TimerIdx, 00502 uint32_t OCChannel) 00503 { 00504 /* Check the parameters */ 00505 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); 00506 00507 /* Enable the timer output */ 00508 (HRTIMx->HRTIM_COMMON).OENR |= OCChannel; 00509 00510 /* Enable the timer counter */ 00511 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00512 00513 } 00514 00515 /** 00516 * @brief Stops the output compare signal generation on the designed timer output 00517 * @param HRTIMx: pointer to HRTIM peripheral 00518 * @param TimerIdx: Timer index 00519 * This parameter can be one of the following values: 00520 * @arg 0x0 to 0x4 for timers A to E 00521 * @param OCChannel: Timer output 00522 * This parameter can be one of the following values: 00523 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00524 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00525 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00526 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00527 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00528 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00529 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00530 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00531 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00532 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00533 * @retval None 00534 */ 00535 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx, 00536 uint32_t TimerIdx, 00537 uint32_t OCChannel) 00538 { 00539 /* Check the parameters */ 00540 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); 00541 00542 /* Disable the timer output */ 00543 HRTIMx->HRTIM_COMMON.DISR |= OCChannel; 00544 00545 /* Disable the timer counter */ 00546 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00547 } 00548 00549 /** 00550 * @brief Starts the PWM output signal generation on the designed timer output 00551 * @param HRTIMx: pointer to HRTIM peripheral 00552 * @param TimerIdx: Timer index 00553 * This parameter can be one of the following values: 00554 * @arg 0x0 to 0x4 for timers A to E 00555 * @param PWMChannel: Timer output 00556 * This parameter can be one of the following values: 00557 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00558 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00559 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00560 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00561 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00562 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00563 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00564 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00565 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00566 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00567 * @retval None 00568 */ 00569 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx, 00570 uint32_t TimerIdx, 00571 uint32_t PWMChannel) 00572 { 00573 /* Check the parameters */ 00574 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); 00575 00576 /* Enable the timer output */ 00577 HRTIMx->HRTIM_COMMON.OENR |= PWMChannel; 00578 00579 /* Enable the timer counter */ 00580 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00581 } 00582 00583 /** 00584 * @brief Stops the PWM output signal generation on the designed timer output 00585 * @param HRTIMx: pointer to HRTIM peripheral 00586 * @param TimerIdx: Timer index 00587 * This parameter can be one of the following values: 00588 * @arg 0x0 to 0x4 for timers A to E 00589 * @param PWMChannel: Timer output 00590 * This parameter can be one of the following values: 00591 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00592 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00593 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00594 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00595 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00596 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00597 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00598 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00599 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00600 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00601 * @retval None 00602 */ 00603 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx, 00604 uint32_t TimerIdx, 00605 uint32_t PWMChannel) 00606 { 00607 /* Check the parameters */ 00608 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); 00609 00610 /* Disable the timer output */ 00611 HRTIMx->HRTIM_COMMON.DISR |= PWMChannel; 00612 00613 /* Disable the timer counter */ 00614 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00615 } 00616 00617 /** 00618 * @brief Enables a basic capture on the designed capture unit 00619 * @param HRTIMx: pointer to HRTIM peripheral 00620 * @param TimerIdx: Timer index 00621 * This parameter can be one of the following values: 00622 * @arg 0x0 to 0x4 for timers A to E 00623 * @param CaptureChannel: Timer output 00624 * This parameter can be one of the following values: 00625 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 00626 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 00627 * @retval None 00628 * @note The external event triggering the capture is available for all timing 00629 * units. It can be used directly and is active as soon as the timing 00630 * unit counter is enabled. 00631 */ 00632 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx, 00633 uint32_t TimerIdx, 00634 uint32_t CaptureChannel) 00635 { 00636 /* Enable the timer counter */ 00637 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00638 00639 } 00640 00641 /** 00642 * @brief Disables a basic capture on the designed capture unit 00643 * @param HRTIMx: pointer to HRTIMx peripheral 00644 * @param TimerIdx: Timer index 00645 * This parameter can be one of the following values: 00646 * @arg 0x0 to 0x4 for timers A to E 00647 * @param CaptureChannel: Timer output 00648 * This parameter can be one of the following values: 00649 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 00650 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 00651 * @retval None 00652 */ 00653 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx, 00654 uint32_t TimerIdx, 00655 uint32_t CaptureChannel) 00656 { 00657 /* Check the parameters */ 00658 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 00659 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); 00660 00661 /* Set the capture unit trigger */ 00662 switch (CaptureChannel) 00663 { 00664 case HRTIM_CAPTUREUNIT_1: 00665 { 00666 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE; 00667 } 00668 break; 00669 case HRTIM_CAPTUREUNIT_2: 00670 { 00671 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE; 00672 } 00673 break; 00674 default: 00675 break; 00676 } 00677 00678 /* Disable the timer counter */ 00679 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) && 00680 (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE)) 00681 { 00682 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00683 } 00684 00685 } 00686 00687 /** 00688 * @brief Enables the basic one pulse signal generation on the designed output 00689 * @param HRTIMx: pointer to HRTIMx peripheral 00690 * @param TimerIdx: Timer index 00691 * This parameter can be one of the following values: 00692 * @arg 0x0 to 0x4 for timers A to E 00693 * @param OnePulseChannel: Timer output 00694 * This parameter can be one of the following values: 00695 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00696 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00697 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00698 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00699 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00700 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00701 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00702 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00703 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00704 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00705 * @retval None 00706 */ 00707 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx, 00708 uint32_t TimerIdx, 00709 uint32_t OnePulseChannel) 00710 { 00711 /* Check the parameters */ 00712 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); 00713 00714 /* Enable the timer output */ 00715 HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel; 00716 00717 /* Enable the timer counter */ 00718 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00719 } 00720 00721 /** 00722 * @brief Disables the basic one pulse signal generation on the designed output 00723 * @param HRTIMx: pointer to HRTIMx peripheral 00724 * @param TimerIdx: Timer index 00725 * This parameter can be one of the following values: 00726 * @arg 0x0 to 0x4 for timers A to E 00727 * @param OnePulseChannel: Timer output 00728 * This parameter can be one of the following values: 00729 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00730 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00731 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00732 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00733 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00734 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00735 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00736 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00737 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00738 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00739 * @retval None 00740 */ 00741 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx, 00742 uint32_t TimerIdx, 00743 uint32_t OnePulseChannel) 00744 { 00745 /* Check the parameters */ 00746 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); 00747 00748 /* Disable the timer output */ 00749 HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel; 00750 00751 /* Disable the timer counter */ 00752 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]); 00753 } 00754 00755 /** 00756 * @brief Starts the counter of the designated timer(s) operating in waveform mode 00757 * Timers can be combined (ORed) to allow for simultaneous counter start 00758 * @param HRTIMx: pointer to HRTIMx peripheral 00759 * @param TimersToStart: Timer counter(s) to start 00760 * This parameter can be any combination of the following values: 00761 * @arg HRTIM_TIMERID_MASTER 00762 * @arg HRTIM_TIMERID_TIMER_A 00763 * @arg HRTIM_TIMERID_TIMER_B 00764 * @arg HRTIM_TIMERID_TIMER_C 00765 * @arg HRTIM_TIMERID_TIMER_D 00766 * @arg HRTIM_TIMERID_TIMER_E 00767 * @retval None 00768 */ 00769 void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx, 00770 uint32_t TimersToStart) 00771 { 00772 /* Enable timer(s) counter */ 00773 HRTIMx->HRTIM_MASTER.MCR |= TimersToStart; 00774 } 00775 00776 /** 00777 * @brief Stops the counter of the designated timer(s) operating in waveform mode 00778 * Timers can be combined (ORed) to allow for simultaneous counter stop 00779 * @param HRTIMx: pointer to HRTIMx peripheral 00780 * @param TimersToStop: Timer counter(s) to stop 00781 * This parameter can be any combination of the following values: 00782 * @arg HRTIM_TIMERID_MASTER 00783 * @arg HRTIM_TIMERID_TIMER_A 00784 * @arg HRTIM_TIMERID_TIMER_B 00785 * @arg HRTIM_TIMERID_TIMER_C 00786 * @arg HRTIM_TIMERID_TIMER_D 00787 * @arg HRTIM_TIMERID_TIMER_E 00788 * @retval None 00789 */ 00790 void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx, 00791 uint32_t TimersToStop) 00792 { 00793 /* Disable timer(s) counter */ 00794 HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop; 00795 } 00796 00797 /** 00798 * @brief Enables the generation of the waveform signal on the designated output(s) 00799 * Outputs can be combined (ORed) to allow for simultaneous output enabling 00800 * @param HRTIMx: pointer to HRTIMx peripheral 00801 * @param OutputsToStart: Timer output(s) to enable 00802 * This parameter can be any combination of the following values: 00803 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00804 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00805 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00806 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00807 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00808 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00809 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00810 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00811 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00812 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00813 * @retval None 00814 */ 00815 void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx, 00816 uint32_t OutputsToStart) 00817 { 00818 /* Enable the HRTIM outputs */ 00819 HRTIMx->HRTIM_COMMON.OENR = OutputsToStart; 00820 } 00821 00822 /** 00823 * @brief Disables the generation of the waveform signal on the designated output(s) 00824 * Outputs can be combined (ORed) to allow for simultaneous output disabling 00825 * @param HRTIMx: pointer to HRTIMx peripheral 00826 * @param OutputsToStop: Timer output(s) to disable 00827 * This parameter can be any combination of the following values: 00828 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 00829 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 00830 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 00831 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 00832 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 00833 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 00834 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 00835 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 00836 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 00837 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 00838 * @retval None 00839 */ 00840 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx, 00841 uint32_t OutputsToStop) 00842 { 00843 /* Disable the HRTIM outputs */ 00844 HRTIMx->HRTIM_COMMON.DISR = OutputsToStop; 00845 } 00846 00847 /** 00848 * @brief Enables or disables the Master and slaves interrupt request 00849 * @param HRTIMx: pointer to HRTIMx peripheral 00850 * @param TimerIdx: Timer index 00851 * This parameter can be one of the following values: 00852 * @arg 0x0 to 0x4 for timers A to E 00853 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. 00854 * This parameter can be any combination of the following values: 00855 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source 00856 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source 00857 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source 00858 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source 00859 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source 00860 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source 00861 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source 00862 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source 00863 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source 00864 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source 00865 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source 00866 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source 00867 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source 00868 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source 00869 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source 00870 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source 00871 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source 00872 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source 00873 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source 00874 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source 00875 * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source 00876 * @param NewState: new state of the TIM interrupts. 00877 * This parameter can be: ENABLE or DISABLE. 00878 * @retval None 00879 */ 00880 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState) 00881 { 00882 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00883 00884 switch(TimerIdx) 00885 { 00886 case HRTIM_TIMERINDEX_MASTER: 00887 { 00888 if(NewState != DISABLE) 00889 { 00890 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT; 00891 } 00892 else 00893 { 00894 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT; 00895 } 00896 } 00897 break; 00898 case HRTIM_TIMERINDEX_TIMER_A: 00899 case HRTIM_TIMERINDEX_TIMER_B: 00900 case HRTIM_TIMERINDEX_TIMER_C: 00901 case HRTIM_TIMERINDEX_TIMER_D: 00902 case HRTIM_TIMERINDEX_TIMER_E: 00903 { 00904 if(NewState != DISABLE) 00905 { 00906 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT; 00907 } 00908 else 00909 { 00910 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT; 00911 } 00912 } 00913 break; 00914 00915 default: 00916 break; 00917 } 00918 } 00919 00920 /** 00921 * @brief Enables or disables the common interrupt request 00922 * @param HRTIMx: pointer to HRTIMx peripheral 00923 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. 00924 * This parameter can be any combination of the following values: 00925 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source 00926 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source 00927 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source 00928 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source 00929 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source 00930 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source 00931 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source 00932 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source 00933 * @param NewState: new state of the TIM interrupts. 00934 * This parameter can be: ENABLE or DISABLE. 00935 * @retval None 00936 */ 00937 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState) 00938 { 00939 if(NewState != DISABLE) 00940 { 00941 HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT; 00942 } 00943 else 00944 { 00945 HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT; 00946 } 00947 } 00948 00949 /** 00950 * @brief Clears the Master and slaves interrupt flags 00951 * @param HRTIMx: pointer to HRTIMx peripheral 00952 * @param TimerIdx: Timer index 00953 * This parameter can be one of the following values: 00954 * @arg 0x0 to 0x4 for timers A to E 00955 * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared. 00956 * This parameter can be any combination of the following values: 00957 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag 00958 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag 00959 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag 00960 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag 00961 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag 00962 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag 00963 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag 00964 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag 00965 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag 00966 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag 00967 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag 00968 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag 00969 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag 00970 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag 00971 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag 00972 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag 00973 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag 00974 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag 00975 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag 00976 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag 00977 * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag 00978 * @retval None 00979 */ 00980 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) 00981 { 00982 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 00983 00984 switch(TimerIdx) 00985 { 00986 case HRTIM_TIMERINDEX_MASTER: 00987 { 00988 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG; 00989 } 00990 break; 00991 case HRTIM_TIMERINDEX_TIMER_A: 00992 case HRTIM_TIMERINDEX_TIMER_B: 00993 case HRTIM_TIMERINDEX_TIMER_C: 00994 case HRTIM_TIMERINDEX_TIMER_D: 00995 case HRTIM_TIMERINDEX_TIMER_E: 00996 { 00997 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG; 00998 } 00999 break; 01000 01001 default: 01002 break; 01003 } 01004 } 01005 01006 /** 01007 * @brief Clears the common interrupt flags 01008 * @param HRTIMx: pointer to HRTIMx peripheral 01009 * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared. 01010 * This parameter can be any combination of the following values: 01011 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag 01012 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag 01013 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag 01014 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag 01015 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag 01016 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag 01017 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag 01018 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag 01019 * @retval None 01020 */ 01021 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG) 01022 { 01023 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG; 01024 } 01025 01026 /** 01027 * @brief Clears the Master and slaves interrupt request pending bits 01028 * @param HRTIMx: pointer to HRTIMx peripheral 01029 * @param TimerIdx: Timer index 01030 * This parameter can be one of the following values: 01031 * @arg 0x0 to 0x4 for timers A to E 01032 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled. 01033 * This parameter can be any combination of the following values: 01034 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source 01035 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source 01036 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source 01037 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source 01038 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source 01039 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source 01040 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source 01041 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source 01042 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source 01043 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source 01044 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source 01045 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source 01046 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source 01047 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source 01048 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source 01049 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source 01050 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source 01051 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source 01052 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source 01053 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source 01054 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source 01055 * @retval None 01056 */ 01057 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) 01058 { 01059 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 01060 01061 switch(TimerIdx) 01062 { 01063 case HRTIM_TIMERINDEX_MASTER: 01064 { 01065 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT; 01066 } 01067 break; 01068 case HRTIM_TIMERINDEX_TIMER_A: 01069 case HRTIM_TIMERINDEX_TIMER_B: 01070 case HRTIM_TIMERINDEX_TIMER_C: 01071 case HRTIM_TIMERINDEX_TIMER_D: 01072 case HRTIM_TIMERINDEX_TIMER_E: 01073 { 01074 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT; 01075 } 01076 break; 01077 01078 default: 01079 break; 01080 } 01081 } 01082 01083 /** 01084 * @brief Clears the common interrupt pending bits 01085 * @param HRTIMx: pointer to HRTIMx peripheral 01086 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared. 01087 * This parameter can be any combination of the following values: 01088 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source 01089 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source 01090 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source 01091 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source 01092 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source 01093 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source 01094 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source 01095 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source 01096 * @retval None 01097 */ 01098 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT) 01099 { 01100 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT; 01101 } 01102 01103 01104 /** 01105 * @brief Checks whether the specified HRTIM flag is set or not. 01106 * @param HRTIMx: pointer to HRTIMx peripheral 01107 * @param TimerIdx: Timer index 01108 * This parameter can be one of the following values: 01109 * @arg 0x0 to 0x4 for timers A to E 01110 * @param HRTIM_FLAG: specifies the HRTIM flags to check. 01111 * This parameter can be any combination of the following values: 01112 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag 01113 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag 01114 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag 01115 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag 01116 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag 01117 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag 01118 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag 01119 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag 01120 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag 01121 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag 01122 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag 01123 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag 01124 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag 01125 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag 01126 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag 01127 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag 01128 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag 01129 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag 01130 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag 01131 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag 01132 * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag 01133 * @retval The new state of HRTIM_FLAG (SET or RESET). 01134 */ 01135 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) 01136 { 01137 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 01138 01139 FlagStatus bitstatus = RESET; 01140 01141 switch(TimerIdx) 01142 { 01143 case HRTIM_TIMERINDEX_MASTER: 01144 { 01145 if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET) 01146 { 01147 bitstatus = SET; 01148 } 01149 else 01150 { 01151 bitstatus = RESET; 01152 } 01153 } 01154 break; 01155 01156 case HRTIM_TIMERINDEX_TIMER_A: 01157 case HRTIM_TIMERINDEX_TIMER_B: 01158 case HRTIM_TIMERINDEX_TIMER_C: 01159 case HRTIM_TIMERINDEX_TIMER_D: 01160 case HRTIM_TIMERINDEX_TIMER_E: 01161 { 01162 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET) 01163 { 01164 bitstatus = SET; 01165 } 01166 else 01167 { 01168 bitstatus = RESET; 01169 } 01170 } 01171 break; 01172 01173 default: 01174 break; 01175 } 01176 return bitstatus; 01177 } 01178 01179 /** 01180 * @brief Checks whether the specified HRTIM common flag is set or not. 01181 * @param HRTIMx: pointer to HRTIMx peripheral 01182 * @param HRTIM_FLAG: specifies the HRTIM flags to check. 01183 * This parameter can be any combination of the following values: 01184 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag 01185 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag 01186 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag 01187 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag 01188 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag 01189 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag 01190 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag 01191 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag 01192 * @retval The new state of HRTIM_FLAG (SET or RESET). 01193 */ 01194 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG) 01195 { 01196 FlagStatus bitstatus = RESET; 01197 01198 if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET) 01199 { 01200 bitstatus = SET; 01201 } 01202 else 01203 { 01204 bitstatus = RESET; 01205 } 01206 return bitstatus; 01207 } 01208 01209 /** 01210 * @brief Checks whether the specified HRTIM interrupt has occurred or not. 01211 * @param HRTIMx: pointer to HRTIMx peripheral 01212 * @param TimerIdx: Timer index 01213 * This parameter can be one of the following values: 01214 * @arg 0x0 to 0x4 for timers A to E 01215 * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared. 01216 * This parameter can be any combination of the following values: 01217 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt 01218 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt 01219 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt 01220 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt 01221 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt 01222 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt 01223 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt 01224 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt 01225 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt 01226 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt 01227 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt 01228 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt 01229 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt 01230 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt 01231 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt 01232 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt 01233 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt 01234 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt 01235 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt 01236 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt 01237 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt 01238 * @retval The new state of the HRTIM_IT(SET or RESET). 01239 */ 01240 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) 01241 { 01242 ITStatus bitstatus = RESET; 01243 uint16_t itstatus = 0x0, itenable = 0x0; 01244 01245 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 01246 01247 switch(TimerIdx) 01248 { 01249 case HRTIM_TIMERINDEX_MASTER: 01250 { 01251 itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT; 01252 01253 itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT; 01254 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 01255 { 01256 bitstatus = SET; 01257 } 01258 else 01259 { 01260 bitstatus = RESET; 01261 } 01262 } 01263 break; 01264 01265 case HRTIM_TIMERINDEX_TIMER_A: 01266 case HRTIM_TIMERINDEX_TIMER_B: 01267 case HRTIM_TIMERINDEX_TIMER_C: 01268 case HRTIM_TIMERINDEX_TIMER_D: 01269 case HRTIM_TIMERINDEX_TIMER_E: 01270 { 01271 itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT; 01272 01273 itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT; 01274 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 01275 { 01276 bitstatus = SET; 01277 } 01278 else 01279 { 01280 bitstatus = RESET; 01281 } 01282 } 01283 break; 01284 01285 default: 01286 break; 01287 } 01288 return bitstatus; 01289 } 01290 01291 /** 01292 * @brief Checks whether the specified HRTIM common interrupt has occurred or not. 01293 * @param HRTIMx: pointer to HRTIMx peripheral 01294 * @param HRTIM_IT: specifies the HRTIM interrupt source to check. 01295 * This parameter can be any combination of the following values: 01296 * @arg HRTIM_IT_FLT1: Fault 1 interrupt 01297 * @arg HRTIM_IT_FLT2: Fault 2 interrupt 01298 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt 01299 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt 01300 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt 01301 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt 01302 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag 01303 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt 01304 * @retval The new state of HRTIM_FLAG (SET or RESET). 01305 */ 01306 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT) 01307 { 01308 ITStatus bitstatus = RESET; 01309 uint16_t itstatus = 0x0, itenable = 0x0; 01310 01311 itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT; 01312 itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT; 01313 01314 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 01315 { 01316 bitstatus = SET; 01317 } 01318 else 01319 { 01320 bitstatus = RESET; 01321 } 01322 01323 return bitstatus; 01324 } 01325 01326 /** 01327 * @brief Enables or disables the HRTIMx's DMA Requests. 01328 * @param HRTIMx: pointer to HRTIMx peripheral 01329 * @param TimerIdx: Timer index 01330 * This parameter can be one of the following values: 01331 * @arg 0x0 to 0x4 for timers A to E 01332 * @param HRTIM_DMA: specifies the DMA Request sources. 01333 * This parameter can be any combination of the following values: 01334 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source 01335 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source 01336 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source 01337 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source 01338 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source 01339 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source 01340 * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source 01341 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source 01342 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source 01343 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source 01344 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source 01345 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source 01346 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source 01347 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source 01348 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source 01349 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source 01350 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source 01351 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source 01352 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source 01353 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source 01354 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source 01355 * @param NewState: new state of the DMA Request sources. 01356 * This parameter can be: ENABLE or DISABLE. 01357 * @retval None 01358 */ 01359 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState) 01360 { 01361 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); 01362 01363 switch(TimerIdx) 01364 { 01365 case HRTIM_TIMERINDEX_MASTER: 01366 { 01367 if(NewState != DISABLE) 01368 { 01369 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA; 01370 } 01371 else 01372 { 01373 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA; 01374 } 01375 } 01376 break; 01377 case HRTIM_TIMERINDEX_TIMER_A: 01378 case HRTIM_TIMERINDEX_TIMER_B: 01379 case HRTIM_TIMERINDEX_TIMER_C: 01380 case HRTIM_TIMERINDEX_TIMER_D: 01381 case HRTIM_TIMERINDEX_TIMER_E: 01382 { 01383 if(NewState != DISABLE) 01384 { 01385 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA; 01386 } 01387 else 01388 { 01389 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA; 01390 } 01391 } 01392 break; 01393 01394 default: 01395 break; 01396 } 01397 } 01398 01399 /** 01400 * @} 01401 */ 01402 01403 /** @defgroup HRTIM_Group3 Peripheral Control methods 01404 * @brief management functions 01405 * 01406 @verbatim 01407 =============================================================================== 01408 ##### Peripheral Control methods ##### 01409 =============================================================================== 01410 [..] 01411 This subsection provides a set of functions allowing to control the HRTIMx data 01412 transfers. 01413 01414 @endverbatim 01415 * @{ 01416 */ 01417 01418 /** 01419 * @brief Configures an output in basic output compare mode 01420 * @param HRTIMx: pointer to HRTIMx peripheral 01421 * @param TimerIdx: Timer index 01422 * This parameter can be one of the following values: 01423 * @arg 0x0 to 0x4 for timers A to E 01424 * @param OCChannel: Timer output 01425 * This parameter can be one of the following values: 01426 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 01427 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 01428 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 01429 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 01430 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 01431 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 01432 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 01433 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 01434 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 01435 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 01436 * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure 01437 * @note When the timer operates in basic output compare mode: 01438 * Output 1 is implicitly controlled by the compare unit 1 01439 * Output 2 is implicitly controlled by the compare unit 2 01440 * Output Set/Reset crossbar is set according to the selected output compare mode: 01441 * Toggle: SETxyR = RSTxyR = CMPy 01442 * Active: SETxyR = CMPy, RSTxyR = 0 01443 * Inactive: SETxy =0, RSTxy = CMPy 01444 * @retval None 01445 */ 01446 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIMx, 01447 uint32_t TimerIdx, 01448 uint32_t OCChannel, 01449 HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg) 01450 { 01451 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; 01452 HRTIM_CompareCfgTypeDef CompareCfg; 01453 HRTIM_OutputCfgTypeDef OutputCfg; 01454 01455 /* Check parameters */ 01456 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); 01457 assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode)); 01458 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity)); 01459 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState)); 01460 01461 /* Configure timer compare unit */ 01462 switch (OCChannel) 01463 { 01464 case HRTIM_OUTPUT_TA1: 01465 case HRTIM_OUTPUT_TB1: 01466 case HRTIM_OUTPUT_TC1: 01467 case HRTIM_OUTPUT_TD1: 01468 case HRTIM_OUTPUT_TE1: 01469 { 01470 CompareUnit = HRTIM_COMPAREUNIT_1; 01471 } 01472 break; 01473 case HRTIM_OUTPUT_TA2: 01474 case HRTIM_OUTPUT_TB2: 01475 case HRTIM_OUTPUT_TC2: 01476 case HRTIM_OUTPUT_TD2: 01477 case HRTIM_OUTPUT_TE2: 01478 { 01479 CompareUnit = HRTIM_COMPAREUNIT_2; 01480 } 01481 break; 01482 default: 01483 break; 01484 } 01485 01486 CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse; 01487 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; 01488 CompareCfg.AutoDelayedTimeout = 0; 01489 01490 HRTIM_CompareUnitConfig(HRTIMx, 01491 TimerIdx, 01492 CompareUnit, 01493 &CompareCfg); 01494 01495 /* Configure timer output */ 01496 OutputCfg.Polarity = pBasicOCChannelCfg->Polarity; 01497 OutputCfg.IdleState = pBasicOCChannelCfg->IdleState; 01498 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; 01499 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; 01500 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; 01501 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; 01502 01503 switch (pBasicOCChannelCfg->Mode) 01504 { 01505 case HRTIM_BASICOCMODE_TOGGLE: 01506 { 01507 if (CompareUnit == HRTIM_COMPAREUNIT_1) 01508 { 01509 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; 01510 } 01511 else 01512 { 01513 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; 01514 } 01515 OutputCfg.ResetSource = OutputCfg.SetSource; 01516 } 01517 break; 01518 case HRTIM_BASICOCMODE_ACTIVE: 01519 { 01520 if (CompareUnit == HRTIM_COMPAREUNIT_1) 01521 { 01522 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; 01523 } 01524 else 01525 { 01526 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; 01527 } 01528 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; 01529 } 01530 break; 01531 case HRTIM_BASICOCMODE_INACTIVE: 01532 { 01533 if (CompareUnit == HRTIM_COMPAREUNIT_1) 01534 { 01535 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1; 01536 } 01537 else 01538 { 01539 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2; 01540 } 01541 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; 01542 } 01543 break; 01544 default: 01545 break; 01546 } 01547 01548 HRTIM_OutputConfig(HRTIMx, TimerIdx, OCChannel, &OutputCfg); 01549 } 01550 01551 /** 01552 * @brief Configures an output in basic PWM mode 01553 * @param HRTIMx: pointer to HRTIMx peripheral 01554 * @param TimerIdx: Timer index 01555 * This parameter can be one of the following values: 01556 * @arg 0x0 to 0x4 for timers A to E 01557 * @param PWMChannel: Timer output 01558 * This parameter can be one of the following values: 01559 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 01560 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 01561 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 01562 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 01563 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 01564 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 01565 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 01566 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 01567 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 01568 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 01569 * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure 01570 * @note When the timer operates in basic PWM output mode: 01571 * Output 1 is implicitly controlled by the compare unit 1 01572 * Output 2 is implicitly controlled by the compare unit 2 01573 * Output Set/Reset crossbar is set as follows: 01574 * Output 1: SETx1R = CMP1, RSTx1R = PER 01575 * Output 2: SETx2R = CMP2, RST2R = PER 01576 * @retval None 01577 */ 01578 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIMx, 01579 uint32_t TimerIdx, 01580 uint32_t PWMChannel, 01581 HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg) 01582 { 01583 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; 01584 HRTIM_CompareCfgTypeDef CompareCfg; 01585 HRTIM_OutputCfgTypeDef OutputCfg; 01586 01587 /* Check parameters */ 01588 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); 01589 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity)); 01590 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState)); 01591 01592 /* Configure timer compare unit */ 01593 switch (PWMChannel) 01594 { 01595 case HRTIM_OUTPUT_TA1: 01596 case HRTIM_OUTPUT_TB1: 01597 case HRTIM_OUTPUT_TC1: 01598 case HRTIM_OUTPUT_TD1: 01599 case HRTIM_OUTPUT_TE1: 01600 { 01601 CompareUnit = HRTIM_COMPAREUNIT_1; 01602 } 01603 break; 01604 case HRTIM_OUTPUT_TA2: 01605 case HRTIM_OUTPUT_TB2: 01606 case HRTIM_OUTPUT_TC2: 01607 case HRTIM_OUTPUT_TD2: 01608 case HRTIM_OUTPUT_TE2: 01609 { 01610 CompareUnit = HRTIM_COMPAREUNIT_2; 01611 } 01612 break; 01613 default: 01614 break; 01615 } 01616 01617 CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse; 01618 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; 01619 CompareCfg.AutoDelayedTimeout = 0; 01620 01621 HRTIM_CompareUnitConfig(HRTIMx, 01622 TimerIdx, 01623 CompareUnit, 01624 &CompareCfg); 01625 01626 /* Configure timer output */ 01627 OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity; 01628 OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState; 01629 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; 01630 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; 01631 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; 01632 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; 01633 01634 if (CompareUnit == HRTIM_COMPAREUNIT_1) 01635 { 01636 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; 01637 } 01638 else 01639 { 01640 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; 01641 } 01642 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER; 01643 01644 HRTIM_OutputConfig(HRTIMx, TimerIdx, PWMChannel, &OutputCfg); 01645 } 01646 01647 /** 01648 * @brief Configures a basic capture 01649 * @param HRTIMx: pointer to HRTIMx peripheral 01650 * @param TimerIdx: Timer index 01651 * This parameter can be one of the following values: 01652 * @arg 0x0 to 0x4 for timers A to E 01653 * @param CaptureChannel: Capture unit 01654 * This parameter can be one of the following values: 01655 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 01656 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 01657 * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure 01658 * @note When the timer operates in basic capture mode the capture is triggered 01659 * by the designated external event and GPIO input is implicitly used as event source. 01660 * The capture can be triggered by a rising edge, a falling edge or both 01661 * edges on event channel. 01662 * @retval None 01663 */ 01664 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx, 01665 uint32_t TimerIdx, 01666 uint32_t CaptureChannel, 01667 HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg) 01668 { 01669 HRTIM_EventCfgTypeDef EventCfg; 01670 01671 /* Check parameters */ 01672 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 01673 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel)); 01674 assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event)); 01675 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity)); 01676 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity)); 01677 assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter)); 01678 01679 /* Configure external event channel */ 01680 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; 01681 EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter; 01682 EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity; 01683 EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity; 01684 EventCfg.Source = HRTIM_EVENTSRC_1; 01685 01686 HRTIM_ExternalEventConfig(HRTIMx, 01687 pBasicCaptureChannelCfg->Event, 01688 &EventCfg); 01689 01690 /* Memorize capture trigger (will be configured when the capture is started */ 01691 HRTIM_CaptureUnitConfig(HRTIMx, 01692 TimerIdx, 01693 CaptureChannel, 01694 pBasicCaptureChannelCfg->Event); 01695 } 01696 01697 /** 01698 * @brief Configures an output basic one pulse mode 01699 * @param HRTIMx: pointer to HRTIMx peripheral 01700 * @param TimerIdx: Timer index 01701 * This parameter can be one of the following values: 01702 * @arg 0x0 to 0x4 for timers A to E 01703 * @param OnePulseChannel: Timer output 01704 * This parameter can be one of the following values: 01705 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 01706 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 01707 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 01708 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 01709 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 01710 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 01711 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 01712 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 01713 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 01714 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 01715 * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure 01716 * @note When the timer operates in basic one pulse mode: 01717 * the timer counter is implicitly started by the reset event, 01718 * the reset of the timer counter is triggered by the designated external event 01719 * GPIO input is implicitly used as event source, 01720 * Output 1 is implicitly controlled by the compare unit 1, 01721 * Output 2 is implicitly controlled by the compare unit 2. 01722 * Output Set/Reset crossbar is set as follows: 01723 * Output 1: SETx1R = CMP1, RSTx1R = PER 01724 * Output 2: SETx2R = CMP2, RST2R = PER 01725 * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE 01726 * @retval None 01727 */ 01728 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIMx, 01729 uint32_t TimerIdx, 01730 uint32_t OnePulseChannel, 01731 HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg) 01732 { 01733 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1; 01734 HRTIM_CompareCfgTypeDef CompareCfg; 01735 HRTIM_OutputCfgTypeDef OutputCfg; 01736 HRTIM_EventCfgTypeDef EventCfg; 01737 01738 /* Check parameters */ 01739 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel)); 01740 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity)); 01741 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState)); 01742 assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event)); 01743 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity)); 01744 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity)); 01745 assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter)); 01746 01747 /* Configure timer compare unit */ 01748 switch (OnePulseChannel) 01749 { 01750 case HRTIM_OUTPUT_TA1: 01751 case HRTIM_OUTPUT_TB1: 01752 case HRTIM_OUTPUT_TC1: 01753 case HRTIM_OUTPUT_TD1: 01754 case HRTIM_OUTPUT_TE1: 01755 { 01756 CompareUnit = HRTIM_COMPAREUNIT_1; 01757 } 01758 break; 01759 case HRTIM_OUTPUT_TA2: 01760 case HRTIM_OUTPUT_TB2: 01761 case HRTIM_OUTPUT_TC2: 01762 case HRTIM_OUTPUT_TD2: 01763 case HRTIM_OUTPUT_TE2: 01764 { 01765 CompareUnit = HRTIM_COMPAREUNIT_2; 01766 } 01767 break; 01768 default: 01769 break; 01770 } 01771 01772 CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse; 01773 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR; 01774 CompareCfg.AutoDelayedTimeout = 0; 01775 01776 HRTIM_CompareUnitConfig(HRTIMx, 01777 TimerIdx, 01778 CompareUnit, 01779 &CompareCfg); 01780 01781 /* Configure timer output */ 01782 OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity; 01783 OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState; 01784 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE; 01785 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE; 01786 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED; 01787 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR; 01788 01789 if (CompareUnit == HRTIM_COMPAREUNIT_1) 01790 { 01791 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1; 01792 } 01793 else 01794 { 01795 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2; 01796 } 01797 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER; 01798 01799 HRTIM_OutputConfig(HRTIMx, 01800 TimerIdx, 01801 OnePulseChannel, 01802 &OutputCfg); 01803 01804 /* Configure external event channel */ 01805 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE; 01806 EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter; 01807 EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity; 01808 EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity; 01809 EventCfg.Source = HRTIM_EVENTSRC_1; 01810 01811 HRTIM_ExternalEventConfig(HRTIMx, 01812 pBasicOnePulseChannelCfg->Event, 01813 &EventCfg); 01814 01815 /* Configure the timer reset register */ 01816 HRTIM_TIM_ResetConfig(HRTIMx, 01817 TimerIdx, 01818 pBasicOnePulseChannelCfg->Event); 01819 } 01820 01821 /** 01822 * @brief Configures the general behavior of a timer operating in waveform mode 01823 * @param HRTIMx: pointer to HRTIMx peripheral 01824 * @param TimerIdx: Timer index 01825 * This parameter can be one of the following values: 01826 * @arg 0x0 to 0x4 for timers A to E 01827 * @param pTimerCfg: pointer to the timer configuration structure 01828 * @note When the timer operates in waveform mode, all the features supported by 01829 * the HRTIMx are available without any limitation. 01830 * @retval None 01831 */ 01832 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx, 01833 uint32_t TimerIdx, 01834 HRTIM_TimerCfgTypeDef * pTimerCfg) 01835 { 01836 uint32_t HRTIM_timcr; 01837 uint32_t HRTIM_timfltr; 01838 uint32_t HRTIM_timoutr; 01839 uint32_t HRTIM_timrstr; 01840 01841 /* Check parameters */ 01842 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 01843 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull)); 01844 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable)); 01845 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock)); 01846 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion)); 01847 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode)); 01848 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger)); 01849 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger)); 01850 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate)); 01851 01852 /* Configure timing unit (Timer A to Timer E) */ 01853 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; 01854 HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR; 01855 HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR; 01856 HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR; 01857 01858 /* Set the push-pull mode */ 01859 HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL); 01860 HRTIM_timcr |= pTimerCfg->PushPull; 01861 01862 /* Enable/Disable registers update on timer counter reset */ 01863 HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU); 01864 HRTIM_timcr |= pTimerCfg->ResetUpdate; 01865 01866 /* Set the timer update trigger */ 01867 HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER); 01868 HRTIM_timcr |= pTimerCfg->UpdateTrigger; 01869 01870 /* Enable/Disable the fault channel at timer level */ 01871 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN); 01872 HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN); 01873 01874 /* Lock/Unlock fault sources at timer level */ 01875 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK); 01876 HRTIM_timfltr |= pTimerCfg->FaultLock; 01877 01878 /* Enable/Disable dead time insertion at timer level */ 01879 HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN); 01880 HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion; 01881 01882 /* Enable/Disable delayed protection at timer level */ 01883 HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN); 01884 HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode; 01885 01886 /* Set the timer counter reset trigger */ 01887 HRTIM_timrstr = pTimerCfg->ResetTrigger; 01888 01889 /* Update the HRTIMx registers */ 01890 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; 01891 HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr; 01892 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr; 01893 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr; 01894 } 01895 01896 /** 01897 * @brief Configures the compare unit of a timer operating in waveform mode 01898 * @param HRTIMx: pointer to HRTIMx peripheral 01899 * @param TimerIdx: Timer index 01900 * 0xFF for master timer 01901 * This parameter can be one of the following values: 01902 * @arg 0x0 to 0x4 for timers A to E 01903 * @param CompareUnit: Compare unit to configure 01904 * This parameter can be one of the following values: 01905 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 01906 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 01907 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 01908 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 01909 * @param pCompareCfg: pointer to the compare unit configuration structure 01910 * @note When auto delayed mode is required for compare unit 2 or compare unit 4, 01911 * application has to configure separately the capture unit. Capture unit 01912 * to configure in that case depends on the compare unit auto delayed mode 01913 * is applied to (see below): 01914 * Auto delayed on output compare 2: capture unit 1 must be configured 01915 * Auto delayed on output compare 4: capture unit 2 must be configured 01916 * @retval None 01917 */ 01918 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx, 01919 uint32_t TimerIdx, 01920 uint32_t CompareUnit, 01921 HRTIM_CompareCfgTypeDef* pCompareCfg) 01922 { 01923 uint32_t HRTIM_timcr; 01924 01925 /* Check parameters */ 01926 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 01927 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode)); 01928 01929 /* Configure the compare unit */ 01930 switch (CompareUnit) 01931 { 01932 case HRTIM_COMPAREUNIT_1: 01933 { 01934 /* Set the compare value */ 01935 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue; 01936 } 01937 break; 01938 case HRTIM_COMPAREUNIT_2: 01939 { 01940 /* Set the compare value */ 01941 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue; 01942 01943 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) 01944 { 01945 /* Configure auto-delayed mode */ 01946 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; 01947 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2; 01948 HRTIM_timcr |= pCompareCfg->AutoDelayedMode; 01949 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; 01950 01951 /* Set the compare value for timeout compare unit (if any) */ 01952 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) 01953 { 01954 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; 01955 } 01956 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) 01957 { 01958 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; 01959 } 01960 } 01961 } 01962 break; 01963 case HRTIM_COMPAREUNIT_3: 01964 { 01965 /* Set the compare value */ 01966 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue; 01967 } 01968 break; 01969 case HRTIM_COMPAREUNIT_4: 01970 { 01971 /* Set the compare value */ 01972 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue; 01973 01974 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR) 01975 { 01976 /* Configure auto-delayed mode */ 01977 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; 01978 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4; 01979 HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2); 01980 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; 01981 01982 /* Set the compare value for timeout compare unit (if any) */ 01983 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) 01984 { 01985 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout; 01986 } 01987 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3) 01988 { 01989 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout; 01990 } 01991 } 01992 } 01993 break; 01994 default: 01995 break; 01996 } 01997 } 01998 01999 /** 02000 * @brief Sets the HRTIMx Master Comparex Register value 02001 * @param HRTIMx: pointer to HRTIMx peripheral 02002 * @param CompareUnit: Compare unit to configure 02003 * This parameter can be one of the following values: 02004 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 02005 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 02006 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 02007 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 02008 * @param Compare: specifies the Comparex register new value 02009 * @retval None 02010 */ 02011 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx, 02012 uint32_t CompareUnit, 02013 uint32_t Compare) 02014 { 02015 /* Check parameters */ 02016 assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit)); 02017 02018 /* Configure the compare unit */ 02019 switch (CompareUnit) 02020 { 02021 case HRTIM_COMPAREUNIT_1: 02022 { 02023 /* Set the compare value */ 02024 HRTIMx->HRTIM_MASTER.MCMP1R = Compare; 02025 } 02026 break; 02027 case HRTIM_COMPAREUNIT_2: 02028 { 02029 /* Set the compare value */ 02030 HRTIMx->HRTIM_MASTER.MCMP2R = Compare; 02031 } 02032 break; 02033 case HRTIM_COMPAREUNIT_3: 02034 { 02035 /* Set the compare value */ 02036 HRTIMx->HRTIM_MASTER.MCMP3R = Compare; 02037 } 02038 break; 02039 case HRTIM_COMPAREUNIT_4: 02040 { 02041 /* Set the compare value */ 02042 HRTIMx->HRTIM_MASTER.MCMP4R = Compare; 02043 } 02044 break; 02045 default: 02046 break; 02047 } 02048 } 02049 02050 /** 02051 * @brief Sets the HRTIMx Slave Comparex Register value 02052 * @param HRTIMx: pointer to HRTIMx peripheral 02053 * @param CompareUnit: Compare unit to configure 02054 * This parameter can be one of the following values: 02055 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 02056 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 02057 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 02058 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 02059 * @param Compare: specifies the Comparex register new value 02060 * @retval None 02061 */ 02062 void HRTIM_SlaveSetCompare(HRTIM_TypeDef * HRTIMx, 02063 uint32_t TimerIdx, 02064 uint32_t CompareUnit, 02065 uint32_t Compare) 02066 { 02067 /* Check parameters */ 02068 assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit)); 02069 02070 /* Configure the compare unit */ 02071 switch (CompareUnit) 02072 { 02073 case HRTIM_COMPAREUNIT_1: 02074 { 02075 /* Set the compare value */ 02076 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = Compare; 02077 } 02078 break; 02079 case HRTIM_COMPAREUNIT_2: 02080 { 02081 /* Set the compare value */ 02082 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = Compare; 02083 } 02084 break; 02085 case HRTIM_COMPAREUNIT_3: 02086 { 02087 /* Set the compare value */ 02088 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = Compare; 02089 } 02090 break; 02091 case HRTIM_COMPAREUNIT_4: 02092 { 02093 /* Set the compare value */ 02094 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = Compare; 02095 } 02096 break; 02097 default: 02098 break; 02099 } 02100 } 02101 /** 02102 * @brief Configures the capture unit of a timer operating in waveform mode 02103 * @param HRTIMx: pointer to HRTIMx peripheral 02104 * @param TimerIdx: Timer index 02105 * This parameter can be one of the following values: 02106 * @arg 0x0 to 0x4 for timers A to E 02107 * @param CaptureChannel: Capture unit to configure 02108 * This parameter can be one of the following values: 02109 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 02110 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 02111 * @param pCaptureCfg: pointer to the compare unit configuration structure 02112 * @retval None 02113 */ 02114 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx, 02115 uint32_t TimerIdx, 02116 uint32_t CaptureUnit, 02117 HRTIM_CaptureCfgTypeDef* pCaptureCfg) 02118 { 02119 /* Configure the capture unit */ 02120 switch (CaptureUnit) 02121 { 02122 case HRTIM_CAPTUREUNIT_1: 02123 { 02124 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger; 02125 } 02126 break; 02127 case HRTIM_CAPTUREUNIT_2: 02128 { 02129 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger; 02130 } 02131 break; 02132 default: 02133 break; 02134 } 02135 } 02136 02137 /** 02138 * @brief Configures the output of a timer operating in waveform mode 02139 * @param HRTIMx: pointer to HRTIMx peripheral 02140 * @param TimerIdx: Timer index 02141 * This parameter can be one of the following values: 02142 * @arg 0x0 to 0x4 for timers A to E 02143 * @param Output: Timer output 02144 * This parameter can be one of the following values: 02145 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 02146 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 02147 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 02148 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 02149 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 02150 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 02151 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 02152 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 02153 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 02154 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 02155 * @param pOutputCfg: pointer to the timer output configuration structure 02156 * @retval None 02157 */ 02158 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIMx, 02159 uint32_t TimerIdx, 02160 uint32_t Output, 02161 HRTIM_OutputCfgTypeDef * pOutputCfg) 02162 { 02163 /* Check parameters */ 02164 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); 02165 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity)); 02166 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState)); 02167 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode)); 02168 assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState)); 02169 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable)); 02170 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed)); 02171 02172 /* Configure the timer output */ 02173 HRTIM_OutputConfig(HRTIMx, TimerIdx, Output, pOutputCfg); 02174 } 02175 02176 /** 02177 * @brief Configures the event filtering capabilities of a timer (blanking, windowing) 02178 * @param HRTIMx: pointer to HRTIMx peripheral 02179 * @param TimerIdx: Timer index 02180 * This parameter can be one of the following values: 02181 * @arg 0x0 to 0x4 for timers A to E 02182 * @param Event: external event for which timer event filtering must be configured 02183 * This parameter can be one of the following values: 02184 * @arg HRTIM_EVENT_1: External event 1 02185 * @arg HRTIM_EVENT_2: External event 2 02186 * @arg HRTIM_EVENT_3: External event 3 02187 * @arg HRTIM_EVENT_4: External event 4 02188 * @arg HRTIM_EVENT_5: External event 5 02189 * @arg HRTIM_EVENT_6: External event 6 02190 * @arg HRTIM_EVENT_7: External event 7 02191 * @arg HRTIM_EVENT_8: External event 8 02192 * @arg HRTIM_EVENT_9: External event 9 02193 * @arg HRTIM_EVENT_10: External event 10 02194 * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure 02195 * @retval None 02196 */ 02197 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx, 02198 uint32_t TimerIdx, 02199 uint32_t Event, 02200 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) 02201 { 02202 uint32_t HRTIM_eefr; 02203 02204 /* Check parameters */ 02205 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 02206 assert_param(IS_HRTIM_EVENT(Event)); 02207 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter)); 02208 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch)); 02209 02210 /* Configure timer event filtering capabilities */ 02211 switch (Event) 02212 { 02213 case HRTIM_TIMEVENTFILTER_NONE: 02214 { 02215 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0; 02216 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0; 02217 } 02218 break; 02219 case HRTIM_EVENT_1: 02220 { 02221 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; 02222 HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH); 02223 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch); 02224 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; 02225 } 02226 break; 02227 case HRTIM_EVENT_2: 02228 { 02229 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; 02230 HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH); 02231 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); 02232 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; 02233 } 02234 break; 02235 case HRTIM_EVENT_3: 02236 { 02237 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; 02238 HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH); 02239 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); 02240 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; 02241 } 02242 break; 02243 case HRTIM_EVENT_4: 02244 { 02245 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; 02246 HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH); 02247 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); 02248 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; 02249 } 02250 break; 02251 case HRTIM_EVENT_5: 02252 { 02253 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1; 02254 HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH); 02255 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); 02256 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr; 02257 } 02258 break; 02259 case HRTIM_EVENT_6: 02260 { 02261 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; 02262 HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH); 02263 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch); 02264 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; 02265 } 02266 break; 02267 case HRTIM_EVENT_7: 02268 { 02269 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; 02270 HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH); 02271 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6); 02272 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; 02273 } 02274 break; 02275 case HRTIM_EVENT_8: 02276 { 02277 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; 02278 HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH); 02279 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12); 02280 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; 02281 } 02282 break; 02283 case HRTIM_EVENT_9: 02284 { 02285 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; 02286 HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH); 02287 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18); 02288 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; 02289 } 02290 break; 02291 case HRTIM_EVENT_10: 02292 { 02293 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2; 02294 HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH); 02295 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24); 02296 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr; 02297 } 02298 break; 02299 default: 02300 break; 02301 } 02302 } 02303 02304 /** 02305 * @brief Configures the dead time insertion feature for a timer 02306 * @param HRTIMx: pointer to HRTIMx peripheral 02307 * @param TimerIdx: Timer index 02308 * This parameter can be one of the following values: 02309 * @arg 0x0 to 0x4 for timers A to E 02310 * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure 02311 * @retval None 02312 */ 02313 void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx, 02314 uint32_t TimerIdx, 02315 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) 02316 { 02317 uint32_t HRTIM_dtr; 02318 02319 /* Check parameters */ 02320 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 02321 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign)); 02322 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock)); 02323 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock)); 02324 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign)); 02325 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock)); 02326 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock)); 02327 02328 HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR; 02329 02330 /* Clear timer dead times configuration */ 02331 HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC | 02332 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF | 02333 HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK); 02334 02335 /* Set timer dead times configuration */ 02336 HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10); 02337 HRTIM_dtr |= pDeadTimeCfg->RisingValue; 02338 HRTIM_dtr |= pDeadTimeCfg->RisingSign; 02339 HRTIM_dtr |= pDeadTimeCfg->RisingSignLock; 02340 HRTIM_dtr |= pDeadTimeCfg->RisingLock; 02341 HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16); 02342 HRTIM_dtr |= pDeadTimeCfg->FallingSign; 02343 HRTIM_dtr |= pDeadTimeCfg->FallingSignLock; 02344 HRTIM_dtr |= pDeadTimeCfg->FallingLock; 02345 02346 /* Update the HRTIMx registers */ 02347 HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr; 02348 } 02349 02350 /** 02351 * @brief Configures the chopper mode feature for a timer 02352 * @param HRTIMx: pointer to HRTIMx peripheral 02353 * @param TimerIdx: Timer index 02354 * This parameter can be one of the following values: 02355 * @arg 0x0 to 0x4 for timers A to E 02356 * @param pChopperModeCfg: pointer to the chopper mode configuration structure 02357 * @retval None 02358 */ 02359 void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx, 02360 uint32_t TimerIdx, 02361 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) 02362 { 02363 uint32_t HRTIM_chpr; 02364 02365 /* Check parameters */ 02366 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 02367 02368 HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR; 02369 02370 /* Clear timer chopper mode configuration */ 02371 HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW); 02372 02373 /* Set timer chopper mode configuration */ 02374 HRTIM_chpr |= pChopperModeCfg->CarrierFreq; 02375 HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4); 02376 HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7); 02377 02378 /* Update the HRTIMx registers */ 02379 HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr; 02380 } 02381 02382 /** 02383 * @brief Configures the burst DMA controller for a timer 02384 * @param HRTIMx: pointer to HRTIMx peripheral 02385 * @param TimerIdx: Timer index 02386 * This parameter can be one of the following values: 02387 * @arg 0x5 for master timer 02388 * @arg 0x0 to 0x4 for timers A to E 02389 * @param RegistersToUpdate: registers to be written by DMA 02390 * This parameter can be any combination of the following values: 02391 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR 02392 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR 02393 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER 02394 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT 02395 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER 02396 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP 02397 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1 02398 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2 02399 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3 02400 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4 02401 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR 02402 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R 02403 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R 02404 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R 02405 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R 02406 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1 02407 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2 02408 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR 02409 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR 02410 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR 02411 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR 02412 * @retval None 02413 */ 02414 void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx, 02415 uint32_t TimerIdx, 02416 uint32_t RegistersToUpdate) 02417 { 02418 /* Check parameters */ 02419 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate)); 02420 02421 /* Set the burst DMA timer update register */ 02422 switch (TimerIdx) 02423 { 02424 case HRTIM_TIMERINDEX_TIMER_A: 02425 { 02426 HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate; 02427 } 02428 break; 02429 case HRTIM_TIMERINDEX_TIMER_B: 02430 { 02431 HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate; 02432 } 02433 break; 02434 case HRTIM_TIMERINDEX_TIMER_C: 02435 { 02436 HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate; 02437 } 02438 break; 02439 case HRTIM_TIMERINDEX_TIMER_D: 02440 { 02441 HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate; 02442 } 02443 break; 02444 case HRTIM_TIMERINDEX_TIMER_E: 02445 { 02446 HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate; 02447 } 02448 break; 02449 case HRTIM_TIMERINDEX_MASTER: 02450 { 02451 HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate; 02452 } 02453 break; 02454 default: 02455 break; 02456 } 02457 } 02458 02459 /** 02460 * @brief Configures the external input/output synchronization of the HRTIMx 02461 * @param HRTIMx: pointer to HRTIMx peripheral 02462 * @param pSynchroCfg: pointer to the input/output synchronization configuration structure 02463 * @retval None 02464 */ 02465 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg) 02466 { 02467 uint32_t HRTIM_mcr; 02468 02469 /* Check parameters */ 02470 assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource)); 02471 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource)); 02472 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity)); 02473 02474 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR; 02475 02476 /* Set the synchronization input source */ 02477 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN); 02478 HRTIM_mcr |= pSynchroCfg->SyncInputSource; 02479 02480 /* Set the event to be sent on the synchronization output */ 02481 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC); 02482 HRTIM_mcr |= pSynchroCfg->SyncOutputSource; 02483 02484 /* Set the polarity of the synchronization output */ 02485 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT); 02486 HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity; 02487 02488 /* Update the HRTIMx registers */ 02489 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr; 02490 } 02491 02492 /** 02493 * @brief Configures the burst mode feature of the HRTIMx 02494 * @param HRTIMx: pointer to HRTIMx peripheral 02495 * @param pBurstModeCfg: pointer to the burst mode configuration structure 02496 * @retval None 02497 */ 02498 void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx, 02499 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) 02500 { 02501 uint32_t HRTIM_bmcr; 02502 02503 /* Check parameters */ 02504 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode)); 02505 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource)); 02506 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler)); 02507 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable)); 02508 02509 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; 02510 02511 /* Set the burst mode operating mode */ 02512 HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM); 02513 HRTIM_bmcr |= pBurstModeCfg->Mode; 02514 02515 /* Set the burst mode clock source */ 02516 HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK); 02517 HRTIM_bmcr |= pBurstModeCfg->ClockSource; 02518 02519 /* Set the burst mode prescaler */ 02520 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC); 02521 HRTIM_bmcr |= pBurstModeCfg->Prescaler; 02522 02523 /* Enable/disable burst mode registers preload */ 02524 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN); 02525 HRTIM_bmcr |= pBurstModeCfg->PreloadEnable; 02526 02527 /* Set the burst mode trigger */ 02528 HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger; 02529 02530 /* Set the burst mode compare value */ 02531 HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration; 02532 02533 /* Set the burst mode period */ 02534 HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period; 02535 02536 /* Update the HRTIMx registers */ 02537 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; 02538 } 02539 02540 /** 02541 * @brief Configures the conditioning of an external event 02542 * @param HRTIMx: pointer to HRTIMx peripheral 02543 * @param Event: external event to configure 02544 * This parameter can be one of the following values: 02545 * @arg HRTIM_EVENT_1: External event 1 02546 * @arg HRTIM_EVENT_2: External event 2 02547 * @arg HRTIM_EVENT_3: External event 3 02548 * @arg HRTIM_EVENT_4: External event 4 02549 * @arg HRTIM_EVENT_5: External event 5 02550 * @arg HRTIM_EVENT_6: External event 6 02551 * @arg HRTIM_EVENT_7: External event 7 02552 * @arg HRTIM_EVENT_8: External event 8 02553 * @arg HRTIM_EVENT_9: External event 9 02554 * @arg HRTIM_EVENT_10: External event 10 02555 * @param pEventCfg: pointer to the event conditioning configuration structure 02556 * @retval None 02557 */ 02558 void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx, 02559 uint32_t Event, 02560 HRTIM_EventCfgTypeDef* pEventCfg) 02561 { 02562 /* Check parameters */ 02563 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source)); 02564 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity)); 02565 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity)); 02566 assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode)); 02567 assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter)); 02568 02569 /* Configure the event channel */ 02570 HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg); 02571 02572 } 02573 02574 /** 02575 * @brief Configures the external event conditioning block prescaler 02576 * @param HRTIMx: pointer to HRTIMx peripheral 02577 * @param Prescaler: Prescaler value 02578 * This parameter can be one of the following values: 02579 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx 02580 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2 02581 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4 02582 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8 02583 * @retval None 02584 */ 02585 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx, 02586 uint32_t Prescaler) 02587 { 02588 uint32_t HRTIM_eecr3; 02589 02590 /* Check parameters */ 02591 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler)); 02592 02593 /* Set the external event prescaler */ 02594 HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3; 02595 HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD); 02596 HRTIM_eecr3 |= Prescaler; 02597 02598 /* Update the HRTIMx registers */ 02599 HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3; 02600 } 02601 02602 /** 02603 * @brief Configures the conditioning of fault input 02604 * @param HRTIMx: pointer to HRTIMx peripheral 02605 * @param Fault: fault input to configure 02606 * This parameter can be one of the following values: 02607 * @arg HRTIM_FAULT_1: Fault input 1 02608 * @arg HRTIM_FAULT_2: Fault input 2 02609 * @arg HRTIM_FAULT_3: Fault input 3 02610 * @arg HRTIM_FAULT_4: Fault input 4 02611 * @arg HRTIM_FAULT_5: Fault input 5 02612 * @param pFaultCfg: pointer to the fault conditioning configuration structure 02613 * @retval None 02614 */ 02615 void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx, 02616 HRTIM_FaultCfgTypeDef* pFaultCfg, 02617 uint32_t Fault) 02618 { 02619 uint32_t HRTIM_fltinr1; 02620 uint32_t HRTIM_fltinr2; 02621 02622 /* Check parameters */ 02623 assert_param(IS_HRTIM_FAULT(Fault)); 02624 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source)); 02625 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity)); 02626 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter)); 02627 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock)); 02628 02629 /* Configure fault channel */ 02630 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1; 02631 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; 02632 02633 switch (Fault) 02634 { 02635 case HRTIM_FAULT_1: 02636 { 02637 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); 02638 HRTIM_fltinr1 |= pFaultCfg->Polarity; 02639 HRTIM_fltinr1 |= pFaultCfg->Source; 02640 HRTIM_fltinr1 |= pFaultCfg->Filter; 02641 HRTIM_fltinr1 |= pFaultCfg->Lock; 02642 } 02643 break; 02644 case HRTIM_FAULT_2: 02645 { 02646 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); 02647 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8); 02648 HRTIM_fltinr1 |= (pFaultCfg->Source << 8); 02649 HRTIM_fltinr1 |= (pFaultCfg->Filter << 8); 02650 HRTIM_fltinr1 |= (pFaultCfg->Lock << 8); 02651 } 02652 break; 02653 case HRTIM_FAULT_3: 02654 { 02655 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); 02656 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16); 02657 HRTIM_fltinr1 |= (pFaultCfg->Source << 16); 02658 HRTIM_fltinr1 |= (pFaultCfg->Filter << 16); 02659 HRTIM_fltinr1 |= (pFaultCfg->Lock << 16); 02660 } 02661 break; 02662 case HRTIM_FAULT_4: 02663 { 02664 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); 02665 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24); 02666 HRTIM_fltinr1 |= (pFaultCfg->Source << 24); 02667 HRTIM_fltinr1 |= (pFaultCfg->Filter << 24); 02668 HRTIM_fltinr1 |= (pFaultCfg->Lock << 24); 02669 } 02670 break; 02671 case HRTIM_FAULT_5: 02672 { 02673 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); 02674 HRTIM_fltinr2 |= pFaultCfg->Polarity; 02675 HRTIM_fltinr2 |= pFaultCfg->Source; 02676 HRTIM_fltinr2 |= pFaultCfg->Filter; 02677 HRTIM_fltinr2 |= pFaultCfg->Lock; 02678 } 02679 break; 02680 default: 02681 break; 02682 } 02683 02684 /* Update the HRTIMx registers */ 02685 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1; 02686 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; 02687 } 02688 02689 /** 02690 * @brief Configures the fault conditioning block prescaler 02691 * @param HRTIMx: pointer to HRTIMx peripheral 02692 * @param Prescaler: Prescaler value 02693 * This parameter can be one of the following values: 02694 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx 02695 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2 02696 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4 02697 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8 02698 * @retval None 02699 */ 02700 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx, 02701 uint32_t Prescaler) 02702 { 02703 uint32_t HRTIM_fltinr2; 02704 02705 /* Check parameters */ 02706 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler)); 02707 02708 /* Set the external event prescaler */ 02709 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; 02710 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD); 02711 HRTIM_fltinr2 |= Prescaler; 02712 02713 /* Update the HRTIMx registers */ 02714 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; 02715 } 02716 02717 /** 02718 * @brief Enables or disables the HRTIMx Fault mode. 02719 * @param HRTIMx: pointer to HRTIMx peripheral 02720 * @param Fault: fault input to configure 02721 * This parameter can be one of the following values: 02722 * @arg HRTIM_FAULT_1: Fault input 1 02723 * @arg HRTIM_FAULT_2: Fault input 2 02724 * @arg HRTIM_FAULT_3: Fault input 3 02725 * @arg HRTIM_FAULT_4: Fault input 4 02726 * @arg HRTIM_FAULT_5: Fault input 5 02727 * @param Enable: Fault mode controller enabling 02728 * This parameter can be one of the following values: 02729 * @arg HRTIM_FAULT_ENABLED: Fault mode enabled 02730 * @arg HRTIM_FAULT_DISABLED: Fault mode disabled 02731 * @retval None 02732 */ 02733 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable) 02734 { 02735 uint32_t HRTIM_fltinr1; 02736 uint32_t HRTIM_fltinr2; 02737 02738 /* Check parameters */ 02739 assert_param(IS_HRTIM_FAULT(Fault)); 02740 assert_param(IS_HRTIM_FAULTCTL(Enable)); 02741 02742 /* Configure fault channel */ 02743 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1; 02744 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2; 02745 02746 switch (Fault) 02747 { 02748 case HRTIM_FAULT_1: 02749 { 02750 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E; 02751 HRTIM_fltinr1 |= Enable; 02752 } 02753 break; 02754 case HRTIM_FAULT_2: 02755 { 02756 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E; 02757 HRTIM_fltinr1 |= (Enable<< 8); 02758 } 02759 break; 02760 case HRTIM_FAULT_3: 02761 { 02762 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E; 02763 HRTIM_fltinr1 |= (Enable << 16); 02764 } 02765 break; 02766 case HRTIM_FAULT_4: 02767 { 02768 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E; 02769 HRTIM_fltinr1 |= (Enable << 24); 02770 } 02771 break; 02772 case HRTIM_FAULT_5: 02773 { 02774 HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E; 02775 HRTIM_fltinr2 |= Enable; 02776 } 02777 break; 02778 default: 02779 break; 02780 } 02781 02782 /* Update the HRTIMx registers */ 02783 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1; 02784 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2; 02785 } 02786 02787 /** 02788 * @brief Configures both the ADC trigger register update source and the ADC 02789 * trigger source. 02790 * @param HRTIMx: pointer to HRTIMx peripheral 02791 * @param ADC trigger: ADC trigger to configure 02792 * This parameter can be one of the following values: 02793 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1 02794 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2 02795 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3 02796 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4 02797 * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure 02798 * @retval None 02799 */ 02800 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx, 02801 uint32_t ADCTrigger, 02802 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) 02803 { 02804 uint32_t HRTIM_cr1; 02805 02806 /* Check parameters */ 02807 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger)); 02808 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource)); 02809 02810 /* Set the ADC trigger update source */ 02811 HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1; 02812 02813 switch (ADCTrigger) 02814 { 02815 case HRTIM_ADCTRIGGER_1: 02816 { 02817 HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC); 02818 HRTIM_cr1 |= pADCTriggerCfg->UpdateSource; 02819 02820 /* Set the ADC trigger 1 source */ 02821 HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger; 02822 } 02823 break; 02824 case HRTIM_ADCTRIGGER_2: 02825 { 02826 HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC); 02827 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3); 02828 02829 /* Set the ADC trigger 2 source */ 02830 HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger; 02831 } 02832 break; 02833 case HRTIM_ADCTRIGGER_3: 02834 { 02835 HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC); 02836 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6); 02837 02838 /* Set the ADC trigger 3 source */ 02839 HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger; 02840 } 02841 case HRTIM_ADCTRIGGER_4: 02842 { 02843 HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC); 02844 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9); 02845 02846 /* Set the ADC trigger 4 source */ 02847 HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger; 02848 } 02849 break; 02850 default: 02851 break; 02852 } 02853 02854 /* Update the HRTIMx registers */ 02855 HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1; 02856 } 02857 02858 02859 /** 02860 * @brief Enables or disables the HRTIMx burst mode controller. 02861 * @param HRTIMx: pointer to HRTIMx peripheral 02862 * @param Enable: Burst mode controller enabling 02863 * This parameter can be one of the following values: 02864 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled 02865 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled 02866 * @retval None 02867 */ 02868 void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable) 02869 { 02870 uint32_t HRTIM_bmcr; 02871 02872 /* Check parameters */ 02873 assert_param(IS_HRTIM_BURSTMODECTL(Enable)); 02874 02875 /* Enable/Disable the burst mode controller */ 02876 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; 02877 HRTIM_bmcr &= ~(HRTIM_BMCR_BME); 02878 HRTIM_bmcr |= Enable; 02879 02880 /* Update the HRTIMx registers */ 02881 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; 02882 } 02883 02884 /** 02885 * @brief Triggers a software capture on the designed capture unit 02886 * @param HRTIMx: pointer to HRTIMx peripheral 02887 * @param TimerIdx: Timer index 02888 * This parameter can be one of the following values: 02889 * @arg 0x0 to 0x4 for timers A to E 02890 * @param CaptureUnit: Capture unit to trig 02891 * This parameter can be one of the following values: 02892 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 02893 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 02894 * @retval None 02895 * @note The 'software capture' bit in the capture configuration register is 02896 * automatically reset by hardware 02897 */ 02898 void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx, 02899 uint32_t TimerIdx, 02900 uint32_t CaptureUnit) 02901 { 02902 /* Check parameters */ 02903 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 02904 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); 02905 02906 /* Force a software capture on concerned capture unit */ 02907 switch (CaptureUnit) 02908 { 02909 case HRTIM_CAPTUREUNIT_1: 02910 { 02911 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT; 02912 } 02913 break; 02914 case HRTIM_CAPTUREUNIT_2: 02915 { 02916 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT; 02917 } 02918 break; 02919 default: 02920 break; 02921 } 02922 } 02923 02924 /** 02925 * @brief Triggers the update of the registers of one or several timers 02926 * @param HRTIMx: pointer to HRTIMx peripheral 02927 * @param TimersToUpdate: timers concerned with the software register update 02928 * This parameter can be any combination of the following values: 02929 * @arg HRTIM_TIMERUPDATE_MASTER 02930 * @arg HRTIM_TIMERUPDATE_A 02931 * @arg HRTIM_TIMERUPDATE_B 02932 * @arg HRTIM_TIMERUPDATE_C 02933 * @arg HRTIM_TIMERUPDATE_D 02934 * @arg HRTIM_TIMERUPDATE_E 02935 * @retval None 02936 * @note The 'software update' bits in the HRTIMx control register 2 register are 02937 * automatically reset by hardware 02938 */ 02939 void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx, 02940 uint32_t TimersToUpdate) 02941 { 02942 /* Check parameters */ 02943 assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate)); 02944 02945 /* Force timer(s) registers update */ 02946 HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate; 02947 02948 } 02949 02950 /** 02951 * @brief Triggers the reset of one or several timers 02952 * @param HRTIMx: pointer to HRTIMx peripheral 02953 * @param TimersToUpdate: timers concerned with the software counter reset 02954 * This parameter can be any combination of the following values: 02955 * @arg HRTIM_TIMER_MASTER 02956 * @arg HRTIM_TIMER_A 02957 * @arg HRTIM_TIMER_B 02958 * @arg HRTIM_TIMER_C 02959 * @arg HRTIM_TIMER_D 02960 * @arg HRTIM_TIMER_E 02961 * @retval None 02962 * @note The 'software reset' bits in the HRTIMx control register 2 are 02963 * automatically reset by hardware 02964 */ 02965 void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx, 02966 uint32_t TimersToReset) 02967 { 02968 /* Check parameters */ 02969 assert_param(IS_HRTIM_TIMERRESET(TimersToReset)); 02970 02971 /* Force timer(s) registers update */ 02972 HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset; 02973 02974 } 02975 02976 /** 02977 * @brief Forces the timer output to its active or inactive state 02978 * @param HRTIMx: pointer to HRTIMx peripheral 02979 * @param TimerIdx: Timer index 02980 * This parameter can be one of the following values: 02981 * @arg 0x0 to 0x4 for timers A to E 02982 * @param Output: Timer output 02983 * This parameter can be one of the following values: 02984 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 02985 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 02986 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 02987 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 02988 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 02989 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 02990 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 02991 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 02992 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 02993 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 02994 * @param OutputLevel: indicates whether the output is forced to its active or inactive state 02995 * This parameter can be one of the following values: 02996 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state 02997 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state 02998 * @retval None 02999 * @note The 'software set/reset trigger' bit in the output set/reset registers 03000 * is automatically reset by hardware 03001 */ 03002 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx, 03003 uint32_t TimerIdx, 03004 uint32_t Output, 03005 uint32_t OutputLevel) 03006 { 03007 /* Check parameters */ 03008 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); 03009 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel)); 03010 03011 /* Force timer output level */ 03012 switch (Output) 03013 { 03014 case HRTIM_OUTPUT_TA1: 03015 case HRTIM_OUTPUT_TB1: 03016 case HRTIM_OUTPUT_TC1: 03017 case HRTIM_OUTPUT_TD1: 03018 case HRTIM_OUTPUT_TE1: 03019 { 03020 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) 03021 { 03022 /* Force output to its active state */ 03023 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST; 03024 } 03025 else 03026 { 03027 /* Force output to its inactive state */ 03028 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT; 03029 } 03030 } 03031 break; 03032 case HRTIM_OUTPUT_TA2: 03033 case HRTIM_OUTPUT_TB2: 03034 case HRTIM_OUTPUT_TC2: 03035 case HRTIM_OUTPUT_TD2: 03036 case HRTIM_OUTPUT_TE2: 03037 { 03038 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE) 03039 { 03040 /* Force output to its active state */ 03041 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST; 03042 } 03043 else 03044 { 03045 /* Force output to its inactive state */ 03046 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT; 03047 } 03048 } 03049 break; 03050 default: 03051 break; 03052 } 03053 } 03054 03055 03056 /** 03057 * @} 03058 */ 03059 03060 /** @defgroup HRTIM_Group4 Peripheral State methods 03061 * @brief Peripheral State functions 03062 * 03063 @verbatim 03064 =============================================================================== 03065 ##### Peripheral State methods ##### 03066 =============================================================================== 03067 [..] 03068 This subsection permit to get in run-time the status of the peripheral 03069 and the data flow. 03070 03071 @endverbatim 03072 * @{ 03073 */ 03074 03075 /** 03076 * @brief Returns actual value of the capture register of the designated capture unit 03077 * @param HRTIMx: pointer to HRTIMx peripheral 03078 * @param TimerIdx: Timer index 03079 * This parameter can be one of the following values: 03080 * @arg 0x0 to 0x4 for timers A to E 03081 * @param CaptureUnit: Capture unit to trig 03082 * This parameter can be one of the following values: 03083 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 03084 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 03085 * @retval Captured value 03086 */ 03087 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx, 03088 uint32_t TimerIdx, 03089 uint32_t CaptureUnit) 03090 { 03091 uint32_t captured_value = 0; 03092 03093 /* Check parameters */ 03094 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 03095 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit)); 03096 03097 /* Read captured value */ 03098 switch (CaptureUnit) 03099 { 03100 case HRTIM_CAPTUREUNIT_1: 03101 { 03102 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR; 03103 } 03104 break; 03105 case HRTIM_CAPTUREUNIT_2: 03106 { 03107 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR; 03108 } 03109 break; 03110 default: 03111 break; 03112 } 03113 03114 return captured_value; 03115 } 03116 03117 /** 03118 * @brief Returns actual level (active or inactive) of the designated output 03119 * @param HRTIMx: pointer to HRTIMx peripheral 03120 * @param TimerIdx: Timer index 03121 * This parameter can be one of the following values: 03122 * @arg 0x0 to 0x4 for timers A to E 03123 * @param Output: Timer output 03124 * This parameter can be one of the following values: 03125 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 03126 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 03127 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 03128 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 03129 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 03130 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 03131 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 03132 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 03133 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 03134 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 03135 * @retval Output level 03136 * @note Returned output level is taken before the output stage (chopper, 03137 * polarity). 03138 */ 03139 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx, 03140 uint32_t TimerIdx, 03141 uint32_t Output) 03142 { 03143 uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE; 03144 03145 /* Check parameters */ 03146 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); 03147 03148 /* Read the output level */ 03149 switch (Output) 03150 { 03151 case HRTIM_OUTPUT_TA1: 03152 case HRTIM_OUTPUT_TB1: 03153 case HRTIM_OUTPUT_TC1: 03154 case HRTIM_OUTPUT_TD1: 03155 case HRTIM_OUTPUT_TE1: 03156 { 03157 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET) 03158 { 03159 output_level = HRTIM_OUTPUTLEVEL_ACTIVE; 03160 } 03161 else 03162 { 03163 output_level = HRTIM_OUTPUTLEVEL_INACTIVE; 03164 } 03165 } 03166 break; 03167 case HRTIM_OUTPUT_TA2: 03168 case HRTIM_OUTPUT_TB2: 03169 case HRTIM_OUTPUT_TC2: 03170 case HRTIM_OUTPUT_TD2: 03171 case HRTIM_OUTPUT_TE2: 03172 { 03173 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET) 03174 { 03175 output_level = HRTIM_OUTPUTLEVEL_ACTIVE; 03176 } 03177 else 03178 { 03179 output_level = HRTIM_OUTPUTLEVEL_INACTIVE; 03180 } 03181 } 03182 break; 03183 default: 03184 break; 03185 } 03186 03187 return output_level; 03188 } 03189 03190 /** 03191 * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output 03192 * @param HRTIMx: pointer to HRTIMx peripheral 03193 * @param TimerIdx: Timer index 03194 * This parameter can be one of the following values: 03195 * @arg 0x0 to 0x4 for timers A to E 03196 * @param Output: Timer output 03197 * This parameter can be one of the following values: 03198 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 03199 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 03200 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 03201 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 03202 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 03203 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 03204 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 03205 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 03206 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1 03207 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 03208 * @retval Output state 03209 */ 03210 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx, 03211 uint32_t TimerIdx, 03212 uint32_t Output) 03213 { 03214 uint32_t output_bit = 0; 03215 uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE; 03216 03217 /* Check parameters */ 03218 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); 03219 03220 /* Set output state according to output control status and output disable status */ 03221 switch (Output) 03222 { 03223 case HRTIM_OUTPUT_TA1: 03224 { 03225 output_bit = HRTIM_OENR_TA1OEN; 03226 } 03227 break; 03228 case HRTIM_OUTPUT_TA2: 03229 { 03230 output_bit = HRTIM_OENR_TA2OEN; 03231 } 03232 break; 03233 case HRTIM_OUTPUT_TB1: 03234 { 03235 output_bit = HRTIM_OENR_TB1OEN; 03236 } 03237 break; 03238 case HRTIM_OUTPUT_TB2: 03239 { 03240 output_bit = HRTIM_OENR_TB2OEN; 03241 } 03242 break; 03243 case HRTIM_OUTPUT_TC1: 03244 { 03245 output_bit = HRTIM_OENR_TC1OEN; 03246 } 03247 break; 03248 case HRTIM_OUTPUT_TC2: 03249 { 03250 output_bit = HRTIM_OENR_TC2OEN; 03251 } 03252 break; 03253 case HRTIM_OUTPUT_TD1: 03254 { 03255 output_bit = HRTIM_OENR_TD1OEN; 03256 } 03257 break; 03258 case HRTIM_OUTPUT_TD2: 03259 { 03260 output_bit = HRTIM_OENR_TD2OEN; 03261 } 03262 break; 03263 case HRTIM_OUTPUT_TE1: 03264 { 03265 output_bit = HRTIM_OENR_TE1OEN; 03266 } 03267 break; 03268 case HRTIM_OUTPUT_TE2: 03269 { 03270 output_bit = HRTIM_OENR_TE2OEN; 03271 } 03272 break; 03273 default: 03274 break; 03275 } 03276 03277 if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET) 03278 { 03279 /* Output is enabled: output in RUN state (whatever output disable status is)*/ 03280 output_state = HRTIM_OUTPUTSTATE_RUN; 03281 } 03282 else 03283 { 03284 if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET) 03285 { 03286 /* Output is disabled: output in FAULT state */ 03287 output_state = HRTIM_OUTPUTSTATE_FAULT; 03288 } 03289 else 03290 { 03291 /* Output is disabled: output in IDLE state */ 03292 output_state = HRTIM_OUTPUTSTATE_IDLE; 03293 } 03294 } 03295 03296 return(output_state); 03297 } 03298 03299 /** 03300 * @brief Returns the level (active or inactive) of the designated output 03301 * when the delayed protection was triggered 03302 * @param HRTIMx: pointer to HRTIMx peripheral 03303 * @param TimerIdx: Timer index 03304 * This parameter can be one of the following values: 03305 * @arg 0x0 to 0x4 for timers A to E 03306 * @param Output: Timer output 03307 * This parameter can be one of the following values: 03308 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1 03309 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2 03310 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1 03311 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2 03312 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1 03313 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2 03314 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1 03315 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2 03316 * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1 03317 * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2 03318 * @retval Delayed protection status 03319 */ 03320 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx, 03321 uint32_t TimerIdx, 03322 uint32_t Output) 03323 { 03324 uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; 03325 03326 /* Check parameters */ 03327 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); 03328 03329 /* Read the delayed protection status */ 03330 switch (Output) 03331 { 03332 case HRTIM_OUTPUT_TA1: 03333 case HRTIM_OUTPUT_TB1: 03334 case HRTIM_OUTPUT_TC1: 03335 case HRTIM_OUTPUT_TD1: 03336 case HRTIM_OUTPUT_TE1: 03337 { 03338 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET) 03339 { 03340 /* Output 1 was active when the delayed idle protection was triggered */ 03341 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE; 03342 } 03343 else 03344 { 03345 /* Output 1 was inactive when the delayed idle protection was triggered */ 03346 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; 03347 } 03348 } 03349 break; 03350 case HRTIM_OUTPUT_TA2: 03351 case HRTIM_OUTPUT_TB2: 03352 case HRTIM_OUTPUT_TC2: 03353 case HRTIM_OUTPUT_TD2: 03354 case HRTIM_OUTPUT_TE2: 03355 { 03356 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET) 03357 { 03358 /* Output 2 was active when the delayed idle protection was triggered */ 03359 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE; 03360 } 03361 else 03362 { 03363 /* Output 2 was inactive when the delayed idle protection was triggered */ 03364 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE; 03365 } 03366 } 03367 break; 03368 default: 03369 break; 03370 } 03371 03372 return delayed_protection_status; 03373 } 03374 03375 /** 03376 * @brief Returns the actual status (active or inactive) of the burst mode controller 03377 * @param HRTIMx: pointer to HRTIMx peripheral 03378 * @retval Burst mode controller status 03379 */ 03380 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx) 03381 { 03382 uint32_t burst_mode_status; 03383 03384 /* Read burst mode status */ 03385 burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT); 03386 03387 return burst_mode_status; 03388 } 03389 03390 /** 03391 * @brief Indicates on which output the signal is currently active (when the 03392 * push pull mode is enabled) 03393 * @param HRTIMx: pointer to HRTIMx peripheral 03394 * @param TimerIdx: Timer index 03395 * This parameter can be one of the following values: 03396 * @arg 0x0 to 0x4 for timers A to E 03397 * @retval Burst mode controller status 03398 */ 03399 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx, 03400 uint32_t TimerIdx) 03401 { 03402 uint32_t current_pushpull_status; 03403 03404 /* Check the parameters */ 03405 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 03406 03407 /* Read current push pull status */ 03408 current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT); 03409 03410 return current_pushpull_status; 03411 } 03412 03413 03414 /** 03415 * @brief Indicates on which output the signal was applied, in push-pull mode 03416 balanced fault mode or delayed idle mode, when the protection was triggered 03417 * @param HRTIMx: pointer to HRTIMx peripheral 03418 * @param TimerIdx: Timer index 03419 * This parameter can be one of the following values: 03420 * @arg 0x0 to 0x4 for timers A to E 03421 * @retval Idle Push Pull Status 03422 */ 03423 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx, 03424 uint32_t TimerIdx) 03425 { 03426 uint32_t idle_pushpull_status; 03427 03428 /* Check the parameters */ 03429 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); 03430 03431 /* Read current push pull status */ 03432 idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT); 03433 03434 return idle_pushpull_status; 03435 } 03436 03437 /** 03438 * @brief Configures the master timer time base 03439 * @param HRTIMx: pointer to HRTIMx peripheral 03440 * @retval None 03441 */ 03442 void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 03443 { 03444 /* Set the prescaler ratio */ 03445 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC); 03446 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio; 03447 03448 /* Set the operating mode */ 03449 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG); 03450 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode; 03451 03452 /* Update the HRTIMx registers */ 03453 HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period; 03454 HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter; 03455 } 03456 03457 /** 03458 * @brief Configures timing unit (timer A to timer E) time base 03459 * @param HRTIMx: pointer to HRTIMx peripheral 03460 * @param TimerIdx: Timer index 03461 * @retval None 03462 */ 03463 void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct) 03464 { 03465 /* Set the prescaler ratio */ 03466 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC); 03467 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio; 03468 03469 /* Set the operating mode */ 03470 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG); 03471 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode; 03472 03473 /* Update the HRTIMx registers */ 03474 HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period; 03475 HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter; 03476 } 03477 03478 /** 03479 * @brief Configures the master timer in waveform mode 03480 * @param HRTIMx: pointer to HRTIMx peripheral 03481 * @param TimerIdx: Timer index 03482 * @param pTimerInit: pointer to the timer initialization data structure 03483 * @retval None 03484 */ 03485 void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, 03486 HRTIM_TimerInitTypeDef * pTimerInit) 03487 { 03488 uint32_t HRTIM_mcr; 03489 uint32_t HRTIM_bmcr; 03490 03491 /* Configure master timer */ 03492 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR; 03493 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; 03494 03495 /* Enable/Disable the half mode */ 03496 HRTIM_mcr &= ~(HRTIM_MCR_HALF); 03497 HRTIM_mcr |= pTimerInit->HalfModeEnable; 03498 03499 /* Enable/Disable the timer start upon synchronization event reception */ 03500 HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM); 03501 HRTIM_mcr |= pTimerInit->StartOnSync; 03502 03503 /* Enable/Disable the timer reset upon synchronization event reception */ 03504 HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM); 03505 HRTIM_mcr |= pTimerInit->ResetOnSync; 03506 03507 /* Enable/Disable the DAC synchronization event generation */ 03508 HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC); 03509 HRTIM_mcr |= pTimerInit->DACSynchro; 03510 03511 /* Enable/Disable preload mechanism for timer registers */ 03512 HRTIM_mcr &= ~(HRTIM_MCR_PREEN); 03513 HRTIM_mcr |= pTimerInit->PreloadEnable; 03514 03515 /* Master timer registers update handling */ 03516 HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA); 03517 HRTIM_mcr |= (pTimerInit->UpdateGating << 2); 03518 03519 /* Enable/Disable registers update on repetition */ 03520 HRTIM_mcr &= ~(HRTIM_MCR_MREPU); 03521 HRTIM_mcr |= pTimerInit->RepetitionUpdate; 03522 03523 /* Set the timer burst mode */ 03524 HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM); 03525 HRTIM_bmcr |= pTimerInit->BurstMode; 03526 03527 /* Update the HRTIMx registers */ 03528 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr; 03529 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; 03530 03531 } 03532 03533 /** 03534 * @brief Configures timing unit (timer A to timer E) in waveform mode 03535 * @param HRTIMx: pointer to HRTIMx peripheral 03536 * @param TimerIdx: Timer index 03537 * @param pTimerInit: pointer to the timer initialization data structure 03538 * @retval None 03539 */ 03540 void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx, 03541 uint32_t TimerIdx, 03542 HRTIM_TimerInitTypeDef * pTimerInit) 03543 { 03544 uint32_t HRTIM_timcr; 03545 uint32_t HRTIM_bmcr; 03546 03547 /* Configure timing unit */ 03548 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR; 03549 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR; 03550 03551 /* Enable/Disable the half mode */ 03552 HRTIM_timcr &= ~(HRTIM_TIMCR_HALF); 03553 HRTIM_timcr |= pTimerInit->HalfModeEnable; 03554 03555 /* Enable/Disable the timer start upon synchronization event reception */ 03556 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT); 03557 HRTIM_timcr |= pTimerInit->StartOnSync; 03558 03559 /* Enable/Disable the timer reset upon synchronization event reception */ 03560 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST); 03561 HRTIM_timcr |= pTimerInit->ResetOnSync; 03562 03563 /* Enable/Disable the DAC synchronization event generation */ 03564 HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC); 03565 HRTIM_timcr |= pTimerInit->DACSynchro; 03566 03567 /* Enable/Disable preload mechanism for timer registers */ 03568 HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN); 03569 HRTIM_timcr |= pTimerInit->PreloadEnable; 03570 03571 /* Timing unit registers update handling */ 03572 HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT); 03573 HRTIM_timcr |= pTimerInit->UpdateGating; 03574 03575 /* Enable/Disable registers update on repetition */ 03576 HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU); 03577 if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED) 03578 { 03579 HRTIM_timcr |= HRTIM_TIMCR_TREPU; 03580 } 03581 03582 /* Set the timer burst mode */ 03583 switch (TimerIdx) 03584 { 03585 case HRTIM_TIMERINDEX_TIMER_A: 03586 { 03587 HRTIM_bmcr &= ~(HRTIM_BMCR_TABM); 03588 HRTIM_bmcr |= ( pTimerInit->BurstMode << 1); 03589 } 03590 break; 03591 case HRTIM_TIMERINDEX_TIMER_B: 03592 { 03593 HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM); 03594 HRTIM_bmcr |= ( pTimerInit->BurstMode << 2); 03595 } 03596 break; 03597 case HRTIM_TIMERINDEX_TIMER_C: 03598 { 03599 HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM); 03600 HRTIM_bmcr |= ( pTimerInit->BurstMode << 3); 03601 } 03602 break; 03603 case HRTIM_TIMERINDEX_TIMER_D: 03604 { 03605 HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM); 03606 HRTIM_bmcr |= ( pTimerInit->BurstMode << 4); 03607 } 03608 break; 03609 case HRTIM_TIMERINDEX_TIMER_E: 03610 { 03611 HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM); 03612 HRTIM_bmcr |= ( pTimerInit->BurstMode << 5); 03613 } 03614 break; 03615 default: 03616 break; 03617 } 03618 03619 /* Update the HRTIMx registers */ 03620 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr; 03621 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr; 03622 } 03623 03624 /** 03625 * @brief Configures a compare unit 03626 * @param HRTIMx: pointer to HRTIMx peripheral 03627 * @param TimerIdx: Timer index 03628 * @param CompareUnit: Compare unit identifier 03629 * @param pCompareCfg: pointer to the compare unit configuration data structure 03630 * @retval None 03631 */ 03632 void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx, 03633 uint32_t TimerIdx, 03634 uint32_t CompareUnit, 03635 HRTIM_CompareCfgTypeDef * pCompareCfg) 03636 { 03637 if (TimerIdx == HRTIM_TIMERINDEX_MASTER) 03638 { 03639 /* Configure the compare unit of the master timer */ 03640 switch (CompareUnit) 03641 { 03642 case HRTIM_COMPAREUNIT_1: 03643 { 03644 HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue; 03645 } 03646 break; 03647 case HRTIM_COMPAREUNIT_2: 03648 { 03649 HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue; 03650 } 03651 break; 03652 case HRTIM_COMPAREUNIT_3: 03653 { 03654 HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue; 03655 } 03656 break; 03657 case HRTIM_COMPAREUNIT_4: 03658 { 03659 HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue; 03660 } 03661 break; 03662 default: 03663 break; 03664 } 03665 } 03666 else 03667 { 03668 /* Configure the compare unit of the timing unit */ 03669 switch (CompareUnit) 03670 { 03671 case HRTIM_COMPAREUNIT_1: 03672 { 03673 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue; 03674 } 03675 break; 03676 case HRTIM_COMPAREUNIT_2: 03677 { 03678 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue; 03679 } 03680 break; 03681 case HRTIM_COMPAREUNIT_3: 03682 { 03683 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue; 03684 } 03685 break; 03686 case HRTIM_COMPAREUNIT_4: 03687 { 03688 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue; 03689 } 03690 break; 03691 default: 03692 break; 03693 } 03694 } 03695 } 03696 03697 /** 03698 * @brief Configures a capture unit 03699 * @param HRTIMx: pointer to HRTIMx peripheral 03700 * @param TimerIdx: Timer index 03701 * @param CaptureUnit: Capture unit identifier 03702 * @param pCaptureCfg: pointer to the compare unit configuration data structure 03703 * @retval None 03704 */ 03705 void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx, 03706 uint32_t TimerIdx, 03707 uint32_t CaptureUnit, 03708 uint32_t Event) 03709 { 03710 uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; 03711 03712 switch (Event) 03713 { 03714 case HRTIM_EVENT_1: 03715 { 03716 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1; 03717 } 03718 break; 03719 case HRTIM_EVENT_2: 03720 { 03721 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2; 03722 } 03723 break; 03724 case HRTIM_EVENT_3: 03725 { 03726 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3; 03727 } 03728 break; 03729 case HRTIM_EVENT_4: 03730 { 03731 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4; 03732 } 03733 break; 03734 case HRTIM_EVENT_5: 03735 { 03736 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5; 03737 } 03738 break; 03739 case HRTIM_EVENT_6: 03740 { 03741 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6; 03742 } 03743 break; 03744 case HRTIM_EVENT_7: 03745 { 03746 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7; 03747 } 03748 break; 03749 case HRTIM_EVENT_8: 03750 { 03751 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8; 03752 } 03753 break; 03754 case HRTIM_EVENT_9: 03755 { 03756 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9; 03757 } 03758 break; 03759 case HRTIM_EVENT_10: 03760 { 03761 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10; 03762 } 03763 break; 03764 default: 03765 break; 03766 03767 } 03768 switch (CaptureUnit) 03769 { 03770 case HRTIM_CAPTUREUNIT_1: 03771 { 03772 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger; 03773 } 03774 break; 03775 case HRTIM_CAPTUREUNIT_2: 03776 { 03777 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger; 03778 } 03779 break; 03780 default: 03781 break; 03782 } 03783 } 03784 03785 /** 03786 * @brief Configures the output of a timing unit 03787 * @param HRTIMx: pointer to HRTIMx peripheral 03788 * @param TimerIdx: Timer index 03789 * @param Output: timing unit output identifier 03790 * @param pOutputCfg: pointer to the output configuration data structure 03791 * @retval None 03792 */ 03793 void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx, 03794 uint32_t TimerIdx, 03795 uint32_t Output, 03796 HRTIM_OutputCfgTypeDef * pOutputCfg) 03797 { 03798 uint32_t HRTIM_outr; 03799 uint32_t shift = 0; 03800 03801 HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR; 03802 03803 switch (Output) 03804 { 03805 case HRTIM_OUTPUT_TA1: 03806 case HRTIM_OUTPUT_TB1: 03807 case HRTIM_OUTPUT_TC1: 03808 case HRTIM_OUTPUT_TD1: 03809 case HRTIM_OUTPUT_TE1: 03810 { 03811 /* Set the output set/reset crossbar */ 03812 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource; 03813 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource; 03814 03815 shift = 0; 03816 } 03817 break; 03818 case HRTIM_OUTPUT_TA2: 03819 case HRTIM_OUTPUT_TB2: 03820 case HRTIM_OUTPUT_TC2: 03821 case HRTIM_OUTPUT_TD2: 03822 case HRTIM_OUTPUT_TE2: 03823 { 03824 /* Set the output set/reset crossbar */ 03825 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource; 03826 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource; 03827 03828 shift = 16; 03829 } 03830 break; 03831 default: 03832 break; 03833 } 03834 03835 /* Clear output config */ 03836 HRTIM_outr &= ~((HRTIM_OUTR_POL1 | 03837 HRTIM_OUTR_IDLM1 | 03838 HRTIM_OUTR_IDLES1| 03839 HRTIM_OUTR_FAULT1| 03840 HRTIM_OUTR_CHP1 | 03841 HRTIM_OUTR_DIDL1) << shift); 03842 03843 /* Set the polarity */ 03844 HRTIM_outr |= (pOutputCfg->Polarity << shift); 03845 03846 /* Set the IDLE mode */ 03847 HRTIM_outr |= (pOutputCfg->IdleMode << shift); 03848 03849 /* Set the IDLE state */ 03850 HRTIM_outr |= (pOutputCfg->IdleState << shift); 03851 03852 /* Set the FAULT state */ 03853 HRTIM_outr |= (pOutputCfg->FaultState << shift); 03854 03855 /* Set the chopper mode */ 03856 HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift); 03857 03858 /* Set the burst mode entry mode */ 03859 HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift); 03860 03861 /* Update HRTIMx register */ 03862 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr; 03863 } 03864 03865 /** 03866 * @brief Configures an external event channel 03867 * @param HRTIMx: pointer to HRTIMx peripheral 03868 * @param Event: Event channel identifier 03869 * @param pEventCfg: pointer to the event channel configuration data structure 03870 * @retval None 03871 */ 03872 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx, 03873 uint32_t Event, 03874 HRTIM_EventCfgTypeDef *pEventCfg) 03875 { 03876 uint32_t hrtim_eecr1; 03877 uint32_t hrtim_eecr2; 03878 uint32_t hrtim_eecr3; 03879 03880 /* Configure external event channel */ 03881 hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1; 03882 hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2; 03883 hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3; 03884 03885 switch (Event) 03886 { 03887 case HRTIM_EVENT_1: 03888 { 03889 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST); 03890 hrtim_eecr1 |= pEventCfg->Source; 03891 hrtim_eecr1 |= pEventCfg->Polarity; 03892 hrtim_eecr1 |= pEventCfg->Sensitivity; 03893 /* Update the HRTIM registers (all bit fields but EE1FAST bit) */ 03894 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03895 /* Update the HRTIM registers (EE1FAST bit) */ 03896 hrtim_eecr1 |= pEventCfg->FastMode; 03897 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03898 } 03899 break; 03900 case HRTIM_EVENT_2: 03901 { 03902 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST); 03903 hrtim_eecr1 |= (pEventCfg->Source << 6); 03904 hrtim_eecr1 |= (pEventCfg->Polarity << 6); 03905 hrtim_eecr1 |= (pEventCfg->Sensitivity << 6); 03906 /* Update the HRTIM registers (all bit fields but EE2FAST bit) */ 03907 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03908 /* Update the HRTIM registers (EE2FAST bit) */ 03909 hrtim_eecr1 |= (pEventCfg->FastMode << 6); 03910 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03911 } 03912 break; 03913 case HRTIM_EVENT_3: 03914 { 03915 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST); 03916 hrtim_eecr1 |= (pEventCfg->Source << 12); 03917 hrtim_eecr1 |= (pEventCfg->Polarity << 12); 03918 hrtim_eecr1 |= (pEventCfg->Sensitivity << 12); 03919 /* Update the HRTIM registers (all bit fields but EE3FAST bit) */ 03920 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03921 /* Update the HRTIM registers (EE3FAST bit) */ 03922 hrtim_eecr1 |= (pEventCfg->FastMode << 12); 03923 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03924 } 03925 break; 03926 case HRTIM_EVENT_4: 03927 { 03928 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST); 03929 hrtim_eecr1 |= (pEventCfg->Source << 18); 03930 hrtim_eecr1 |= (pEventCfg->Polarity << 18); 03931 hrtim_eecr1 |= (pEventCfg->Sensitivity << 18); 03932 /* Update the HRTIM registers (all bit fields but EE4FAST bit) */ 03933 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03934 /* Update the HRTIM registers (EE4FAST bit) */ 03935 hrtim_eecr1 |= (pEventCfg->FastMode << 18); 03936 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03937 } 03938 break; 03939 case HRTIM_EVENT_5: 03940 { 03941 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST); 03942 hrtim_eecr1 |= (pEventCfg->Source << 24); 03943 hrtim_eecr1 |= (pEventCfg->Polarity << 24); 03944 hrtim_eecr1 |= (pEventCfg->Sensitivity << 24); 03945 /* Update the HRTIM registers (all bit fields but EE5FAST bit) */ 03946 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03947 /* Update the HRTIM registers (EE5FAST bit) */ 03948 hrtim_eecr1 |= (pEventCfg->FastMode << 24); 03949 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1; 03950 } 03951 break; 03952 case HRTIM_EVENT_6: 03953 { 03954 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS); 03955 hrtim_eecr2 |= pEventCfg->Source; 03956 hrtim_eecr2 |= pEventCfg->Polarity; 03957 hrtim_eecr2 |= pEventCfg->Sensitivity; 03958 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F); 03959 hrtim_eecr3 |= pEventCfg->Filter; 03960 /* Update the HRTIM registers */ 03961 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; 03962 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; 03963 } 03964 break; 03965 case HRTIM_EVENT_7: 03966 { 03967 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS); 03968 hrtim_eecr2 |= (pEventCfg->Source << 6); 03969 hrtim_eecr2 |= (pEventCfg->Polarity << 6); 03970 hrtim_eecr2 |= (pEventCfg->Sensitivity << 6); 03971 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F); 03972 hrtim_eecr3 |= (pEventCfg->Filter << 6); 03973 /* Update the HRTIM registers */ 03974 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; 03975 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; 03976 } 03977 break; 03978 case HRTIM_EVENT_8: 03979 { 03980 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS); 03981 hrtim_eecr2 |= (pEventCfg->Source << 12); 03982 hrtim_eecr2 |= (pEventCfg->Polarity << 12); 03983 hrtim_eecr2 |= (pEventCfg->Sensitivity << 12); 03984 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F); 03985 hrtim_eecr3 |= (pEventCfg->Filter << 12); 03986 /* Update the HRTIM registers */ 03987 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; 03988 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; 03989 } 03990 break; 03991 case HRTIM_EVENT_9: 03992 { 03993 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS); 03994 hrtim_eecr2 |= (pEventCfg->Source << 18); 03995 hrtim_eecr2 |= (pEventCfg->Polarity << 18); 03996 hrtim_eecr2 |= (pEventCfg->Sensitivity << 18); 03997 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F); 03998 hrtim_eecr3 |= (pEventCfg->Filter << 18); 03999 /* Update the HRTIM registers */ 04000 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; 04001 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; 04002 } 04003 break; 04004 case HRTIM_EVENT_10: 04005 { 04006 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS); 04007 hrtim_eecr2 |= (pEventCfg->Source << 24); 04008 hrtim_eecr2 |= (pEventCfg->Polarity << 24); 04009 hrtim_eecr2 |= (pEventCfg->Sensitivity << 24); 04010 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F); 04011 hrtim_eecr3 |= (pEventCfg->Filter << 24); 04012 /* Update the HRTIM registers */ 04013 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2; 04014 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3; 04015 } 04016 break; 04017 default: 04018 break; 04019 } 04020 } 04021 04022 /** 04023 * @brief Configures the timer counter reset 04024 * @param HRTIMx: pointer to HRTIMx peripheral 04025 * @param TimerIdx: Timer index 04026 * @param Event: Event channel identifier 04027 * @retval None 04028 */ 04029 void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx, 04030 uint32_t TimerIdx, 04031 uint32_t Event) 04032 { 04033 switch (Event) 04034 { 04035 case HRTIM_EVENT_1: 04036 { 04037 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1; 04038 } 04039 break; 04040 case HRTIM_EVENT_2: 04041 { 04042 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2; 04043 } 04044 break; 04045 case HRTIM_EVENT_3: 04046 { 04047 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3; 04048 } 04049 break; 04050 case HRTIM_EVENT_4: 04051 { 04052 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4; 04053 } 04054 break; 04055 case HRTIM_EVENT_5: 04056 { 04057 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5; 04058 } 04059 break; 04060 case HRTIM_EVENT_6: 04061 { 04062 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6; 04063 } 04064 break; 04065 case HRTIM_EVENT_7: 04066 { 04067 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7; 04068 } 04069 break; 04070 case HRTIM_EVENT_8: 04071 { 04072 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8; 04073 } 04074 break; 04075 case HRTIM_EVENT_9: 04076 { 04077 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9; 04078 } 04079 break; 04080 case HRTIM_EVENT_10: 04081 { 04082 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10; 04083 } 04084 break; 04085 default: 04086 break; 04087 } 04088 } 04089 /** 04090 * @} 04091 */ 04092 /** 04093 * @} 04094 */ 04095 04096 /** 04097 * @} 04098 */ 04099 04100 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 04101 04102 04103
Generated on Tue Jul 12 2022 17:34:44 by
