stm32f30x_dma.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file contains all the functions prototypes for the DMA firmware
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00013   *
00014   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00015   * You may not use this file except in compliance with the License.
00016   * You may obtain a copy of the License at:
00017   *
00018   *        http://www.st.com/software_license_agreement_liberty_v2
00019   *
00020   * Unless required by applicable law or agreed to in writing, software 
00021   * distributed under the License is distributed on an "AS IS" BASIS, 
00022   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00023   * See the License for the specific language governing permissions and
00024   * limitations under the License.
00025   *
00026   ******************************************************************************
00027   */
00028 
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM32F30x_DMA_H
00031 #define __STM32F30x_DMA_H
00032 
00033 #ifdef __cplusplus
00034  extern "C" {
00035 #endif
00036 
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f30x.h"
00039 
00040 /** @addtogroup STM32F30x_StdPeriph_Driver
00041   * @{
00042   */
00043 
00044 /** @addtogroup DMA
00045   * @{
00046   */
00047 
00048 /* Exported types ------------------------------------------------------------*/
00049 
00050 /** 
00051   * @brief  DMA Init structures definition
00052   */
00053 typedef struct
00054 {
00055   uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
00056 
00057   uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
00058 
00059   uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
00060                                         This parameter can be a value of @ref DMA_data_transfer_direction     */
00061 
00062   uint16_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
00063                                         The data unit is equal to the configuration set in DMA_PeripheralDataSize
00064                                         or DMA_MemoryDataSize members depending in the transfer direction.    */
00065 
00066   uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
00067                                         This parameter can be a value of @ref DMA_peripheral_incremented_mode */
00068 
00069   uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
00070                                         This parameter can be a value of @ref DMA_memory_incremented_mode     */
00071 
00072   uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
00073                                         This parameter can be a value of @ref DMA_peripheral_data_size        */
00074 
00075   uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
00076                                         This parameter can be a value of @ref DMA_memory_data_size            */
00077 
00078   uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
00079                                         This parameter can be a value of @ref DMA_circular_normal_mode
00080                                         @note: The circular buffer mode cannot be used if the memory-to-memory
00081                                               data transfer is configured on the selected Channel */
00082 
00083   uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
00084                                         This parameter can be a value of @ref DMA_priority_level              */
00085 
00086   uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
00087                                         This parameter can be a value of @ref DMA_memory_to_memory            */
00088 }DMA_InitTypeDef;
00089 
00090 /* Exported constants --------------------------------------------------------*/
00091 
00092 /** @defgroup DMA_Exported_Constants
00093   * @{
00094   */
00095   
00096 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
00097                                    ((PERIPH) == DMA1_Channel2) || \
00098                                    ((PERIPH) == DMA1_Channel3) || \
00099                                    ((PERIPH) == DMA1_Channel4) || \
00100                                    ((PERIPH) == DMA1_Channel5) || \
00101                                    ((PERIPH) == DMA1_Channel6) || \
00102                                    ((PERIPH) == DMA1_Channel7) || \
00103                                    ((PERIPH) == DMA2_Channel1) || \
00104                                    ((PERIPH) == DMA2_Channel2) || \
00105                                    ((PERIPH) == DMA2_Channel3) || \
00106                                    ((PERIPH) == DMA2_Channel4) || \
00107                                    ((PERIPH) == DMA2_Channel5))
00108 
00109 /** @defgroup DMA_data_transfer_direction 
00110   * @{
00111   */
00112 
00113 #define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
00114 #define DMA_DIR_PeripheralDST              DMA_CCR_DIR
00115 
00116 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
00117                          ((DIR) == DMA_DIR_PeripheralDST))
00118 /**
00119   * @}
00120   */
00121 
00122 
00123 /** @defgroup DMA_peripheral_incremented_mode 
00124   * @{
00125   */
00126 
00127 #define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
00128 #define DMA_PeripheralInc_Enable           DMA_CCR_PINC
00129 
00130 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
00131                                             ((STATE) == DMA_PeripheralInc_Enable))
00132 /**
00133   * @}
00134   */
00135 
00136 /** @defgroup DMA_memory_incremented_mode 
00137   * @{
00138   */
00139 
00140 #define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
00141 #define DMA_MemoryInc_Enable               DMA_CCR_MINC
00142 
00143 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
00144                                         ((STATE) == DMA_MemoryInc_Enable))
00145 /**
00146   * @}
00147   */
00148 
00149 /** @defgroup DMA_peripheral_data_size 
00150   * @{
00151   */
00152 
00153 #define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
00154 #define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
00155 #define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
00156 
00157 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
00158                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
00159                                            ((SIZE) == DMA_PeripheralDataSize_Word))
00160 /**
00161   * @}
00162   */
00163 
00164 /** @defgroup DMA_memory_data_size 
00165   * @{
00166   */
00167 
00168 #define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
00169 #define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
00170 #define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
00171 
00172 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
00173                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
00174                                        ((SIZE) == DMA_MemoryDataSize_Word))
00175 /**
00176   * @}
00177   */
00178 
00179 /** @defgroup DMA_circular_normal_mode 
00180   * @{
00181   */
00182 
00183 #define DMA_Mode_Normal                    ((uint32_t)0x00000000)
00184 #define DMA_Mode_Circular                  DMA_CCR_CIRC
00185 
00186 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
00187 /**
00188   * @}
00189   */
00190 
00191 /** @defgroup DMA_priority_level 
00192   * @{
00193   */
00194 
00195 #define DMA_Priority_VeryHigh              DMA_CCR_PL
00196 #define DMA_Priority_High                  DMA_CCR_PL_1
00197 #define DMA_Priority_Medium                DMA_CCR_PL_0
00198 #define DMA_Priority_Low                   ((uint32_t)0x00000000)
00199 
00200 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
00201                                    ((PRIORITY) == DMA_Priority_High) || \
00202                                    ((PRIORITY) == DMA_Priority_Medium) || \
00203                                    ((PRIORITY) == DMA_Priority_Low))
00204 /**
00205   * @}
00206   */
00207 
00208 /** @defgroup DMA_memory_to_memory 
00209   * @{
00210   */
00211 
00212 #define DMA_M2M_Disable                    ((uint32_t)0x00000000)
00213 #define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
00214 
00215 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
00216 
00217 /**
00218   * @}
00219   */
00220 
00221 /** @defgroup DMA_interrupts_definition
00222   * @{
00223   */
00224 
00225 #define DMA_IT_TC                          ((uint32_t)0x00000002)
00226 #define DMA_IT_HT                          ((uint32_t)0x00000004)
00227 #define DMA_IT_TE                          ((uint32_t)0x00000008)
00228 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
00229 
00230 #define DMA1_IT_GL1                        ((uint32_t)0x00000001)
00231 #define DMA1_IT_TC1                        ((uint32_t)0x00000002)
00232 #define DMA1_IT_HT1                        ((uint32_t)0x00000004)
00233 #define DMA1_IT_TE1                        ((uint32_t)0x00000008)
00234 #define DMA1_IT_GL2                        ((uint32_t)0x00000010)
00235 #define DMA1_IT_TC2                        ((uint32_t)0x00000020)
00236 #define DMA1_IT_HT2                        ((uint32_t)0x00000040)
00237 #define DMA1_IT_TE2                        ((uint32_t)0x00000080)
00238 #define DMA1_IT_GL3                        ((uint32_t)0x00000100)
00239 #define DMA1_IT_TC3                        ((uint32_t)0x00000200)
00240 #define DMA1_IT_HT3                        ((uint32_t)0x00000400)
00241 #define DMA1_IT_TE3                        ((uint32_t)0x00000800)
00242 #define DMA1_IT_GL4                        ((uint32_t)0x00001000)
00243 #define DMA1_IT_TC4                        ((uint32_t)0x00002000)
00244 #define DMA1_IT_HT4                        ((uint32_t)0x00004000)
00245 #define DMA1_IT_TE4                        ((uint32_t)0x00008000)
00246 #define DMA1_IT_GL5                        ((uint32_t)0x00010000)
00247 #define DMA1_IT_TC5                        ((uint32_t)0x00020000)
00248 #define DMA1_IT_HT5                        ((uint32_t)0x00040000)
00249 #define DMA1_IT_TE5                        ((uint32_t)0x00080000)
00250 #define DMA1_IT_GL6                        ((uint32_t)0x00100000)
00251 #define DMA1_IT_TC6                        ((uint32_t)0x00200000)
00252 #define DMA1_IT_HT6                        ((uint32_t)0x00400000)
00253 #define DMA1_IT_TE6                        ((uint32_t)0x00800000)
00254 #define DMA1_IT_GL7                        ((uint32_t)0x01000000)
00255 #define DMA1_IT_TC7                        ((uint32_t)0x02000000)
00256 #define DMA1_IT_HT7                        ((uint32_t)0x04000000)
00257 #define DMA1_IT_TE7                        ((uint32_t)0x08000000)
00258 
00259 #define DMA2_IT_GL1                        ((uint32_t)0x10000001)
00260 #define DMA2_IT_TC1                        ((uint32_t)0x10000002)
00261 #define DMA2_IT_HT1                        ((uint32_t)0x10000004)
00262 #define DMA2_IT_TE1                        ((uint32_t)0x10000008)
00263 #define DMA2_IT_GL2                        ((uint32_t)0x10000010)
00264 #define DMA2_IT_TC2                        ((uint32_t)0x10000020)
00265 #define DMA2_IT_HT2                        ((uint32_t)0x10000040)
00266 #define DMA2_IT_TE2                        ((uint32_t)0x10000080)
00267 #define DMA2_IT_GL3                        ((uint32_t)0x10000100)
00268 #define DMA2_IT_TC3                        ((uint32_t)0x10000200)
00269 #define DMA2_IT_HT3                        ((uint32_t)0x10000400)
00270 #define DMA2_IT_TE3                        ((uint32_t)0x10000800)
00271 #define DMA2_IT_GL4                        ((uint32_t)0x10001000)
00272 #define DMA2_IT_TC4                        ((uint32_t)0x10002000)
00273 #define DMA2_IT_HT4                        ((uint32_t)0x10004000)
00274 #define DMA2_IT_TE4                        ((uint32_t)0x10008000)
00275 #define DMA2_IT_GL5                        ((uint32_t)0x10010000)
00276 #define DMA2_IT_TC5                        ((uint32_t)0x10020000)
00277 #define DMA2_IT_HT5                        ((uint32_t)0x10040000)
00278 #define DMA2_IT_TE5                        ((uint32_t)0x10080000)
00279 
00280 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
00281 
00282 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
00283                            ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
00284                            ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
00285                            ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
00286                            ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
00287                            ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
00288                            ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
00289                            ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
00290                            ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
00291                            ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
00292                            ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
00293                            ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
00294                            ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
00295                            ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
00296                            ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
00297                            ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
00298                            ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
00299                            ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
00300                            ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
00301                            ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
00302                            ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
00303                            ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
00304                            ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
00305                            ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
00306 
00307 /**
00308   * @}
00309   */
00310 
00311 /** @defgroup DMA_flags_definition 
00312   * @{
00313   */
00314   
00315 #define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
00316 #define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
00317 #define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
00318 #define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
00319 #define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
00320 #define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
00321 #define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
00322 #define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
00323 #define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
00324 #define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
00325 #define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
00326 #define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
00327 #define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
00328 #define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
00329 #define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
00330 #define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
00331 #define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
00332 #define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
00333 #define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
00334 #define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
00335 #define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
00336 #define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
00337 #define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
00338 #define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
00339 #define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
00340 #define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
00341 #define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
00342 #define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
00343 
00344 #define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
00345 #define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
00346 #define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
00347 #define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
00348 #define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
00349 #define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
00350 #define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
00351 #define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
00352 #define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
00353 #define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
00354 #define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
00355 #define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
00356 #define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
00357 #define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
00358 #define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
00359 #define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
00360 #define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
00361 #define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
00362 #define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
00363 #define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
00364 
00365 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
00366 
00367 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
00368                                ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
00369                                ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
00370                                ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
00371                                ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
00372                                ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
00373                                ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
00374                                ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
00375                                ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
00376                                ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
00377                                ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
00378                                ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
00379                                ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
00380                                ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
00381                                ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
00382                                ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
00383                                ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
00384                                ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
00385                                ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
00386                                ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
00387                                ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
00388                                ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
00389                                ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
00390                                ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
00391 
00392 /**
00393   * @}
00394   */
00395 
00396 /**
00397   * @}
00398   */
00399 
00400 /* Exported macro ------------------------------------------------------------*/
00401 /* Exported functions ------------------------------------------------------- */
00402 
00403 /* Function used to set the DMA configuration to the default reset state ******/
00404 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
00405 
00406 /* Initialization and Configuration functions *********************************/
00407 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
00408 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
00409 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
00410 
00411 /* Data Counter functions******************************************************/ 
00412 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
00413 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
00414 
00415 /* Interrupts and flags management functions **********************************/
00416 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00417 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
00418 void DMA_ClearFlag(uint32_t DMAy_FLAG);
00419 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
00420 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
00421 
00422 #ifdef __cplusplus
00423 }
00424 #endif
00425 
00426 #endif /*__STM32F30x_DMA_H */
00427 
00428 /**
00429   * @}
00430   */
00431 
00432 /**
00433   * @}
00434   */
00435 
00436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/