stm32f30x_dma.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Direct Memory Access controller (DMA):
00009   *           + Initialization and Configuration
00010   *           + Data Counter
00011   *           + Interrupts and flags management
00012   *
00013   @verbatim
00014     
00015  ===============================================================================
00016                        ##### How to use this driver #####
00017  ===============================================================================
00018     [..]
00019     (#) Enable The DMA controller clock using 
00020         RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or 
00021         using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
00022     (#) Enable and configure the peripheral to be connected to the DMA channel
00023         (except for internal SRAM / FLASH memories: no initialization is necessary). 
00024     (#) For a given Channel, program the Source and Destination addresses,  
00025         the transfer Direction, the Buffer Size, the Peripheral and Memory
00026         Incrementation mode and Data Size, the Circular or Normal mode, 
00027         the channel transfer Priority and the Memory-to-Memory transfer 
00028         mode (if needed) using the DMA_Init() function.
00029     (#) Enable the NVIC and the corresponding interrupt(s) using the function 
00030         DMA_ITConfig() if you need to use DMA interrupts.
00031     (#) Enable the DMA channel using the DMA_Cmd() function.
00032     (#) Activate the needed channel Request using PPP_DMACmd() function for
00033         any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
00034         The function allowing this operation is provided in each PPP peripheral
00035         driver (ie. SPI_DMACmd for SPI peripheral).
00036     (#) Optionally, you can configure the number of data to be transferred
00037         when the channel is disabled (ie. after each Transfer Complete event
00038         or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
00039         And you can get the number of remaining data to be transferred using 
00040         the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
00041         enabled and running).
00042     (#) To control DMA events you can use one of the following two methods:
00043         (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
00044         (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
00045              phase and DMA_GetITStatus() function into interrupt routines in
00046              communication phase.
00047              After checking on a flag you should clear it using DMA_ClearFlag()
00048              function. And after checking on an interrupt event you should 
00049              clear it using DMA_ClearITPendingBit() function.
00050 
00051   @endverbatim
00052 
00053   ******************************************************************************
00054   * @attention
00055   *
00056   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00057   *
00058   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00059   * You may not use this file except in compliance with the License.
00060   * You may obtain a copy of the License at:
00061   *
00062   *        http://www.st.com/software_license_agreement_liberty_v2
00063   *
00064   * Unless required by applicable law or agreed to in writing, software 
00065   * distributed under the License is distributed on an "AS IS" BASIS, 
00066   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00067   * See the License for the specific language governing permissions and
00068   * limitations under the License.
00069   *
00070   ******************************************************************************
00071   */
00072 
00073 /* Includes ------------------------------------------------------------------*/
00074 #include "stm32f30x_dma.h"
00075 
00076 /** @addtogroup STM32F30x_StdPeriph_Driver
00077   * @{
00078   */
00079 
00080 /** @defgroup DMA 
00081   * @brief DMA driver modules
00082   * @{
00083   */
00084 
00085 /* Private typedef -----------------------------------------------------------*/
00086 /* Private define ------------------------------------------------------------*/
00087 #define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
00088 #define FLAG_Mask        ((uint32_t)0x10000000) /* DMA2 FLAG mask */
00089 
00090 
00091 /* DMA1 Channelx interrupt pending bit masks */
00092 #define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00093 #define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00094 #define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00095 #define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00096 #define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00097 #define DMA1_CHANNEL6_IT_MASK    ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
00098 #define DMA1_CHANNEL7_IT_MASK    ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
00099 
00100 /* DMA2 Channelx interrupt pending bit masks */
00101 #define DMA2_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
00102 #define DMA2_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
00103 #define DMA2_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
00104 #define DMA2_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
00105 #define DMA2_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
00106 
00107 /* Private macro -------------------------------------------------------------*/
00108 /* Private variables ---------------------------------------------------------*/
00109 /* Private function prototypes -----------------------------------------------*/
00110 /* Private functions ---------------------------------------------------------*/
00111 
00112 /** @defgroup DMA_Private_Functions 
00113   * @{
00114   */
00115 
00116 /** @defgroup  DMA_Group1 Initialization and Configuration functions
00117  *  @brief   Initialization and Configuration functions
00118  *
00119 @verbatim
00120  ===============================================================================
00121               ##### Initialization and Configuration functions #####
00122  ===============================================================================
00123     [..] This subsection provides functions allowing to initialize the DMA channel 
00124          source and destination addresses, incrementation and data sizes, transfer 
00125          direction, buffer size, circular/normal mode selection, memory-to-memory 
00126          mode selection and channel priority value.
00127     [..] The DMA_Init() function follows the DMA configuration procedures as described 
00128          in reference manual (RM00316).
00129 
00130 @endverbatim
00131   * @{
00132   */
00133   
00134 /**
00135   * @brief  Deinitializes the DMAy Channelx registers to their default reset
00136   *         values.
00137   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00138   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00139   * @retval None
00140   */
00141 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
00142 {
00143   /* Check the parameters */
00144   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00145 
00146   /* Disable the selected DMAy Channelx */
00147   DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
00148 
00149   /* Reset DMAy Channelx control register */
00150   DMAy_Channelx->CCR  = 0;
00151 
00152   /* Reset DMAy Channelx remaining bytes register */
00153   DMAy_Channelx->CNDTR = 0;
00154 
00155   /* Reset DMAy Channelx peripheral address register */
00156   DMAy_Channelx->CPAR  = 0;
00157 
00158   /* Reset DMAy Channelx memory address register */
00159   DMAy_Channelx->CMAR = 0;
00160 
00161   if (DMAy_Channelx == DMA1_Channel1)
00162   {
00163     /* Reset interrupt pending bits for DMA1 Channel1 */
00164     DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
00165   }
00166   else if (DMAy_Channelx == DMA1_Channel2)
00167   {
00168     /* Reset interrupt pending bits for DMA1 Channel2 */
00169     DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
00170   }
00171   else if (DMAy_Channelx == DMA1_Channel3)
00172   {
00173     /* Reset interrupt pending bits for DMA1 Channel3 */
00174     DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
00175   }
00176   else if (DMAy_Channelx == DMA1_Channel4)
00177   {
00178     /* Reset interrupt pending bits for DMA1 Channel4 */
00179     DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
00180   }
00181   else if (DMAy_Channelx == DMA1_Channel5)
00182   {
00183     /* Reset interrupt pending bits for DMA1 Channel5 */
00184     DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
00185   }
00186   else if (DMAy_Channelx == DMA1_Channel6)
00187   {
00188     /* Reset interrupt pending bits for DMA1 Channel6 */
00189     DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
00190   }
00191   else if (DMAy_Channelx == DMA1_Channel7)
00192   {
00193     /* Reset interrupt pending bits for DMA1 Channel7 */
00194     DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
00195   }
00196   else if (DMAy_Channelx == DMA2_Channel1)
00197   {
00198     /* Reset interrupt pending bits for DMA2 Channel1 */
00199     DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
00200   }
00201   else if (DMAy_Channelx == DMA2_Channel2)
00202   {
00203     /* Reset interrupt pending bits for DMA2 Channel2 */
00204     DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
00205   }
00206   else if (DMAy_Channelx == DMA2_Channel3)
00207   {
00208     /* Reset interrupt pending bits for DMA2 Channel3 */
00209     DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
00210   }
00211   else if (DMAy_Channelx == DMA2_Channel4)
00212   {
00213     /* Reset interrupt pending bits for DMA2 Channel4 */
00214     DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
00215   }
00216   else
00217   { 
00218     if (DMAy_Channelx == DMA2_Channel5)
00219     {
00220       /* Reset interrupt pending bits for DMA2 Channel5 */
00221       DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
00222     }
00223   }
00224 }
00225 
00226 /**
00227   * @brief  Initializes the DMAy Channelx according to the specified parameters 
00228   *         in the DMA_InitStruct.
00229   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00230   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00231   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
00232   *         the configuration information for the specified DMA Channel.
00233   * @retval None
00234   */
00235 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
00236 {
00237   uint32_t tmpreg = 0;
00238 
00239   /* Check the parameters */
00240   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00241   assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
00242   assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
00243   assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
00244   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
00245   assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
00246   assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
00247   assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
00248   assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
00249 
00250 /*--------------------------- DMAy Channelx CCR Configuration ----------------*/
00251   /* Get the DMAy_Channelx CCR value */
00252   tmpreg = DMAy_Channelx->CCR;
00253 
00254   /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00255   tmpreg &= CCR_CLEAR_MASK;
00256 
00257   /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
00258   /* Set DIR bit according to DMA_DIR value */
00259   /* Set CIRC bit according to DMA_Mode value */
00260   /* Set PINC bit according to DMA_PeripheralInc value */
00261   /* Set MINC bit according to DMA_MemoryInc value */
00262   /* Set PSIZE bits according to DMA_PeripheralDataSize value */
00263   /* Set MSIZE bits according to DMA_MemoryDataSize value */
00264   /* Set PL bits according to DMA_Priority value */
00265   /* Set the MEM2MEM bit according to DMA_M2M value */
00266   tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00267             DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
00268             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
00269             DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
00270 
00271   /* Write to DMAy Channelx CCR */
00272   DMAy_Channelx->CCR = tmpreg;
00273 
00274 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
00275   /* Write to DMAy Channelx CNDTR */
00276   DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00277 
00278 /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
00279   /* Write to DMAy Channelx CPAR */
00280   DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
00281 
00282 /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
00283   /* Write to DMAy Channelx CMAR */
00284   DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
00285 }
00286 
00287 /**
00288   * @brief  Fills each DMA_InitStruct member with its default value.
00289   * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
00290   *         be initialized.
00291   * @retval None
00292   */
00293 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
00294 {
00295 /*-------------- Reset DMA init structure parameters values ------------------*/
00296   /* Initialize the DMA_PeripheralBaseAddr member */
00297   DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
00298   /* Initialize the DMA_MemoryBaseAddr member */
00299   DMA_InitStruct->DMA_MemoryBaseAddr = 0;
00300   /* Initialize the DMA_DIR member */
00301   DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
00302   /* Initialize the DMA_BufferSize member */
00303   DMA_InitStruct->DMA_BufferSize = 0;
00304   /* Initialize the DMA_PeripheralInc member */
00305   DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00306   /* Initialize the DMA_MemoryInc member */
00307   DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00308   /* Initialize the DMA_PeripheralDataSize member */
00309   DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00310   /* Initialize the DMA_MemoryDataSize member */
00311   DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00312   /* Initialize the DMA_Mode member */
00313   DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
00314   /* Initialize the DMA_Priority member */
00315   DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
00316   /* Initialize the DMA_M2M member */
00317   DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
00318 }
00319 
00320 /**
00321   * @brief  Enables or disables the specified DMAy Channelx.
00322   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00323   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00324   * @param  NewState: new state of the DMAy Channelx. 
00325   *         This parameter can be: ENABLE or DISABLE.
00326   * @retval None
00327   */
00328 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
00329 {
00330   /* Check the parameters */
00331   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00332   assert_param(IS_FUNCTIONAL_STATE(NewState));
00333 
00334   if (NewState != DISABLE)
00335   {
00336     /* Enable the selected DMAy Channelx */
00337     DMAy_Channelx->CCR |= DMA_CCR_EN;
00338   }
00339   else
00340   {
00341     /* Disable the selected DMAy Channelx */
00342     DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
00343   }
00344 }
00345 
00346 /**
00347   * @}
00348   */
00349   
00350 /** @defgroup DMA_Group2 Data Counter functions
00351  *  @brief   Data Counter functions
00352  *
00353 @verbatim  
00354  ===============================================================================
00355                       ##### Data Counter functions #####
00356  ===============================================================================
00357     [..] This subsection provides function allowing to configure and read the buffer 
00358          size (number of data to be transferred).The DMA data counter can be written 
00359          only when the DMA channel is disabled (ie. after transfer complete event).
00360     [..] The following function can be used to write the Channel data counter value:
00361          (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
00362     [..]
00363     (@) It is advised to use this function rather than DMA_Init() in situations 
00364         where only the Data buffer needs to be reloaded.
00365     [..] The DMA data counter can be read to indicate the number of remaining transfers 
00366          for the relative DMA channel. This counter is decremented at the end of each 
00367          data transfer and when the transfer is complete: 
00368          (+) If Normal mode is selected: the counter is set to 0.
00369          (+) If Circular mode is selected: the counter is reloaded with the initial 
00370          value(configured before enabling the DMA channel).
00371     [..] The following function can be used to read the Channel data counter value:
00372          (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
00373 
00374 @endverbatim
00375   * @{
00376   */
00377 
00378 /**
00379   * @brief  Sets the number of data units in the current DMAy Channelx transfer.
00380   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00381   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00382   * @param  DataNumber: The number of data units in the current DMAy Channelx
00383   *         transfer.   
00384   * @note   This function can only be used when the DMAy_Channelx is disabled.
00385   * @retval None.
00386   */
00387 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
00388 {
00389   /* Check the parameters */
00390   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00391 
00392 /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
00393   /* Write to DMAy Channelx CNDTR */
00394   DMAy_Channelx->CNDTR = DataNumber;
00395 }
00396 
00397 /**
00398   * @brief  Returns the number of remaining data units in the current
00399   *         DMAy Channelx transfer.
00400   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00401   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00402   * @retval The number of remaining data units in the current DMAy Channelx
00403   *         transfer.
00404   */
00405 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
00406 {
00407   /* Check the parameters */
00408   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00409   /* Return the number of remaining data units for DMAy Channelx */
00410   return ((uint16_t)(DMAy_Channelx->CNDTR));
00411 }
00412 
00413 /**
00414   * @}
00415   */
00416   
00417 /** @defgroup DMA_Group3 Interrupts and flags management functions
00418  *  @brief   Interrupts and flags management functions  
00419  *
00420 @verbatim
00421  ===============================================================================
00422           ##### Interrupts and flags management functions #####
00423  ===============================================================================
00424     [..] This subsection provides functions allowing to configure the DMA Interrupt 
00425          sources and check or clear the flags or pending bits status.
00426          The user should identify which mode will be used in his application to manage 
00427          the DMA controller events: Polling mode or Interrupt mode. 
00428   
00429   *** Polling Mode ***
00430   ====================
00431     [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller 
00432          number, x : DMA channel number):
00433          (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
00434          (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
00435          (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
00436          (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
00437              above occurred.
00438     [..]         
00439     (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
00440         same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
00441     [..] In this Mode it is advised to use the following functions:
00442          (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
00443          (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
00444 
00445   *** Interrupt Mode ***
00446   ======================
00447     [..] Each DMA channel can be managed through 4 Interrupts:
00448     (+) Interrupt Source
00449        (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
00450             event.
00451        (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete 
00452             event.
00453        (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
00454        (##) DMA_IT_GL: to indicate that at least one of the interrupts described 
00455             above occurred.
00456     -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
00457          the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
00458     [..] In this Mode it is advised to use the following functions:
00459          (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
00460          (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
00461          (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
00462 
00463 @endverbatim
00464   * @{
00465   */ 
00466 
00467 /**
00468   * @brief  Enables or disables the specified DMAy Channelx interrupts.
00469   * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and 
00470   *         x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
00471   * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
00472   *         or disabled. 
00473   *   This parameter can be any combination of the following values:
00474   *     @arg DMA_IT_TC: Transfer complete interrupt mask
00475   *     @arg DMA_IT_HT: Half transfer interrupt mask
00476   *     @arg DMA_IT_TE: Transfer error interrupt mask
00477   * @param  NewState: new state of the specified DMA interrupts.
00478   *         This parameter can be: ENABLE or DISABLE.
00479   * @retval None
00480   */
00481 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
00482 {
00483   /* Check the parameters */
00484   assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
00485   assert_param(IS_DMA_CONFIG_IT(DMA_IT));
00486   assert_param(IS_FUNCTIONAL_STATE(NewState));
00487   
00488   if (NewState != DISABLE)
00489   {
00490     /* Enable the selected DMA interrupts */
00491     DMAy_Channelx->CCR |= DMA_IT;
00492   }
00493   else
00494   {
00495     /* Disable the selected DMA interrupts */
00496     DMAy_Channelx->CCR &= ~DMA_IT;
00497   }
00498 }
00499 
00500 /**
00501   * @brief  Checks whether the specified DMAy Channelx flag is set or not.
00502   * @param  DMAy_FLAG: specifies the flag to check.
00503   *   This parameter can be one of the following values:
00504   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00505   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00506   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00507   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00508   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00509   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00510   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00511   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00512   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00513   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00514   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00515   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00516   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00517   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00518   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00519   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00520   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00521   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00522   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00523   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00524   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00525   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00526   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00527   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00528   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00529   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00530   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00531   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00532   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00533   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00534   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00535   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00536   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00537   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00538   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00539   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00540   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00541   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00542   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00543   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00544   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00545   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00546   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00547   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00548   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00549   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00550   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00551   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00552   *     
00553   * @note
00554   *    The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags 
00555   *    relative to the same channel is set (Transfer Complete, Half-transfer 
00556   *    Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or 
00557   *    DMAy_FLAG_TEx). 
00558   *      
00559   * @retval The new state of DMAy_FLAG (SET or RESET).
00560   */
00561 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
00562 {
00563   FlagStatus bitstatus = RESET;
00564   uint32_t tmpreg = 0;
00565   
00566   /* Check the parameters */
00567   assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
00568 
00569   /* Calculate the used DMAy */
00570   if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
00571   {
00572     /* Get DMA2 ISR register value */
00573     tmpreg = DMA2->ISR ;
00574   }
00575   else
00576   {
00577     /* Get DMA1 ISR register value */
00578     tmpreg = DMA1->ISR ;
00579   }
00580 
00581   /* Check the status of the specified DMAy flag */
00582   if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
00583   {
00584     /* DMAy_FLAG is set */
00585     bitstatus = SET;
00586   }
00587   else
00588   {
00589     /* DMAy_FLAG is reset */
00590     bitstatus = RESET;
00591   }
00592   
00593   /* Return the DMAy_FLAG status */
00594   return  bitstatus;
00595 }
00596 
00597 /**
00598   * @brief  Clears the DMAy Channelx's pending flags.
00599   * @param  DMAy_FLAG: specifies the flag to clear.
00600   *   This parameter can be any combination (for the same DMA) of the following values:
00601   *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
00602   *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
00603   *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
00604   *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
00605   *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
00606   *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
00607   *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
00608   *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
00609   *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
00610   *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
00611   *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
00612   *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
00613   *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
00614   *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
00615   *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
00616   *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
00617   *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
00618   *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
00619   *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
00620   *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
00621   *     @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
00622   *     @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
00623   *     @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
00624   *     @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
00625   *     @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
00626   *     @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
00627   *     @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
00628   *     @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
00629   *     @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
00630   *     @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
00631   *     @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
00632   *     @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
00633   *     @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
00634   *     @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
00635   *     @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
00636   *     @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
00637   *     @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
00638   *     @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
00639   *     @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
00640   *     @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
00641   *     @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
00642   *     @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
00643   *     @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
00644   *     @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
00645   *     @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
00646   *     @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
00647   *     @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
00648   *     @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
00649   *
00650   * @note
00651   *    Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
00652   *    relative to the same channel (Transfer Complete, Half-transfer Complete and
00653   *    Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
00654   *
00655   * @retval None
00656   */
00657 void DMA_ClearFlag(uint32_t DMAy_FLAG)
00658 {
00659   /* Check the parameters */
00660   assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
00661 
00662 /* Calculate the used DMAy */
00663   if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
00664   {
00665     /* Clear the selected DMAy flags */
00666     DMA2->IFCR = DMAy_FLAG;
00667   }
00668   else
00669   {
00670     /* Clear the selected DMAy flags */
00671     DMA1->IFCR = DMAy_FLAG;
00672   }
00673 }
00674 
00675 /**
00676   * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
00677   * @param  DMAy_IT: specifies the DMAy interrupt source to check. 
00678   *   This parameter can be one of the following values:
00679   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00680   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00681   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00682   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00683   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00684   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00685   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00686   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00687   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00688   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00689   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00690   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00691   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00692   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00693   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00694   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00695   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00696   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00697   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00698   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00699   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00700   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00701   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00702   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00703   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00704   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00705   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00706   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00707   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00708   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00709   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00710   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00711   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00712   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00713   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00714   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00715   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00716   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00717   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00718   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00719   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00720   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00721   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00722   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00723   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00724   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00725   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00726   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00727   *     
00728   * @note
00729   *    The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other 
00730   *    interrupts relative to the same channel is set (Transfer Complete, 
00731   *    Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, 
00732   *    DMAy_IT_HTx or DMAy_IT_TEx). 
00733   *      
00734   * @retval The new state of DMAy_IT (SET or RESET).
00735   */
00736 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
00737 {
00738   ITStatus bitstatus = RESET;
00739   uint32_t tmpreg = 0;
00740 
00741   /* Check the parameters */
00742   assert_param(IS_DMA_GET_IT(DMAy_IT));
00743 
00744   /* Calculate the used DMA */
00745   if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
00746   {
00747     /* Get DMA2 ISR register value */
00748     tmpreg = DMA2->ISR;
00749   }
00750   else
00751   {
00752     /* Get DMA1 ISR register value */
00753     tmpreg = DMA1->ISR;
00754   }
00755 
00756   /* Check the status of the specified DMAy interrupt */
00757   if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
00758   {
00759     /* DMAy_IT is set */
00760     bitstatus = SET;
00761   }
00762   else
00763   {
00764     /* DMAy_IT is reset */
00765     bitstatus = RESET;
00766   }
00767   /* Return the DMAy_IT status */
00768   return  bitstatus;
00769 }
00770 
00771 /**
00772   * @brief  Clears the DMAy Channelx's interrupt pending bits.
00773   * @param  DMAy_IT: specifies the DMAy interrupt pending bit to clear.
00774   *   This parameter can be any combination (for the same DMA) of the following values:
00775   *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
00776   *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
00777   *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
00778   *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
00779   *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
00780   *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
00781   *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
00782   *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
00783   *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
00784   *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
00785   *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
00786   *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
00787   *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
00788   *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
00789   *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
00790   *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
00791   *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
00792   *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
00793   *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
00794   *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
00795   *     @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
00796   *     @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
00797   *     @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
00798   *     @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
00799   *     @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
00800   *     @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
00801   *     @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
00802   *     @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
00803   *     @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
00804   *     @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
00805   *     @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
00806   *     @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
00807   *     @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
00808   *     @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
00809   *     @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
00810   *     @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
00811   *     @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
00812   *     @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
00813   *     @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
00814   *     @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
00815   *     @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
00816   *     @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
00817   *     @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
00818   *     @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
00819   *     @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
00820   *     @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
00821   *     @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
00822   *     @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
00823   *     
00824   * @note
00825   *    Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other 
00826   *    interrupts relative to the same channel (Transfer Complete, Half-transfer 
00827   *    Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and 
00828   *    DMAy_IT_TEx).  
00829   *        
00830   * @retval None
00831   */
00832 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
00833 {
00834   /* Check the parameters */
00835   assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
00836   
00837   /* Calculate the used DMAy */
00838   if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
00839   {
00840     /* Clear the selected DMAy interrupt pending bits */
00841     DMA2->IFCR = DMAy_IT;
00842   }
00843   else
00844   {
00845     /* Clear the selected DMAy interrupt pending bits */
00846     DMA1->IFCR = DMAy_IT;
00847   }
00848 }
00849 
00850 /**
00851   * @}
00852   */
00853 
00854 /**
00855   * @}
00856   */
00857 
00858 /**
00859   * @}
00860   */
00861 
00862 /**
00863   * @}
00864   */
00865 
00866 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/