Diff: src/system_stm32f30x.c

Revision:

1:f8e3e71af478

Parent:

0:404f5a4f1385

--- a/src/system_stm32f30x.c	Mon May 09 04:00:25 2016 +0000
+++ b/src/system_stm32f30x.c	Thu Apr 26 03:11:18 2018 +0000
@@ -197,6 +197,49 @@
 #endif  
 }
 
+struct __FILE { int handle; };
+
+typedef struct __FILE FILE;
+
+FILE __stdout;
+FILE __stdin;
+
+static int serial_init_done=0;
+
+static void serial_init() {
+    if(!serial_init_done) {
+        serial_init_done=1;
+        RCC->AHBENR |= RCC_AHBPeriph_GPIOC;
+        RCC->APB2ENR |= RCC_APB2Periph_USART1;
+        GPIOC->AFR[0] = (GPIOC->AFR[0] & 0xff00ffff) | 0x770000; // alt funcs for GPIOC4 and 5 are 7
+        GPIOC->OSPEEDR |= 0xf00; // speed high
+        GPIOC->OTYPER &= ~0x30; // output type pp
+        GPIOC->MODER = (GPIOC->MODER & ~0xf00) | 0xa00; // mode af
+        GPIOC->PUPDR = (GPIOC->PUPDR & ~0xf00) | 0x500; // pull up
+        USART1->CR1 &= ~USART_CR1_UE; // disable so we can change settings
+        USART1->CR2 = (USART1->CR2 & ~USART_CR2_STOP) | USART_StopBits_1;
+        USART1->CR1 = (USART1->CR1 & 0xFFFFE6F3) | USART_WordLength_8b | USART_Parity_No | USART_Mode_Rx | USART_Mode_Tx;
+        USART1->CR3 = (USART1->CR3 & 0xFFFFFCFF) | USART_HardwareFlowControl_None;
+        USART1->BRR = SystemCoreClock/115200; // set baud rate
+        USART1->CR1 |= USART_CR1_UE; // enable serial port
+    }
+}
+
+int fputc(int ch, FILE *f) {
+    serial_init();
+    USART1->TDR = ch & 0x1ff;
+    while (!(USART1->ISR & USART_FLAG_TXE));
+    return ch;
+}
+
+int fgetc(FILE *f) {
+    serial_init();
+    if(USART1->ISR & USART_FLAG_ORE)
+        USART1->ISR &= ~USART_FLAG_ORE;
+    while(!(USART1->ISR & USART_FLAG_RXNE));
+    return USART1->RDR & 0xff;
+}
+
 /**
    * @brief  Update SystemCoreClock variable according to Clock Register Values.
   *         The SystemCoreClock variable contains the core clock (HCLK), it can