Martin Johnson / STM32F3-Discovery

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src/system_stm32f30x.c@0:404f5a4f1385, 2016-05-09 (annotated)

Committer:
MartinJohnson
Date:
Mon May 09 04:00:25 2016 +0000
Revision:
0:404f5a4f1385
Child:
1:f8e3e71af478
Initial library for STM32F3 discovery board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MartinJohnson 0:404f5a4f1385 1 /**
MartinJohnson 0:404f5a4f1385 2 ******************************************************************************
MartinJohnson 0:404f5a4f1385 3 * @file system_stm32f30x.c
MartinJohnson 0:404f5a4f1385 4 * @author MCD Application Team
MartinJohnson 0:404f5a4f1385 5 * @version V1.2.2
MartinJohnson 0:404f5a4f1385 6 * @date 27-February-2015
MartinJohnson 0:404f5a4f1385 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
MartinJohnson 0:404f5a4f1385 8 * This file contains the system clock configuration for STM32F30x devices,
MartinJohnson 0:404f5a4f1385 9 * and is generated by the clock configuration tool
MartinJohnson 0:404f5a4f1385 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
MartinJohnson 0:404f5a4f1385 11 *
MartinJohnson 0:404f5a4f1385 12 * 1. This file provides two functions and one global variable to be called from
MartinJohnson 0:404f5a4f1385 13 * user application:
MartinJohnson 0:404f5a4f1385 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
MartinJohnson 0:404f5a4f1385 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
MartinJohnson 0:404f5a4f1385 16 * depending on the configuration made in the clock xls tool.
MartinJohnson 0:404f5a4f1385 17 * This function is called at startup just after reset and
MartinJohnson 0:404f5a4f1385 18 * before branch to main program. This call is made inside
MartinJohnson 0:404f5a4f1385 19 * the "startup_stm32f30x.s" file.
MartinJohnson 0:404f5a4f1385 20 *
MartinJohnson 0:404f5a4f1385 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
MartinJohnson 0:404f5a4f1385 22 * by the user application to setup the SysTick
MartinJohnson 0:404f5a4f1385 23 * timer or configure other parameters.
MartinJohnson 0:404f5a4f1385 24 *
MartinJohnson 0:404f5a4f1385 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
MartinJohnson 0:404f5a4f1385 26 * be called whenever the core clock is changed
MartinJohnson 0:404f5a4f1385 27 * during program execution.
MartinJohnson 0:404f5a4f1385 28 *
MartinJohnson 0:404f5a4f1385 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
MartinJohnson 0:404f5a4f1385 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
MartinJohnson 0:404f5a4f1385 31 * configure the system clock before to branch to main program.
MartinJohnson 0:404f5a4f1385 32 *
MartinJohnson 0:404f5a4f1385 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
MartinJohnson 0:404f5a4f1385 34 * function will do nothing and HSI still used as system clock source. User can
MartinJohnson 0:404f5a4f1385 35 * add some code to deal with this issue inside the SetSysClock() function.
MartinJohnson 0:404f5a4f1385 36 *
MartinJohnson 0:404f5a4f1385 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
MartinJohnson 0:404f5a4f1385 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
MartinJohnson 0:404f5a4f1385 39 * through PLL, and you are using different crystal you have to adapt the HSE
MartinJohnson 0:404f5a4f1385 40 * value to your own configuration.
MartinJohnson 0:404f5a4f1385 41 *
MartinJohnson 0:404f5a4f1385 42 * 5. This file configures the system clock as follows:
MartinJohnson 0:404f5a4f1385 43 *=============================================================================
MartinJohnson 0:404f5a4f1385 44 * Supported STM32F30x device
MartinJohnson 0:404f5a4f1385 45 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 46 * System Clock source | PLL (HSE)
MartinJohnson 0:404f5a4f1385 47 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 48 * SYSCLK(Hz) | 72000000
MartinJohnson 0:404f5a4f1385 49 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 50 * HCLK(Hz) | 72000000
MartinJohnson 0:404f5a4f1385 51 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 52 * AHB Prescaler | 1
MartinJohnson 0:404f5a4f1385 53 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 54 * APB2 Prescaler | 1
MartinJohnson 0:404f5a4f1385 55 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 56 * APB1 Prescaler | 2
MartinJohnson 0:404f5a4f1385 57 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 58 * HSE Frequency(Hz) | 8000000
MartinJohnson 0:404f5a4f1385 59 *----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 60 * PLLMUL | 9
MartinJohnson 0:404f5a4f1385 61 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 62 * PREDIV | 1
MartinJohnson 0:404f5a4f1385 63 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 64 * USB Clock | DISABLE
MartinJohnson 0:404f5a4f1385 65 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 66 * Flash Latency(WS) | 2
MartinJohnson 0:404f5a4f1385 67 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 68 * Prefetch Buffer | ON
MartinJohnson 0:404f5a4f1385 69 *-----------------------------------------------------------------------------
MartinJohnson 0:404f5a4f1385 70 *=============================================================================
MartinJohnson 0:404f5a4f1385 71 ******************************************************************************
MartinJohnson 0:404f5a4f1385 72 * @attention
MartinJohnson 0:404f5a4f1385 73 *
MartinJohnson 0:404f5a4f1385 74 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
MartinJohnson 0:404f5a4f1385 75 *
MartinJohnson 0:404f5a4f1385 76 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
MartinJohnson 0:404f5a4f1385 77 * You may not use this file except in compliance with the License.
MartinJohnson 0:404f5a4f1385 78 * You may obtain a copy of the License at:
MartinJohnson 0:404f5a4f1385 79 *
MartinJohnson 0:404f5a4f1385 80 * http://www.st.com/software_license_agreement_liberty_v2
MartinJohnson 0:404f5a4f1385 81 *
MartinJohnson 0:404f5a4f1385 82 * Unless required by applicable law or agreed to in writing, software
MartinJohnson 0:404f5a4f1385 83 * distributed under the License is distributed on an "AS IS" BASIS,
MartinJohnson 0:404f5a4f1385 84 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MartinJohnson 0:404f5a4f1385 85 * See the License for the specific language governing permissions and
MartinJohnson 0:404f5a4f1385 86 * limitations under the License.
MartinJohnson 0:404f5a4f1385 87 *
MartinJohnson 0:404f5a4f1385 88 ******************************************************************************
MartinJohnson 0:404f5a4f1385 89 */
MartinJohnson 0:404f5a4f1385 90 /** @addtogroup CMSIS
MartinJohnson 0:404f5a4f1385 91 * @{
MartinJohnson 0:404f5a4f1385 92 */
MartinJohnson 0:404f5a4f1385 93
MartinJohnson 0:404f5a4f1385 94 /** @addtogroup stm32f30x_system
MartinJohnson 0:404f5a4f1385 95 * @{
MartinJohnson 0:404f5a4f1385 96 */
MartinJohnson 0:404f5a4f1385 97
MartinJohnson 0:404f5a4f1385 98 /** @addtogroup STM32F30x_System_Private_Includes
MartinJohnson 0:404f5a4f1385 99 * @{
MartinJohnson 0:404f5a4f1385 100 */
MartinJohnson 0:404f5a4f1385 101
MartinJohnson 0:404f5a4f1385 102 #include "stm32f30x.h"
MartinJohnson 0:404f5a4f1385 103
MartinJohnson 0:404f5a4f1385 104 /**
MartinJohnson 0:404f5a4f1385 105 * @}
MartinJohnson 0:404f5a4f1385 106 */
MartinJohnson 0:404f5a4f1385 107
MartinJohnson 0:404f5a4f1385 108 /* Private typedef -----------------------------------------------------------*/
MartinJohnson 0:404f5a4f1385 109
MartinJohnson 0:404f5a4f1385 110 /** @addtogroup STM32F30x_System_Private_Defines
MartinJohnson 0:404f5a4f1385 111 * @{
MartinJohnson 0:404f5a4f1385 112 */
MartinJohnson 0:404f5a4f1385 113 /*!< Uncomment the following line if you need to relocate your vector Table in
MartinJohnson 0:404f5a4f1385 114 Internal SRAM. */
MartinJohnson 0:404f5a4f1385 115 /* #define VECT_TAB_SRAM */
MartinJohnson 0:404f5a4f1385 116 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
MartinJohnson 0:404f5a4f1385 117 This value must be a multiple of 0x200. */
MartinJohnson 0:404f5a4f1385 118 /**
MartinJohnson 0:404f5a4f1385 119 * @}
MartinJohnson 0:404f5a4f1385 120 */
MartinJohnson 0:404f5a4f1385 121
MartinJohnson 0:404f5a4f1385 122 /* Private macro -------------------------------------------------------------*/
MartinJohnson 0:404f5a4f1385 123
MartinJohnson 0:404f5a4f1385 124 /** @addtogroup STM32F30x_System_Private_Variables
MartinJohnson 0:404f5a4f1385 125 * @{
MartinJohnson 0:404f5a4f1385 126 */
MartinJohnson 0:404f5a4f1385 127
MartinJohnson 0:404f5a4f1385 128 uint32_t SystemCoreClock = 72000000;
MartinJohnson 0:404f5a4f1385 129
MartinJohnson 0:404f5a4f1385 130 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
MartinJohnson 0:404f5a4f1385 131
MartinJohnson 0:404f5a4f1385 132 /**
MartinJohnson 0:404f5a4f1385 133 * @}
MartinJohnson 0:404f5a4f1385 134 */
MartinJohnson 0:404f5a4f1385 135
MartinJohnson 0:404f5a4f1385 136 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
MartinJohnson 0:404f5a4f1385 137 * @{
MartinJohnson 0:404f5a4f1385 138 */
MartinJohnson 0:404f5a4f1385 139
MartinJohnson 0:404f5a4f1385 140 static void SetSysClock(void);
MartinJohnson 0:404f5a4f1385 141
MartinJohnson 0:404f5a4f1385 142 /**
MartinJohnson 0:404f5a4f1385 143 * @}
MartinJohnson 0:404f5a4f1385 144 */
MartinJohnson 0:404f5a4f1385 145
MartinJohnson 0:404f5a4f1385 146 /** @addtogroup STM32F30x_System_Private_Functions
MartinJohnson 0:404f5a4f1385 147 * @{
MartinJohnson 0:404f5a4f1385 148 */
MartinJohnson 0:404f5a4f1385 149
MartinJohnson 0:404f5a4f1385 150 /**
MartinJohnson 0:404f5a4f1385 151 * @brief Setup the microcontroller system
MartinJohnson 0:404f5a4f1385 152 * Initialize the Embedded Flash Interface, the PLL and update the
MartinJohnson 0:404f5a4f1385 153 * SystemFrequency variable.
MartinJohnson 0:404f5a4f1385 154 * @param None
MartinJohnson 0:404f5a4f1385 155 * @retval None
MartinJohnson 0:404f5a4f1385 156 */
MartinJohnson 0:404f5a4f1385 157 void SystemInit(void)
MartinJohnson 0:404f5a4f1385 158 {
MartinJohnson 0:404f5a4f1385 159 /* FPU settings ------------------------------------------------------------*/
MartinJohnson 0:404f5a4f1385 160 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
MartinJohnson 0:404f5a4f1385 161 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
MartinJohnson 0:404f5a4f1385 162 #endif
MartinJohnson 0:404f5a4f1385 163
MartinJohnson 0:404f5a4f1385 164 /* Reset the RCC clock configuration to the default reset state ------------*/
MartinJohnson 0:404f5a4f1385 165 /* Set HSION bit */
MartinJohnson 0:404f5a4f1385 166 RCC->CR |= (uint32_t)0x00000001;
MartinJohnson 0:404f5a4f1385 167
MartinJohnson 0:404f5a4f1385 168 /* Reset CFGR register */
MartinJohnson 0:404f5a4f1385 169 RCC->CFGR &= 0xF87FC00C;
MartinJohnson 0:404f5a4f1385 170
MartinJohnson 0:404f5a4f1385 171 /* Reset HSEON, CSSON and PLLON bits */
MartinJohnson 0:404f5a4f1385 172 RCC->CR &= (uint32_t)0xFEF6FFFF;
MartinJohnson 0:404f5a4f1385 173
MartinJohnson 0:404f5a4f1385 174 /* Reset HSEBYP bit */
MartinJohnson 0:404f5a4f1385 175 RCC->CR &= (uint32_t)0xFFFBFFFF;
MartinJohnson 0:404f5a4f1385 176
MartinJohnson 0:404f5a4f1385 177 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
MartinJohnson 0:404f5a4f1385 178 RCC->CFGR &= (uint32_t)0xFF80FFFF;
MartinJohnson 0:404f5a4f1385 179
MartinJohnson 0:404f5a4f1385 180 /* Reset PREDIV1[3:0] bits */
MartinJohnson 0:404f5a4f1385 181 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
MartinJohnson 0:404f5a4f1385 182
MartinJohnson 0:404f5a4f1385 183 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
MartinJohnson 0:404f5a4f1385 184 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
MartinJohnson 0:404f5a4f1385 185
MartinJohnson 0:404f5a4f1385 186 /* Disable all interrupts */
MartinJohnson 0:404f5a4f1385 187 RCC->CIR = 0x00000000;
MartinJohnson 0:404f5a4f1385 188
MartinJohnson 0:404f5a4f1385 189 /* Configure the System clock source, PLL Multiplier and Divider factors,
MartinJohnson 0:404f5a4f1385 190 AHB/APBx prescalers and Flash settings ----------------------------------*/
MartinJohnson 0:404f5a4f1385 191 SetSysClock();
MartinJohnson 0:404f5a4f1385 192
MartinJohnson 0:404f5a4f1385 193 #ifdef VECT_TAB_SRAM
MartinJohnson 0:404f5a4f1385 194 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
MartinJohnson 0:404f5a4f1385 195 #else
MartinJohnson 0:404f5a4f1385 196 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
MartinJohnson 0:404f5a4f1385 197 #endif
MartinJohnson 0:404f5a4f1385 198 }
MartinJohnson 0:404f5a4f1385 199
MartinJohnson 0:404f5a4f1385 200 /**
MartinJohnson 0:404f5a4f1385 201 * @brief Update SystemCoreClock variable according to Clock Register Values.
MartinJohnson 0:404f5a4f1385 202 * The SystemCoreClock variable contains the core clock (HCLK), it can
MartinJohnson 0:404f5a4f1385 203 * be used by the user application to setup the SysTick timer or configure
MartinJohnson 0:404f5a4f1385 204 * other parameters.
MartinJohnson 0:404f5a4f1385 205 *
MartinJohnson 0:404f5a4f1385 206 * @note Each time the core clock (HCLK) changes, this function must be called
MartinJohnson 0:404f5a4f1385 207 * to update SystemCoreClock variable value. Otherwise, any configuration
MartinJohnson 0:404f5a4f1385 208 * based on this variable will be incorrect.
MartinJohnson 0:404f5a4f1385 209 *
MartinJohnson 0:404f5a4f1385 210 * @note - The system frequency computed by this function is not the real
MartinJohnson 0:404f5a4f1385 211 * frequency in the chip. It is calculated based on the predefined
MartinJohnson 0:404f5a4f1385 212 * constant and the selected clock source:
MartinJohnson 0:404f5a4f1385 213 *
MartinJohnson 0:404f5a4f1385 214 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
MartinJohnson 0:404f5a4f1385 215 *
MartinJohnson 0:404f5a4f1385 216 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
MartinJohnson 0:404f5a4f1385 217 *
MartinJohnson 0:404f5a4f1385 218 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
MartinJohnson 0:404f5a4f1385 219 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
MartinJohnson 0:404f5a4f1385 220 *
MartinJohnson 0:404f5a4f1385 221 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
MartinJohnson 0:404f5a4f1385 222 * 8 MHz) but the real value may vary depending on the variations
MartinJohnson 0:404f5a4f1385 223 * in voltage and temperature.
MartinJohnson 0:404f5a4f1385 224 *
MartinJohnson 0:404f5a4f1385 225 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
MartinJohnson 0:404f5a4f1385 226 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
MartinJohnson 0:404f5a4f1385 227 * frequency of the crystal used. Otherwise, this function may
MartinJohnson 0:404f5a4f1385 228 * have wrong result.
MartinJohnson 0:404f5a4f1385 229 *
MartinJohnson 0:404f5a4f1385 230 * - The result of this function could be not correct when using fractional
MartinJohnson 0:404f5a4f1385 231 * value for HSE crystal.
MartinJohnson 0:404f5a4f1385 232 *
MartinJohnson 0:404f5a4f1385 233 * @param None
MartinJohnson 0:404f5a4f1385 234 * @retval None
MartinJohnson 0:404f5a4f1385 235 */
MartinJohnson 0:404f5a4f1385 236 void SystemCoreClockUpdate (void)
MartinJohnson 0:404f5a4f1385 237 {
MartinJohnson 0:404f5a4f1385 238 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
MartinJohnson 0:404f5a4f1385 239
MartinJohnson 0:404f5a4f1385 240 /* Get SYSCLK source -------------------------------------------------------*/
MartinJohnson 0:404f5a4f1385 241 tmp = RCC->CFGR & RCC_CFGR_SWS;
MartinJohnson 0:404f5a4f1385 242
MartinJohnson 0:404f5a4f1385 243 switch (tmp)
MartinJohnson 0:404f5a4f1385 244 {
MartinJohnson 0:404f5a4f1385 245 case 0x00: /* HSI used as system clock */
MartinJohnson 0:404f5a4f1385 246 SystemCoreClock = HSI_VALUE;
MartinJohnson 0:404f5a4f1385 247 break;
MartinJohnson 0:404f5a4f1385 248 case 0x04: /* HSE used as system clock */
MartinJohnson 0:404f5a4f1385 249 SystemCoreClock = HSE_VALUE;
MartinJohnson 0:404f5a4f1385 250 break;
MartinJohnson 0:404f5a4f1385 251 case 0x08: /* PLL used as system clock */
MartinJohnson 0:404f5a4f1385 252 /* Get PLL clock source and multiplication factor ----------------------*/
MartinJohnson 0:404f5a4f1385 253 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
MartinJohnson 0:404f5a4f1385 254 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
MartinJohnson 0:404f5a4f1385 255 pllmull = ( pllmull >> 18) + 2;
MartinJohnson 0:404f5a4f1385 256
MartinJohnson 0:404f5a4f1385 257 if (pllsource == 0x00)
MartinJohnson 0:404f5a4f1385 258 {
MartinJohnson 0:404f5a4f1385 259 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
MartinJohnson 0:404f5a4f1385 260 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
MartinJohnson 0:404f5a4f1385 261 }
MartinJohnson 0:404f5a4f1385 262 else
MartinJohnson 0:404f5a4f1385 263 {
MartinJohnson 0:404f5a4f1385 264 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
MartinJohnson 0:404f5a4f1385 265 /* HSE oscillator clock selected as PREDIV1 clock entry */
MartinJohnson 0:404f5a4f1385 266 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
MartinJohnson 0:404f5a4f1385 267 }
MartinJohnson 0:404f5a4f1385 268 break;
MartinJohnson 0:404f5a4f1385 269 default: /* HSI used as system clock */
MartinJohnson 0:404f5a4f1385 270 SystemCoreClock = HSI_VALUE;
MartinJohnson 0:404f5a4f1385 271 break;
MartinJohnson 0:404f5a4f1385 272 }
MartinJohnson 0:404f5a4f1385 273 /* Compute HCLK clock frequency ----------------*/
MartinJohnson 0:404f5a4f1385 274 /* Get HCLK prescaler */
MartinJohnson 0:404f5a4f1385 275 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
MartinJohnson 0:404f5a4f1385 276 /* HCLK clock frequency */
MartinJohnson 0:404f5a4f1385 277 SystemCoreClock >>= tmp;
MartinJohnson 0:404f5a4f1385 278 }
MartinJohnson 0:404f5a4f1385 279
MartinJohnson 0:404f5a4f1385 280 /**
MartinJohnson 0:404f5a4f1385 281 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
MartinJohnson 0:404f5a4f1385 282 * AHB/APBx prescalers and Flash settings
MartinJohnson 0:404f5a4f1385 283 * @note This function should be called only once the RCC clock configuration
MartinJohnson 0:404f5a4f1385 284 * is reset to the default reset state (done in SystemInit() function).
MartinJohnson 0:404f5a4f1385 285 * @param None
MartinJohnson 0:404f5a4f1385 286 * @retval None
MartinJohnson 0:404f5a4f1385 287 */
MartinJohnson 0:404f5a4f1385 288 static void SetSysClock(void)
MartinJohnson 0:404f5a4f1385 289 {
MartinJohnson 0:404f5a4f1385 290 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
MartinJohnson 0:404f5a4f1385 291
MartinJohnson 0:404f5a4f1385 292 /******************************************************************************/
MartinJohnson 0:404f5a4f1385 293 /* PLL (clocked by HSE) used as System clock source */
MartinJohnson 0:404f5a4f1385 294 /******************************************************************************/
MartinJohnson 0:404f5a4f1385 295
MartinJohnson 0:404f5a4f1385 296 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
MartinJohnson 0:404f5a4f1385 297 /* Enable HSE */
MartinJohnson 0:404f5a4f1385 298 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
MartinJohnson 0:404f5a4f1385 299
MartinJohnson 0:404f5a4f1385 300 /* Wait till HSE is ready and if Time out is reached exit */
MartinJohnson 0:404f5a4f1385 301 do
MartinJohnson 0:404f5a4f1385 302 {
MartinJohnson 0:404f5a4f1385 303 HSEStatus = RCC->CR & RCC_CR_HSERDY;
MartinJohnson 0:404f5a4f1385 304 StartUpCounter++;
MartinJohnson 0:404f5a4f1385 305 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
MartinJohnson 0:404f5a4f1385 306
MartinJohnson 0:404f5a4f1385 307 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
MartinJohnson 0:404f5a4f1385 308 {
MartinJohnson 0:404f5a4f1385 309 HSEStatus = (uint32_t)0x01;
MartinJohnson 0:404f5a4f1385 310 }
MartinJohnson 0:404f5a4f1385 311 else
MartinJohnson 0:404f5a4f1385 312 {
MartinJohnson 0:404f5a4f1385 313 HSEStatus = (uint32_t)0x00;
MartinJohnson 0:404f5a4f1385 314 }
MartinJohnson 0:404f5a4f1385 315
MartinJohnson 0:404f5a4f1385 316 if (HSEStatus == (uint32_t)0x01)
MartinJohnson 0:404f5a4f1385 317 {
MartinJohnson 0:404f5a4f1385 318 /* Enable Prefetch Buffer and set Flash Latency */
MartinJohnson 0:404f5a4f1385 319 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
MartinJohnson 0:404f5a4f1385 320
MartinJohnson 0:404f5a4f1385 321 /* HCLK = SYSCLK / 1 */
MartinJohnson 0:404f5a4f1385 322 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
MartinJohnson 0:404f5a4f1385 323
MartinJohnson 0:404f5a4f1385 324 /* PCLK2 = HCLK / 1 */
MartinJohnson 0:404f5a4f1385 325 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
MartinJohnson 0:404f5a4f1385 326
MartinJohnson 0:404f5a4f1385 327 /* PCLK1 = HCLK / 2 */
MartinJohnson 0:404f5a4f1385 328 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
MartinJohnson 0:404f5a4f1385 329
MartinJohnson 0:404f5a4f1385 330 /* PLL configuration */
MartinJohnson 0:404f5a4f1385 331 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
MartinJohnson 0:404f5a4f1385 332 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
MartinJohnson 0:404f5a4f1385 333
MartinJohnson 0:404f5a4f1385 334 /* Enable PLL */
MartinJohnson 0:404f5a4f1385 335 RCC->CR |= RCC_CR_PLLON;
MartinJohnson 0:404f5a4f1385 336
MartinJohnson 0:404f5a4f1385 337 /* Wait till PLL is ready */
MartinJohnson 0:404f5a4f1385 338 while((RCC->CR & RCC_CR_PLLRDY) == 0)
MartinJohnson 0:404f5a4f1385 339 {
MartinJohnson 0:404f5a4f1385 340 }
MartinJohnson 0:404f5a4f1385 341
MartinJohnson 0:404f5a4f1385 342 /* Select PLL as system clock source */
MartinJohnson 0:404f5a4f1385 343 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
MartinJohnson 0:404f5a4f1385 344 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
MartinJohnson 0:404f5a4f1385 345
MartinJohnson 0:404f5a4f1385 346 /* Wait till PLL is used as system clock source */
MartinJohnson 0:404f5a4f1385 347 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
MartinJohnson 0:404f5a4f1385 348 {
MartinJohnson 0:404f5a4f1385 349 }
MartinJohnson 0:404f5a4f1385 350 }
MartinJohnson 0:404f5a4f1385 351 else
MartinJohnson 0:404f5a4f1385 352 { /* If HSE fails to start-up, the application will have wrong clock
MartinJohnson 0:404f5a4f1385 353 configuration. User can add here some code to deal with this error */
MartinJohnson 0:404f5a4f1385 354 }
MartinJohnson 0:404f5a4f1385 355 }
MartinJohnson 0:404f5a4f1385 356
MartinJohnson 0:404f5a4f1385 357 /**
MartinJohnson 0:404f5a4f1385 358 * @}
MartinJohnson 0:404f5a4f1385 359 */
MartinJohnson 0:404f5a4f1385 360
MartinJohnson 0:404f5a4f1385 361 /**
MartinJohnson 0:404f5a4f1385 362 * @}
MartinJohnson 0:404f5a4f1385 363 */
MartinJohnson 0:404f5a4f1385 364
MartinJohnson 0:404f5a4f1385 365 /**
MartinJohnson 0:404f5a4f1385 366 * @}
MartinJohnson 0:404f5a4f1385 367 */
MartinJohnson 0:404f5a4f1385 368
MartinJohnson 0:404f5a4f1385 369 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
MartinJohnson 0:404f5a4f1385 370