Diff: video.c

Revision:

12:f819427d0bec

Parent:

6:f16335989076

Child:

14:3035b3271395

--- a/video.c	Thu May 17 21:27:22 2018 +0000
+++ b/video.c	Fri May 18 01:26:09 2018 +0000
@@ -123,9 +123,9 @@
 	
 	*/
 
-	TimerPeriod = 2048;
-	Channel1Pulse = 144;		/* HSYNC */
-	Channel2Pulse = 360; 		/* HSYNC + BACK PORCH */
+	TimerPeriod = 2231;//2287;
+	Channel1Pulse = 274;		/* HSYNC */
+	Channel2Pulse = 411; 		/* HSYNC + BACK PORCH */
 	
 	TIM1->CR1 &= ~TIM_CR1_CEN;
 	TIM1->PSC=0;
@@ -159,7 +159,7 @@
 	//TIM16->CR1 |= TIM_CR1_OPM; 
 	
 	TIM8->DIER |= TIM_DIER_UDE;
-	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 4 ;
+	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 4;//TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | 4 ; // reset mode from tim1
 	//TIM16->SMCR |= TIM_SMCR_MSM;
 	//TIM16->CR2 = (TIM16->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1;// TIM_TRGOSource_Update mode
 	
@@ -181,18 +181,19 @@
 
 	/* VSYNC (TIM2_CH2) and VSYNC_BACKPORCH (TIM2_CH3) */
 	/* Channel 2 and 3 Configuration in PWM mode */
-	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// triggered slave mode trigger source 0
-	
-	
-	TimerPeriod = 625;		/* Vertical lines */
+	//TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0 (tim1)
+	//TIM2->CR2 |= TIM_CR2_MMS_0; // enable
+//	int rate=36000000;
+	TimerPeriod = 525;		/* Vertical lines */
 	Channel2Pulse = 2;		/* Sync pulse */
-	Channel3Pulse = 24;		/* Sync pulse + Back porch */
+	Channel3Pulse = 35;		/* Sync pulse + Back porch */
 
 	TIM2->CR1 &= ~TIM_CR1_CEN;
-	TIM2->PSC=0;
+	TIM2->PSC=2286;//1143; // 72MHz/1144=31.468KHz 
 	TIM2->ARR=TimerPeriod;
 	TIM2->CNT=0;
 
+	TIM2->CR2 |= TIM_CR2_MMS_1; // master mode: TRGO is an update
 	// disable Capture and Compare 2 and 3
 	TIM2->CCER &= ~(TIM_CCER_CC2E | TIM_CCER_CC3E);
 	// set output compare 1 to PWM mode with preload
@@ -200,6 +201,8 @@
 	TIM2->CCR2=Channel2Pulse;
 	TIM2->CCR3=Channel3Pulse;
 	
+	
+	
 //	TIM2->CCR2 |= TIM_CR2_OIS1; // output idle state set
 	// enable Capture and Compare 2 and 3
 	TIM2->CCER |=  TIM_CCER_CC2E |  TIM_CCER_CC3E | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
@@ -252,7 +255,7 @@
 //	and start the DMA to output a single frame buffer line through the GPIO device.
 //*****************************************************************************
 //__attribute__((interrupt)) 
-
+int hlines=0,dlines=0;
 __attribute__ ((section ("ccmram"))) void TIM1_CC_IRQHandler(void) {
 	if (vflag) {
 		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// 0x3093;
@@ -260,6 +263,7 @@
 		
 		TIM8->CR1 |= TIM_CR1_CEN;
 		//TIM8->CNT=7;//4-(TIM1->CNT&7);
+		hlines++;
 	}
 	TIM1->SR = 0xFFFB; //~TIM_IT_CC2;
 }
@@ -269,13 +273,16 @@
 //	Sets the 'vflag' variable to 1 (valid vertical frame).
 //*****************************************************************************
 //__attribute__((interrupt)) 
+extern int sysTicks;
 __attribute__ ((section ("ccmram"))) void TIM2_IRQHandler(void) {
 	vflag = 1;
 	TIM2->SR = 0xFFF7; //~TIM_IT_CC3;
 		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
 	//	TIM8->CNT=0;
 	//	TIM8->CR1 |= TIM_CR1_CEN;
-
+		printf("%d %d %d\n",sysTicks,hlines,dlines);
+		hlines=0;
+		dlines=0;
 }
 
 //*****************************************************************************
@@ -290,10 +297,10 @@
 	TIM8->CNT=0;
 	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;// | DMA_CCR_EN;// 0x3093; 0x92;// | (1<<10) | (1<<8);
 	DMA2_Channel1->CNDTR = HTOTAL;
-	
+	dlines++;
 	
 	vdraw++;
-	if (vdraw == 3) {
+	if (vdraw == 4) {
 		vdraw = 0;
 		vline++;
 		if (vline == VID_VSIZE) {