Diff: video.c

Revision:

14:3035b3271395

Parent:

12:f819427d0bec

Child:

16:915db2280bc4

--- a/video.c	Thu May 31 03:27:48 2018 +0000
+++ b/video.c	Thu May 31 03:38:14 2018 +0000
@@ -2,7 +2,8 @@
  * STM32 VGA demo
  * Copyright (C) 2012 Artekit Italy
  * http://www.artekit.eu
- * Written by Ruben H. Meleca
+ * Originally Written by Ruben H. Meleca
+ * updated for STM32F3 discovery with colour VGA output
  
 ### video.c
  
@@ -28,13 +29,12 @@
 //  \ o  o  o  o Xo   /		H=HSync=PA8	R=Red=PD0
 //   \ o  o Ho Vo  o /		V=Vsync=PA1 G=Green=PD1
 //    --------------		            B=Blue=PD2
-//
+// 8x2 connector
 // R G B o   o X X 
 // o o o o o H V o
 // 
 #include "stm32f30x.h"
 #include "video.h"
-#define HTOTAL	(VID_HSIZE+3)					/* Total bytes to send */
 
 __attribute__ ((aligned (4))) u8 volatile fba[VID_VSIZE*HTOTAL];	/* Frame buffer */
 
@@ -86,8 +86,8 @@
 	gpio_set_af(GPIOA,8,6,GPIO_OUTPUT_PUSH_PULL, GPIO_NO_PULL, GPIO_SPEED_LOW);
 
 	/*
-		SVGA 800x600 @ 56 Hz
-		Vertical refresh	35.15625 kHz
+		VGA 640x480 @ 60 Hz
+		Vertical refresh	31.46875 kHz
 		Pixel freq.			36.0 MHz
 		
 		1 system tick @ 72Mhz = 0,0138 us
@@ -97,103 +97,93 @@
 		Horizontal timing
 		-----------------
 		
-		Timer 1 period = 35156 Hz
-		
-		Timer 1 channel 1 generates a pulse for HSYNC each 28.4 us.
-		28.4 us	= Visible area + Front porch + Sync pulse + Back porch.
-		HSYNC is 2 us long, so the math to do is:
-		2us / 0,0138us = 144 system ticks.
-		
-		Timer 1 channel 2 generates a pulse equal to HSYNC + back porch.
-		This interrupt will fire the DMA request to draw on the screen if vflag == 1.
-		Since firing the DMA takes more or less 800ns, we'll add some extra time.
-		The math for HSYNC + back porch is:
-		(2us + 3,55us - dma) / 0,0138us = +-350 system ticks
+		Timer 1 period = 31468.53 Hz		
 	
 		Horizontal timing info
 		----------------------
 
-						Dots	us
-		--------------------------------------------		
-		Visible area	800		22.222222222222
-		Front porch		24		0.66666666666667
-		Sync pulse		72		2
-		Back porch		128		3.5555555555556
-		Whole line		1024	28.444444444444
+						Dots	us					ticks
+		----------------------------------------------------		
+		Visible area	640		25.422045680238		1830
+		Front porch		16		0.6355511420059		46
+		Sync pulse		96		3.8133068520357		275
+		Back porch		48		1.9066534260179		137
+		Whole line		800		31.777557100298		2288
+		Sync + bp		144		5.7199602780536		412
 	
 	*/
 
-	TimerPeriod = 2231;//2287;
-	Channel1Pulse = 274;		/* HSYNC */
-	Channel2Pulse = 411; 		/* HSYNC + BACK PORCH */
+	TimerPeriod = 2288;//2303;
+	Channel1Pulse = 275;//274;//274;//277;		/* HSYNC */
+	Channel3Pulse = 412;//412;//394;
 	
 	TIM1->CR1 &= ~TIM_CR1_CEN;
+	
 	TIM1->PSC=0;
 	TIM1->ARR=TimerPeriod;
 	TIM1->CNT=0;
 	
-	// disable Capture and Compare 1 and 2
-	TIM1->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+	// disable Capture and Compare
+	TIM1->CCER &= ~(TIM_CCER_CC1E);
 	// set output compare 1 to PWM mode with preload
 	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)) | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
-	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S)) | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2CE;
 	TIM1->CCR1=Channel1Pulse;
-	TIM1->CCR2=Channel2Pulse;
-//	TIM1->CCR3=Channel2Pulse+100;
-	//TIM1->CCR2 |= TIM_CR2_OIS1; // output idle state set
-//	TIM1->CCR3 |= TIM_CR2_OIS1; 
 	// enable Capture and Compare 1
-	TIM1->CCER |=  TIM_CCER_CC1E |  TIM_CCER_CC2E  | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
+	TIM1->CCER |=  TIM_CCER_CC1E | TIM_CCER_CC1P ; // output polarity low
 	// main output enable
     TIM1->BDTR |= TIM_BDTR_MOE; 
 	
-	TIM1->SMCR |= TIM_SMCR_MSM; // master slave mode
-	
-	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (3<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
+	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (2<<4); // TIM_TRGOSource_Update mode
 	
 	TIM8->CR1 &= ~TIM_CR1_CEN;
-	TIM8->CR1 |= TIM_CR1_ARPE;
+	TIM8->CR1 |= TIM_CR1_ARPE | TIM_CR1_URS;
 	TIM8->PSC=0;
 	TIM8->ARR=8;
 	TIM8->CNT=0;
-	//TIM16->CR1 |= TIM_CR1_OPM; 
 	
 	TIM8->DIER |= TIM_DIER_UDE;
-	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 4;//TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | 4 ; // reset mode from tim1
-	//TIM16->SMCR |= TIM_SMCR_MSM;
-	//TIM16->CR2 = (TIM16->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1;// TIM_TRGOSource_Update mode
+	
+	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 | (3<<4); // trigger mode from itr3 (tim3)
 	
+	TIM3->CR1 &= ~TIM_CR1_CEN;
+	TIM3->PSC=0;
+	TIM3->ARR=Channel3Pulse;
+	TIM3->CNT=0;
+	TIM3->CR1 |= TIM_CR1_ARPE | TIM_CR1_URS;
+	TIM3->CR1 |= TIM_CR1_OPM; 
+	TIM3->SMCR=TIM3->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 ; // trigger mode from itr0 (tim1)
+	TIM3->CR2 = (TIM3->CR2 & ~TIM_CR2_MMS) | (2<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
+
 	/*
 		Vertical timing
 		---------------
 		
-		Polarity of vertical sync pulse is positive.
+		Polarity of vertical sync pulse is negative.
 
 						Lines
 		------------------------------
-		Visible area	600
-		Front porch		1
+		Visible area	480
+		Front porch		10
 		Sync pulse		2
-		Back porch		22
-		Whole frame		625
+		Back porch		33
+		Whole frame		525
 		
 	*/
 
 	/* VSYNC (TIM2_CH2) and VSYNC_BACKPORCH (TIM2_CH3) */
 	/* Channel 2 and 3 Configuration in PWM mode */
-	//TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0 (tim1)
-	//TIM2->CR2 |= TIM_CR2_MMS_0; // enable
-//	int rate=36000000;
+	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0
+	
+	
 	TimerPeriod = 525;		/* Vertical lines */
 	Channel2Pulse = 2;		/* Sync pulse */
 	Channel3Pulse = 35;		/* Sync pulse + Back porch */
 
 	TIM2->CR1 &= ~TIM_CR1_CEN;
-	TIM2->PSC=2286;//1143; // 72MHz/1144=31.468KHz 
+	TIM2->PSC=0;
 	TIM2->ARR=TimerPeriod;
 	TIM2->CNT=0;
 
-	TIM2->CR2 |= TIM_CR2_MMS_1; // master mode: TRGO is an update
 	// disable Capture and Compare 2 and 3
 	TIM2->CCER &= ~(TIM_CCER_CC2E | TIM_CCER_CC3E);
 	// set output compare 1 to PWM mode with preload
@@ -201,9 +191,6 @@
 	TIM2->CCR2=Channel2Pulse;
 	TIM2->CCR3=Channel3Pulse;
 	
-	
-	
-//	TIM2->CCR2 |= TIM_CR2_OIS1; // output idle state set
 	// enable Capture and Compare 2 and 3
 	TIM2->CCER |=  TIM_CCER_CC2E |  TIM_CCER_CC3E | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
 	
@@ -214,35 +201,30 @@
 	NVIC->ISER[TIM2_IRQn >> 0x05] = 1 << (TIM2_IRQn & 0x1F); // Interrupt enable
 	
 	TIM2->DIER |= TIM_DIER_CC3IE;
-	
-	NVIC->IP[TIM1_CC_IRQn]=0; // Interrupt Priority, lower is higher priority
-	NVIC->ISER[TIM1_CC_IRQn >> 0x05] = 1 << (TIM1_CC_IRQn & 0x1F); // Interrupt enable
-
-	TIM1->DIER |= TIM_DIER_CC2IE;
 
 	TIM2->CR1 |= TIM_CR1_CEN;
 	TIM1->CR1 |= TIM_CR1_CEN;
 }
 
-void DMA_Configuration(void) {
-	//gpio_set_af(GPIOA,7,5,GPIO_OUTPUT_PUSH_PULL, GPIO_NO_PULL, GPIO_SPEED_HIGH);
-	
-	GPIOD->PUPDR = (GPIOD->PUPDR & ~0xffff) | 0;//xaaaa; // pull down (1010)
-	GPIOD->OSPEEDR = (GPIOD->OSPEEDR & ~(0xffff)) | 0xffff;
-	
+void DMA_Configuration(void) {	
+	RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN;
+	RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM8EN ;
+	RCC->AHBENR |= RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIODEN;
+
+	GPIOD->MODER = (GPIOD->MODER&0xffff0000) | 0x5555; // output mode for PD0-7
+	GPIOD->PUPDR = (GPIOD->PUPDR & ~0xffff);// | 0xaaaa; // pull down (1010)
+//	GPIOD->OTYPER |= 0x8;
+	GPIOD->OSPEEDR = (GPIOD->OSPEEDR & ~0xffff) | 0xffff;
 	
 	RCC->AHBENR |= RCC_AHBENR_DMA2EN;
     // direction = peripheral dest, memory inc, peripheral size=halfword, memory size=byte, priority level=high, transmission complete interrupt enabled
     DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;
-//    DMA1_Channel3->CCR =  DMA_CCR_PINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_MEM2MEM;
     // bytes to transfer
-    DMA2_Channel1->CNDTR = HTOTAL*2;
+    DMA2_Channel1->CNDTR = HTOTAL;
     // peripheral address
     DMA2_Channel1->CPAR =(uint32_t) &GPIOD->ODR;
     // memory address
     DMA2_Channel1->CMAR =(u32) fba+fboffset;
-    // enable CC DMA for TIM16
-   // TIM16->DIER |= TIM_DIER_CC1DE;
 	// configure NVIC
     NVIC->IP[DMA2_Channel1_IRQn]=16; // Interrupt Priority, lower is higher priority
 	NVIC->ISER[DMA2_Channel1_IRQn >> 0x05] = 1 << (DMA2_Channel1_IRQn & 0x1F); // Interrupt enable
@@ -250,39 +232,21 @@
 }
 
 //*****************************************************************************
-//	This irq is generated at the end of the horizontal back porch.
-//	Test if inside a valid vertical start frame (vflag variable), 
-//	and start the DMA to output a single frame buffer line through the GPIO device.
-//*****************************************************************************
-//__attribute__((interrupt)) 
-int hlines=0,dlines=0;
-__attribute__ ((section ("ccmram"))) void TIM1_CC_IRQHandler(void) {
-	if (vflag) {
-		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// 0x3093;
-//		TIM8->CNT=0;//TIM8->ARR;
-		
-		TIM8->CR1 |= TIM_CR1_CEN;
-		//TIM8->CNT=7;//4-(TIM1->CNT&7);
-		hlines++;
-	}
-	TIM1->SR = 0xFFFB; //~TIM_IT_CC2;
-}
-
-//*****************************************************************************
 //	This irq is generated at the end of the vertical back porch.
 //	Sets the 'vflag' variable to 1 (valid vertical frame).
 //*****************************************************************************
-//__attribute__((interrupt)) 
-extern int sysTicks;
+
+uint32_t dummy=0;
 __attribute__ ((section ("ccmram"))) void TIM2_IRQHandler(void) {
 	vflag = 1;
 	TIM2->SR = 0xFFF7; //~TIM_IT_CC3;
-		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
-	//	TIM8->CNT=0;
-	//	TIM8->CR1 |= TIM_CR1_CEN;
-		printf("%d %d %d\n",sysTicks,hlines,dlines);
-		hlines=0;
-		dlines=0;
+	TIM8->CR1 &= ~TIM_CR1_CEN;
+	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE ;
+	DMA2_Channel1->CNDTR = HTOTAL;
+	TIM8->CNT=0;
+	DMA2_Channel1->CPAR=(uint32_t)&dummy;//(uint32_t) &GPIOD->ODR+1;
+	GPIOD->ODR=0x00;
+	DMA2_Channel1->CCR = DMA_CCR_DIR  | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// | DMA_CCR_CIRC;
 }
 
 //*****************************************************************************
@@ -290,39 +254,43 @@
 //	It will increment the line number and set the corresponding line pointer
 //	in the DMA register.
 //*****************************************************************************
-//__attribute__((interrupt)) 
+
 __attribute__ ((section ("ccmram"))) void DMA2_Channel1_IRQHandler(void) {	
 	DMA2->IFCR = DMA_ISR_TCIF1;
 	TIM8->CR1 &= ~TIM_CR1_CEN;
 	TIM8->CNT=0;
-	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;// | DMA_CCR_EN;// 0x3093; 0x92;// | (1<<10) | (1<<8);
+	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;
 	DMA2_Channel1->CNDTR = HTOTAL;
-	dlines++;
-	
+	DMA2_Channel1->CPAR=(uint32_t) &GPIOD->ODR;;
 	vdraw++;
-	if (vdraw == 4) {
+	if (vdraw == 3) {
 		vdraw = 0;
 		vline++;
 		if (vline == VID_VSIZE) {
 			vdraw = vline = vflag = 0;
-			DMA2_Channel1->CMAR = (u32) fba+fboffset;
+			DMA2_Channel1->CMAR = (u32)fba;
+			DMA2_Channel1->CPAR=(uint32_t)&dummy;
+			GPIOD->ODR=0x00;
 		} else {
 			DMA2_Channel1->CMAR += HTOTAL;
 		}
 	}
-//	if(vflag)
-//		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
+	if(vflag)
+		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
+	
 	
 }
+
 __attribute__ ((section ("ccmram"))) void vidNextBuffer(void) {
-	    char *fp=(unsigned *)fb[0];
-	    for(int i=0;i<VID_VSIZE*HTOTAL;i++)
-	    	*fp++=(*fp>>4);//&0xf0f0f0f;
+	    unsigned *fp=(unsigned *)fba;
+	    for(int i=0;i<VID_VSIZE*HTOTAL/4;i++)
+	    	*fp++=(*fp>>4)&0xf0f0f0f;
 }
 
 __attribute__ ((section ("ccmram"))) void waitForRefresh(void) {
 	while(vflag) __wfi();
 }
+
 void vidClearScreen(void) {
 	u16 x, y;
 
@@ -346,7 +314,7 @@
 	DMA_Configuration();
 	TIMER_Configuration();
 	for(i=0;i<VID_VSIZE;i++)
-		fb[i]=fba+i*HTOTAL;
+		fb[i]=fba+i*HTOTAL+2;
 	vidClearScreen();
 }