Diff: AD7190.h

Revision:

0:49fe1d7a6628

Child:

1:00d6e45e037a

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/AD7190.h	Tue Jan 28 09:42:48 2014 +0000
@@ -0,0 +1,152 @@
+/***************************************************************************//**
+ * @file   AD7190.cpp
+ * @brief  Header of the AD7190 driver.
+ * @author Mario Poneder
+ * @date   28/01/2013
+ *
+ * This class is based on the implementation from Dan Nechita (Analog Devices).
+*******************************************************************************/
+
+#ifndef __AD7190_H__
+#define __AD7190_H__
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "mbed.h"
+
+/******************************************************************************/
+/******************************** AD7190 **************************************/
+/******************************************************************************/
+
+/* AD7190 Register Map */
+#define REG_COMM        0   // Communications Register (WO, 8-bit) 
+#define REG_STAT        0   // Status Register         (RO, 8-bit) 
+#define REG_MODE        1   // Mode Register           (RW, 24-bit 
+#define REG_CONF        2   // Configuration Register  (RW, 24-bit)
+#define REG_DATA        3   // Data Register           (RO, 24/32-bit) 
+#define REG_ID          4   // ID Register             (RO, 8-bit) 
+#define REG_GPOCON      5   // GPOCON Register         (RW, 8-bit) 
+#define REG_OFFSET      6   // Offset Register         (RW, 24-bit 
+#define REG_FULLSCALE   7   // Full-Scale Register     (RW, 24-bit)
+
+/* Communications Register Bit Designations (REG_COMM) */
+#define COMM_WEN        (1 << 7)            // Write Enable. 
+#define COMM_WRITE      (0 << 6)            // Write Operation.
+#define COMM_READ       (1 << 6)            // Read Operation. 
+#define COMM_ADDR(x)    (((x) & 0x7) << 3)  // Register Address. 
+#define COMM_CREAD      (1 << 2)            // Continuous Read of Data Register.
+
+/* Status Register Bit Designations (REG_STAT) */
+#define STAT_RDY        (1 << 7)    // Ready.
+#define STAT_ERR        (1 << 6)    // ADC error bit.
+#define STAT_NOREF      (1 << 5)    // Error no external reference. 
+#define STAT_PARITY     (1 << 4)    // Parity check of the data register. 
+#define STAT_CH2        (1 << 2)    // Channel 2. 
+#define STAT_CH1        (1 << 1)    // Channel 1. 
+#define STAT_CH0        (1 << 0)    // Channel 0. 
+
+/* Mode Register Bit Designations (REG_MODE) */
+#define MODE_SEL(x)     (((x) & 0x7) << 21)     // Operation Mode Select.
+#define MODE_DAT_STA    (1 << 20)               // Status Register transmission.
+#define MODE_CLKSRC(x)  (((x) & 0x3) << 18)     // Clock Source Select.
+#define MODE_SINC3      (1 << 15)               // SINC3 Filter Select.
+#define MODE_ENPAR      (1 << 13)               // Parity Enable.
+#define MODE_SCYCLE     (1 << 11)               // Single cycle conversion.
+#define MODE_REJ60      (1 << 10)               // 50/60Hz notch filter.
+#define MODE_RATE(x)    ((x) & 0x3FF)           // Filter Update Rate Select.
+
+/* Mode Register: MODE_SEL(x) options */
+#define MODE_CONT               0   // Continuous Conversion Mode.
+#define MODE_SINGLE             1   // Single Conversion Mode.
+#define MODE_IDLE               2   // Idle Mode.
+#define MODE_PWRDN              3   // Power-Down Mode.
+#define MODE_CAL_INT_ZERO       4   // Internal Zero-Scale Calibration.
+#define MODE_CAL_INT_FULL       5   // Internal Full-Scale Calibration.
+#define MODE_CAL_SYS_ZERO       6   // System Zero-Scale Calibration.
+#define MODE_CAL_SYS_FULL       7   // System Full-Scale Calibration.
+
+/* Mode Register: MODE_CLKSRC(x) options */
+#define CLK_EXT_MCLK1_2         0   // External crystal. The external crystal
+                                    // is connected from MCLK1 to MCLK2.
+#define CLK_EXT_MCLK2           1   // External Clock applied to MCLK2 
+#define CLK_INT                 2   // Internal 4.92 MHz clock. 
+                                    // Pin MCLK2 is tristated.
+#define CLK_INT_CO              3   // Internal 4.92 MHz clock. The internal
+                                    // clock is available on MCLK2.
+
+/* Configuration Register Bit Designations (REG_CONF) */
+#define CONF_CHOP       (1 << 23)           // CHOP enable.
+#define CONF_REFSEL     (1 << 20)           // REFIN1/REFIN2 Reference Select.
+#define CONF_CHAN(x)    (((x) & 0xFF) << 8) // Channel select.
+#define CONF_BURN       (1 << 7)            // Burnout current enable.
+#define CONF_REFDET     (1 << 6)            // Reference detect enable.
+#define CONF_BUF        (1 << 4)            // Buffered Mode Enable.
+#define CONF_UNIPOLAR   (1 << 3)            // Unipolar/Bipolar Enable.
+#define CONF_GAIN(x)    ((x) & 0x7)         // Gain Select.
+
+/* Configuration Register: CONF_CHAN(x) options */
+#define CH_AIN1P_AIN2M      0   // AIN1(+) - AIN2(-)       
+#define CH_AIN3P_AIN4M      1   // AIN3(+) - AIN4(-)       
+#define CH_TEMP_SENSOR      2   // Temperature sensor       
+#define CH_AIN2P_AIN2M      3   // AIN2(+) - AIN2(-)       
+#define CH_AIN1P_AINCOM     4   // AIN1(+) - AINCOM       
+#define CH_AIN2P_AINCOM     5   // AIN2(+) - AINCOM       
+#define CH_AIN3P_AINCOM     6   // AIN3(+) - AINCOM       
+#define CH_AIN4P_AINCOM     7   // AIN4(+) - AINCOM
+
+/* Configuration Register: CONF_GAIN(x) options */
+                                // ADC Input Range (5 V Reference)
+#define CONF_GAIN_1         0   // Gain 1    +-5 V
+#define CONF_GAIN_8         3   // Gain 8    +-625 mV
+#define CONF_GAIN_16        4   // Gain 16   +-312.5 mV
+#define CONF_GAIN_32        5   // Gain 32   +-156.2 mV
+#define CONF_GAIN_64        6   // Gain 64   +-78.125 mV
+#define CONF_GAIN_128       7   // Gain 128  +-39.06 mV
+
+/* ID Register Bit Designations (REG_ID) */
+#define ID_AD7190           0x4
+#define ID_MASK             0x0F
+
+/* GPOCON Register Bit Designations (REG_GPOCON) */
+#define GPOCON_BPDSW        (1 << 6)    // Bridge power-down switch enable
+#define GPOCON_GP32EN       (1 << 5)    // Digital Output P3 and P2 enable
+#define GPOCON_GP10EN       (1 << 4)    // Digital Output P1 and P0 enable
+#define GPOCON_P3DAT        (1 << 3)    // P3 state
+#define GPOCON_P2DAT        (1 << 2)    // P2 state
+#define GPOCON_P1DAT        (1 << 1)    // P1 state
+#define GPOCON_P0DAT        (1 << 0)    // P0 state
+
+/***************************************************************************//**
+ * @brief Specifies the prototype of the sample callback function.
+ *        Example:
+ *          void SampleCallback(unsigned long data, unsigned char channel);
+*******************************************************************************/
+typedef void (*pSampleCallback_t)(unsigned long, unsigned char);
+
+class AD7190
+{
+private:
+    
+    DigitalIn   _rdy;       // Ready input pin (DOUT/RDY)
+    InterruptIn _rdyInt;    // Ready interrupt input pin (DOUT/RDY)
+    SPI         _spi;       // MOSI -> DIN, MISO <- DOUT/RDY , SCLK -> SCLK
+    
+    pSampleCallback_t sampleCallbackFunction;
+    
+    void SampleInterrupt(void);
+    
+public:
+
+    AD7190(PinName rdy, PinName mosi, PinName miso, PinName sclk);
+
+    void StartContinuousRead(pSampleCallback_t sampleCallbackFunction);
+    void StopContinuousRead(void);
+    void SetRegisterValue(unsigned char registerAddress, unsigned long registerValue);
+    unsigned long GetRegisterValue(unsigned char registerAddress);
+    bool Init(void);
+    void Reset(void);
+    void WaitRdyGoLow(void);
+};
+
+#endif /* __AD7190_H__ */