Toyomasa Watarai
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mbed-dev-lpcx1769
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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG_STK3401/efm32pg1b_emu.h@50:a417edff4437, 2016-01-15 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jan 15 07:45:16 2016 +0000
- Revision:
- 50:a417edff4437
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9
Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/
Remove doubling of buffer size in realiseEndpoint()
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 50:a417edff4437 | 1 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 2 | * @file efm32pg1b_emu.h |
| mbed_official | 50:a417edff4437 | 3 | * @brief EFM32PG1B_EMU register and bit field definitions |
| mbed_official | 50:a417edff4437 | 4 | * @version 4.2.0 |
| mbed_official | 50:a417edff4437 | 5 | ****************************************************************************** |
| mbed_official | 50:a417edff4437 | 6 | * @section License |
| mbed_official | 50:a417edff4437 | 7 | * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 50:a417edff4437 | 8 | ****************************************************************************** |
| mbed_official | 50:a417edff4437 | 9 | * |
| mbed_official | 50:a417edff4437 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 50:a417edff4437 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 50:a417edff4437 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 50:a417edff4437 | 13 | * |
| mbed_official | 50:a417edff4437 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 50:a417edff4437 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 50:a417edff4437 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 50:a417edff4437 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 50:a417edff4437 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 50:a417edff4437 | 19 | * |
| mbed_official | 50:a417edff4437 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 50:a417edff4437 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 50:a417edff4437 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 50:a417edff4437 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 50:a417edff4437 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 50:a417edff4437 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 50:a417edff4437 | 26 | * |
| mbed_official | 50:a417edff4437 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 50:a417edff4437 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 50:a417edff4437 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 50:a417edff4437 | 30 | * |
| mbed_official | 50:a417edff4437 | 31 | *****************************************************************************/ |
| mbed_official | 50:a417edff4437 | 32 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 33 | * @addtogroup Parts |
| mbed_official | 50:a417edff4437 | 34 | * @{ |
| mbed_official | 50:a417edff4437 | 35 | ******************************************************************************/ |
| mbed_official | 50:a417edff4437 | 36 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 37 | * @defgroup EFM32PG1B_EMU |
| mbed_official | 50:a417edff4437 | 38 | * @{ |
| mbed_official | 50:a417edff4437 | 39 | * @brief EFM32PG1B_EMU Register Declaration |
| mbed_official | 50:a417edff4437 | 40 | *****************************************************************************/ |
| mbed_official | 50:a417edff4437 | 41 | typedef struct |
| mbed_official | 50:a417edff4437 | 42 | { |
| mbed_official | 50:a417edff4437 | 43 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 50:a417edff4437 | 44 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 50:a417edff4437 | 45 | __IO uint32_t LOCK; /**< Configuration Lock Register */ |
| mbed_official | 50:a417edff4437 | 46 | __IO uint32_t RAM0CTRL; /**< Memory Control Register */ |
| mbed_official | 50:a417edff4437 | 47 | __IO uint32_t CMD; /**< Command Register */ |
| mbed_official | 50:a417edff4437 | 48 | __IO uint32_t PERACTCONF; /**< Peripheral to Peripheral Activation Clock Configuration */ |
| mbed_official | 50:a417edff4437 | 49 | __IO uint32_t EM4CTRL; /**< EM4 Control Register */ |
| mbed_official | 50:a417edff4437 | 50 | __IO uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ |
| mbed_official | 50:a417edff4437 | 51 | __I uint32_t TEMP; /**< Value of last temperature measurement */ |
| mbed_official | 50:a417edff4437 | 52 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 50:a417edff4437 | 53 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 50:a417edff4437 | 54 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 50:a417edff4437 | 55 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 50:a417edff4437 | 56 | __IO uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ |
| mbed_official | 50:a417edff4437 | 57 | __IO uint32_t PWRCFG; /**< Power Configuration Register. */ |
| mbed_official | 50:a417edff4437 | 58 | __IO uint32_t PWRCTRL; /**< Power Control Register. */ |
| mbed_official | 50:a417edff4437 | 59 | __IO uint32_t DCDCCTRL; /**< DCDC Control */ |
| mbed_official | 50:a417edff4437 | 60 | |
| mbed_official | 50:a417edff4437 | 61 | uint32_t RESERVED0[2]; /**< Reserved for future use **/ |
| mbed_official | 50:a417edff4437 | 62 | __IO uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ |
| mbed_official | 50:a417edff4437 | 63 | __IO uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ |
| mbed_official | 50:a417edff4437 | 64 | __IO uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ |
| mbed_official | 50:a417edff4437 | 65 | |
| mbed_official | 50:a417edff4437 | 66 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
| mbed_official | 50:a417edff4437 | 67 | __IO uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ |
| mbed_official | 50:a417edff4437 | 68 | __IO uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */ |
| mbed_official | 50:a417edff4437 | 69 | __IO uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ |
| mbed_official | 50:a417edff4437 | 70 | |
| mbed_official | 50:a417edff4437 | 71 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| mbed_official | 50:a417edff4437 | 72 | __IO uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ |
| mbed_official | 50:a417edff4437 | 73 | __IO uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ |
| mbed_official | 50:a417edff4437 | 74 | |
| mbed_official | 50:a417edff4437 | 75 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
| mbed_official | 50:a417edff4437 | 76 | __I uint32_t DCDCSYNC; /**< DCDC Read Status Register */ |
| mbed_official | 50:a417edff4437 | 77 | |
| mbed_official | 50:a417edff4437 | 78 | uint32_t RESERVED4[5]; /**< Reserved for future use **/ |
| mbed_official | 50:a417edff4437 | 79 | __IO uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ |
| mbed_official | 50:a417edff4437 | 80 | __IO uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ |
| mbed_official | 50:a417edff4437 | 81 | __IO uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ |
| mbed_official | 50:a417edff4437 | 82 | __IO uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ |
| mbed_official | 50:a417edff4437 | 83 | } EMU_TypeDef; /** @} */ |
| mbed_official | 50:a417edff4437 | 84 | |
| mbed_official | 50:a417edff4437 | 85 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 86 | * @defgroup EFM32PG1B_EMU_BitFields |
| mbed_official | 50:a417edff4437 | 87 | * @{ |
| mbed_official | 50:a417edff4437 | 88 | *****************************************************************************/ |
| mbed_official | 50:a417edff4437 | 89 | |
| mbed_official | 50:a417edff4437 | 90 | /* Bit fields for EMU CTRL */ |
| mbed_official | 50:a417edff4437 | 91 | #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ |
| mbed_official | 50:a417edff4437 | 92 | #define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */ |
| mbed_official | 50:a417edff4437 | 93 | #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ |
| mbed_official | 50:a417edff4437 | 94 | #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ |
| mbed_official | 50:a417edff4437 | 95 | #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ |
| mbed_official | 50:a417edff4437 | 96 | #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| mbed_official | 50:a417edff4437 | 97 | #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| mbed_official | 50:a417edff4437 | 98 | |
| mbed_official | 50:a417edff4437 | 99 | /* Bit fields for EMU STATUS */ |
| mbed_official | 50:a417edff4437 | 100 | #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 101 | #define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 102 | #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ |
| mbed_official | 50:a417edff4437 | 103 | #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ |
| mbed_official | 50:a417edff4437 | 104 | #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ |
| mbed_official | 50:a417edff4437 | 105 | #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 106 | #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 107 | #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ |
| mbed_official | 50:a417edff4437 | 108 | #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ |
| mbed_official | 50:a417edff4437 | 109 | #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ |
| mbed_official | 50:a417edff4437 | 110 | #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 111 | #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 112 | #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ |
| mbed_official | 50:a417edff4437 | 113 | #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ |
| mbed_official | 50:a417edff4437 | 114 | #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ |
| mbed_official | 50:a417edff4437 | 115 | #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 116 | #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 117 | #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ |
| mbed_official | 50:a417edff4437 | 118 | #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ |
| mbed_official | 50:a417edff4437 | 119 | #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ |
| mbed_official | 50:a417edff4437 | 120 | #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 121 | #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 122 | #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ |
| mbed_official | 50:a417edff4437 | 123 | #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ |
| mbed_official | 50:a417edff4437 | 124 | #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ |
| mbed_official | 50:a417edff4437 | 125 | #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 126 | #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 127 | #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ |
| mbed_official | 50:a417edff4437 | 128 | #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ |
| mbed_official | 50:a417edff4437 | 129 | #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ |
| mbed_official | 50:a417edff4437 | 130 | #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 131 | #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 132 | #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ |
| mbed_official | 50:a417edff4437 | 133 | #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ |
| mbed_official | 50:a417edff4437 | 134 | #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ |
| mbed_official | 50:a417edff4437 | 135 | #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 136 | #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 137 | #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 138 | #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 139 | #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 140 | #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ |
| mbed_official | 50:a417edff4437 | 141 | |
| mbed_official | 50:a417edff4437 | 142 | /* Bit fields for EMU LOCK */ |
| mbed_official | 50:a417edff4437 | 143 | #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 144 | #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 145 | #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ |
| mbed_official | 50:a417edff4437 | 146 | #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ |
| mbed_official | 50:a417edff4437 | 147 | #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 148 | #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 149 | #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 150 | #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 151 | #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 152 | #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 153 | #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 154 | #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 155 | #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 156 | #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ |
| mbed_official | 50:a417edff4437 | 157 | |
| mbed_official | 50:a417edff4437 | 158 | /* Bit fields for EMU RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 159 | #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 160 | #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 161 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ |
| mbed_official | 50:a417edff4437 | 162 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ |
| mbed_official | 50:a417edff4437 | 163 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 164 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 165 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 166 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 167 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 168 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 169 | #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 170 | #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 171 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 172 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 173 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 174 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ |
| mbed_official | 50:a417edff4437 | 175 | |
| mbed_official | 50:a417edff4437 | 176 | /* Bit fields for EMU CMD */ |
| mbed_official | 50:a417edff4437 | 177 | #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ |
| mbed_official | 50:a417edff4437 | 178 | #define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */ |
| mbed_official | 50:a417edff4437 | 179 | #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ |
| mbed_official | 50:a417edff4437 | 180 | #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ |
| mbed_official | 50:a417edff4437 | 181 | #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ |
| mbed_official | 50:a417edff4437 | 182 | #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ |
| mbed_official | 50:a417edff4437 | 183 | #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ |
| mbed_official | 50:a417edff4437 | 184 | |
| mbed_official | 50:a417edff4437 | 185 | /* Bit fields for EMU PERACTCONF */ |
| mbed_official | 50:a417edff4437 | 186 | #define _EMU_PERACTCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PERACTCONF */ |
| mbed_official | 50:a417edff4437 | 187 | #define _EMU_PERACTCONF_MASK 0x00000001UL /**< Mask for EMU_PERACTCONF */ |
| mbed_official | 50:a417edff4437 | 188 | #define EMU_PERACTCONF_RACPER (0x1UL << 0) /**< Enable PER clock when RAC is activated */ |
| mbed_official | 50:a417edff4437 | 189 | #define _EMU_PERACTCONF_RACPER_SHIFT 0 /**< Shift value for EMU_RACPER */ |
| mbed_official | 50:a417edff4437 | 190 | #define _EMU_PERACTCONF_RACPER_MASK 0x1UL /**< Bit mask for EMU_RACPER */ |
| mbed_official | 50:a417edff4437 | 191 | #define _EMU_PERACTCONF_RACPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PERACTCONF */ |
| mbed_official | 50:a417edff4437 | 192 | #define EMU_PERACTCONF_RACPER_DEFAULT (_EMU_PERACTCONF_RACPER_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PERACTCONF */ |
| mbed_official | 50:a417edff4437 | 193 | |
| mbed_official | 50:a417edff4437 | 194 | /* Bit fields for EMU EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 195 | #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 196 | #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 197 | #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ |
| mbed_official | 50:a417edff4437 | 198 | #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ |
| mbed_official | 50:a417edff4437 | 199 | #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ |
| mbed_official | 50:a417edff4437 | 200 | #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 201 | #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 202 | #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 203 | #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 204 | #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 205 | #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 206 | #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ |
| mbed_official | 50:a417edff4437 | 207 | #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ |
| mbed_official | 50:a417edff4437 | 208 | #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ |
| mbed_official | 50:a417edff4437 | 209 | #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 210 | #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 211 | #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ |
| mbed_official | 50:a417edff4437 | 212 | #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ |
| mbed_official | 50:a417edff4437 | 213 | #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ |
| mbed_official | 50:a417edff4437 | 214 | #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 215 | #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 216 | #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ |
| mbed_official | 50:a417edff4437 | 217 | #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ |
| mbed_official | 50:a417edff4437 | 218 | #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ |
| mbed_official | 50:a417edff4437 | 219 | #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 220 | #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 221 | #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ |
| mbed_official | 50:a417edff4437 | 222 | #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ |
| mbed_official | 50:a417edff4437 | 223 | #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 224 | #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 225 | #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 226 | #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 227 | #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 228 | #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 229 | #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 230 | #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 231 | #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ |
| mbed_official | 50:a417edff4437 | 232 | #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ |
| mbed_official | 50:a417edff4437 | 233 | #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 234 | #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| mbed_official | 50:a417edff4437 | 235 | |
| mbed_official | 50:a417edff4437 | 236 | /* Bit fields for EMU TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 237 | #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 238 | #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 239 | #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 240 | #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 241 | #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 242 | #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 243 | #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 244 | #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 245 | #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 246 | #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 247 | #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temerature */ |
| mbed_official | 50:a417edff4437 | 248 | #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ |
| mbed_official | 50:a417edff4437 | 249 | #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ |
| mbed_official | 50:a417edff4437 | 250 | #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 251 | #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| mbed_official | 50:a417edff4437 | 252 | |
| mbed_official | 50:a417edff4437 | 253 | /* Bit fields for EMU TEMP */ |
| mbed_official | 50:a417edff4437 | 254 | #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 255 | #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 256 | #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 257 | #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 258 | #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 259 | #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 260 | |
| mbed_official | 50:a417edff4437 | 261 | /* Bit fields for EMU IF */ |
| mbed_official | 50:a417edff4437 | 262 | #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 263 | #define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 264 | #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ |
| mbed_official | 50:a417edff4437 | 265 | #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 266 | #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 267 | #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 268 | #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 269 | #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ |
| mbed_official | 50:a417edff4437 | 270 | #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 271 | #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 272 | #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 273 | #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 274 | #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ |
| mbed_official | 50:a417edff4437 | 275 | #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 276 | #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 277 | #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 278 | #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 279 | #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ |
| mbed_official | 50:a417edff4437 | 280 | #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 281 | #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 282 | #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 283 | #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 284 | #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ |
| mbed_official | 50:a417edff4437 | 285 | #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 286 | #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 287 | #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 288 | #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 289 | #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ |
| mbed_official | 50:a417edff4437 | 290 | #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 291 | #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 292 | #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 293 | #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 294 | #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ |
| mbed_official | 50:a417edff4437 | 295 | #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 296 | #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 297 | #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 298 | #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 299 | #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ |
| mbed_official | 50:a417edff4437 | 300 | #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 301 | #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 302 | #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 303 | #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 304 | #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ |
| mbed_official | 50:a417edff4437 | 305 | #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 306 | #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 307 | #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 308 | #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 309 | #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ |
| mbed_official | 50:a417edff4437 | 310 | #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 311 | #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 312 | #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 313 | #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 314 | #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ |
| mbed_official | 50:a417edff4437 | 315 | #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 316 | #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 317 | #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 318 | #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 319 | #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ |
| mbed_official | 50:a417edff4437 | 320 | #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 321 | #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 322 | #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 323 | #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 324 | #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ |
| mbed_official | 50:a417edff4437 | 325 | #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 326 | #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 327 | #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 328 | #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 329 | #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ |
| mbed_official | 50:a417edff4437 | 330 | #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 331 | #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 332 | #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 333 | #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 334 | #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ |
| mbed_official | 50:a417edff4437 | 335 | #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 336 | #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 337 | #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 338 | #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 339 | #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ |
| mbed_official | 50:a417edff4437 | 340 | #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 341 | #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 342 | #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 343 | #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 344 | #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ |
| mbed_official | 50:a417edff4437 | 345 | #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 346 | #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 347 | #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 348 | #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 349 | #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ |
| mbed_official | 50:a417edff4437 | 350 | #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 351 | #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 352 | #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 353 | #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 354 | #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ |
| mbed_official | 50:a417edff4437 | 355 | #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 356 | #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 357 | #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 358 | #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 50:a417edff4437 | 359 | |
| mbed_official | 50:a417edff4437 | 360 | /* Bit fields for EMU IFS */ |
| mbed_official | 50:a417edff4437 | 361 | #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 362 | #define _EMU_IFS_MASK 0xE11FF0FFUL /**< Mask for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 363 | #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 364 | #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 365 | #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 366 | #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 367 | #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 368 | #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 369 | #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 370 | #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 371 | #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 372 | #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 373 | #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 374 | #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 375 | #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 376 | #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 377 | #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 378 | #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 379 | #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 380 | #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 381 | #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 382 | #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 383 | #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 384 | #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 385 | #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 386 | #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 387 | #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 388 | #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 389 | #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 390 | #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 391 | #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 392 | #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 393 | #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 394 | #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 395 | #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 396 | #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 397 | #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 398 | #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 399 | #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 400 | #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 401 | #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 402 | #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 403 | #define EMU_IFS_VMONPAVDDFALL (0x1UL << 12) /**< Set VMONPAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 404 | #define _EMU_IFS_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 405 | #define _EMU_IFS_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 406 | #define _EMU_IFS_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 407 | #define EMU_IFS_VMONPAVDDFALL_DEFAULT (_EMU_IFS_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 408 | #define EMU_IFS_VMONPAVDDRISE (0x1UL << 13) /**< Set VMONPAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 409 | #define _EMU_IFS_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 410 | #define _EMU_IFS_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 411 | #define _EMU_IFS_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 412 | #define EMU_IFS_VMONPAVDDRISE_DEFAULT (_EMU_IFS_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 413 | #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 414 | #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 415 | #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 416 | #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 417 | #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 418 | #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 419 | #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 420 | #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 421 | #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 422 | #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 423 | #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 424 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 425 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 426 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 427 | #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 428 | #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 429 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 430 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 431 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 432 | #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 433 | #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 434 | #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 435 | #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 436 | #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 437 | #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 438 | #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 439 | #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 440 | #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 441 | #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 442 | #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 443 | #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 444 | #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 445 | #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 446 | #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 447 | #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 448 | #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 449 | #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 450 | #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 451 | #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 452 | #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 453 | #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 454 | #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 455 | #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 456 | #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 457 | #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 458 | #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 459 | #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 460 | #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 461 | #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 462 | #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 463 | #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 464 | #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 465 | #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 466 | #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 467 | #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 50:a417edff4437 | 468 | |
| mbed_official | 50:a417edff4437 | 469 | /* Bit fields for EMU IFC */ |
| mbed_official | 50:a417edff4437 | 470 | #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 471 | #define _EMU_IFC_MASK 0xE11FF0FFUL /**< Mask for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 472 | #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 473 | #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 474 | #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 475 | #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 476 | #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 477 | #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 478 | #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 479 | #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 480 | #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 481 | #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 482 | #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 483 | #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 484 | #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 485 | #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 486 | #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 487 | #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 488 | #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 489 | #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 490 | #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 491 | #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 492 | #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 493 | #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 494 | #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 495 | #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 496 | #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 497 | #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 498 | #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 499 | #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 500 | #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 501 | #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 502 | #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 503 | #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 504 | #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 505 | #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 506 | #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 507 | #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 508 | #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 509 | #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 510 | #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 511 | #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 512 | #define EMU_IFC_VMONPAVDDFALL (0x1UL << 12) /**< Clear VMONPAVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 513 | #define _EMU_IFC_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 514 | #define _EMU_IFC_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 515 | #define _EMU_IFC_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 516 | #define EMU_IFC_VMONPAVDDFALL_DEFAULT (_EMU_IFC_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 517 | #define EMU_IFC_VMONPAVDDRISE (0x1UL << 13) /**< Clear VMONPAVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 518 | #define _EMU_IFC_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 519 | #define _EMU_IFC_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 520 | #define _EMU_IFC_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 521 | #define EMU_IFC_VMONPAVDDRISE_DEFAULT (_EMU_IFC_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 522 | #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 523 | #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 524 | #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 525 | #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 526 | #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 527 | #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 528 | #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 529 | #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 530 | #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 531 | #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 532 | #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 533 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 534 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 535 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 536 | #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 537 | #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 538 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 539 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 540 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 541 | #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 542 | #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 543 | #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 544 | #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 545 | #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 546 | #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 547 | #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 548 | #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 549 | #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 550 | #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 551 | #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 552 | #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 553 | #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 554 | #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 555 | #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 556 | #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 557 | #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 558 | #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 559 | #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 560 | #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 561 | #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 562 | #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 563 | #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 564 | #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 565 | #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 566 | #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 567 | #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 568 | #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 569 | #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 570 | #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 571 | #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 572 | #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ |
| mbed_official | 50:a417edff4437 | 573 | #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 574 | #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 575 | #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 576 | #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 50:a417edff4437 | 577 | |
| mbed_official | 50:a417edff4437 | 578 | /* Bit fields for EMU IEN */ |
| mbed_official | 50:a417edff4437 | 579 | #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 580 | #define _EMU_IEN_MASK 0xE11FF0FFUL /**< Mask for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 581 | #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 582 | #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 583 | #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 584 | #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 585 | #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 586 | #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 587 | #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 588 | #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 589 | #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 590 | #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 591 | #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 592 | #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 593 | #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 594 | #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 595 | #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 596 | #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 597 | #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 598 | #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 599 | #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 600 | #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 601 | #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 602 | #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 603 | #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| mbed_official | 50:a417edff4437 | 604 | #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 605 | #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 606 | #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 607 | #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 608 | #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| mbed_official | 50:a417edff4437 | 609 | #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 610 | #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 611 | #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 612 | #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 613 | #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| mbed_official | 50:a417edff4437 | 614 | #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 615 | #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 616 | #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 617 | #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 618 | #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| mbed_official | 50:a417edff4437 | 619 | #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 620 | #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 621 | #define EMU_IEN_VMONPAVDDFALL (0x1UL << 12) /**< VMONPAVDDFALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 622 | #define _EMU_IEN_VMONPAVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 623 | #define _EMU_IEN_VMONPAVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONPAVDDFALL */ |
| mbed_official | 50:a417edff4437 | 624 | #define _EMU_IEN_VMONPAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 625 | #define EMU_IEN_VMONPAVDDFALL_DEFAULT (_EMU_IEN_VMONPAVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 626 | #define EMU_IEN_VMONPAVDDRISE (0x1UL << 13) /**< VMONPAVDDRISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 627 | #define _EMU_IEN_VMONPAVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 628 | #define _EMU_IEN_VMONPAVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONPAVDDRISE */ |
| mbed_official | 50:a417edff4437 | 629 | #define _EMU_IEN_VMONPAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 630 | #define EMU_IEN_VMONPAVDDRISE_DEFAULT (_EMU_IEN_VMONPAVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 631 | #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 632 | #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 633 | #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| mbed_official | 50:a417edff4437 | 634 | #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 635 | #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 636 | #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 637 | #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 638 | #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| mbed_official | 50:a417edff4437 | 639 | #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 640 | #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 641 | #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 642 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 643 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 644 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 645 | #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 646 | #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 647 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 648 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| mbed_official | 50:a417edff4437 | 649 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 650 | #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 651 | #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 652 | #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 653 | #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| mbed_official | 50:a417edff4437 | 654 | #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 655 | #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 656 | #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 657 | #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 658 | #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| mbed_official | 50:a417edff4437 | 659 | #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 660 | #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 661 | #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 662 | #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 663 | #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| mbed_official | 50:a417edff4437 | 664 | #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 665 | #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 666 | #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 667 | #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 668 | #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| mbed_official | 50:a417edff4437 | 669 | #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 670 | #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 671 | #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 672 | #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 673 | #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| mbed_official | 50:a417edff4437 | 674 | #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 675 | #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 676 | #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 677 | #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 678 | #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| mbed_official | 50:a417edff4437 | 679 | #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 680 | #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 681 | #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ |
| mbed_official | 50:a417edff4437 | 682 | #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 683 | #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| mbed_official | 50:a417edff4437 | 684 | #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 685 | #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 50:a417edff4437 | 686 | |
| mbed_official | 50:a417edff4437 | 687 | /* Bit fields for EMU PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 688 | #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 689 | #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 690 | #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ |
| mbed_official | 50:a417edff4437 | 691 | #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ |
| mbed_official | 50:a417edff4437 | 692 | #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 693 | #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 694 | #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 695 | #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 696 | #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 697 | #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 698 | #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 699 | #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 700 | #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 701 | #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ |
| mbed_official | 50:a417edff4437 | 702 | |
| mbed_official | 50:a417edff4437 | 703 | /* Bit fields for EMU PWRCFG */ |
| mbed_official | 50:a417edff4437 | 704 | #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 705 | #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 706 | #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 707 | #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 708 | #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 709 | #define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 710 | #define _EMU_PWRCFG_PWRCFG_NODCDC 0x00000001UL /**< Mode NODCDC for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 711 | #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 712 | #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 713 | #define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 714 | #define EMU_PWRCFG_PWRCFG_NODCDC (_EMU_PWRCFG_PWRCFG_NODCDC << 0) /**< Shifted mode NODCDC for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 715 | #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ |
| mbed_official | 50:a417edff4437 | 716 | |
| mbed_official | 50:a417edff4437 | 717 | /* Bit fields for EMU PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 718 | #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 719 | #define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 720 | #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ |
| mbed_official | 50:a417edff4437 | 721 | #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ |
| mbed_official | 50:a417edff4437 | 722 | #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ |
| mbed_official | 50:a417edff4437 | 723 | #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 724 | #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 725 | #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 726 | #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 727 | #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 728 | #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ |
| mbed_official | 50:a417edff4437 | 729 | |
| mbed_official | 50:a417edff4437 | 730 | /* Bit fields for EMU DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 731 | #define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 732 | #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 733 | #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ |
| mbed_official | 50:a417edff4437 | 734 | #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ |
| mbed_official | 50:a417edff4437 | 735 | #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 736 | #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 737 | #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 738 | #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 739 | #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 740 | #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 741 | #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 742 | #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 743 | #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 744 | #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 745 | #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< Reserved for internal use. Do not change. */ |
| mbed_official | 50:a417edff4437 | 746 | #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ |
| mbed_official | 50:a417edff4437 | 747 | #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ |
| mbed_official | 50:a417edff4437 | 748 | #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 749 | #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 750 | #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< Reserved for internal use. Do not change. */ |
| mbed_official | 50:a417edff4437 | 751 | #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ |
| mbed_official | 50:a417edff4437 | 752 | #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ |
| mbed_official | 50:a417edff4437 | 753 | #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 754 | #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| mbed_official | 50:a417edff4437 | 755 | |
| mbed_official | 50:a417edff4437 | 756 | /* Bit fields for EMU DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 757 | #define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 758 | #define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 759 | #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ |
| mbed_official | 50:a417edff4437 | 760 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ |
| mbed_official | 50:a417edff4437 | 761 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ |
| mbed_official | 50:a417edff4437 | 762 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 763 | #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 764 | #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ |
| mbed_official | 50:a417edff4437 | 765 | #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ |
| mbed_official | 50:a417edff4437 | 766 | #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 767 | #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 768 | #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ |
| mbed_official | 50:a417edff4437 | 769 | #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ |
| mbed_official | 50:a417edff4437 | 770 | #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 771 | #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 772 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ |
| mbed_official | 50:a417edff4437 | 773 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ |
| mbed_official | 50:a417edff4437 | 774 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 775 | #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 776 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ |
| mbed_official | 50:a417edff4437 | 777 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ |
| mbed_official | 50:a417edff4437 | 778 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 779 | #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 780 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ |
| mbed_official | 50:a417edff4437 | 781 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ |
| mbed_official | 50:a417edff4437 | 782 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 783 | #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 784 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */ |
| mbed_official | 50:a417edff4437 | 785 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */ |
| mbed_official | 50:a417edff4437 | 786 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 787 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 788 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 789 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 790 | #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 791 | #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 792 | #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 793 | #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 794 | #define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 795 | #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ |
| mbed_official | 50:a417edff4437 | 796 | |
| mbed_official | 50:a417edff4437 | 797 | /* Bit fields for EMU DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 798 | #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 799 | #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 800 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ |
| mbed_official | 50:a417edff4437 | 801 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ |
| mbed_official | 50:a417edff4437 | 802 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 803 | #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 804 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ |
| mbed_official | 50:a417edff4437 | 805 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ |
| mbed_official | 50:a417edff4437 | 806 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 807 | #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ |
| mbed_official | 50:a417edff4437 | 808 | |
| mbed_official | 50:a417edff4437 | 809 | /* Bit fields for EMU DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 810 | #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 811 | #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 812 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ |
| mbed_official | 50:a417edff4437 | 813 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ |
| mbed_official | 50:a417edff4437 | 814 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 815 | #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 816 | #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ |
| mbed_official | 50:a417edff4437 | 817 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ |
| mbed_official | 50:a417edff4437 | 818 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ |
| mbed_official | 50:a417edff4437 | 819 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 820 | #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| mbed_official | 50:a417edff4437 | 821 | |
| mbed_official | 50:a417edff4437 | 822 | /* Bit fields for EMU DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 823 | #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 824 | #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 825 | #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ |
| mbed_official | 50:a417edff4437 | 826 | #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ |
| mbed_official | 50:a417edff4437 | 827 | #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ |
| mbed_official | 50:a417edff4437 | 828 | #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 829 | #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 830 | #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 831 | #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 832 | #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 833 | #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 834 | #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ |
| mbed_official | 50:a417edff4437 | 835 | #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ |
| mbed_official | 50:a417edff4437 | 836 | #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 837 | #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ |
| mbed_official | 50:a417edff4437 | 838 | |
| mbed_official | 50:a417edff4437 | 839 | /* Bit fields for EMU DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 840 | #define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 841 | #define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 842 | #define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */ |
| mbed_official | 50:a417edff4437 | 843 | #define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */ |
| mbed_official | 50:a417edff4437 | 844 | #define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 845 | #define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 846 | #define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */ |
| mbed_official | 50:a417edff4437 | 847 | #define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */ |
| mbed_official | 50:a417edff4437 | 848 | #define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */ |
| mbed_official | 50:a417edff4437 | 849 | #define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 850 | #define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 851 | #define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */ |
| mbed_official | 50:a417edff4437 | 852 | #define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */ |
| mbed_official | 50:a417edff4437 | 853 | #define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 854 | #define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 855 | #define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */ |
| mbed_official | 50:a417edff4437 | 856 | #define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */ |
| mbed_official | 50:a417edff4437 | 857 | #define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 858 | #define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 859 | #define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */ |
| mbed_official | 50:a417edff4437 | 860 | #define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */ |
| mbed_official | 50:a417edff4437 | 861 | #define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 862 | #define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */ |
| mbed_official | 50:a417edff4437 | 863 | |
| mbed_official | 50:a417edff4437 | 864 | /* Bit fields for EMU DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 865 | #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 866 | #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 867 | #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ |
| mbed_official | 50:a417edff4437 | 868 | #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ |
| mbed_official | 50:a417edff4437 | 869 | #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ |
| mbed_official | 50:a417edff4437 | 870 | #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 871 | #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 872 | #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 873 | #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 874 | #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 875 | #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 876 | #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ |
| mbed_official | 50:a417edff4437 | 877 | #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ |
| mbed_official | 50:a417edff4437 | 878 | #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 879 | #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ |
| mbed_official | 50:a417edff4437 | 880 | |
| mbed_official | 50:a417edff4437 | 881 | /* Bit fields for EMU DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 882 | #define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 883 | #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 884 | #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */ |
| mbed_official | 50:a417edff4437 | 885 | #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */ |
| mbed_official | 50:a417edff4437 | 886 | #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 887 | #define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 888 | #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< Lp mode duty cycling enable */ |
| mbed_official | 50:a417edff4437 | 889 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ |
| mbed_official | 50:a417edff4437 | 890 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ |
| mbed_official | 50:a417edff4437 | 891 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 892 | #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 893 | #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ |
| mbed_official | 50:a417edff4437 | 894 | #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ |
| mbed_official | 50:a417edff4437 | 895 | #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 896 | #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| mbed_official | 50:a417edff4437 | 897 | |
| mbed_official | 50:a417edff4437 | 898 | /* Bit fields for EMU DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 899 | #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 900 | #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 901 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ |
| mbed_official | 50:a417edff4437 | 902 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ |
| mbed_official | 50:a417edff4437 | 903 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 904 | #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 905 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ |
| mbed_official | 50:a417edff4437 | 906 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ |
| mbed_official | 50:a417edff4437 | 907 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 908 | #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| mbed_official | 50:a417edff4437 | 909 | |
| mbed_official | 50:a417edff4437 | 910 | /* Bit fields for EMU DCDCSYNC */ |
| mbed_official | 50:a417edff4437 | 911 | #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ |
| mbed_official | 50:a417edff4437 | 912 | #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ |
| mbed_official | 50:a417edff4437 | 913 | #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ |
| mbed_official | 50:a417edff4437 | 914 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ |
| mbed_official | 50:a417edff4437 | 915 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ |
| mbed_official | 50:a417edff4437 | 916 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ |
| mbed_official | 50:a417edff4437 | 917 | #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ |
| mbed_official | 50:a417edff4437 | 918 | |
| mbed_official | 50:a417edff4437 | 919 | /* Bit fields for EMU VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 920 | #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 921 | #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 922 | #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| mbed_official | 50:a417edff4437 | 923 | #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 924 | #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 925 | #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 926 | #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 927 | #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| mbed_official | 50:a417edff4437 | 928 | #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 929 | #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 930 | #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 931 | #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 932 | #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| mbed_official | 50:a417edff4437 | 933 | #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 934 | #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 935 | #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 936 | #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 937 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ |
| mbed_official | 50:a417edff4437 | 938 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ |
| mbed_official | 50:a417edff4437 | 939 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 940 | #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 941 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 942 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 943 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 944 | #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 945 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ |
| mbed_official | 50:a417edff4437 | 946 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ |
| mbed_official | 50:a417edff4437 | 947 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 948 | #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 949 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 950 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 951 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 952 | #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 953 | |
| mbed_official | 50:a417edff4437 | 954 | /* Bit fields for EMU VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 955 | #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 956 | #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 957 | #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| mbed_official | 50:a417edff4437 | 958 | #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 959 | #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 960 | #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 961 | #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 962 | #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| mbed_official | 50:a417edff4437 | 963 | #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 964 | #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 965 | #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 966 | #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 967 | #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| mbed_official | 50:a417edff4437 | 968 | #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 969 | #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 970 | #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 971 | #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 972 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 973 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 974 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 975 | #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 976 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 977 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 978 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 979 | #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 980 | |
| mbed_official | 50:a417edff4437 | 981 | /* Bit fields for EMU VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 982 | #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 983 | #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 984 | #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| mbed_official | 50:a417edff4437 | 985 | #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 986 | #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 987 | #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 988 | #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 989 | #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| mbed_official | 50:a417edff4437 | 990 | #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 991 | #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 992 | #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 993 | #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 994 | #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| mbed_official | 50:a417edff4437 | 995 | #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 996 | #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 997 | #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 998 | #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 999 | #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 1000 | #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 1001 | #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 1002 | #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 1003 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 1004 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 1005 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 1006 | #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| mbed_official | 50:a417edff4437 | 1007 | |
| mbed_official | 50:a417edff4437 | 1008 | /* Bit fields for EMU VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1009 | #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1010 | #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1011 | #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ |
| mbed_official | 50:a417edff4437 | 1012 | #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 1013 | #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| mbed_official | 50:a417edff4437 | 1014 | #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1015 | #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1016 | #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| mbed_official | 50:a417edff4437 | 1017 | #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 1018 | #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| mbed_official | 50:a417edff4437 | 1019 | #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1020 | #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1021 | #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| mbed_official | 50:a417edff4437 | 1022 | #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 1023 | #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| mbed_official | 50:a417edff4437 | 1024 | #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1025 | #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1026 | #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ |
| mbed_official | 50:a417edff4437 | 1027 | #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ |
| mbed_official | 50:a417edff4437 | 1028 | #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ |
| mbed_official | 50:a417edff4437 | 1029 | #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1030 | #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1031 | #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 1032 | #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| mbed_official | 50:a417edff4437 | 1033 | #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1034 | #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1035 | #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 1036 | #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| mbed_official | 50:a417edff4437 | 1037 | #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1038 | #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| mbed_official | 50:a417edff4437 | 1039 | |
| mbed_official | 50:a417edff4437 | 1040 | /** @} End of group EFM32PG1B_EMU */ |
| mbed_official | 50:a417edff4437 | 1041 | /** @} End of group Parts */ |
| mbed_official | 50:a417edff4437 | 1042 |