Toyomasa Watarai / mbed-dev-lpcx1769

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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg990f256.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32wg990f256.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
bogdanm 0:9b334a45a8ff 4 * for EFM32WG990F256
bogdanm 0:9b334a45a8ff 5 * @version 3.20.6
bogdanm 0:9b334a45a8ff 6 ******************************************************************************
bogdanm 0:9b334a45a8ff 7 * @section License
bogdanm 0:9b334a45a8ff 8 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 9 ******************************************************************************
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 12 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 13 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 16 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 17 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 18 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 19 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 23 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 24 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 25 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 26 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 29 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 30 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 31 *
bogdanm 0:9b334a45a8ff 32 *****************************************************************************/
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef __EFM32WG990F256_H
bogdanm 0:9b334a45a8ff 35 #define __EFM32WG990F256_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 42 * @addtogroup Parts
bogdanm 0:9b334a45a8ff 43 * @{
bogdanm 0:9b334a45a8ff 44 *****************************************************************************/
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 47 * @defgroup EFM32WG990F256 EFM32WG990F256
bogdanm 0:9b334a45a8ff 48 * @{
bogdanm 0:9b334a45a8ff 49 *****************************************************************************/
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** Interrupt Number Definition */
bogdanm 0:9b334a45a8ff 52 typedef enum IRQn
bogdanm 0:9b334a45a8ff 53 {
bogdanm 0:9b334a45a8ff 54 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/
bogdanm 0:9b334a45a8ff 55 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 56 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 0:9b334a45a8ff 58 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 0:9b334a45a8ff 59 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 0:9b334a45a8ff 60 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 0:9b334a45a8ff 62 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 63 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /****** EFM32WG Peripheral Interrupt Numbers *********************************************/
bogdanm 0:9b334a45a8ff 66 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
bogdanm 0:9b334a45a8ff 67 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
bogdanm 0:9b334a45a8ff 68 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
bogdanm 0:9b334a45a8ff 69 USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
bogdanm 0:9b334a45a8ff 70 USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
bogdanm 0:9b334a45a8ff 71 USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */
bogdanm 0:9b334a45a8ff 72 ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */
bogdanm 0:9b334a45a8ff 73 ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */
bogdanm 0:9b334a45a8ff 74 DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */
bogdanm 0:9b334a45a8ff 75 I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */
bogdanm 0:9b334a45a8ff 76 I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */
bogdanm 0:9b334a45a8ff 77 GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */
bogdanm 0:9b334a45a8ff 78 TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */
bogdanm 0:9b334a45a8ff 79 TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */
bogdanm 0:9b334a45a8ff 80 TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */
bogdanm 0:9b334a45a8ff 81 USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */
bogdanm 0:9b334a45a8ff 82 USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */
bogdanm 0:9b334a45a8ff 83 LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */
bogdanm 0:9b334a45a8ff 84 USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */
bogdanm 0:9b334a45a8ff 85 USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */
bogdanm 0:9b334a45a8ff 86 UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */
bogdanm 0:9b334a45a8ff 87 UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */
bogdanm 0:9b334a45a8ff 88 UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */
bogdanm 0:9b334a45a8ff 89 UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */
bogdanm 0:9b334a45a8ff 90 LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */
bogdanm 0:9b334a45a8ff 91 LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */
bogdanm 0:9b334a45a8ff 92 LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */
bogdanm 0:9b334a45a8ff 93 PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */
bogdanm 0:9b334a45a8ff 94 PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */
bogdanm 0:9b334a45a8ff 95 PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */
bogdanm 0:9b334a45a8ff 96 RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */
bogdanm 0:9b334a45a8ff 97 BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */
bogdanm 0:9b334a45a8ff 98 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */
bogdanm 0:9b334a45a8ff 99 VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */
bogdanm 0:9b334a45a8ff 100 LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */
bogdanm 0:9b334a45a8ff 101 MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */
bogdanm 0:9b334a45a8ff 102 AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */
bogdanm 0:9b334a45a8ff 103 EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */
bogdanm 0:9b334a45a8ff 104 EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */
bogdanm 0:9b334a45a8ff 105 FPUEH_IRQn = 39, /*!< 16+39 EFM32 FPUEH Interrupt */
bogdanm 0:9b334a45a8ff 106 } IRQn_Type;
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 109 * @defgroup EFM32WG990F256_Core EFM32WG990F256 Core
bogdanm 0:9b334a45a8ff 110 * @{
bogdanm 0:9b334a45a8ff 111 * @brief Processor and Core Peripheral Section
bogdanm 0:9b334a45a8ff 112 *****************************************************************************/
bogdanm 0:9b334a45a8ff 113 #define __MPU_PRESENT 1 /**< Presence of MPU */
bogdanm 0:9b334a45a8ff 114 #define __FPU_PRESENT 1 /**< Presence of FPU */
bogdanm 0:9b334a45a8ff 115 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
bogdanm 0:9b334a45a8ff 116 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /** @} End of group EFM32WG990F256_Core */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 121 * @defgroup EFM32WG990F256_Part EFM32WG990F256 Part
bogdanm 0:9b334a45a8ff 122 * @{
bogdanm 0:9b334a45a8ff 123 ******************************************************************************/
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /** Part family */
bogdanm 0:9b334a45a8ff 126 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
bogdanm 0:9b334a45a8ff 127 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* If part number is not defined as compiler option, define it */
bogdanm 0:9b334a45a8ff 130 #if !defined(EFM32WG990F256)
bogdanm 0:9b334a45a8ff 131 #define EFM32WG990F256 1 /**< Wonder Gecko Part */
bogdanm 0:9b334a45a8ff 132 #endif
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** Configure part number */
bogdanm 0:9b334a45a8ff 135 #define PART_NUMBER "EFM32WG990F256" /**< Part Number */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /** Memory Base addresses and limits */
bogdanm 0:9b334a45a8ff 138 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
bogdanm 0:9b334a45a8ff 139 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
bogdanm 0:9b334a45a8ff 140 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
bogdanm 0:9b334a45a8ff 141 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
bogdanm 0:9b334a45a8ff 142 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
bogdanm 0:9b334a45a8ff 143 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
bogdanm 0:9b334a45a8ff 144 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
bogdanm 0:9b334a45a8ff 145 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
bogdanm 0:9b334a45a8ff 146 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
bogdanm 0:9b334a45a8ff 147 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
bogdanm 0:9b334a45a8ff 148 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
bogdanm 0:9b334a45a8ff 149 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
bogdanm 0:9b334a45a8ff 150 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
bogdanm 0:9b334a45a8ff 151 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
bogdanm 0:9b334a45a8ff 152 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
bogdanm 0:9b334a45a8ff 153 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
bogdanm 0:9b334a45a8ff 154 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
bogdanm 0:9b334a45a8ff 155 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
bogdanm 0:9b334a45a8ff 156 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
bogdanm 0:9b334a45a8ff 157 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
bogdanm 0:9b334a45a8ff 158 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
bogdanm 0:9b334a45a8ff 159 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
bogdanm 0:9b334a45a8ff 160 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
bogdanm 0:9b334a45a8ff 161 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
bogdanm 0:9b334a45a8ff 162 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
bogdanm 0:9b334a45a8ff 163 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
bogdanm 0:9b334a45a8ff 164 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
bogdanm 0:9b334a45a8ff 165 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
bogdanm 0:9b334a45a8ff 166 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
bogdanm 0:9b334a45a8ff 167 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
bogdanm 0:9b334a45a8ff 168 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
bogdanm 0:9b334a45a8ff 169 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /** Bit banding area */
bogdanm 0:9b334a45a8ff 172 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
bogdanm 0:9b334a45a8ff 173 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /** Flash and SRAM limits for EFM32WG990F256 */
bogdanm 0:9b334a45a8ff 176 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
bogdanm 0:9b334a45a8ff 177 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
bogdanm 0:9b334a45a8ff 178 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
bogdanm 0:9b334a45a8ff 179 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
bogdanm 0:9b334a45a8ff 180 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
bogdanm 0:9b334a45a8ff 181 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
bogdanm 0:9b334a45a8ff 182 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
bogdanm 0:9b334a45a8ff 183 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /** AF channels connect the different on-chip peripherals with the af-mux */
bogdanm 0:9b334a45a8ff 186 #define AFCHAN_MAX 163
bogdanm 0:9b334a45a8ff 187 #define AFCHANLOC_MAX 7
bogdanm 0:9b334a45a8ff 188 /** Analog AF channels */
bogdanm 0:9b334a45a8ff 189 #define AFACHAN_MAX 53
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /* Part number capabilities */
bogdanm 0:9b334a45a8ff 192 #define USART_PRESENT /**< USART is available in this part */
bogdanm 0:9b334a45a8ff 193 #define USART_COUNT 3 /**< 3 USARTs available */
bogdanm 0:9b334a45a8ff 194 #define UART_PRESENT /**< UART is available in this part */
bogdanm 0:9b334a45a8ff 195 #define UART_COUNT 2 /**< 2 UARTs available */
bogdanm 0:9b334a45a8ff 196 #define TIMER_PRESENT /**< TIMER is available in this part */
bogdanm 0:9b334a45a8ff 197 #define TIMER_COUNT 4 /**< 4 TIMERs available */
bogdanm 0:9b334a45a8ff 198 #define ACMP_PRESENT /**< ACMP is available in this part */
bogdanm 0:9b334a45a8ff 199 #define ACMP_COUNT 2 /**< 2 ACMPs available */
bogdanm 0:9b334a45a8ff 200 #define LEUART_PRESENT /**< LEUART is available in this part */
bogdanm 0:9b334a45a8ff 201 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
bogdanm 0:9b334a45a8ff 202 #define LETIMER_PRESENT /**< LETIMER is available in this part */
bogdanm 0:9b334a45a8ff 203 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
bogdanm 0:9b334a45a8ff 204 #define PCNT_PRESENT /**< PCNT is available in this part */
bogdanm 0:9b334a45a8ff 205 #define PCNT_COUNT 3 /**< 3 PCNTs available */
bogdanm 0:9b334a45a8ff 206 #define I2C_PRESENT /**< I2C is available in this part */
bogdanm 0:9b334a45a8ff 207 #define I2C_COUNT 2 /**< 2 I2Cs available */
bogdanm 0:9b334a45a8ff 208 #define ADC_PRESENT /**< ADC is available in this part */
bogdanm 0:9b334a45a8ff 209 #define ADC_COUNT 1 /**< 1 ADCs available */
bogdanm 0:9b334a45a8ff 210 #define DAC_PRESENT /**< DAC is available in this part */
bogdanm 0:9b334a45a8ff 211 #define DAC_COUNT 1 /**< 1 DACs available */
bogdanm 0:9b334a45a8ff 212 #define DMA_PRESENT
bogdanm 0:9b334a45a8ff 213 #define DMA_COUNT 1
bogdanm 0:9b334a45a8ff 214 #define AES_PRESENT
bogdanm 0:9b334a45a8ff 215 #define AES_COUNT 1
bogdanm 0:9b334a45a8ff 216 #define USBC_PRESENT
bogdanm 0:9b334a45a8ff 217 #define USBC_COUNT 1
bogdanm 0:9b334a45a8ff 218 #define USB_PRESENT
bogdanm 0:9b334a45a8ff 219 #define USB_COUNT 1
bogdanm 0:9b334a45a8ff 220 #define LE_PRESENT
bogdanm 0:9b334a45a8ff 221 #define LE_COUNT 1
bogdanm 0:9b334a45a8ff 222 #define MSC_PRESENT
bogdanm 0:9b334a45a8ff 223 #define MSC_COUNT 1
bogdanm 0:9b334a45a8ff 224 #define EMU_PRESENT
bogdanm 0:9b334a45a8ff 225 #define EMU_COUNT 1
bogdanm 0:9b334a45a8ff 226 #define RMU_PRESENT
bogdanm 0:9b334a45a8ff 227 #define RMU_COUNT 1
bogdanm 0:9b334a45a8ff 228 #define CMU_PRESENT
bogdanm 0:9b334a45a8ff 229 #define CMU_COUNT 1
bogdanm 0:9b334a45a8ff 230 #define LESENSE_PRESENT
bogdanm 0:9b334a45a8ff 231 #define LESENSE_COUNT 1
bogdanm 0:9b334a45a8ff 232 #define EBI_PRESENT
bogdanm 0:9b334a45a8ff 233 #define EBI_COUNT 1
bogdanm 0:9b334a45a8ff 234 #define FPUEH_PRESENT
bogdanm 0:9b334a45a8ff 235 #define FPUEH_COUNT 1
bogdanm 0:9b334a45a8ff 236 #define RTC_PRESENT
bogdanm 0:9b334a45a8ff 237 #define RTC_COUNT 1
bogdanm 0:9b334a45a8ff 238 #define GPIO_PRESENT
bogdanm 0:9b334a45a8ff 239 #define GPIO_COUNT 1
bogdanm 0:9b334a45a8ff 240 #define VCMP_PRESENT
bogdanm 0:9b334a45a8ff 241 #define VCMP_COUNT 1
bogdanm 0:9b334a45a8ff 242 #define PRS_PRESENT
bogdanm 0:9b334a45a8ff 243 #define PRS_COUNT 1
bogdanm 0:9b334a45a8ff 244 #define OPAMP_PRESENT
bogdanm 0:9b334a45a8ff 245 #define OPAMP_COUNT 1
bogdanm 0:9b334a45a8ff 246 #define BU_PRESENT
bogdanm 0:9b334a45a8ff 247 #define BU_COUNT 1
bogdanm 0:9b334a45a8ff 248 #define LCD_PRESENT
bogdanm 0:9b334a45a8ff 249 #define LCD_COUNT 1
bogdanm 0:9b334a45a8ff 250 #define BURTC_PRESENT
bogdanm 0:9b334a45a8ff 251 #define BURTC_COUNT 1
bogdanm 0:9b334a45a8ff 252 #define HFXTAL_PRESENT
bogdanm 0:9b334a45a8ff 253 #define HFXTAL_COUNT 1
bogdanm 0:9b334a45a8ff 254 #define LFXTAL_PRESENT
bogdanm 0:9b334a45a8ff 255 #define LFXTAL_COUNT 1
bogdanm 0:9b334a45a8ff 256 #define WDOG_PRESENT
bogdanm 0:9b334a45a8ff 257 #define WDOG_COUNT 1
bogdanm 0:9b334a45a8ff 258 #define DBG_PRESENT
bogdanm 0:9b334a45a8ff 259 #define DBG_COUNT 1
bogdanm 0:9b334a45a8ff 260 #define ETM_PRESENT
bogdanm 0:9b334a45a8ff 261 #define ETM_COUNT 1
bogdanm 0:9b334a45a8ff 262 #define BOOTLOADER_PRESENT
bogdanm 0:9b334a45a8ff 263 #define BOOTLOADER_COUNT 1
bogdanm 0:9b334a45a8ff 264 #define ANALOG_PRESENT
bogdanm 0:9b334a45a8ff 265 #define ANALOG_COUNT 1
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 0:9b334a45a8ff 268 #include "system_efm32wg.h" /* System Header */
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /** @} End of group EFM32WG990F256_Part */
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 273 * @defgroup EFM32WG990F256_Peripheral_TypeDefs EFM32WG990F256 Peripheral TypeDefs
bogdanm 0:9b334a45a8ff 274 * @{
bogdanm 0:9b334a45a8ff 275 * @brief Device Specific Peripheral Register Structures
bogdanm 0:9b334a45a8ff 276 *****************************************************************************/
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 #include "efm32wg_dma_ch.h"
bogdanm 0:9b334a45a8ff 279 #include "efm32wg_dma.h"
bogdanm 0:9b334a45a8ff 280 #include "efm32wg_aes.h"
bogdanm 0:9b334a45a8ff 281 #include "efm32wg_usb_hc.h"
bogdanm 0:9b334a45a8ff 282 #include "efm32wg_usb_diep.h"
bogdanm 0:9b334a45a8ff 283 #include "efm32wg_usb_doep.h"
bogdanm 0:9b334a45a8ff 284 #include "efm32wg_usb.h"
bogdanm 0:9b334a45a8ff 285 #include "efm32wg_msc.h"
bogdanm 0:9b334a45a8ff 286 #include "efm32wg_emu.h"
bogdanm 0:9b334a45a8ff 287 #include "efm32wg_rmu.h"
bogdanm 0:9b334a45a8ff 288 #include "efm32wg_cmu.h"
bogdanm 0:9b334a45a8ff 289 #include "efm32wg_lesense_st.h"
bogdanm 0:9b334a45a8ff 290 #include "efm32wg_lesense_buf.h"
bogdanm 0:9b334a45a8ff 291 #include "efm32wg_lesense_ch.h"
bogdanm 0:9b334a45a8ff 292 #include "efm32wg_lesense.h"
bogdanm 0:9b334a45a8ff 293 #include "efm32wg_ebi.h"
bogdanm 0:9b334a45a8ff 294 #include "efm32wg_fpueh.h"
bogdanm 0:9b334a45a8ff 295 #include "efm32wg_usart.h"
bogdanm 0:9b334a45a8ff 296 #include "efm32wg_timer_cc.h"
bogdanm 0:9b334a45a8ff 297 #include "efm32wg_timer.h"
bogdanm 0:9b334a45a8ff 298 #include "efm32wg_acmp.h"
bogdanm 0:9b334a45a8ff 299 #include "efm32wg_leuart.h"
bogdanm 0:9b334a45a8ff 300 #include "efm32wg_rtc.h"
bogdanm 0:9b334a45a8ff 301 #include "efm32wg_letimer.h"
bogdanm 0:9b334a45a8ff 302 #include "efm32wg_pcnt.h"
bogdanm 0:9b334a45a8ff 303 #include "efm32wg_i2c.h"
bogdanm 0:9b334a45a8ff 304 #include "efm32wg_gpio_p.h"
bogdanm 0:9b334a45a8ff 305 #include "efm32wg_gpio.h"
bogdanm 0:9b334a45a8ff 306 #include "efm32wg_vcmp.h"
bogdanm 0:9b334a45a8ff 307 #include "efm32wg_prs_ch.h"
bogdanm 0:9b334a45a8ff 308 #include "efm32wg_prs.h"
bogdanm 0:9b334a45a8ff 309 #include "efm32wg_adc.h"
bogdanm 0:9b334a45a8ff 310 #include "efm32wg_dac.h"
bogdanm 0:9b334a45a8ff 311 #include "efm32wg_lcd.h"
bogdanm 0:9b334a45a8ff 312 #include "efm32wg_burtc_ret.h"
bogdanm 0:9b334a45a8ff 313 #include "efm32wg_burtc.h"
bogdanm 0:9b334a45a8ff 314 #include "efm32wg_wdog.h"
bogdanm 0:9b334a45a8ff 315 #include "efm32wg_etm.h"
bogdanm 0:9b334a45a8ff 316 #include "efm32wg_dma_descriptor.h"
bogdanm 0:9b334a45a8ff 317 #include "efm32wg_devinfo.h"
bogdanm 0:9b334a45a8ff 318 #include "efm32wg_romtable.h"
bogdanm 0:9b334a45a8ff 319 #include "efm32wg_calibrate.h"
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 /** @} End of group EFM32WG990F256_Peripheral_TypeDefs */
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 324 * @defgroup EFM32WG990F256_Peripheral_Base EFM32WG990F256 Peripheral Memory Map
bogdanm 0:9b334a45a8ff 325 * @{
bogdanm 0:9b334a45a8ff 326 *****************************************************************************/
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
bogdanm 0:9b334a45a8ff 329 #define AES_BASE (0x400E0000UL) /**< AES base address */
bogdanm 0:9b334a45a8ff 330 #define USB_BASE (0x400C4000UL) /**< USB base address */
bogdanm 0:9b334a45a8ff 331 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
bogdanm 0:9b334a45a8ff 332 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
bogdanm 0:9b334a45a8ff 333 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
bogdanm 0:9b334a45a8ff 334 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
bogdanm 0:9b334a45a8ff 335 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
bogdanm 0:9b334a45a8ff 336 #define EBI_BASE (0x40008000UL) /**< EBI base address */
bogdanm 0:9b334a45a8ff 337 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
bogdanm 0:9b334a45a8ff 338 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
bogdanm 0:9b334a45a8ff 339 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
bogdanm 0:9b334a45a8ff 340 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
bogdanm 0:9b334a45a8ff 341 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
bogdanm 0:9b334a45a8ff 342 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
bogdanm 0:9b334a45a8ff 343 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
bogdanm 0:9b334a45a8ff 344 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
bogdanm 0:9b334a45a8ff 345 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
bogdanm 0:9b334a45a8ff 346 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
bogdanm 0:9b334a45a8ff 347 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
bogdanm 0:9b334a45a8ff 348 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
bogdanm 0:9b334a45a8ff 349 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
bogdanm 0:9b334a45a8ff 350 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
bogdanm 0:9b334a45a8ff 351 #define RTC_BASE (0x40080000UL) /**< RTC base address */
bogdanm 0:9b334a45a8ff 352 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
bogdanm 0:9b334a45a8ff 353 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
bogdanm 0:9b334a45a8ff 354 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
bogdanm 0:9b334a45a8ff 355 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
bogdanm 0:9b334a45a8ff 356 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
bogdanm 0:9b334a45a8ff 357 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
bogdanm 0:9b334a45a8ff 358 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
bogdanm 0:9b334a45a8ff 359 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
bogdanm 0:9b334a45a8ff 360 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
bogdanm 0:9b334a45a8ff 361 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
bogdanm 0:9b334a45a8ff 362 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
bogdanm 0:9b334a45a8ff 363 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
bogdanm 0:9b334a45a8ff 364 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
bogdanm 0:9b334a45a8ff 365 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
bogdanm 0:9b334a45a8ff 366 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
bogdanm 0:9b334a45a8ff 367 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
bogdanm 0:9b334a45a8ff 368 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
bogdanm 0:9b334a45a8ff 369 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
bogdanm 0:9b334a45a8ff 370 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
bogdanm 0:9b334a45a8ff 371 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /** @} End of group EFM32WG990F256_Peripheral_Base */
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 376 * @defgroup EFM32WG990F256_Peripheral_Declaration EFM32WG990F256 Peripheral Declarations
bogdanm 0:9b334a45a8ff 377 * @{
bogdanm 0:9b334a45a8ff 378 *****************************************************************************/
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
bogdanm 0:9b334a45a8ff 381 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
bogdanm 0:9b334a45a8ff 382 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
bogdanm 0:9b334a45a8ff 383 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
bogdanm 0:9b334a45a8ff 384 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
bogdanm 0:9b334a45a8ff 385 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
bogdanm 0:9b334a45a8ff 386 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
bogdanm 0:9b334a45a8ff 387 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
bogdanm 0:9b334a45a8ff 388 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
bogdanm 0:9b334a45a8ff 389 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
bogdanm 0:9b334a45a8ff 390 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
bogdanm 0:9b334a45a8ff 391 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
bogdanm 0:9b334a45a8ff 392 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
bogdanm 0:9b334a45a8ff 393 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
bogdanm 0:9b334a45a8ff 394 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
bogdanm 0:9b334a45a8ff 395 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
bogdanm 0:9b334a45a8ff 396 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
bogdanm 0:9b334a45a8ff 397 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
bogdanm 0:9b334a45a8ff 398 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
bogdanm 0:9b334a45a8ff 399 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
bogdanm 0:9b334a45a8ff 400 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
bogdanm 0:9b334a45a8ff 401 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
bogdanm 0:9b334a45a8ff 402 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
bogdanm 0:9b334a45a8ff 403 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
bogdanm 0:9b334a45a8ff 404 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
bogdanm 0:9b334a45a8ff 405 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
bogdanm 0:9b334a45a8ff 406 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
bogdanm 0:9b334a45a8ff 407 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
bogdanm 0:9b334a45a8ff 408 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
bogdanm 0:9b334a45a8ff 409 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
bogdanm 0:9b334a45a8ff 410 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
bogdanm 0:9b334a45a8ff 411 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
bogdanm 0:9b334a45a8ff 412 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
bogdanm 0:9b334a45a8ff 413 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
bogdanm 0:9b334a45a8ff 414 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
bogdanm 0:9b334a45a8ff 415 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
bogdanm 0:9b334a45a8ff 416 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
bogdanm 0:9b334a45a8ff 417 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
bogdanm 0:9b334a45a8ff 418 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
bogdanm 0:9b334a45a8ff 419 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
bogdanm 0:9b334a45a8ff 420 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
bogdanm 0:9b334a45a8ff 421 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 /** @} End of group EFM32WG990F256_Peripheral_Declaration */
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 426 * @defgroup EFM32WG990F256_BitFields EFM32WG990F256 Bit Fields
bogdanm 0:9b334a45a8ff 427 * @{
bogdanm 0:9b334a45a8ff 428 *****************************************************************************/
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 #include "efm32wg_prs_signals.h"
bogdanm 0:9b334a45a8ff 431 #include "efm32wg_dmareq.h"
bogdanm 0:9b334a45a8ff 432 #include "efm32wg_dmactrl.h"
bogdanm 0:9b334a45a8ff 433 #include "efm32wg_uart.h"
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 436 * @defgroup EFM32WG990F256_UNLOCK EFM32WG990F256 Unlock Codes
bogdanm 0:9b334a45a8ff 437 * @{
bogdanm 0:9b334a45a8ff 438 *****************************************************************************/
bogdanm 0:9b334a45a8ff 439 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
bogdanm 0:9b334a45a8ff 440 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
bogdanm 0:9b334a45a8ff 441 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
bogdanm 0:9b334a45a8ff 442 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
bogdanm 0:9b334a45a8ff 443 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
bogdanm 0:9b334a45a8ff 444 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /** @} End of group EFM32WG990F256_UNLOCK */
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /** @} End of group EFM32WG990F256_BitFields */
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 451 * @defgroup EFM32WG990F256_Alternate_Function EFM32WG990F256 Alternate Function
bogdanm 0:9b334a45a8ff 452 * @{
bogdanm 0:9b334a45a8ff 453 *****************************************************************************/
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 #include "efm32wg_af_ports.h"
bogdanm 0:9b334a45a8ff 456 #include "efm32wg_af_pins.h"
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /** @} End of group EFM32WG990F256_Alternate_Function */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 461 * @brief Set the value of a bit field within a register.
bogdanm 0:9b334a45a8ff 462 *
bogdanm 0:9b334a45a8ff 463 * @param REG
bogdanm 0:9b334a45a8ff 464 * The register to update
bogdanm 0:9b334a45a8ff 465 * @param MASK
bogdanm 0:9b334a45a8ff 466 * The mask for the bit field to update
bogdanm 0:9b334a45a8ff 467 * @param VALUE
bogdanm 0:9b334a45a8ff 468 * The value to write to the bit field
bogdanm 0:9b334a45a8ff 469 * @param OFFSET
bogdanm 0:9b334a45a8ff 470 * The number of bits that the field is offset within the register.
bogdanm 0:9b334a45a8ff 471 * 0 (zero) means LSB.
bogdanm 0:9b334a45a8ff 472 *****************************************************************************/
bogdanm 0:9b334a45a8ff 473 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
bogdanm 0:9b334a45a8ff 474 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /** @} End of group EFM32WG990F256 */
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /** @} End of group Parts */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482 #endif
bogdanm 0:9b334a45a8ff 483 #endif /* __EFM32WG990F256_H */