Toyomasa Watarai / easy-connect-type-yd

Easily add all supported connectivity methods to your mbed OS project

Dependencies:   type-yd-driver

mcr20a-rf-driver/source/MCR20Drv.c@0:615f90842ce8, 2017-07-12 (annotated)

Committer:
MACRUM
Date:
Wed Jul 12 10:52:58 2017 +0000
Revision:
0:615f90842ce8
Initial commit

Who changed what in which revision?

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MACRUM 0:615f90842ce8 1 /*!
MACRUM 0:615f90842ce8 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
MACRUM 0:615f90842ce8 3 * All rights reserved.
MACRUM 0:615f90842ce8 4 *
MACRUM 0:615f90842ce8 5 * \file MCR20Drv.c
MACRUM 0:615f90842ce8 6 *
MACRUM 0:615f90842ce8 7 * Redistribution and use in source and binary forms, with or without modification,
MACRUM 0:615f90842ce8 8 * are permitted provided that the following conditions are met:
MACRUM 0:615f90842ce8 9 *
MACRUM 0:615f90842ce8 10 * o Redistributions of source code must retain the above copyright notice, this list
MACRUM 0:615f90842ce8 11 * of conditions and the following disclaimer.
MACRUM 0:615f90842ce8 12 *
MACRUM 0:615f90842ce8 13 * o Redistributions in binary form must reproduce the above copyright notice, this
MACRUM 0:615f90842ce8 14 * list of conditions and the following disclaimer in the documentation and/or
MACRUM 0:615f90842ce8 15 * other materials provided with the distribution.
MACRUM 0:615f90842ce8 16 *
MACRUM 0:615f90842ce8 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
MACRUM 0:615f90842ce8 18 * contributors may be used to endorse or promote products derived from this
MACRUM 0:615f90842ce8 19 * software without specific prior written permission.
MACRUM 0:615f90842ce8 20 *
MACRUM 0:615f90842ce8 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
MACRUM 0:615f90842ce8 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
MACRUM 0:615f90842ce8 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
MACRUM 0:615f90842ce8 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
MACRUM 0:615f90842ce8 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
MACRUM 0:615f90842ce8 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
MACRUM 0:615f90842ce8 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
MACRUM 0:615f90842ce8 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
MACRUM 0:615f90842ce8 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
MACRUM 0:615f90842ce8 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MACRUM 0:615f90842ce8 31 */
MACRUM 0:615f90842ce8 32
MACRUM 0:615f90842ce8 33
MACRUM 0:615f90842ce8 34 /*****************************************************************************
MACRUM 0:615f90842ce8 35 * INCLUDED HEADERS *
MACRUM 0:615f90842ce8 36 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 37 * Add to this section all the headers that this module needs to include. *
MACRUM 0:615f90842ce8 38 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 39 *****************************************************************************/
MACRUM 0:615f90842ce8 40
MACRUM 0:615f90842ce8 41 #include "platform/arm_hal_interrupt.h"
MACRUM 0:615f90842ce8 42 #include "MCR20Drv.h"
MACRUM 0:615f90842ce8 43 #include "MCR20Reg.h"
MACRUM 0:615f90842ce8 44 #include "XcvrSpi.h"
MACRUM 0:615f90842ce8 45
MACRUM 0:615f90842ce8 46
MACRUM 0:615f90842ce8 47 /*****************************************************************************
MACRUM 0:615f90842ce8 48 * PRIVATE VARIABLES *
MACRUM 0:615f90842ce8 49 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 50 * Add to this section all the variables and constants that have local *
MACRUM 0:615f90842ce8 51 * (file) scope. *
MACRUM 0:615f90842ce8 52 * Each of this declarations shall be preceded by the 'static' keyword. *
MACRUM 0:615f90842ce8 53 * These variables / constants cannot be accessed outside this module. *
MACRUM 0:615f90842ce8 54 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 55 *****************************************************************************/
MACRUM 0:615f90842ce8 56 uint32_t mPhyIrqDisableCnt = 1;
MACRUM 0:615f90842ce8 57
MACRUM 0:615f90842ce8 58 /*****************************************************************************
MACRUM 0:615f90842ce8 59 * PUBLIC VARIABLES *
MACRUM 0:615f90842ce8 60 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 61 * Add to this section all the variables and constants that have global *
MACRUM 0:615f90842ce8 62 * (project) scope. *
MACRUM 0:615f90842ce8 63 * These variables / constants can be accessed outside this module. *
MACRUM 0:615f90842ce8 64 * These variables / constants shall be preceded by the 'extern' keyword in *
MACRUM 0:615f90842ce8 65 * the interface header. *
MACRUM 0:615f90842ce8 66 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 67 *****************************************************************************/
MACRUM 0:615f90842ce8 68
MACRUM 0:615f90842ce8 69 /*****************************************************************************
MACRUM 0:615f90842ce8 70 * PRIVATE FUNCTIONS PROTOTYPES *
MACRUM 0:615f90842ce8 71 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 72 * Add to this section all the functions prototypes that have local (file) *
MACRUM 0:615f90842ce8 73 * scope. *
MACRUM 0:615f90842ce8 74 * These functions cannot be accessed outside this module. *
MACRUM 0:615f90842ce8 75 * These declarations shall be preceded by the 'static' keyword. *
MACRUM 0:615f90842ce8 76 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 77 *****************************************************************************/
MACRUM 0:615f90842ce8 78
MACRUM 0:615f90842ce8 79 /*****************************************************************************
MACRUM 0:615f90842ce8 80 * PRIVATE FUNCTIONS *
MACRUM 0:615f90842ce8 81 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 82 * Add to this section all the functions that have local (file) scope. *
MACRUM 0:615f90842ce8 83 * These functions cannot be accessed outside this module. *
MACRUM 0:615f90842ce8 84 * These definitions shall be preceded by the 'static' keyword. *
MACRUM 0:615f90842ce8 85 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 86 *****************************************************************************/
MACRUM 0:615f90842ce8 87
MACRUM 0:615f90842ce8 88
MACRUM 0:615f90842ce8 89 /*****************************************************************************
MACRUM 0:615f90842ce8 90 * PUBLIC FUNCTIONS *
MACRUM 0:615f90842ce8 91 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 92 * Add to this section all the functions that have global (project) scope. *
MACRUM 0:615f90842ce8 93 * These functions can be accessed outside this module. *
MACRUM 0:615f90842ce8 94 * These functions shall have their declarations (prototypes) within the *
MACRUM 0:615f90842ce8 95 * interface header file and shall be preceded by the 'extern' keyword. *
MACRUM 0:615f90842ce8 96 *---------------------------------------------------------------------------*
MACRUM 0:615f90842ce8 97 *****************************************************************************/
MACRUM 0:615f90842ce8 98
MACRUM 0:615f90842ce8 99 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 100 * Name: MCR20Drv_Init
MACRUM 0:615f90842ce8 101 * Description: -
MACRUM 0:615f90842ce8 102 * Parameters: -
MACRUM 0:615f90842ce8 103 * Return: -
MACRUM 0:615f90842ce8 104 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 105 void MCR20Drv_Init
MACRUM 0:615f90842ce8 106 (
MACRUM 0:615f90842ce8 107 void
MACRUM 0:615f90842ce8 108 )
MACRUM 0:615f90842ce8 109 {
MACRUM 0:615f90842ce8 110 xcvr_spi_init(gXcvrSpiInstance_c);
MACRUM 0:615f90842ce8 111 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 112
MACRUM 0:615f90842ce8 113 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 114 #if !defined(TARGET_KW24D)
MACRUM 0:615f90842ce8 115 MCR20Drv_RST_B_Deassert();
MACRUM 0:615f90842ce8 116 #endif
MACRUM 0:615f90842ce8 117 RF_IRQ_Init();
MACRUM 0:615f90842ce8 118 RF_IRQ_Disable();
MACRUM 0:615f90842ce8 119 mPhyIrqDisableCnt = 1;
MACRUM 0:615f90842ce8 120 }
MACRUM 0:615f90842ce8 121
MACRUM 0:615f90842ce8 122 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 123 * Name: MCR20Drv_DirectAccessSPIWrite
MACRUM 0:615f90842ce8 124 * Description: -
MACRUM 0:615f90842ce8 125 * Parameters: -
MACRUM 0:615f90842ce8 126 * Return: -
MACRUM 0:615f90842ce8 127 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 128 void MCR20Drv_DirectAccessSPIWrite
MACRUM 0:615f90842ce8 129 (
MACRUM 0:615f90842ce8 130 uint8_t address,
MACRUM 0:615f90842ce8 131 uint8_t value
MACRUM 0:615f90842ce8 132 )
MACRUM 0:615f90842ce8 133 {
MACRUM 0:615f90842ce8 134 uint16_t txData;
MACRUM 0:615f90842ce8 135
MACRUM 0:615f90842ce8 136 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 137
MACRUM 0:615f90842ce8 138 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 139
MACRUM 0:615f90842ce8 140 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 141
MACRUM 0:615f90842ce8 142 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
MACRUM 0:615f90842ce8 143 txData |= value << 8;
MACRUM 0:615f90842ce8 144
MACRUM 0:615f90842ce8 145 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 146
MACRUM 0:615f90842ce8 147 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 148 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 149 }
MACRUM 0:615f90842ce8 150
MACRUM 0:615f90842ce8 151 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 152 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
MACRUM 0:615f90842ce8 153 * Description: -
MACRUM 0:615f90842ce8 154 * Parameters: -
MACRUM 0:615f90842ce8 155 * Return: -
MACRUM 0:615f90842ce8 156 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 157 void MCR20Drv_DirectAccessSPIMultiByteWrite
MACRUM 0:615f90842ce8 158 (
MACRUM 0:615f90842ce8 159 uint8_t startAddress,
MACRUM 0:615f90842ce8 160 uint8_t * byteArray,
MACRUM 0:615f90842ce8 161 uint8_t numOfBytes
MACRUM 0:615f90842ce8 162 )
MACRUM 0:615f90842ce8 163 {
MACRUM 0:615f90842ce8 164 uint8_t txData;
MACRUM 0:615f90842ce8 165
MACRUM 0:615f90842ce8 166 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 167 {
MACRUM 0:615f90842ce8 168 return;
MACRUM 0:615f90842ce8 169 }
MACRUM 0:615f90842ce8 170
MACRUM 0:615f90842ce8 171 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 172
MACRUM 0:615f90842ce8 173 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 174
MACRUM 0:615f90842ce8 175 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 176
MACRUM 0:615f90842ce8 177 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
MACRUM 0:615f90842ce8 178
MACRUM 0:615f90842ce8 179 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 180 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
MACRUM 0:615f90842ce8 181
MACRUM 0:615f90842ce8 182 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 183 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 184 }
MACRUM 0:615f90842ce8 185
MACRUM 0:615f90842ce8 186 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 187 * Name: MCR20Drv_PB_SPIByteWrite
MACRUM 0:615f90842ce8 188 * Description: -
MACRUM 0:615f90842ce8 189 * Parameters: -
MACRUM 0:615f90842ce8 190 * Return: -
MACRUM 0:615f90842ce8 191 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 192 void MCR20Drv_PB_SPIByteWrite
MACRUM 0:615f90842ce8 193 (
MACRUM 0:615f90842ce8 194 uint8_t address,
MACRUM 0:615f90842ce8 195 uint8_t value
MACRUM 0:615f90842ce8 196 )
MACRUM 0:615f90842ce8 197 {
MACRUM 0:615f90842ce8 198 uint32_t txData;
MACRUM 0:615f90842ce8 199
MACRUM 0:615f90842ce8 200 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 201
MACRUM 0:615f90842ce8 202 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 203
MACRUM 0:615f90842ce8 204 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 205
MACRUM 0:615f90842ce8 206 txData = TransceiverSPI_WriteSelect |
MACRUM 0:615f90842ce8 207 TransceiverSPI_PacketBuffAccessSelect |
MACRUM 0:615f90842ce8 208 TransceiverSPI_PacketBuffByteModeSelect;
MACRUM 0:615f90842ce8 209 txData |= (address) << 8;
MACRUM 0:615f90842ce8 210 txData |= (value) << 16;
MACRUM 0:615f90842ce8 211
MACRUM 0:615f90842ce8 212 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
MACRUM 0:615f90842ce8 213
MACRUM 0:615f90842ce8 214 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 215 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 216 }
MACRUM 0:615f90842ce8 217
MACRUM 0:615f90842ce8 218 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 219 * Name: MCR20Drv_PB_SPIBurstWrite
MACRUM 0:615f90842ce8 220 * Description: -
MACRUM 0:615f90842ce8 221 * Parameters: -
MACRUM 0:615f90842ce8 222 * Return: -
MACRUM 0:615f90842ce8 223 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 224 void MCR20Drv_PB_SPIBurstWrite
MACRUM 0:615f90842ce8 225 (
MACRUM 0:615f90842ce8 226 uint8_t * byteArray,
MACRUM 0:615f90842ce8 227 uint8_t numOfBytes
MACRUM 0:615f90842ce8 228 )
MACRUM 0:615f90842ce8 229 {
MACRUM 0:615f90842ce8 230 uint8_t txData;
MACRUM 0:615f90842ce8 231
MACRUM 0:615f90842ce8 232 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 233 {
MACRUM 0:615f90842ce8 234 return;
MACRUM 0:615f90842ce8 235 }
MACRUM 0:615f90842ce8 236
MACRUM 0:615f90842ce8 237 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 238
MACRUM 0:615f90842ce8 239 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 240
MACRUM 0:615f90842ce8 241 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 242
MACRUM 0:615f90842ce8 243 txData = TransceiverSPI_WriteSelect |
MACRUM 0:615f90842ce8 244 TransceiverSPI_PacketBuffAccessSelect |
MACRUM 0:615f90842ce8 245 TransceiverSPI_PacketBuffBurstModeSelect;
MACRUM 0:615f90842ce8 246
MACRUM 0:615f90842ce8 247 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1);
MACRUM 0:615f90842ce8 248 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
MACRUM 0:615f90842ce8 249
MACRUM 0:615f90842ce8 250 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 251 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 252 }
MACRUM 0:615f90842ce8 253
MACRUM 0:615f90842ce8 254 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 255 * Name: MCR20Drv_DirectAccessSPIRead
MACRUM 0:615f90842ce8 256 * Description: -
MACRUM 0:615f90842ce8 257 * Parameters: -
MACRUM 0:615f90842ce8 258 * Return: -
MACRUM 0:615f90842ce8 259 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 260
MACRUM 0:615f90842ce8 261 uint8_t MCR20Drv_DirectAccessSPIRead
MACRUM 0:615f90842ce8 262 (
MACRUM 0:615f90842ce8 263 uint8_t address
MACRUM 0:615f90842ce8 264 )
MACRUM 0:615f90842ce8 265 {
MACRUM 0:615f90842ce8 266 uint8_t txData;
MACRUM 0:615f90842ce8 267 uint8_t rxData;
MACRUM 0:615f90842ce8 268
MACRUM 0:615f90842ce8 269 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 270
MACRUM 0:615f90842ce8 271 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 272
MACRUM 0:615f90842ce8 273 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 274
MACRUM 0:615f90842ce8 275 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
MACRUM 0:615f90842ce8 276 TransceiverSPI_ReadSelect;
MACRUM 0:615f90842ce8 277
MACRUM 0:615f90842ce8 278 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 279 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
MACRUM 0:615f90842ce8 280
MACRUM 0:615f90842ce8 281 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 282 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 283
MACRUM 0:615f90842ce8 284 return rxData;
MACRUM 0:615f90842ce8 285
MACRUM 0:615f90842ce8 286 }
MACRUM 0:615f90842ce8 287
MACRUM 0:615f90842ce8 288 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 289 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
MACRUM 0:615f90842ce8 290 * Description: -
MACRUM 0:615f90842ce8 291 * Parameters: -
MACRUM 0:615f90842ce8 292 * Return: -
MACRUM 0:615f90842ce8 293 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 294 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
MACRUM 0:615f90842ce8 295 (
MACRUM 0:615f90842ce8 296 uint8_t startAddress,
MACRUM 0:615f90842ce8 297 uint8_t * byteArray,
MACRUM 0:615f90842ce8 298 uint8_t numOfBytes
MACRUM 0:615f90842ce8 299 )
MACRUM 0:615f90842ce8 300 {
MACRUM 0:615f90842ce8 301 uint8_t txData;
MACRUM 0:615f90842ce8 302 uint8_t phyIRQSTS1;
MACRUM 0:615f90842ce8 303
MACRUM 0:615f90842ce8 304 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 305 {
MACRUM 0:615f90842ce8 306 return 0;
MACRUM 0:615f90842ce8 307 }
MACRUM 0:615f90842ce8 308
MACRUM 0:615f90842ce8 309 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 310
MACRUM 0:615f90842ce8 311 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 312
MACRUM 0:615f90842ce8 313 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 314
MACRUM 0:615f90842ce8 315 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
MACRUM 0:615f90842ce8 316 TransceiverSPI_ReadSelect;
MACRUM 0:615f90842ce8 317
MACRUM 0:615f90842ce8 318 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
MACRUM 0:615f90842ce8 319 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
MACRUM 0:615f90842ce8 320
MACRUM 0:615f90842ce8 321 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 322 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 323
MACRUM 0:615f90842ce8 324 return phyIRQSTS1;
MACRUM 0:615f90842ce8 325 }
MACRUM 0:615f90842ce8 326
MACRUM 0:615f90842ce8 327 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 328 * Name: MCR20Drv_PB_SPIBurstRead
MACRUM 0:615f90842ce8 329 * Description: -
MACRUM 0:615f90842ce8 330 * Parameters: -
MACRUM 0:615f90842ce8 331 * Return: -
MACRUM 0:615f90842ce8 332 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 333 uint8_t MCR20Drv_PB_SPIBurstRead
MACRUM 0:615f90842ce8 334 (
MACRUM 0:615f90842ce8 335 uint8_t * byteArray,
MACRUM 0:615f90842ce8 336 uint8_t numOfBytes
MACRUM 0:615f90842ce8 337 )
MACRUM 0:615f90842ce8 338 {
MACRUM 0:615f90842ce8 339 uint8_t txData;
MACRUM 0:615f90842ce8 340 uint8_t phyIRQSTS1;
MACRUM 0:615f90842ce8 341
MACRUM 0:615f90842ce8 342 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 343 {
MACRUM 0:615f90842ce8 344 return 0;
MACRUM 0:615f90842ce8 345 }
MACRUM 0:615f90842ce8 346
MACRUM 0:615f90842ce8 347 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 348
MACRUM 0:615f90842ce8 349 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 350
MACRUM 0:615f90842ce8 351 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 352
MACRUM 0:615f90842ce8 353 txData = TransceiverSPI_ReadSelect |
MACRUM 0:615f90842ce8 354 TransceiverSPI_PacketBuffAccessSelect |
MACRUM 0:615f90842ce8 355 TransceiverSPI_PacketBuffBurstModeSelect;
MACRUM 0:615f90842ce8 356
MACRUM 0:615f90842ce8 357 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
MACRUM 0:615f90842ce8 358 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
MACRUM 0:615f90842ce8 359
MACRUM 0:615f90842ce8 360 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 361 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 362
MACRUM 0:615f90842ce8 363 return phyIRQSTS1;
MACRUM 0:615f90842ce8 364 }
MACRUM 0:615f90842ce8 365
MACRUM 0:615f90842ce8 366 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 367 * Name: MCR20Drv_IndirectAccessSPIWrite
MACRUM 0:615f90842ce8 368 * Description: -
MACRUM 0:615f90842ce8 369 * Parameters: -
MACRUM 0:615f90842ce8 370 * Return: -
MACRUM 0:615f90842ce8 371 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 372 void MCR20Drv_IndirectAccessSPIWrite
MACRUM 0:615f90842ce8 373 (
MACRUM 0:615f90842ce8 374 uint8_t address,
MACRUM 0:615f90842ce8 375 uint8_t value
MACRUM 0:615f90842ce8 376 )
MACRUM 0:615f90842ce8 377 {
MACRUM 0:615f90842ce8 378 uint32_t txData;
MACRUM 0:615f90842ce8 379
MACRUM 0:615f90842ce8 380 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 381
MACRUM 0:615f90842ce8 382 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 383
MACRUM 0:615f90842ce8 384 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 385
MACRUM 0:615f90842ce8 386 txData = TransceiverSPI_IARIndexReg;
MACRUM 0:615f90842ce8 387 txData |= (address) << 8;
MACRUM 0:615f90842ce8 388 txData |= (value) << 16;
MACRUM 0:615f90842ce8 389
MACRUM 0:615f90842ce8 390 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
MACRUM 0:615f90842ce8 391
MACRUM 0:615f90842ce8 392 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 393 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 394 }
MACRUM 0:615f90842ce8 395
MACRUM 0:615f90842ce8 396 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 397 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
MACRUM 0:615f90842ce8 398 * Description: -
MACRUM 0:615f90842ce8 399 * Parameters: -
MACRUM 0:615f90842ce8 400 * Return: -
MACRUM 0:615f90842ce8 401 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 402 void MCR20Drv_IndirectAccessSPIMultiByteWrite
MACRUM 0:615f90842ce8 403 (
MACRUM 0:615f90842ce8 404 uint8_t startAddress,
MACRUM 0:615f90842ce8 405 uint8_t * byteArray,
MACRUM 0:615f90842ce8 406 uint8_t numOfBytes
MACRUM 0:615f90842ce8 407 )
MACRUM 0:615f90842ce8 408 {
MACRUM 0:615f90842ce8 409 uint16_t txData;
MACRUM 0:615f90842ce8 410
MACRUM 0:615f90842ce8 411 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 412 {
MACRUM 0:615f90842ce8 413 return;
MACRUM 0:615f90842ce8 414 }
MACRUM 0:615f90842ce8 415
MACRUM 0:615f90842ce8 416 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 417
MACRUM 0:615f90842ce8 418 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
MACRUM 0:615f90842ce8 419
MACRUM 0:615f90842ce8 420 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 421
MACRUM 0:615f90842ce8 422 txData = TransceiverSPI_IARIndexReg;
MACRUM 0:615f90842ce8 423 txData |= (startAddress) << 8;
MACRUM 0:615f90842ce8 424
MACRUM 0:615f90842ce8 425 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 426 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
MACRUM 0:615f90842ce8 427
MACRUM 0:615f90842ce8 428 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 429 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 430 }
MACRUM 0:615f90842ce8 431
MACRUM 0:615f90842ce8 432 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 433 * Name: MCR20Drv_IndirectAccessSPIRead
MACRUM 0:615f90842ce8 434 * Description: -
MACRUM 0:615f90842ce8 435 * Parameters: -
MACRUM 0:615f90842ce8 436 * Return: -
MACRUM 0:615f90842ce8 437 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 438 uint8_t MCR20Drv_IndirectAccessSPIRead
MACRUM 0:615f90842ce8 439 (
MACRUM 0:615f90842ce8 440 uint8_t address
MACRUM 0:615f90842ce8 441 )
MACRUM 0:615f90842ce8 442 {
MACRUM 0:615f90842ce8 443 uint16_t txData;
MACRUM 0:615f90842ce8 444 uint8_t rxData;
MACRUM 0:615f90842ce8 445
MACRUM 0:615f90842ce8 446 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 447
MACRUM 0:615f90842ce8 448 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 449
MACRUM 0:615f90842ce8 450 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 451
MACRUM 0:615f90842ce8 452 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
MACRUM 0:615f90842ce8 453 txData |= (address) << 8;
MACRUM 0:615f90842ce8 454
MACRUM 0:615f90842ce8 455 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 456 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
MACRUM 0:615f90842ce8 457
MACRUM 0:615f90842ce8 458 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 459 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 460
MACRUM 0:615f90842ce8 461 return rxData;
MACRUM 0:615f90842ce8 462 }
MACRUM 0:615f90842ce8 463
MACRUM 0:615f90842ce8 464 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 465 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
MACRUM 0:615f90842ce8 466 * Description: -
MACRUM 0:615f90842ce8 467 * Parameters: -
MACRUM 0:615f90842ce8 468 * Return: -
MACRUM 0:615f90842ce8 469 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 470 void MCR20Drv_IndirectAccessSPIMultiByteRead
MACRUM 0:615f90842ce8 471 (
MACRUM 0:615f90842ce8 472 uint8_t startAddress,
MACRUM 0:615f90842ce8 473 uint8_t * byteArray,
MACRUM 0:615f90842ce8 474 uint8_t numOfBytes
MACRUM 0:615f90842ce8 475 )
MACRUM 0:615f90842ce8 476 {
MACRUM 0:615f90842ce8 477 uint16_t txData;
MACRUM 0:615f90842ce8 478
MACRUM 0:615f90842ce8 479 if( (numOfBytes == 0) || (byteArray == 0) )
MACRUM 0:615f90842ce8 480 {
MACRUM 0:615f90842ce8 481 return;
MACRUM 0:615f90842ce8 482 }
MACRUM 0:615f90842ce8 483
MACRUM 0:615f90842ce8 484 ProtectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 485
MACRUM 0:615f90842ce8 486 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
MACRUM 0:615f90842ce8 487
MACRUM 0:615f90842ce8 488 gXcvrAssertCS_d();
MACRUM 0:615f90842ce8 489
MACRUM 0:615f90842ce8 490 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
MACRUM 0:615f90842ce8 491 txData |= (startAddress) << 8;
MACRUM 0:615f90842ce8 492
MACRUM 0:615f90842ce8 493 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
MACRUM 0:615f90842ce8 494 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
MACRUM 0:615f90842ce8 495
MACRUM 0:615f90842ce8 496 gXcvrDeassertCS_d();
MACRUM 0:615f90842ce8 497 UnprotectFromMCR20Interrupt();
MACRUM 0:615f90842ce8 498 }
MACRUM 0:615f90842ce8 499
MACRUM 0:615f90842ce8 500 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 501 * Name: MCR20Drv_IsIrqPending
MACRUM 0:615f90842ce8 502 * Description: -
MACRUM 0:615f90842ce8 503 * Parameters: -
MACRUM 0:615f90842ce8 504 * Return: -
MACRUM 0:615f90842ce8 505 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 506 uint32_t MCR20Drv_IsIrqPending
MACRUM 0:615f90842ce8 507 (
MACRUM 0:615f90842ce8 508 void
MACRUM 0:615f90842ce8 509 )
MACRUM 0:615f90842ce8 510 {
MACRUM 0:615f90842ce8 511 return RF_isIRQ_Pending();
MACRUM 0:615f90842ce8 512 }
MACRUM 0:615f90842ce8 513
MACRUM 0:615f90842ce8 514 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 515 * Name: MCR20Drv_IRQ_Disable
MACRUM 0:615f90842ce8 516 * Description: -
MACRUM 0:615f90842ce8 517 * Parameters: -
MACRUM 0:615f90842ce8 518 * Return: -
MACRUM 0:615f90842ce8 519 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 520 void MCR20Drv_IRQ_Disable
MACRUM 0:615f90842ce8 521 (
MACRUM 0:615f90842ce8 522 void
MACRUM 0:615f90842ce8 523 )
MACRUM 0:615f90842ce8 524 {
MACRUM 0:615f90842ce8 525 platform_enter_critical();
MACRUM 0:615f90842ce8 526
MACRUM 0:615f90842ce8 527 if( mPhyIrqDisableCnt == 0 )
MACRUM 0:615f90842ce8 528 {
MACRUM 0:615f90842ce8 529 RF_IRQ_Disable();
MACRUM 0:615f90842ce8 530 }
MACRUM 0:615f90842ce8 531
MACRUM 0:615f90842ce8 532 mPhyIrqDisableCnt++;
MACRUM 0:615f90842ce8 533
MACRUM 0:615f90842ce8 534 platform_exit_critical();
MACRUM 0:615f90842ce8 535 }
MACRUM 0:615f90842ce8 536
MACRUM 0:615f90842ce8 537 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 538 * Name: MCR20Drv_IRQ_Enable
MACRUM 0:615f90842ce8 539 * Description: -
MACRUM 0:615f90842ce8 540 * Parameters: -
MACRUM 0:615f90842ce8 541 * Return: -
MACRUM 0:615f90842ce8 542 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 543 void MCR20Drv_IRQ_Enable
MACRUM 0:615f90842ce8 544 (
MACRUM 0:615f90842ce8 545 void
MACRUM 0:615f90842ce8 546 )
MACRUM 0:615f90842ce8 547 {
MACRUM 0:615f90842ce8 548 platform_enter_critical();
MACRUM 0:615f90842ce8 549
MACRUM 0:615f90842ce8 550 if( mPhyIrqDisableCnt )
MACRUM 0:615f90842ce8 551 {
MACRUM 0:615f90842ce8 552 mPhyIrqDisableCnt--;
MACRUM 0:615f90842ce8 553
MACRUM 0:615f90842ce8 554 if( mPhyIrqDisableCnt == 0 )
MACRUM 0:615f90842ce8 555 {
MACRUM 0:615f90842ce8 556 RF_IRQ_Enable();
MACRUM 0:615f90842ce8 557 }
MACRUM 0:615f90842ce8 558 }
MACRUM 0:615f90842ce8 559
MACRUM 0:615f90842ce8 560 platform_exit_critical();
MACRUM 0:615f90842ce8 561 }
MACRUM 0:615f90842ce8 562
MACRUM 0:615f90842ce8 563 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 564 * Name: MCR20Drv_RST_Assert
MACRUM 0:615f90842ce8 565 * Description: -
MACRUM 0:615f90842ce8 566 * Parameters: -
MACRUM 0:615f90842ce8 567 * Return: -
MACRUM 0:615f90842ce8 568 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 569 void MCR20Drv_RST_B_Assert
MACRUM 0:615f90842ce8 570 (
MACRUM 0:615f90842ce8 571 void
MACRUM 0:615f90842ce8 572 )
MACRUM 0:615f90842ce8 573 {
MACRUM 0:615f90842ce8 574 RF_RST_Set(0);
MACRUM 0:615f90842ce8 575 }
MACRUM 0:615f90842ce8 576
MACRUM 0:615f90842ce8 577 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 578 * Name: MCR20Drv_RST_Deassert
MACRUM 0:615f90842ce8 579 * Description: -
MACRUM 0:615f90842ce8 580 * Parameters: -
MACRUM 0:615f90842ce8 581 * Return: -
MACRUM 0:615f90842ce8 582 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 583 void MCR20Drv_RST_B_Deassert
MACRUM 0:615f90842ce8 584 (
MACRUM 0:615f90842ce8 585 void
MACRUM 0:615f90842ce8 586 )
MACRUM 0:615f90842ce8 587 {
MACRUM 0:615f90842ce8 588 RF_RST_Set(1);
MACRUM 0:615f90842ce8 589 }
MACRUM 0:615f90842ce8 590
MACRUM 0:615f90842ce8 591 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 592 * Name: MCR20Drv_SoftRST_Assert
MACRUM 0:615f90842ce8 593 * Description: -
MACRUM 0:615f90842ce8 594 * Parameters: -
MACRUM 0:615f90842ce8 595 * Return: -
MACRUM 0:615f90842ce8 596 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 597 void MCR20Drv_SoftRST_Assert
MACRUM 0:615f90842ce8 598 (
MACRUM 0:615f90842ce8 599 void
MACRUM 0:615f90842ce8 600 )
MACRUM 0:615f90842ce8 601 {
MACRUM 0:615f90842ce8 602 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
MACRUM 0:615f90842ce8 603 }
MACRUM 0:615f90842ce8 604
MACRUM 0:615f90842ce8 605 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 606 * Name: MCR20Drv_SoftRST_Deassert
MACRUM 0:615f90842ce8 607 * Description: -
MACRUM 0:615f90842ce8 608 * Parameters: -
MACRUM 0:615f90842ce8 609 * Return: -
MACRUM 0:615f90842ce8 610 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 611 void MCR20Drv_SoftRST_Deassert
MACRUM 0:615f90842ce8 612 (
MACRUM 0:615f90842ce8 613 void
MACRUM 0:615f90842ce8 614 )
MACRUM 0:615f90842ce8 615 {
MACRUM 0:615f90842ce8 616 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
MACRUM 0:615f90842ce8 617 }
MACRUM 0:615f90842ce8 618
MACRUM 0:615f90842ce8 619 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 620 * Name: MCR20Drv_Soft_RESET
MACRUM 0:615f90842ce8 621 * Description: -
MACRUM 0:615f90842ce8 622 * Parameters: -
MACRUM 0:615f90842ce8 623 * Return: -
MACRUM 0:615f90842ce8 624 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 625 void MCR20Drv_Soft_RESET
MACRUM 0:615f90842ce8 626 (
MACRUM 0:615f90842ce8 627 void
MACRUM 0:615f90842ce8 628 )
MACRUM 0:615f90842ce8 629 {
MACRUM 0:615f90842ce8 630 //assert SOG_RST
MACRUM 0:615f90842ce8 631 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
MACRUM 0:615f90842ce8 632
MACRUM 0:615f90842ce8 633 //deassert SOG_RST
MACRUM 0:615f90842ce8 634 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
MACRUM 0:615f90842ce8 635 }
MACRUM 0:615f90842ce8 636
MACRUM 0:615f90842ce8 637 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 638 * Name: MCR20Drv_RESET
MACRUM 0:615f90842ce8 639 * Description: -
MACRUM 0:615f90842ce8 640 * Parameters: -
MACRUM 0:615f90842ce8 641 * Return: -
MACRUM 0:615f90842ce8 642 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 643 void MCR20Drv_RESET
MACRUM 0:615f90842ce8 644 (
MACRUM 0:615f90842ce8 645 void
MACRUM 0:615f90842ce8 646 )
MACRUM 0:615f90842ce8 647 {
MACRUM 0:615f90842ce8 648 #if !defined(TARGET_KW24D)
MACRUM 0:615f90842ce8 649 volatile uint32_t delay = 1000;
MACRUM 0:615f90842ce8 650 //assert RST_B
MACRUM 0:615f90842ce8 651 MCR20Drv_RST_B_Assert();
MACRUM 0:615f90842ce8 652
MACRUM 0:615f90842ce8 653 while(delay--);
MACRUM 0:615f90842ce8 654
MACRUM 0:615f90842ce8 655 //deassert RST_B
MACRUM 0:615f90842ce8 656 MCR20Drv_RST_B_Deassert();
MACRUM 0:615f90842ce8 657 #endif
MACRUM 0:615f90842ce8 658 }
MACRUM 0:615f90842ce8 659
MACRUM 0:615f90842ce8 660 /*---------------------------------------------------------------------------
MACRUM 0:615f90842ce8 661 * Name: MCR20Drv_Set_CLK_OUT_Freq
MACRUM 0:615f90842ce8 662 * Description: -
MACRUM 0:615f90842ce8 663 * Parameters: -
MACRUM 0:615f90842ce8 664 * Return: -
MACRUM 0:615f90842ce8 665 *---------------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 666 void MCR20Drv_Set_CLK_OUT_Freq
MACRUM 0:615f90842ce8 667 (
MACRUM 0:615f90842ce8 668 uint8_t freqDiv
MACRUM 0:615f90842ce8 669 )
MACRUM 0:615f90842ce8 670 {
MACRUM 0:615f90842ce8 671 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
MACRUM 0:615f90842ce8 672
MACRUM 0:615f90842ce8 673 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
MACRUM 0:615f90842ce8 674 {
MACRUM 0:615f90842ce8 675 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
MACRUM 0:615f90842ce8 676 }
MACRUM 0:615f90842ce8 677
MACRUM 0:615f90842ce8 678 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
MACRUM 0:615f90842ce8 679 }