Toyomasa Watarai / Mbed OS Mbed-example-WS-W27

Dependencies:   MMA7660 LM75B

easy-connect/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp@0:119624335925, 2018-06-30 (annotated)

Committer:
MACRUM
Date:
Sat Jun 30 01:40:30 2018 +0000
Revision:
0:119624335925
Initial commit

Who changed what in which revision?

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MACRUM 0:119624335925 1 /*
MACRUM 0:119624335925 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
MACRUM 0:119624335925 3 * SPDX-License-Identifier: Apache-2.0
MACRUM 0:119624335925 4 * Licensed under the Apache License, Version 2.0 (the License); you may
MACRUM 0:119624335925 5 * not use this file except in compliance with the License.
MACRUM 0:119624335925 6 * You may obtain a copy of the License at
MACRUM 0:119624335925 7 *
MACRUM 0:119624335925 8 * http://www.apache.org/licenses/LICENSE-2.0
MACRUM 0:119624335925 9 *
MACRUM 0:119624335925 10 * Unless required by applicable law or agreed to in writing, software
MACRUM 0:119624335925 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
MACRUM 0:119624335925 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MACRUM 0:119624335925 13 * See the License for the specific language governing permissions and
MACRUM 0:119624335925 14 * limitations under the License.
MACRUM 0:119624335925 15 */
MACRUM 0:119624335925 16 #include "NanostackRfPhyMcr20a.h"
MACRUM 0:119624335925 17
MACRUM 0:119624335925 18 #ifdef MBED_CONF_NANOSTACK_CONFIGURATION
MACRUM 0:119624335925 19
MACRUM 0:119624335925 20 #include "ns_types.h"
MACRUM 0:119624335925 21 #include "platform/arm_hal_interrupt.h"
MACRUM 0:119624335925 22 #include "nanostack/platform/arm_hal_phy.h"
MACRUM 0:119624335925 23 #include <string.h>
MACRUM 0:119624335925 24 #include "rtos.h"
MACRUM 0:119624335925 25
MACRUM 0:119624335925 26 /* Freescale headers which are for C files */
MACRUM 0:119624335925 27 extern "C" {
MACRUM 0:119624335925 28 #include "MCR20Drv.h"
MACRUM 0:119624335925 29 #include "MCR20Reg.h"
MACRUM 0:119624335925 30 #include "MCR20Overwrites.h"
MACRUM 0:119624335925 31 }
MACRUM 0:119624335925 32
MACRUM 0:119624335925 33
MACRUM 0:119624335925 34 #define RF_BUFFER_SIZE 128
MACRUM 0:119624335925 35
MACRUM 0:119624335925 36 /*Radio RX and TX state definitions*/
MACRUM 0:119624335925 37 #define RFF_ON 0x01
MACRUM 0:119624335925 38 #define RFF_RX 0x02
MACRUM 0:119624335925 39 #define RFF_TX 0x04
MACRUM 0:119624335925 40 #define RFF_CCA 0x08
MACRUM 0:119624335925 41
MACRUM 0:119624335925 42 #define RF_MODE_NORMAL 0
MACRUM 0:119624335925 43 #define RF_MODE_SNIFFER 1
MACRUM 0:119624335925 44
MACRUM 0:119624335925 45 #define RF_CCA_THRESHOLD 75 /* -75 dBm */
MACRUM 0:119624335925 46
MACRUM 0:119624335925 47 #define RF_TX_POWER_MAX 0
MACRUM 0:119624335925 48
MACRUM 0:119624335925 49 /* PHY constants in symbols */
MACRUM 0:119624335925 50 #define gPhyWarmUpTime_c 9
MACRUM 0:119624335925 51 #define gPhySHRDuration_c 10
MACRUM 0:119624335925 52 #define gPhySymbolsPerOctet_c 2
MACRUM 0:119624335925 53 #define gPhyAckWaitDuration_c 54
MACRUM 0:119624335925 54
MACRUM 0:119624335925 55 #define gCcaED_c 0
MACRUM 0:119624335925 56 #define gCcaCCA_MODE1_c 1
MACRUM 0:119624335925 57
MACRUM 0:119624335925 58 #define gXcvrRunState_d gXcvrPwrAutodoze_c
MACRUM 0:119624335925 59 #if !defined(TARGET_KW24D)
MACRUM 0:119624335925 60 #define gXcvrLowPowerState_d gXcvrPwrHibernate_c
MACRUM 0:119624335925 61 #else
MACRUM 0:119624335925 62 #define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
MACRUM 0:119624335925 63 #endif
MACRUM 0:119624335925 64
MACRUM 0:119624335925 65 /* MCR20A XCVR states */
MACRUM 0:119624335925 66 typedef enum xcvrState_tag{
MACRUM 0:119624335925 67 gIdle_c,
MACRUM 0:119624335925 68 gRX_c,
MACRUM 0:119624335925 69 gTX_c,
MACRUM 0:119624335925 70 gCCA_c,
MACRUM 0:119624335925 71 gTR_c,
MACRUM 0:119624335925 72 gCCCA_c,
MACRUM 0:119624335925 73 }xcvrState_t;
MACRUM 0:119624335925 74
MACRUM 0:119624335925 75 /* MCR20A XCVR low power states */
MACRUM 0:119624335925 76 typedef enum xcvrPwrMode_tag{
MACRUM 0:119624335925 77 gXcvrPwrIdle_c,
MACRUM 0:119624335925 78 gXcvrPwrAutodoze_c,
MACRUM 0:119624335925 79 gXcvrPwrDoze_c,
MACRUM 0:119624335925 80 gXcvrPwrHibernate_c
MACRUM 0:119624335925 81 }xcvrPwrMode_t;
MACRUM 0:119624335925 82
MACRUM 0:119624335925 83
MACRUM 0:119624335925 84 /*RF Part Type*/
MACRUM 0:119624335925 85 typedef enum
MACRUM 0:119624335925 86 {
MACRUM 0:119624335925 87 FREESCALE_UNKNOW_DEV = 0,
MACRUM 0:119624335925 88 FREESCALE_MCR20A
MACRUM 0:119624335925 89 }rf_trx_part_e;
MACRUM 0:119624335925 90
MACRUM 0:119624335925 91 /*Atmel RF states*/
MACRUM 0:119624335925 92 typedef enum
MACRUM 0:119624335925 93 {
MACRUM 0:119624335925 94 NOP = 0x00,
MACRUM 0:119624335925 95 BUSY_RX = 0x01,
MACRUM 0:119624335925 96 RF_TX_START = 0x02,
MACRUM 0:119624335925 97 FORCE_TRX_OFF = 0x03,
MACRUM 0:119624335925 98 FORCE_PLL_ON = 0x04,
MACRUM 0:119624335925 99 RX_ON = 0x06,
MACRUM 0:119624335925 100 TRX_OFF = 0x08,
MACRUM 0:119624335925 101 PLL_ON = 0x09,
MACRUM 0:119624335925 102 BUSY_RX_AACK = 0x11,
MACRUM 0:119624335925 103 SLEEP = 0x0F,
MACRUM 0:119624335925 104 RX_AACK_ON = 0x16,
MACRUM 0:119624335925 105 TX_ARET_ON = 0x19
MACRUM 0:119624335925 106 }rf_trx_states_t;
MACRUM 0:119624335925 107
MACRUM 0:119624335925 108 /*RF receive buffer*/
MACRUM 0:119624335925 109 static uint8_t rf_buffer[RF_BUFFER_SIZE];
MACRUM 0:119624335925 110
MACRUM 0:119624335925 111 /* TX info */
MACRUM 0:119624335925 112 static uint8_t radio_tx_power = 0x17; /* 0 dBm */
MACRUM 0:119624335925 113 static uint8_t mac_tx_handle = 0;
MACRUM 0:119624335925 114 static uint8_t need_ack = 0;
MACRUM 0:119624335925 115 static uint16_t tx_len = 0;
MACRUM 0:119624335925 116
MACRUM 0:119624335925 117 /* RF driver data */
MACRUM 0:119624335925 118 static xcvrState_t mPhySeqState;
MACRUM 0:119624335925 119 static xcvrPwrMode_t mPwrState;
MACRUM 0:119624335925 120 static phy_device_driver_s device_driver;
MACRUM 0:119624335925 121 static uint8_t mStatusAndControlRegs[8];
MACRUM 0:119624335925 122 static uint8_t rf_rnd = 0;
MACRUM 0:119624335925 123 static int8_t rf_radio_driver_id = -1;
MACRUM 0:119624335925 124 static uint8_t MAC_address[8] = {1, 2, 3, 4, 5, 6, 7, 8};
MACRUM 0:119624335925 125
MACRUM 0:119624335925 126 /* Driver instance handle and hardware */
MACRUM 0:119624335925 127 static NanostackRfPhyMcr20a *rf = NULL;
MACRUM 0:119624335925 128 static SPI *spi = NULL;
MACRUM 0:119624335925 129 static DigitalOut *cs = NULL;
MACRUM 0:119624335925 130 static DigitalOut *rst = NULL;
MACRUM 0:119624335925 131 static InterruptIn *irq = NULL;
MACRUM 0:119624335925 132 static DigitalIn *irq_pin = NULL;
MACRUM 0:119624335925 133 static Thread irq_thread(osPriorityRealtime, 1024);
MACRUM 0:119624335925 134
MACRUM 0:119624335925 135 /* Channel info */ /* 2405 2410 2415 2420 2425 2430 2435 2440 2445 2450 2455 2460 2465 2470 2475 2480 */
MACRUM 0:119624335925 136 static const uint8_t pll_int[16] = {0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D};
MACRUM 0:119624335925 137 static const uint16_t pll_frac[16] = {0x2800, 0x5000, 0x7800, 0xA000, 0xC800, 0xF000, 0x1800, 0x4000, 0x6800, 0x9000, 0xB800, 0xE000, 0x0800, 0x3000, 0x5800, 0x8000};
MACRUM 0:119624335925 138
MACRUM 0:119624335925 139 /* Channel configurations for 2.4 */
MACRUM 0:119624335925 140 static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
MACRUM 0:119624335925 141
MACRUM 0:119624335925 142 static const phy_device_channel_page_s phy_channel_pages[] = {
MACRUM 0:119624335925 143 { CHANNEL_PAGE_0, &phy_24ghz},
MACRUM 0:119624335925 144 { CHANNEL_PAGE_0, NULL}
MACRUM 0:119624335925 145 };
MACRUM 0:119624335925 146
MACRUM 0:119624335925 147
MACRUM 0:119624335925 148 static rf_trx_part_e rf_radio_type_read(void);
MACRUM 0:119624335925 149
MACRUM 0:119624335925 150 MBED_UNUSED static void rf_ack_wait_timer_start(uint16_t slots);
MACRUM 0:119624335925 151 MBED_UNUSED static void rf_ack_wait_timer_stop(void);
MACRUM 0:119624335925 152 MBED_UNUSED static void rf_handle_cca_ed_done(void);
MACRUM 0:119624335925 153 MBED_UNUSED static void rf_handle_tx_end(void);
MACRUM 0:119624335925 154 MBED_UNUSED static void rf_handle_rx_end(void);
MACRUM 0:119624335925 155 MBED_UNUSED static void rf_on(void);
MACRUM 0:119624335925 156 MBED_UNUSED static void rf_receive(void);
MACRUM 0:119624335925 157 MBED_UNUSED static void rf_poll_trx_state_change(rf_trx_states_t trx_state);
MACRUM 0:119624335925 158 MBED_UNUSED static void rf_init(void);
MACRUM 0:119624335925 159 MBED_UNUSED static void rf_set_mac_address(const uint8_t *ptr);
MACRUM 0:119624335925 160 MBED_UNUSED static int8_t rf_device_register(void);
MACRUM 0:119624335925 161 MBED_UNUSED static void rf_device_unregister(void);
MACRUM 0:119624335925 162 MBED_UNUSED static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
MACRUM 0:119624335925 163 MBED_UNUSED static void rf_cca_abort(void);
MACRUM 0:119624335925 164 MBED_UNUSED static void rf_read_mac_address(uint8_t *ptr);
MACRUM 0:119624335925 165 MBED_UNUSED static int8_t rf_read_random(void);
MACRUM 0:119624335925 166 MBED_UNUSED static void rf_calibration_cb(void);
MACRUM 0:119624335925 167 MBED_UNUSED static void rf_init_phy_mode(void);
MACRUM 0:119624335925 168 MBED_UNUSED static void rf_ack_wait_timer_interrupt(void);
MACRUM 0:119624335925 169 MBED_UNUSED static void rf_calibration_timer_interrupt(void);
MACRUM 0:119624335925 170 MBED_UNUSED static void rf_calibration_timer_start(uint32_t slots);
MACRUM 0:119624335925 171 MBED_UNUSED static void rf_cca_timer_interrupt(void);
MACRUM 0:119624335925 172 MBED_UNUSED static void rf_cca_timer_start(uint32_t slots);
MACRUM 0:119624335925 173 MBED_UNUSED static uint16_t rf_get_phy_mtu_size(void);
MACRUM 0:119624335925 174 MBED_UNUSED static uint8_t rf_scale_lqi(int8_t rssi);
MACRUM 0:119624335925 175
MACRUM 0:119624335925 176 /**
MACRUM 0:119624335925 177 * RF output power write
MACRUM 0:119624335925 178 *
MACRUM 0:119624335925 179 * \brief TX power has to be set before network start.
MACRUM 0:119624335925 180 *
MACRUM 0:119624335925 181 * \param power
MACRUM 0:119624335925 182 * See datasheet for TX power settings
MACRUM 0:119624335925 183 *
MACRUM 0:119624335925 184 * \return 0, Supported Value
MACRUM 0:119624335925 185 * \return -1, Not Supported Value
MACRUM 0:119624335925 186 */
MACRUM 0:119624335925 187 MBED_UNUSED static int8_t rf_tx_power_set(uint8_t power);
MACRUM 0:119624335925 188 MBED_UNUSED static uint8_t rf_tx_power_get(void);
MACRUM 0:119624335925 189 MBED_UNUSED static int8_t rf_enable_antenna_diversity(void);
MACRUM 0:119624335925 190
MACRUM 0:119624335925 191 /* Private functions */
MACRUM 0:119624335925 192 MBED_UNUSED static void rf_abort(void);
MACRUM 0:119624335925 193 MBED_UNUSED static void rf_promiscuous(uint8_t mode);
MACRUM 0:119624335925 194 MBED_UNUSED static void rf_get_timestamp(uint32_t *pRetClk);
MACRUM 0:119624335925 195 MBED_UNUSED static void rf_set_timeout(uint32_t *pEndTime);
MACRUM 0:119624335925 196 MBED_UNUSED static void rf_set_power_state(xcvrPwrMode_t newState);
MACRUM 0:119624335925 197 MBED_UNUSED static uint8_t rf_if_read_rnd(void);
MACRUM 0:119624335925 198 MBED_UNUSED static uint8_t rf_convert_LQI(uint8_t hwLqi);
MACRUM 0:119624335925 199 MBED_UNUSED static uint8_t rf_get_channel_energy(void);
MACRUM 0:119624335925 200 MBED_UNUSED static uint8_t rf_convert_energy_level(uint8_t energyLevel);
MACRUM 0:119624335925 201 MBED_UNUSED static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi);
MACRUM 0:119624335925 202 MBED_UNUSED static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
MACRUM 0:119624335925 203 MBED_UNUSED static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
MACRUM 0:119624335925 204 MBED_UNUSED static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
MACRUM 0:119624335925 205 MBED_UNUSED static void rf_mac64_read(uint8_t *address);
MACRUM 0:119624335925 206 static void PHY_InterruptThread(void);
MACRUM 0:119624335925 207 static void handle_interrupt(void);
MACRUM 0:119624335925 208
MACRUM 0:119624335925 209
MACRUM 0:119624335925 210 /*
MACRUM 0:119624335925 211 * \brief Read connected radio part.
MACRUM 0:119624335925 212 *
MACRUM 0:119624335925 213 * This function only return valid information when rf_init() is called
MACRUM 0:119624335925 214 *
MACRUM 0:119624335925 215 * \return
MACRUM 0:119624335925 216 */
MACRUM 0:119624335925 217 static rf_trx_part_e rf_radio_type_read(void)
MACRUM 0:119624335925 218 {
MACRUM 0:119624335925 219 return FREESCALE_MCR20A;
MACRUM 0:119624335925 220 }
MACRUM 0:119624335925 221
MACRUM 0:119624335925 222 /*
MACRUM 0:119624335925 223 * \brief Function initialises and registers the RF driver.
MACRUM 0:119624335925 224 *
MACRUM 0:119624335925 225 * \param none
MACRUM 0:119624335925 226 *
MACRUM 0:119624335925 227 * \return rf_radio_driver_id Driver ID given by NET library
MACRUM 0:119624335925 228 */
MACRUM 0:119624335925 229 static int8_t rf_device_register(void)
MACRUM 0:119624335925 230 {
MACRUM 0:119624335925 231 rf_trx_part_e radio_type;
MACRUM 0:119624335925 232
MACRUM 0:119624335925 233 rf_init();
MACRUM 0:119624335925 234
MACRUM 0:119624335925 235
MACRUM 0:119624335925 236
MACRUM 0:119624335925 237 radio_type = rf_radio_type_read();
MACRUM 0:119624335925 238 if(radio_type == FREESCALE_MCR20A)
MACRUM 0:119624335925 239 {
MACRUM 0:119624335925 240 /*Set pointer to MAC address*/
MACRUM 0:119624335925 241 device_driver.PHY_MAC = MAC_address;
MACRUM 0:119624335925 242 device_driver.driver_description = (char*)"FREESCALE_MAC";
MACRUM 0:119624335925 243
MACRUM 0:119624335925 244 //Create setup Used Radio chips
MACRUM 0:119624335925 245 /*Type of RF PHY is SubGHz*/
MACRUM 0:119624335925 246 device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
MACRUM 0:119624335925 247
MACRUM 0:119624335925 248 device_driver.phy_channel_pages = phy_channel_pages;
MACRUM 0:119624335925 249 /*Maximum size of payload is 127*/
MACRUM 0:119624335925 250 device_driver.phy_MTU = 127;
MACRUM 0:119624335925 251 /*No header in PHY*/
MACRUM 0:119624335925 252 device_driver.phy_header_length = 0;
MACRUM 0:119624335925 253 /*No tail in PHY*/
MACRUM 0:119624335925 254 device_driver.phy_tail_length = 0;
MACRUM 0:119624335925 255 /*Set address write function*/
MACRUM 0:119624335925 256 device_driver.address_write = &rf_address_write;
MACRUM 0:119624335925 257 /*Set RF extension function*/
MACRUM 0:119624335925 258 device_driver.extension = &rf_extension;
MACRUM 0:119624335925 259 /*Set RF state control function*/
MACRUM 0:119624335925 260 device_driver.state_control = &rf_interface_state_control;
MACRUM 0:119624335925 261 /*Set transmit function*/
MACRUM 0:119624335925 262 device_driver.tx = &rf_start_cca;
MACRUM 0:119624335925 263 /*Upper layer callbacks init to NULL*/
MACRUM 0:119624335925 264 device_driver.phy_rx_cb = NULL;
MACRUM 0:119624335925 265 device_driver.phy_tx_done_cb = NULL;
MACRUM 0:119624335925 266 /*Virtual upper data callback init to NULL*/
MACRUM 0:119624335925 267 device_driver.arm_net_virtual_rx_cb = NULL;
MACRUM 0:119624335925 268 device_driver.arm_net_virtual_tx_cb = NULL;
MACRUM 0:119624335925 269
MACRUM 0:119624335925 270 /*Register device driver*/
MACRUM 0:119624335925 271 rf_radio_driver_id = arm_net_phy_register(&device_driver);
MACRUM 0:119624335925 272 }
MACRUM 0:119624335925 273
MACRUM 0:119624335925 274 return rf_radio_driver_id;
MACRUM 0:119624335925 275 }
MACRUM 0:119624335925 276
MACRUM 0:119624335925 277 /*
MACRUM 0:119624335925 278 * \brief Function unregisters the RF driver.
MACRUM 0:119624335925 279 *
MACRUM 0:119624335925 280 * \param none
MACRUM 0:119624335925 281 *
MACRUM 0:119624335925 282 * \return none
MACRUM 0:119624335925 283 */
MACRUM 0:119624335925 284 static void rf_device_unregister(void)
MACRUM 0:119624335925 285 {
MACRUM 0:119624335925 286 arm_net_phy_unregister(rf_radio_driver_id);
MACRUM 0:119624335925 287 }
MACRUM 0:119624335925 288
MACRUM 0:119624335925 289 /*
MACRUM 0:119624335925 290 * \brief Function returns the generated 8-bit random value for seeding Pseudo-random generator.
MACRUM 0:119624335925 291 *
MACRUM 0:119624335925 292 * \param none
MACRUM 0:119624335925 293 *
MACRUM 0:119624335925 294 * \return random value
MACRUM 0:119624335925 295 */
MACRUM 0:119624335925 296 static int8_t rf_read_random(void)
MACRUM 0:119624335925 297 {
MACRUM 0:119624335925 298 return rf_rnd;
MACRUM 0:119624335925 299 }
MACRUM 0:119624335925 300
MACRUM 0:119624335925 301 /*
MACRUM 0:119624335925 302 * \brief Function is a call back for ACK wait timeout.
MACRUM 0:119624335925 303 *
MACRUM 0:119624335925 304 * \param none
MACRUM 0:119624335925 305 *
MACRUM 0:119624335925 306 * \return none
MACRUM 0:119624335925 307 */
MACRUM 0:119624335925 308 static void rf_ack_wait_timer_interrupt(void)
MACRUM 0:119624335925 309 {
MACRUM 0:119624335925 310 /* The packet was transmitted successfully, but no ACK was received */
MACRUM 0:119624335925 311 if (device_driver.phy_tx_done_cb) {
MACRUM 0:119624335925 312 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
MACRUM 0:119624335925 313 }
MACRUM 0:119624335925 314 rf_receive();
MACRUM 0:119624335925 315 }
MACRUM 0:119624335925 316
MACRUM 0:119624335925 317 /*
MACRUM 0:119624335925 318 * \brief Function is a call back for calibration interval timer.
MACRUM 0:119624335925 319 *
MACRUM 0:119624335925 320 * \param none
MACRUM 0:119624335925 321 *
MACRUM 0:119624335925 322 * \return none
MACRUM 0:119624335925 323 */
MACRUM 0:119624335925 324 static void rf_calibration_timer_interrupt(void)
MACRUM 0:119624335925 325 {
MACRUM 0:119624335925 326 }
MACRUM 0:119624335925 327
MACRUM 0:119624335925 328 /*
MACRUM 0:119624335925 329 * \brief Function is a call back for cca interval timer.
MACRUM 0:119624335925 330 *
MACRUM 0:119624335925 331 * \param none
MACRUM 0:119624335925 332 *
MACRUM 0:119624335925 333 * \return none
MACRUM 0:119624335925 334 */
MACRUM 0:119624335925 335 static void rf_cca_timer_interrupt(void)
MACRUM 0:119624335925 336 {
MACRUM 0:119624335925 337 /* CCA time-out handled by Hardware */
MACRUM 0:119624335925 338 }
MACRUM 0:119624335925 339
MACRUM 0:119624335925 340
MACRUM 0:119624335925 341 /*
MACRUM 0:119624335925 342 * \brief Function starts the ACK wait time-out.
MACRUM 0:119624335925 343 *
MACRUM 0:119624335925 344 * \param slots The ACK wait time-out in [symbols]
MACRUM 0:119624335925 345 *
MACRUM 0:119624335925 346 * \return none
MACRUM 0:119624335925 347 */
MACRUM 0:119624335925 348 static void rf_ack_wait_timer_start(uint16_t time)
MACRUM 0:119624335925 349 {
MACRUM 0:119624335925 350 uint32_t timeout;
MACRUM 0:119624335925 351
MACRUM 0:119624335925 352 rf_get_timestamp(&timeout);
MACRUM 0:119624335925 353 timeout += time;
MACRUM 0:119624335925 354 rf_set_timeout(&timeout);
MACRUM 0:119624335925 355 }
MACRUM 0:119624335925 356
MACRUM 0:119624335925 357 /*
MACRUM 0:119624335925 358 * \brief Function starts the calibration interval.
MACRUM 0:119624335925 359 *
MACRUM 0:119624335925 360 * \param slots Given slots, resolution 50us
MACRUM 0:119624335925 361 *
MACRUM 0:119624335925 362 * \return none
MACRUM 0:119624335925 363 */
MACRUM 0:119624335925 364 static void rf_calibration_timer_start(uint32_t slots)
MACRUM 0:119624335925 365 {
MACRUM 0:119624335925 366 (void)slots;
MACRUM 0:119624335925 367 }
MACRUM 0:119624335925 368
MACRUM 0:119624335925 369 /*
MACRUM 0:119624335925 370 * \brief Function starts the CCA timout.
MACRUM 0:119624335925 371 *
MACRUM 0:119624335925 372 * \param slots Given slots, resolution 50us
MACRUM 0:119624335925 373 *
MACRUM 0:119624335925 374 * \return none
MACRUM 0:119624335925 375 */
MACRUM 0:119624335925 376 static void rf_cca_timer_start(uint32_t slots)
MACRUM 0:119624335925 377 {
MACRUM 0:119624335925 378 (void)slots;
MACRUM 0:119624335925 379 }
MACRUM 0:119624335925 380
MACRUM 0:119624335925 381 /*
MACRUM 0:119624335925 382 * \brief Function stops the ACK wait timeout.
MACRUM 0:119624335925 383 *
MACRUM 0:119624335925 384 * \param none
MACRUM 0:119624335925 385 *
MACRUM 0:119624335925 386 * \return none
MACRUM 0:119624335925 387 */
MACRUM 0:119624335925 388 static void rf_ack_wait_timer_stop(void)
MACRUM 0:119624335925 389 {
MACRUM 0:119624335925 390 }
MACRUM 0:119624335925 391
MACRUM 0:119624335925 392 /*
MACRUM 0:119624335925 393 * \brief Function reads the MAC address array.
MACRUM 0:119624335925 394 *
MACRUM 0:119624335925 395 * \param ptr Pointer to read array
MACRUM 0:119624335925 396 *
MACRUM 0:119624335925 397 * \return none
MACRUM 0:119624335925 398 */
MACRUM 0:119624335925 399 static void rf_read_mac_address(uint8_t *ptr)
MACRUM 0:119624335925 400 {
MACRUM 0:119624335925 401 memcpy(ptr, MAC_address, 8);
MACRUM 0:119624335925 402 }
MACRUM 0:119624335925 403
MACRUM 0:119624335925 404 /*
MACRUM 0:119624335925 405 * \brief Function sets the MAC address array.
MACRUM 0:119624335925 406 *
MACRUM 0:119624335925 407 * \param ptr Pointer to given MAC address array
MACRUM 0:119624335925 408 *
MACRUM 0:119624335925 409 * \return none
MACRUM 0:119624335925 410 */
MACRUM 0:119624335925 411 static void rf_set_mac_address(const uint8_t *ptr)
MACRUM 0:119624335925 412 {
MACRUM 0:119624335925 413 memcpy(MAC_address, ptr, 8);
MACRUM 0:119624335925 414 }
MACRUM 0:119624335925 415
MACRUM 0:119624335925 416 static uint16_t rf_get_phy_mtu_size(void)
MACRUM 0:119624335925 417 {
MACRUM 0:119624335925 418 return device_driver.phy_MTU;
MACRUM 0:119624335925 419 }
MACRUM 0:119624335925 420
MACRUM 0:119624335925 421 /*
MACRUM 0:119624335925 422 * \brief Function writes 16-bit address in RF address filter.
MACRUM 0:119624335925 423 *
MACRUM 0:119624335925 424 * \param short_address Given short address
MACRUM 0:119624335925 425 *
MACRUM 0:119624335925 426 * \return none
MACRUM 0:119624335925 427 */
MACRUM 0:119624335925 428 static void rf_set_short_adr(uint8_t * short_address)
MACRUM 0:119624335925 429 {
MACRUM 0:119624335925 430 /* Write one register at a time to be accessible from hibernate mode */
MACRUM 0:119624335925 431 MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_MSB, short_address[0]);
MACRUM 0:119624335925 432 MCR20Drv_IndirectAccessSPIWrite(MACSHORTADDRS0_LSB, short_address[1]);
MACRUM 0:119624335925 433 }
MACRUM 0:119624335925 434
MACRUM 0:119624335925 435 /*
MACRUM 0:119624335925 436 * \brief Function writes PAN Id in RF PAN Id filter.
MACRUM 0:119624335925 437 *
MACRUM 0:119624335925 438 * \param pan_id Given PAN Id
MACRUM 0:119624335925 439 *
MACRUM 0:119624335925 440 * \return none
MACRUM 0:119624335925 441 */
MACRUM 0:119624335925 442 static void rf_set_pan_id(uint8_t *pan_id)
MACRUM 0:119624335925 443 {
MACRUM 0:119624335925 444 /* Write one register at a time to be accessible from hibernate mode */
MACRUM 0:119624335925 445 MCR20Drv_IndirectAccessSPIWrite(MACPANID0_MSB, pan_id[0]);
MACRUM 0:119624335925 446 MCR20Drv_IndirectAccessSPIWrite(MACPANID0_LSB, pan_id[1]);
MACRUM 0:119624335925 447 }
MACRUM 0:119624335925 448
MACRUM 0:119624335925 449 /*
MACRUM 0:119624335925 450 * \brief Function writes 64-bit address in RF address filter.
MACRUM 0:119624335925 451 *
MACRUM 0:119624335925 452 * \param address Given 64-bit address
MACRUM 0:119624335925 453 *
MACRUM 0:119624335925 454 * \return none
MACRUM 0:119624335925 455 */
MACRUM 0:119624335925 456 static void rf_set_address(uint8_t *address)
MACRUM 0:119624335925 457 {
MACRUM 0:119624335925 458 /* Write one register at a time to be accessible from hibernate mode */
MACRUM 0:119624335925 459 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_0, address[7]);
MACRUM 0:119624335925 460 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_8, address[6]);
MACRUM 0:119624335925 461 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_16, address[5]);
MACRUM 0:119624335925 462 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_24, address[4]);
MACRUM 0:119624335925 463 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_32, address[3]);
MACRUM 0:119624335925 464 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_40, address[2]);
MACRUM 0:119624335925 465 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_48, address[1]);
MACRUM 0:119624335925 466 MCR20Drv_IndirectAccessSPIWrite(MACLONGADDRS0_56, address[0]);
MACRUM 0:119624335925 467 }
MACRUM 0:119624335925 468
MACRUM 0:119624335925 469 /*
MACRUM 0:119624335925 470 * \brief Function sets the RF channel.
MACRUM 0:119624335925 471 *
MACRUM 0:119624335925 472 * \param ch New channel
MACRUM 0:119624335925 473 *
MACRUM 0:119624335925 474 * \return none
MACRUM 0:119624335925 475 */
MACRUM 0:119624335925 476 static void rf_channel_set(uint8_t channel)
MACRUM 0:119624335925 477 {
MACRUM 0:119624335925 478 MCR20Drv_DirectAccessSPIWrite(PLL_INT0, pll_int[channel - 11]);
MACRUM 0:119624335925 479 MCR20Drv_DirectAccessSPIMultiByteWrite(PLL_FRAC0_LSB, (uint8_t *) &pll_frac[channel - 11], 2);
MACRUM 0:119624335925 480 }
MACRUM 0:119624335925 481
MACRUM 0:119624335925 482
MACRUM 0:119624335925 483 /*
MACRUM 0:119624335925 484 * \brief Function initialises the radio driver and resets the radio.
MACRUM 0:119624335925 485 *
MACRUM 0:119624335925 486 * \param none
MACRUM 0:119624335925 487 *
MACRUM 0:119624335925 488 * \return none
MACRUM 0:119624335925 489 */
MACRUM 0:119624335925 490 static void rf_init(void)
MACRUM 0:119624335925 491 {
MACRUM 0:119624335925 492 uint32_t index;
MACRUM 0:119624335925 493 mPhySeqState = gIdle_c;
MACRUM 0:119624335925 494 mPwrState = gXcvrPwrIdle_c;
MACRUM 0:119624335925 495 /*Reset RF module*/
MACRUM 0:119624335925 496 MCR20Drv_RESET();
MACRUM 0:119624335925 497 /* Initialize the transceiver SPI driver */
MACRUM 0:119624335925 498 MCR20Drv_Init();
MACRUM 0:119624335925 499 /* Disable Tristate on MISO for SPI reads */
MACRUM 0:119624335925 500 MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02);
MACRUM 0:119624335925 501 /* Set XCVR clock output settings */
MACRUM 0:119624335925 502 #if !defined(TARGET_KW24D)
MACRUM 0:119624335925 503 MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
MACRUM 0:119624335925 504 #endif
MACRUM 0:119624335925 505 /* Set default XCVR power state */
MACRUM 0:119624335925 506 rf_set_power_state(gXcvrRunState_d);
MACRUM 0:119624335925 507
MACRUM 0:119624335925 508 /* PHY_CTRL1 default HW settings + AUTOACK enabled */
MACRUM 0:119624335925 509 mStatusAndControlRegs[PHY_CTRL1] = cPHY_CTRL1_AUTOACK;
MACRUM 0:119624335925 510 /* PHY_CTRL2 : mask all PP interrupts */
MACRUM 0:119624335925 511 mStatusAndControlRegs[PHY_CTRL2] = cPHY_CTRL2_CRC_MSK | \
MACRUM 0:119624335925 512 cPHY_CTRL2_PLL_UNLOCK_MSK | \
MACRUM 0:119624335925 513 /*cPHY_CTRL2_FILTERFAIL_MSK | */ \
MACRUM 0:119624335925 514 cPHY_CTRL2_RX_WMRK_MSK | \
MACRUM 0:119624335925 515 cPHY_CTRL2_CCAMSK | \
MACRUM 0:119624335925 516 cPHY_CTRL2_RXMSK | \
MACRUM 0:119624335925 517 cPHY_CTRL2_TXMSK | \
MACRUM 0:119624335925 518 cPHY_CTRL2_SEQMSK;
MACRUM 0:119624335925 519 /* PHY_CTRL3 : enable timer 3 and disable remaining interrupts */
MACRUM 0:119624335925 520 mStatusAndControlRegs[PHY_CTRL3] = cPHY_CTRL3_ASM_MSK | \
MACRUM 0:119624335925 521 cPHY_CTRL3_PB_ERR_MSK | \
MACRUM 0:119624335925 522 cPHY_CTRL3_WAKE_MSK | \
MACRUM 0:119624335925 523 cPHY_CTRL3_TMR3CMP_EN;
MACRUM 0:119624335925 524 /* PHY_CTRL4 unmask global TRX interrupts, enable 16 bit mode for TC2 - TC2 prime EN */
MACRUM 0:119624335925 525 mStatusAndControlRegs[PHY_CTRL4] = cPHY_CTRL4_TC2PRIME_EN | (gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c);
MACRUM 0:119624335925 526 /* Clear all PP IRQ bits to avoid unexpected interrupts immediately after initialization */
MACRUM 0:119624335925 527 mStatusAndControlRegs[IRQSTS1] = cIRQSTS1_PLL_UNLOCK_IRQ | \
MACRUM 0:119624335925 528 cIRQSTS1_FILTERFAIL_IRQ | \
MACRUM 0:119624335925 529 cIRQSTS1_RXWTRMRKIRQ | \
MACRUM 0:119624335925 530 cIRQSTS1_CCAIRQ | \
MACRUM 0:119624335925 531 cIRQSTS1_RXIRQ | \
MACRUM 0:119624335925 532 cIRQSTS1_TXIRQ | \
MACRUM 0:119624335925 533 cIRQSTS1_SEQIRQ;
MACRUM 0:119624335925 534
MACRUM 0:119624335925 535 mStatusAndControlRegs[IRQSTS2] = cIRQSTS2_ASM_IRQ | cIRQSTS2_PB_ERR_IRQ | cIRQSTS2_WAKE_IRQ;
MACRUM 0:119624335925 536 /* Mask and clear all TMR IRQs */
MACRUM 0:119624335925 537 mStatusAndControlRegs[IRQSTS3] = cIRQSTS3_TMR4MSK | cIRQSTS3_TMR3MSK | cIRQSTS3_TMR2MSK | cIRQSTS3_TMR1MSK | \
MACRUM 0:119624335925 538 cIRQSTS3_TMR4IRQ | cIRQSTS3_TMR3IRQ | cIRQSTS3_TMR2IRQ | cIRQSTS3_TMR1IRQ;
MACRUM 0:119624335925 539 /* Write settings to XCVR */
MACRUM 0:119624335925 540 MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 5);
MACRUM 0:119624335925 541 /* Clear all interrupts */
MACRUM 0:119624335925 542 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, &mStatusAndControlRegs[IRQSTS1], 3);
MACRUM 0:119624335925 543
MACRUM 0:119624335925 544 /* RX_FRAME_FILTER. Accept FrameVersion 0 and 1 packets, reject all others */
MACRUM 0:119624335925 545 MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, (cRX_FRAME_FLT_FRM_VER | \
MACRUM 0:119624335925 546 cRX_FRAME_FLT_BEACON_FT | \
MACRUM 0:119624335925 547 cRX_FRAME_FLT_DATA_FT | \
MACRUM 0:119624335925 548 cRX_FRAME_FLT_CMD_FT ));
MACRUM 0:119624335925 549 /* Direct register overwrites */
MACRUM 0:119624335925 550 for (index = 0; index < sizeof(overwrites_direct)/sizeof(overwrites_t); index++)
MACRUM 0:119624335925 551 MCR20Drv_DirectAccessSPIWrite(overwrites_direct[index].address, overwrites_direct[index].data);
MACRUM 0:119624335925 552 /* Indirect register overwrites */
MACRUM 0:119624335925 553 for (index = 0; index < sizeof(overwrites_indirect)/sizeof(overwrites_t); index++)
MACRUM 0:119624335925 554 MCR20Drv_IndirectAccessSPIWrite(overwrites_indirect[index].address, overwrites_indirect[index].data);
MACRUM 0:119624335925 555
MACRUM 0:119624335925 556 /* Set the CCA energy threshold value */
MACRUM 0:119624335925 557 MCR20Drv_IndirectAccessSPIWrite(CCA1_THRESH, RF_CCA_THRESHOLD);
MACRUM 0:119624335925 558 /* Set prescaller to obtain 1 symbol (16us) timebase */
MACRUM 0:119624335925 559 MCR20Drv_IndirectAccessSPIWrite(TMR_PRESCALE, 0x05);
MACRUM 0:119624335925 560
MACRUM 0:119624335925 561 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 562
MACRUM 0:119624335925 563 /*Read random variable. This will be used when seeding pseudo-random generator*/
MACRUM 0:119624335925 564 rf_rnd = rf_if_read_rnd();
MACRUM 0:119624335925 565 /*Read eui64*/
MACRUM 0:119624335925 566 rf_mac64_read(MAC_address);
MACRUM 0:119624335925 567 /*set default channel to 11*/
MACRUM 0:119624335925 568 rf_channel_set(11);
MACRUM 0:119624335925 569 /*Start receiver*/
MACRUM 0:119624335925 570 rf_receive();
MACRUM 0:119624335925 571 }
MACRUM 0:119624335925 572
MACRUM 0:119624335925 573 /**
MACRUM 0:119624335925 574 * \brief Function gets called when MAC is setting radio off.
MACRUM 0:119624335925 575 *
MACRUM 0:119624335925 576 * \param none
MACRUM 0:119624335925 577 *
MACRUM 0:119624335925 578 * \return none
MACRUM 0:119624335925 579 */
MACRUM 0:119624335925 580 static void rf_off(void)
MACRUM 0:119624335925 581 {
MACRUM 0:119624335925 582 /* Abort any ongoing sequences */
MACRUM 0:119624335925 583 rf_abort();
MACRUM 0:119624335925 584 /* Set XCVR in a low power state */
MACRUM 0:119624335925 585 rf_set_power_state(gXcvrLowPowerState_d);
MACRUM 0:119624335925 586 }
MACRUM 0:119624335925 587
MACRUM 0:119624335925 588 /*
MACRUM 0:119624335925 589 * \brief Function polls the RF state until it has changed to desired state.
MACRUM 0:119624335925 590 *
MACRUM 0:119624335925 591 * \param trx_state RF state
MACRUM 0:119624335925 592 *
MACRUM 0:119624335925 593 * \return none
MACRUM 0:119624335925 594 */
MACRUM 0:119624335925 595 static void rf_poll_trx_state_change(rf_trx_states_t trx_state)
MACRUM 0:119624335925 596 {
MACRUM 0:119624335925 597 (void)trx_state;
MACRUM 0:119624335925 598 }
MACRUM 0:119624335925 599
MACRUM 0:119624335925 600 /*
MACRUM 0:119624335925 601 * \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
MACRUM 0:119624335925 602 *
MACRUM 0:119624335925 603 * \param data_ptr Pointer to TX data
MACRUM 0:119624335925 604 * \param data_length Length of the TX data
MACRUM 0:119624335925 605 * \param tx_handle Handle to transmission
MACRUM 0:119624335925 606 * \return 0 Success
MACRUM 0:119624335925 607 * \return -1 Busy
MACRUM 0:119624335925 608 */
MACRUM 0:119624335925 609 static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
MACRUM 0:119624335925 610 {
MACRUM 0:119624335925 611 uint8_t ccaMode;
MACRUM 0:119624335925 612
MACRUM 0:119624335925 613 /* Parameter validation */
MACRUM 0:119624335925 614 if( !data_ptr || (data_length > 125) || (PHY_LAYER_PAYLOAD != data_protocol) )
MACRUM 0:119624335925 615 {
MACRUM 0:119624335925 616 return -1;
MACRUM 0:119624335925 617 }
MACRUM 0:119624335925 618
MACRUM 0:119624335925 619 if( mPhySeqState == gRX_c )
MACRUM 0:119624335925 620 {
MACRUM 0:119624335925 621 uint8_t phyReg = MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F;
MACRUM 0:119624335925 622 /* Check for an Rx in progress. */
MACRUM 0:119624335925 623 if((phyReg <= 0x06) || (phyReg == 0x15) || (phyReg == 0x16))
MACRUM 0:119624335925 624 {
MACRUM 0:119624335925 625 if (device_driver.phy_tx_done_cb) {
MACRUM 0:119624335925 626 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
MACRUM 0:119624335925 627 }
MACRUM 0:119624335925 628 return -1;
MACRUM 0:119624335925 629 }
MACRUM 0:119624335925 630 rf_abort();
MACRUM 0:119624335925 631 }
MACRUM 0:119624335925 632
MACRUM 0:119624335925 633 /*Check if transmitter is busy*/
MACRUM 0:119624335925 634 if( mPhySeqState != gIdle_c )
MACRUM 0:119624335925 635 {
MACRUM 0:119624335925 636 /*Return busy*/
MACRUM 0:119624335925 637 return -1;
MACRUM 0:119624335925 638 }
MACRUM 0:119624335925 639
MACRUM 0:119624335925 640 /*Store TX handle*/
MACRUM 0:119624335925 641 mac_tx_handle = tx_handle;
MACRUM 0:119624335925 642 /*Check if transmitted data needs to be acked*/
MACRUM 0:119624335925 643 need_ack = (*data_ptr & 0x20) == 0x20;
MACRUM 0:119624335925 644
MACRUM 0:119624335925 645 /* Set XCVR power state in run mode */
MACRUM 0:119624335925 646 rf_set_power_state(gXcvrRunState_d);
MACRUM 0:119624335925 647 /* Load data into XCVR */
MACRUM 0:119624335925 648 tx_len = data_length + 2;
MACRUM 0:119624335925 649 MCR20Drv_PB_SPIBurstWrite(data_ptr - 1, data_length + 1);
MACRUM 0:119624335925 650 MCR20Drv_PB_SPIByteWrite(0,tx_len);
MACRUM 0:119624335925 651
MACRUM 0:119624335925 652 /* Set CCA mode 1 */
MACRUM 0:119624335925 653 ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
MACRUM 0:119624335925 654 if( ccaMode != gCcaCCA_MODE1_c )
MACRUM 0:119624335925 655 {
MACRUM 0:119624335925 656 mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
MACRUM 0:119624335925 657 mStatusAndControlRegs[PHY_CTRL4] |= gCcaCCA_MODE1_c << cPHY_CTRL4_CCATYPE_Shift_c;
MACRUM 0:119624335925 658 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
MACRUM 0:119624335925 659 }
MACRUM 0:119624335925 660
MACRUM 0:119624335925 661 /* Read XCVR registers */
MACRUM 0:119624335925 662 mStatusAndControlRegs[0] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[1], 4);
MACRUM 0:119624335925 663 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 664 mStatusAndControlRegs[PHY_CTRL1] |= gCCA_c;
MACRUM 0:119624335925 665 mPhySeqState = gCCA_c;
MACRUM 0:119624335925 666
MACRUM 0:119624335925 667 /* Ensure that no spurious interrupts are raised */
MACRUM 0:119624335925 668 mStatusAndControlRegs[IRQSTS3] &= 0xF0; /* do not change other IRQ status */
MACRUM 0:119624335925 669 mStatusAndControlRegs[IRQSTS3] |= (cIRQSTS3_TMR3MSK | cIRQSTS3_TMR3IRQ);
MACRUM 0:119624335925 670 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
MACRUM 0:119624335925 671
MACRUM 0:119624335925 672 /* Write XCVR settings */
MACRUM 0:119624335925 673 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 674
MACRUM 0:119624335925 675 /* Unmask SEQ interrupt */
MACRUM 0:119624335925 676 mStatusAndControlRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
MACRUM 0:119624335925 677 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]);
MACRUM 0:119624335925 678
MACRUM 0:119624335925 679 /*Return success*/
MACRUM 0:119624335925 680 return 0;
MACRUM 0:119624335925 681 }
MACRUM 0:119624335925 682
MACRUM 0:119624335925 683 /*
MACRUM 0:119624335925 684 * \brief Function aborts CCA process.
MACRUM 0:119624335925 685 *
MACRUM 0:119624335925 686 * \param none
MACRUM 0:119624335925 687 *
MACRUM 0:119624335925 688 * \return none
MACRUM 0:119624335925 689 */
MACRUM 0:119624335925 690 static void rf_cca_abort(void)
MACRUM 0:119624335925 691 {
MACRUM 0:119624335925 692 rf_abort();
MACRUM 0:119624335925 693 }
MACRUM 0:119624335925 694
MACRUM 0:119624335925 695 /*
MACRUM 0:119624335925 696 * \brief Function starts the transmission of the frame. Called from ISR context!
MACRUM 0:119624335925 697 *
MACRUM 0:119624335925 698 * \param none
MACRUM 0:119624335925 699 *
MACRUM 0:119624335925 700 * \return none
MACRUM 0:119624335925 701 */
MACRUM 0:119624335925 702 static void rf_start_tx(void)
MACRUM 0:119624335925 703 {
MACRUM 0:119624335925 704 /* Perform TxRxAck sequence if required by phyTxMode */
MACRUM 0:119624335925 705 if( need_ack )
MACRUM 0:119624335925 706 {
MACRUM 0:119624335925 707 mStatusAndControlRegs[PHY_CTRL1] |= cPHY_CTRL1_RXACKRQD;
MACRUM 0:119624335925 708 mPhySeqState = gTR_c;
MACRUM 0:119624335925 709 }
MACRUM 0:119624335925 710 else
MACRUM 0:119624335925 711 {
MACRUM 0:119624335925 712 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_RXACKRQD);
MACRUM 0:119624335925 713 mPhySeqState = gTX_c;
MACRUM 0:119624335925 714 }
MACRUM 0:119624335925 715
MACRUM 0:119624335925 716 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 717 mStatusAndControlRegs[PHY_CTRL1] |= mPhySeqState;
MACRUM 0:119624335925 718
MACRUM 0:119624335925 719 /* Unmask SEQ interrupt */
MACRUM 0:119624335925 720 mStatusAndControlRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
MACRUM 0:119624335925 721
MACRUM 0:119624335925 722 /* Start the sequence immediately */
MACRUM 0:119624335925 723 MCR20Drv_DirectAccessSPIMultiByteWrite(PHY_CTRL1, &mStatusAndControlRegs[PHY_CTRL1], 2);
MACRUM 0:119624335925 724
MACRUM 0:119624335925 725 if( need_ack )
MACRUM 0:119624335925 726 {
MACRUM 0:119624335925 727 rf_ack_wait_timer_start(gPhyWarmUpTime_c + gPhySHRDuration_c + tx_len * gPhySymbolsPerOctet_c + gPhyAckWaitDuration_c);
MACRUM 0:119624335925 728 }
MACRUM 0:119624335925 729 }
MACRUM 0:119624335925 730
MACRUM 0:119624335925 731 /*
MACRUM 0:119624335925 732 * \brief Function sets the RF in RX state. Called from ISR context!
MACRUM 0:119624335925 733 *
MACRUM 0:119624335925 734 * \param none
MACRUM 0:119624335925 735 *
MACRUM 0:119624335925 736 * \return none
MACRUM 0:119624335925 737 */
MACRUM 0:119624335925 738 static void rf_receive(void)
MACRUM 0:119624335925 739 {
MACRUM 0:119624335925 740 uint8_t phyRegs[5];
MACRUM 0:119624335925 741
MACRUM 0:119624335925 742 /* RX can start only from Idle state */
MACRUM 0:119624335925 743 if( mPhySeqState != gIdle_c )
MACRUM 0:119624335925 744 {
MACRUM 0:119624335925 745 return;
MACRUM 0:119624335925 746 }
MACRUM 0:119624335925 747
MACRUM 0:119624335925 748 /* Set XCVR power state in run mode */
MACRUM 0:119624335925 749 rf_set_power_state(gXcvrRunState_d);
MACRUM 0:119624335925 750 /* read XVCR settings */
MACRUM 0:119624335925 751 phyRegs[IRQSTS1] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &phyRegs[IRQSTS2], 4);
MACRUM 0:119624335925 752 /* unmask SEQ interrupt */
MACRUM 0:119624335925 753 phyRegs[PHY_CTRL2] &= ~(cPHY_CTRL2_SEQMSK);
MACRUM 0:119624335925 754 /* set XcvrSeq to RX */
MACRUM 0:119624335925 755 phyRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 756 phyRegs[PHY_CTRL1] |= gRX_c;
MACRUM 0:119624335925 757 mPhySeqState = gRX_c;
MACRUM 0:119624335925 758 /* Ensure that no spurious interrupts are raised */
MACRUM 0:119624335925 759 phyRegs[IRQSTS3] &= 0xF0; /* do not change other IRQ status */
MACRUM 0:119624335925 760 phyRegs[IRQSTS3] |= cIRQSTS3_TMR3MSK | cIRQSTS3_TMR3IRQ;
MACRUM 0:119624335925 761 /* sync settings with XCVR */
MACRUM 0:119624335925 762 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, phyRegs, 5);
MACRUM 0:119624335925 763 }
MACRUM 0:119624335925 764
MACRUM 0:119624335925 765 /*
MACRUM 0:119624335925 766 * \brief Function calibrates the radio.
MACRUM 0:119624335925 767 *
MACRUM 0:119624335925 768 * \param none
MACRUM 0:119624335925 769 *
MACRUM 0:119624335925 770 * \return none
MACRUM 0:119624335925 771 */
MACRUM 0:119624335925 772 static void rf_calibration_cb(void)
MACRUM 0:119624335925 773 {
MACRUM 0:119624335925 774 }
MACRUM 0:119624335925 775
MACRUM 0:119624335925 776 /*
MACRUM 0:119624335925 777 * \brief Function sets RF_ON flag when radio is powered.
MACRUM 0:119624335925 778 *
MACRUM 0:119624335925 779 * \param none
MACRUM 0:119624335925 780 *
MACRUM 0:119624335925 781 * \return none
MACRUM 0:119624335925 782 */
MACRUM 0:119624335925 783 static void rf_on(void)
MACRUM 0:119624335925 784 {
MACRUM 0:119624335925 785 }
MACRUM 0:119624335925 786
MACRUM 0:119624335925 787 /*
MACRUM 0:119624335925 788 * \brief Function is a call back for RX end interrupt.
MACRUM 0:119624335925 789 *
MACRUM 0:119624335925 790 * \param none
MACRUM 0:119624335925 791 *
MACRUM 0:119624335925 792 * \return none
MACRUM 0:119624335925 793 */
MACRUM 0:119624335925 794 static void rf_handle_rx_end(void)
MACRUM 0:119624335925 795 {
MACRUM 0:119624335925 796 uint8_t rf_lqi = MCR20Drv_DirectAccessSPIRead(LQI_VALUE);
MACRUM 0:119624335925 797 int8_t rf_rssi = 0;
MACRUM 0:119624335925 798 uint8_t len = mStatusAndControlRegs[RX_FRM_LEN] - 2;
MACRUM 0:119624335925 799
MACRUM 0:119624335925 800
MACRUM 0:119624335925 801 /*Start receiver*/
MACRUM 0:119624335925 802 rf_receive();
MACRUM 0:119624335925 803
MACRUM 0:119624335925 804 /*Check the length is valid*/
MACRUM 0:119624335925 805 if(len > 1 && len < RF_BUFFER_SIZE)
MACRUM 0:119624335925 806 {
MACRUM 0:119624335925 807 rf_lqi = rf_convert_LQI(rf_lqi);
MACRUM 0:119624335925 808 rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi);
MACRUM 0:119624335925 809 /*gcararu: Scale LQI using received RSSI, to match the LQI reported by the ATMEL radio */
MACRUM 0:119624335925 810 rf_lqi = rf_scale_lqi(rf_rssi);
MACRUM 0:119624335925 811
MACRUM 0:119624335925 812 /*Read received packet*/
MACRUM 0:119624335925 813 MCR20Drv_PB_SPIBurstRead(rf_buffer, len);
MACRUM 0:119624335925 814 if (device_driver.phy_rx_cb) {
MACRUM 0:119624335925 815 device_driver.phy_rx_cb(rf_buffer, len, rf_lqi, rf_rssi, rf_radio_driver_id);
MACRUM 0:119624335925 816 }
MACRUM 0:119624335925 817 }
MACRUM 0:119624335925 818 }
MACRUM 0:119624335925 819
MACRUM 0:119624335925 820 /*
MACRUM 0:119624335925 821 * \brief Function is called when MAC is shutting down the radio.
MACRUM 0:119624335925 822 *
MACRUM 0:119624335925 823 * \param none
MACRUM 0:119624335925 824 *
MACRUM 0:119624335925 825 * \return none
MACRUM 0:119624335925 826 */
MACRUM 0:119624335925 827 static void rf_shutdown(void)
MACRUM 0:119624335925 828 {
MACRUM 0:119624335925 829 /*Call RF OFF*/
MACRUM 0:119624335925 830 rf_off();
MACRUM 0:119624335925 831 }
MACRUM 0:119624335925 832
MACRUM 0:119624335925 833 /*
MACRUM 0:119624335925 834 * \brief Function is a call back for TX end interrupt.
MACRUM 0:119624335925 835 *
MACRUM 0:119624335925 836 * \param none
MACRUM 0:119624335925 837 *
MACRUM 0:119624335925 838 * \return none
MACRUM 0:119624335925 839 */
MACRUM 0:119624335925 840 static void rf_handle_tx_end(void)
MACRUM 0:119624335925 841 {
MACRUM 0:119624335925 842 uint8_t rx_frame_pending = mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_RX_FRM_PEND;
MACRUM 0:119624335925 843
MACRUM 0:119624335925 844 /*Start receiver*/
MACRUM 0:119624335925 845 rf_receive();
MACRUM 0:119624335925 846
MACRUM 0:119624335925 847 if (!device_driver.phy_tx_done_cb) {
MACRUM 0:119624335925 848 return;
MACRUM 0:119624335925 849 }
MACRUM 0:119624335925 850
MACRUM 0:119624335925 851 /*Call PHY TX Done API*/
MACRUM 0:119624335925 852 if( need_ack )
MACRUM 0:119624335925 853 {
MACRUM 0:119624335925 854 if( rx_frame_pending )
MACRUM 0:119624335925 855 {
MACRUM 0:119624335925 856 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE_PENDING, 1, 1);
MACRUM 0:119624335925 857 }
MACRUM 0:119624335925 858 else
MACRUM 0:119624335925 859 {
MACRUM 0:119624335925 860 // arm_net_phy_tx_done(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
MACRUM 0:119624335925 861 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_DONE, 1, 1);
MACRUM 0:119624335925 862 }
MACRUM 0:119624335925 863 }
MACRUM 0:119624335925 864 else
MACRUM 0:119624335925 865 {
MACRUM 0:119624335925 866 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 1, 1);
MACRUM 0:119624335925 867 }
MACRUM 0:119624335925 868 }
MACRUM 0:119624335925 869
MACRUM 0:119624335925 870 /*
MACRUM 0:119624335925 871 * \brief Function is a call back for CCA ED done interrupt.
MACRUM 0:119624335925 872 *
MACRUM 0:119624335925 873 * \param none
MACRUM 0:119624335925 874 *
MACRUM 0:119624335925 875 * \return none
MACRUM 0:119624335925 876 */
MACRUM 0:119624335925 877 static void rf_handle_cca_ed_done(void)
MACRUM 0:119624335925 878 {
MACRUM 0:119624335925 879 /*Check the result of CCA process*/
MACRUM 0:119624335925 880 if( !(mStatusAndControlRegs[IRQSTS2] & cIRQSTS2_CCA) )
MACRUM 0:119624335925 881 {
MACRUM 0:119624335925 882 rf_start_tx();
MACRUM 0:119624335925 883 }
MACRUM 0:119624335925 884 else if (device_driver.phy_tx_done_cb)
MACRUM 0:119624335925 885 {
MACRUM 0:119624335925 886 /*Send CCA fail notification*/
MACRUM 0:119624335925 887 device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 1);
MACRUM 0:119624335925 888 }
MACRUM 0:119624335925 889 }
MACRUM 0:119624335925 890
MACRUM 0:119624335925 891 /*
MACRUM 0:119624335925 892 * \brief Function sets the TX power variable.
MACRUM 0:119624335925 893 *
MACRUM 0:119624335925 894 * \param power TX power setting
MACRUM 0:119624335925 895 *
MACRUM 0:119624335925 896 * \return 0 Success
MACRUM 0:119624335925 897 * \return -1 Fail
MACRUM 0:119624335925 898 */
MACRUM 0:119624335925 899 static int8_t rf_tx_power_set(uint8_t power)
MACRUM 0:119624335925 900 {
MACRUM 0:119624335925 901 /* gcapraru: Map MCR20A Tx power levels over ATMEL values */
MACRUM 0:119624335925 902 static uint8_t pwrLevelMapping[16] = {25,25,25,24,24,24,23,23,22,22,21,20,19,18,17,14};
MACRUM 0:119624335925 903
MACRUM 0:119624335925 904 if( power > 15 )
MACRUM 0:119624335925 905 {
MACRUM 0:119624335925 906 return -1;
MACRUM 0:119624335925 907 }
MACRUM 0:119624335925 908
MACRUM 0:119624335925 909 radio_tx_power = power;
MACRUM 0:119624335925 910 MCR20Drv_DirectAccessSPIWrite(PA_PWR, pwrLevelMapping[power]);
MACRUM 0:119624335925 911 return 0;
MACRUM 0:119624335925 912 }
MACRUM 0:119624335925 913
MACRUM 0:119624335925 914 /*
MACRUM 0:119624335925 915 * \brief Function returns the TX power variable.
MACRUM 0:119624335925 916 *
MACRUM 0:119624335925 917 * \param none
MACRUM 0:119624335925 918 *
MACRUM 0:119624335925 919 * \return radio_tx_power TX power variable
MACRUM 0:119624335925 920 */
MACRUM 0:119624335925 921 static uint8_t rf_tx_power_get(void)
MACRUM 0:119624335925 922 {
MACRUM 0:119624335925 923 return radio_tx_power;
MACRUM 0:119624335925 924 }
MACRUM 0:119624335925 925
MACRUM 0:119624335925 926 /*
MACRUM 0:119624335925 927 * \brief Function enables the usage of Antenna diversity.
MACRUM 0:119624335925 928 *
MACRUM 0:119624335925 929 * \param none
MACRUM 0:119624335925 930 *
MACRUM 0:119624335925 931 * \return 0 Success
MACRUM 0:119624335925 932 */
MACRUM 0:119624335925 933 static int8_t rf_enable_antenna_diversity(void)
MACRUM 0:119624335925 934 {
MACRUM 0:119624335925 935 uint8_t phyReg;
MACRUM 0:119624335925 936
MACRUM 0:119624335925 937 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_AGC_CTRL);
MACRUM 0:119624335925 938 phyReg |= cANT_AGC_CTRL_FAD_EN_Mask_c;
MACRUM 0:119624335925 939 MCR20Drv_IndirectAccessSPIWrite(ANT_AGC_CTRL, phyReg);
MACRUM 0:119624335925 940
MACRUM 0:119624335925 941 phyReg = MCR20Drv_IndirectAccessSPIRead(ANT_PAD_CTRL);
MACRUM 0:119624335925 942 phyReg |= 0x02;
MACRUM 0:119624335925 943 MCR20Drv_IndirectAccessSPIWrite(ANT_PAD_CTRL, phyReg);
MACRUM 0:119624335925 944
MACRUM 0:119624335925 945 return 0;
MACRUM 0:119624335925 946 }
MACRUM 0:119624335925 947
MACRUM 0:119624335925 948 /*
MACRUM 0:119624335925 949 * \brief Function gives the control of RF states to MAC.
MACRUM 0:119624335925 950 *
MACRUM 0:119624335925 951 * \param new_state RF state
MACRUM 0:119624335925 952 * \param rf_channel RF channel
MACRUM 0:119624335925 953 *
MACRUM 0:119624335925 954 * \return 0 Success
MACRUM 0:119624335925 955 */
MACRUM 0:119624335925 956 static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
MACRUM 0:119624335925 957 {
MACRUM 0:119624335925 958 int8_t ret_val = 0;
MACRUM 0:119624335925 959 switch (new_state)
MACRUM 0:119624335925 960 {
MACRUM 0:119624335925 961 /*Reset PHY driver and set to idle*/
MACRUM 0:119624335925 962 case PHY_INTERFACE_RESET:
MACRUM 0:119624335925 963 break;
MACRUM 0:119624335925 964 /*Disable PHY Interface driver*/
MACRUM 0:119624335925 965 case PHY_INTERFACE_DOWN:
MACRUM 0:119624335925 966 rf_shutdown();
MACRUM 0:119624335925 967 break;
MACRUM 0:119624335925 968 /*Enable PHY Interface driver*/
MACRUM 0:119624335925 969 case PHY_INTERFACE_UP:
MACRUM 0:119624335925 970 rf_channel_set(rf_channel);
MACRUM 0:119624335925 971 rf_receive();
MACRUM 0:119624335925 972 break;
MACRUM 0:119624335925 973 /*Enable wireless interface ED scan mode*/
MACRUM 0:119624335925 974 case PHY_INTERFACE_RX_ENERGY_STATE:
MACRUM 0:119624335925 975 rf_abort();
MACRUM 0:119624335925 976 rf_channel_set(rf_channel);
MACRUM 0:119624335925 977 break;
MACRUM 0:119624335925 978 case PHY_INTERFACE_SNIFFER_STATE: /**< Enable Sniffer state */
MACRUM 0:119624335925 979 rf_promiscuous(1);
MACRUM 0:119624335925 980 rf_channel_set(rf_channel);
MACRUM 0:119624335925 981 rf_receive();
MACRUM 0:119624335925 982 break;
MACRUM 0:119624335925 983 }
MACRUM 0:119624335925 984 return ret_val;
MACRUM 0:119624335925 985 }
MACRUM 0:119624335925 986
MACRUM 0:119624335925 987 /*
MACRUM 0:119624335925 988 * \brief Function controls the ACK pending, channel setting and energy detection.
MACRUM 0:119624335925 989 *
MACRUM 0:119624335925 990 * \param extension_type Type of control
MACRUM 0:119624335925 991 * \param data_ptr Data from NET library
MACRUM 0:119624335925 992 *
MACRUM 0:119624335925 993 * \return 0 Success
MACRUM 0:119624335925 994 */
MACRUM 0:119624335925 995 static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
MACRUM 0:119624335925 996 {
MACRUM 0:119624335925 997 switch (extension_type)
MACRUM 0:119624335925 998 {
MACRUM 0:119624335925 999 /*Control MAC pending bit for Indirect data transmission*/
MACRUM 0:119624335925 1000 case PHY_EXTENSION_CTRL_PENDING_BIT:
MACRUM 0:119624335925 1001 {
MACRUM 0:119624335925 1002 uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
MACRUM 0:119624335925 1003
MACRUM 0:119624335925 1004 if(*data_ptr)
MACRUM 0:119624335925 1005 {
MACRUM 0:119624335925 1006 reg |= cSRC_CTRL_ACK_FRM_PND;
MACRUM 0:119624335925 1007 }
MACRUM 0:119624335925 1008 else
MACRUM 0:119624335925 1009 {
MACRUM 0:119624335925 1010 reg &= ~cSRC_CTRL_ACK_FRM_PND;
MACRUM 0:119624335925 1011 }
MACRUM 0:119624335925 1012
MACRUM 0:119624335925 1013 MCR20Drv_DirectAccessSPIWrite(SRC_CTRL, reg);
MACRUM 0:119624335925 1014 break;
MACRUM 0:119624335925 1015
MACRUM 0:119624335925 1016 }
MACRUM 0:119624335925 1017 /*Return frame Auto Ack frame pending status*/
MACRUM 0:119624335925 1018 case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS: {
MACRUM 0:119624335925 1019 uint8_t reg = MCR20Drv_DirectAccessSPIRead(SRC_CTRL);
MACRUM 0:119624335925 1020 if (reg & cSRC_CTRL_ACK_FRM_PND) {
MACRUM 0:119624335925 1021 *data_ptr = 1;
MACRUM 0:119624335925 1022 } else {
MACRUM 0:119624335925 1023 *data_ptr = 0;
MACRUM 0:119624335925 1024 }
MACRUM 0:119624335925 1025 break;
MACRUM 0:119624335925 1026 }
MACRUM 0:119624335925 1027 /*Set channel*/
MACRUM 0:119624335925 1028 case PHY_EXTENSION_SET_CHANNEL:
MACRUM 0:119624335925 1029 break;
MACRUM 0:119624335925 1030 /*Read energy on the channel*/
MACRUM 0:119624335925 1031 case PHY_EXTENSION_READ_CHANNEL_ENERGY:
MACRUM 0:119624335925 1032 *data_ptr = rf_get_channel_energy();
MACRUM 0:119624335925 1033 break;
MACRUM 0:119624335925 1034 /*Read status of the link*/
MACRUM 0:119624335925 1035 case PHY_EXTENSION_READ_LINK_STATUS:
MACRUM 0:119624335925 1036 break;
MACRUM 0:119624335925 1037 case PHY_EXTENSION_CONVERT_SIGNAL_INFO:
MACRUM 0:119624335925 1038 break;
MACRUM 0:119624335925 1039 case PHY_EXTENSION_ACCEPT_ANY_BEACON:
MACRUM 0:119624335925 1040 break;
MACRUM 0:119624335925 1041 }
MACRUM 0:119624335925 1042 return 0;
MACRUM 0:119624335925 1043 }
MACRUM 0:119624335925 1044
MACRUM 0:119624335925 1045 /*
MACRUM 0:119624335925 1046 * \brief Function sets the addresses to RF address filters.
MACRUM 0:119624335925 1047 *
MACRUM 0:119624335925 1048 * \param address_type Type of address
MACRUM 0:119624335925 1049 * \param address_ptr Pointer to given address
MACRUM 0:119624335925 1050 *
MACRUM 0:119624335925 1051 * \return 0 Success
MACRUM 0:119624335925 1052 */
MACRUM 0:119624335925 1053 static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
MACRUM 0:119624335925 1054 {
MACRUM 0:119624335925 1055 int8_t ret_val = 0;
MACRUM 0:119624335925 1056 switch (address_type)
MACRUM 0:119624335925 1057 {
MACRUM 0:119624335925 1058 /*Set 48-bit address*/
MACRUM 0:119624335925 1059 case PHY_MAC_48BIT:
MACRUM 0:119624335925 1060 break;
MACRUM 0:119624335925 1061 /*Set 64-bit address*/
MACRUM 0:119624335925 1062 case PHY_MAC_64BIT:
MACRUM 0:119624335925 1063 rf_set_address(address_ptr);
MACRUM 0:119624335925 1064 break;
MACRUM 0:119624335925 1065 /*Set 16-bit address*/
MACRUM 0:119624335925 1066 case PHY_MAC_16BIT:
MACRUM 0:119624335925 1067 rf_set_short_adr(address_ptr);
MACRUM 0:119624335925 1068 break;
MACRUM 0:119624335925 1069 /*Set PAN Id*/
MACRUM 0:119624335925 1070 case PHY_MAC_PANID:
MACRUM 0:119624335925 1071 rf_set_pan_id(address_ptr);
MACRUM 0:119624335925 1072 break;
MACRUM 0:119624335925 1073 }
MACRUM 0:119624335925 1074 return ret_val;
MACRUM 0:119624335925 1075 }
MACRUM 0:119624335925 1076
MACRUM 0:119624335925 1077 static void rf_mac64_read(uint8_t *address)
MACRUM 0:119624335925 1078 {
MACRUM 0:119624335925 1079 /* Write one register at a time to be accessible from hibernate mode */
MACRUM 0:119624335925 1080 address[7] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_0);
MACRUM 0:119624335925 1081 address[6] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_8);
MACRUM 0:119624335925 1082 address[5] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_16);
MACRUM 0:119624335925 1083 address[4] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_24);
MACRUM 0:119624335925 1084 address[3] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_32);
MACRUM 0:119624335925 1085 address[2] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_40);
MACRUM 0:119624335925 1086 address[1] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_48);
MACRUM 0:119624335925 1087 address[0] = MCR20Drv_DirectAccessSPIRead(MACLONGADDRS0_56);
MACRUM 0:119624335925 1088
MACRUM 0:119624335925 1089 }
MACRUM 0:119624335925 1090
MACRUM 0:119624335925 1091 /*
MACRUM 0:119624335925 1092 * \brief Function initialises the ACK wait time and returns the used PHY mode.
MACRUM 0:119624335925 1093 *
MACRUM 0:119624335925 1094 * \param none
MACRUM 0:119624335925 1095 *
MACRUM 0:119624335925 1096 * \return tmp Used PHY mode
MACRUM 0:119624335925 1097 */
MACRUM 0:119624335925 1098 static void rf_init_phy_mode(void)
MACRUM 0:119624335925 1099 {
MACRUM 0:119624335925 1100 }
MACRUM 0:119624335925 1101
MACRUM 0:119624335925 1102 /*
MACRUM 0:119624335925 1103 * \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
MACRUM 0:119624335925 1104 *
MACRUM 0:119624335925 1105 * \param none
MACRUM 0:119624335925 1106 *
MACRUM 0:119624335925 1107 * \return none
MACRUM 0:119624335925 1108 */
MACRUM 0:119624335925 1109 static void PHY_InterruptHandler(void)
MACRUM 0:119624335925 1110 {
MACRUM 0:119624335925 1111 /* Disable and clear transceiver(IRQ_B) interrupt */
MACRUM 0:119624335925 1112 MCR20Drv_IRQ_Disable();
MACRUM 0:119624335925 1113 irq_thread.signal_set(1);
MACRUM 0:119624335925 1114 }
MACRUM 0:119624335925 1115
MACRUM 0:119624335925 1116 static void PHY_InterruptThread(void)
MACRUM 0:119624335925 1117 {
MACRUM 0:119624335925 1118 for (;;) {
MACRUM 0:119624335925 1119 osEvent event = irq_thread.signal_wait(0);
MACRUM 0:119624335925 1120 if (event.status != osEventSignal) {
MACRUM 0:119624335925 1121 continue;
MACRUM 0:119624335925 1122 }
MACRUM 0:119624335925 1123 handle_interrupt();
MACRUM 0:119624335925 1124 }
MACRUM 0:119624335925 1125 }
MACRUM 0:119624335925 1126
MACRUM 0:119624335925 1127 static void handle_interrupt(void)
MACRUM 0:119624335925 1128 {
MACRUM 0:119624335925 1129 uint8_t xcvseqCopy;
MACRUM 0:119624335925 1130
MACRUM 0:119624335925 1131 //MCR20Drv_IRQ_Clear();
MACRUM 0:119624335925 1132
MACRUM 0:119624335925 1133 /* Read transceiver interrupt status and control registers */
MACRUM 0:119624335925 1134 mStatusAndControlRegs[IRQSTS1] =
MACRUM 0:119624335925 1135 MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[IRQSTS2], 7);
MACRUM 0:119624335925 1136
MACRUM 0:119624335925 1137 xcvseqCopy = mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ;
MACRUM 0:119624335925 1138
MACRUM 0:119624335925 1139 /* Flter Fail IRQ */
MACRUM 0:119624335925 1140 if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_FILTERFAIL_IRQ) &&
MACRUM 0:119624335925 1141 !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_FILTERFAIL_MSK) )
MACRUM 0:119624335925 1142 {
MACRUM 0:119624335925 1143 if( xcvseqCopy == gRX_c )
MACRUM 0:119624335925 1144 {
MACRUM 0:119624335925 1145 /* Abort current SEQ */
MACRUM 0:119624335925 1146 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 1147 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 1148 /* Wait for Sequence Idle */
MACRUM 0:119624335925 1149 while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
MACRUM 0:119624335925 1150 /* Clear IRQ flags: */
MACRUM 0:119624335925 1151 MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ);
MACRUM 0:119624335925 1152 /* Restart Rx asap */
MACRUM 0:119624335925 1153 mStatusAndControlRegs[PHY_CTRL1] |= gRX_c;
MACRUM 0:119624335925 1154 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 1155 }
MACRUM 0:119624335925 1156 }
MACRUM 0:119624335925 1157
MACRUM 0:119624335925 1158 /* TMR3 IRQ: ACK wait time-out */
MACRUM 0:119624335925 1159 if( (mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3IRQ) &&
MACRUM 0:119624335925 1160 !(mStatusAndControlRegs[IRQSTS3] & cIRQSTS3_TMR3MSK) )
MACRUM 0:119624335925 1161 {
MACRUM 0:119624335925 1162 /* Disable TMR3 IRQ */
MACRUM 0:119624335925 1163 mStatusAndControlRegs[IRQSTS3] |= cIRQSTS3_TMR3MSK;
MACRUM 0:119624335925 1164
MACRUM 0:119624335925 1165 if( xcvseqCopy == gTR_c )
MACRUM 0:119624335925 1166 {
MACRUM 0:119624335925 1167 /* Set XCVR to Idle */
MACRUM 0:119624335925 1168 mPhySeqState = gIdle_c;
MACRUM 0:119624335925 1169 mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
MACRUM 0:119624335925 1170 /* Mask interrupts */
MACRUM 0:119624335925 1171 mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK;
MACRUM 0:119624335925 1172 /* Sync settings with XCVR */
MACRUM 0:119624335925 1173 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
MACRUM 0:119624335925 1174
MACRUM 0:119624335925 1175 rf_ack_wait_timer_interrupt();
MACRUM 0:119624335925 1176 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1177 return;
MACRUM 0:119624335925 1178 }
MACRUM 0:119624335925 1179 }
MACRUM 0:119624335925 1180
MACRUM 0:119624335925 1181 /* Sequencer interrupt, the autosequence has completed */
MACRUM 0:119624335925 1182 if( (mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_SEQIRQ) &&
MACRUM 0:119624335925 1183 !(mStatusAndControlRegs[PHY_CTRL2] & cPHY_CTRL2_SEQMSK) )
MACRUM 0:119624335925 1184 {
MACRUM 0:119624335925 1185 /* Set XCVR to Idle */
MACRUM 0:119624335925 1186 mPhySeqState = gIdle_c;
MACRUM 0:119624335925 1187 mStatusAndControlRegs[PHY_CTRL1] &= ~( cPHY_CTRL1_XCVSEQ );
MACRUM 0:119624335925 1188 /* Mask interrupts */
MACRUM 0:119624335925 1189 mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_CCAMSK | cPHY_CTRL2_RXMSK | cPHY_CTRL2_TXMSK | cPHY_CTRL2_SEQMSK;
MACRUM 0:119624335925 1190 /* Sync settings with XCVR */
MACRUM 0:119624335925 1191 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 5);
MACRUM 0:119624335925 1192
MACRUM 0:119624335925 1193 /* PLL unlock, the autosequence has been aborted due to PLL unlock */
MACRUM 0:119624335925 1194 if( mStatusAndControlRegs[IRQSTS1] & cIRQSTS1_PLL_UNLOCK_IRQ )
MACRUM 0:119624335925 1195 {
MACRUM 0:119624335925 1196 if(xcvseqCopy == gRX_c)
MACRUM 0:119624335925 1197 {
MACRUM 0:119624335925 1198 rf_receive();
MACRUM 0:119624335925 1199 }
MACRUM 0:119624335925 1200 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1201 return;
MACRUM 0:119624335925 1202 }
MACRUM 0:119624335925 1203
MACRUM 0:119624335925 1204 switch(xcvseqCopy)
MACRUM 0:119624335925 1205 {
MACRUM 0:119624335925 1206 case gTX_c:
MACRUM 0:119624335925 1207 case gTR_c:
MACRUM 0:119624335925 1208 rf_handle_tx_end();
MACRUM 0:119624335925 1209 break;
MACRUM 0:119624335925 1210
MACRUM 0:119624335925 1211 case gRX_c:
MACRUM 0:119624335925 1212 rf_handle_rx_end();
MACRUM 0:119624335925 1213 break;
MACRUM 0:119624335925 1214
MACRUM 0:119624335925 1215 case gCCA_c:
MACRUM 0:119624335925 1216 rf_handle_cca_ed_done();
MACRUM 0:119624335925 1217 break;
MACRUM 0:119624335925 1218
MACRUM 0:119624335925 1219 default:
MACRUM 0:119624335925 1220 break;
MACRUM 0:119624335925 1221 }
MACRUM 0:119624335925 1222
MACRUM 0:119624335925 1223 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1224 return;
MACRUM 0:119624335925 1225 }
MACRUM 0:119624335925 1226 /* Other IRQ. Clear XCVR interrupt flags */
MACRUM 0:119624335925 1227 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
MACRUM 0:119624335925 1228 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1229 }
MACRUM 0:119624335925 1230
MACRUM 0:119624335925 1231 /*
MACRUM 0:119624335925 1232 * \brief Function forces the XCVR to Idle state.
MACRUM 0:119624335925 1233 *
MACRUM 0:119624335925 1234 * \param none
MACRUM 0:119624335925 1235 *
MACRUM 0:119624335925 1236 * \return none
MACRUM 0:119624335925 1237 */
MACRUM 0:119624335925 1238 static void rf_abort(void)
MACRUM 0:119624335925 1239 {
MACRUM 0:119624335925 1240 /* Mask XCVR irq */
MACRUM 0:119624335925 1241 MCR20Drv_IRQ_Disable();
MACRUM 0:119624335925 1242
MACRUM 0:119624335925 1243 mPhySeqState = gIdle_c;
MACRUM 0:119624335925 1244
MACRUM 0:119624335925 1245 mStatusAndControlRegs[IRQSTS1] = MCR20Drv_DirectAccessSPIMultiByteRead(IRQSTS2, &mStatusAndControlRegs[IRQSTS2], 5);
MACRUM 0:119624335925 1246
MACRUM 0:119624335925 1247 /* Mask SEQ interrupt */
MACRUM 0:119624335925 1248 mStatusAndControlRegs[PHY_CTRL2] |= cPHY_CTRL2_SEQMSK;
MACRUM 0:119624335925 1249 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL2, mStatusAndControlRegs[PHY_CTRL2]);
MACRUM 0:119624335925 1250
MACRUM 0:119624335925 1251 if( (mStatusAndControlRegs[PHY_CTRL1] & cPHY_CTRL1_XCVSEQ) != gIdle_c )
MACRUM 0:119624335925 1252 {
MACRUM 0:119624335925 1253 /* Abort current SEQ */
MACRUM 0:119624335925 1254 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 1255 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 1256
MACRUM 0:119624335925 1257 /* Wait for Sequence Idle (if not already) */
MACRUM 0:119624335925 1258 while ((MCR20Drv_DirectAccessSPIRead(SEQ_STATE) & 0x1F) != 0);
MACRUM 0:119624335925 1259 //while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
MACRUM 0:119624335925 1260 mStatusAndControlRegs[IRQSTS1] |= cIRQSTS1_SEQIRQ;
MACRUM 0:119624335925 1261 }
MACRUM 0:119624335925 1262
MACRUM 0:119624335925 1263 /* Clear all PP IRQ bits to avoid unexpected interrupts and mask TMR3 interrupt.
MACRUM 0:119624335925 1264 Do not change TMR IRQ status. */
MACRUM 0:119624335925 1265 mStatusAndControlRegs[IRQSTS3] &= 0xF0;
MACRUM 0:119624335925 1266 mStatusAndControlRegs[IRQSTS3] |= (cIRQSTS3_TMR3MSK | cIRQSTS3_TMR3IRQ);
MACRUM 0:119624335925 1267 MCR20Drv_DirectAccessSPIMultiByteWrite(IRQSTS1, mStatusAndControlRegs, 3);
MACRUM 0:119624335925 1268
MACRUM 0:119624335925 1269 /* Unmask XCVR irq */
MACRUM 0:119624335925 1270 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1271 }
MACRUM 0:119624335925 1272
MACRUM 0:119624335925 1273 /*
MACRUM 0:119624335925 1274 * \brief Function reads a time-stamp value from XCVR [symbols]
MACRUM 0:119624335925 1275 *
MACRUM 0:119624335925 1276 * \param pEndTime pointer to location where time-stamp will be stored
MACRUM 0:119624335925 1277 *
MACRUM 0:119624335925 1278 * \return none
MACRUM 0:119624335925 1279 */
MACRUM 0:119624335925 1280 static void rf_get_timestamp(uint32_t *pRetClk)
MACRUM 0:119624335925 1281 {
MACRUM 0:119624335925 1282 if(NULL == pRetClk)
MACRUM 0:119624335925 1283 {
MACRUM 0:119624335925 1284 return;
MACRUM 0:119624335925 1285 }
MACRUM 0:119624335925 1286
MACRUM 0:119624335925 1287 platform_enter_critical();
MACRUM 0:119624335925 1288
MACRUM 0:119624335925 1289 *pRetClk = 0;
MACRUM 0:119624335925 1290 MCR20Drv_DirectAccessSPIMultiByteRead(EVENT_TMR_LSB, (uint8_t *) pRetClk, 3);
MACRUM 0:119624335925 1291
MACRUM 0:119624335925 1292 platform_exit_critical();
MACRUM 0:119624335925 1293 }
MACRUM 0:119624335925 1294
MACRUM 0:119624335925 1295 /*
MACRUM 0:119624335925 1296 * \brief Function set a time-out to an XCVR sequence.
MACRUM 0:119624335925 1297 *
MACRUM 0:119624335925 1298 * \param pEndTime pointer to the sequence time-out value [symbols]
MACRUM 0:119624335925 1299 *
MACRUM 0:119624335925 1300 * \return none
MACRUM 0:119624335925 1301 */
MACRUM 0:119624335925 1302 static void rf_set_timeout(uint32_t *pEndTime)
MACRUM 0:119624335925 1303 {
MACRUM 0:119624335925 1304 uint8_t phyReg;
MACRUM 0:119624335925 1305
MACRUM 0:119624335925 1306 if(NULL == pEndTime)
MACRUM 0:119624335925 1307 {
MACRUM 0:119624335925 1308 return;
MACRUM 0:119624335925 1309 }
MACRUM 0:119624335925 1310
MACRUM 0:119624335925 1311 platform_enter_critical();
MACRUM 0:119624335925 1312
MACRUM 0:119624335925 1313 phyReg = MCR20Drv_DirectAccessSPIRead(IRQSTS3);
MACRUM 0:119624335925 1314 phyReg &= 0xF0; /* do not change IRQ status */
MACRUM 0:119624335925 1315 phyReg |= (cIRQSTS3_TMR3MSK); /* mask TMR3 interrupt */
MACRUM 0:119624335925 1316 MCR20Drv_DirectAccessSPIWrite(IRQSTS3, phyReg);
MACRUM 0:119624335925 1317
MACRUM 0:119624335925 1318 MCR20Drv_DirectAccessSPIMultiByteWrite(T3CMP_LSB, (uint8_t *) pEndTime, 3);
MACRUM 0:119624335925 1319
MACRUM 0:119624335925 1320 phyReg &= ~(cIRQSTS3_TMR3MSK); /* unmask TMR3 interrupt */
MACRUM 0:119624335925 1321 phyReg |= (cIRQSTS3_TMR3IRQ); /* aknowledge TMR3 IRQ */
MACRUM 0:119624335925 1322 MCR20Drv_DirectAccessSPIWrite(IRQSTS3, phyReg);
MACRUM 0:119624335925 1323
MACRUM 0:119624335925 1324 platform_exit_critical();
MACRUM 0:119624335925 1325 }
MACRUM 0:119624335925 1326
MACRUM 0:119624335925 1327 /*
MACRUM 0:119624335925 1328 * \brief Function reads a random number from RF.
MACRUM 0:119624335925 1329 *
MACRUM 0:119624335925 1330 * \param none
MACRUM 0:119624335925 1331 *
MACRUM 0:119624335925 1332 * \return 8-bit random number
MACRUM 0:119624335925 1333 */
MACRUM 0:119624335925 1334 static uint8_t rf_if_read_rnd(void)
MACRUM 0:119624335925 1335 {
MACRUM 0:119624335925 1336 uint8_t phyReg;
MACRUM 0:119624335925 1337
MACRUM 0:119624335925 1338 MCR20Drv_IRQ_Disable();
MACRUM 0:119624335925 1339 /* Check if XCVR is idle */
MACRUM 0:119624335925 1340 phyReg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL1);
MACRUM 0:119624335925 1341
MACRUM 0:119624335925 1342 if( (phyReg & cPHY_CTRL1_XCVSEQ) == gIdle_c )
MACRUM 0:119624335925 1343 {
MACRUM 0:119624335925 1344 /* Program a new sequence */
MACRUM 0:119624335925 1345 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, phyReg | gCCA_c);
MACRUM 0:119624335925 1346 /* Wait for sequence to finish */
MACRUM 0:119624335925 1347 while( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ) );
MACRUM 0:119624335925 1348 /* Clear interrupt flag */
MACRUM 0:119624335925 1349 MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_SEQIRQ);
MACRUM 0:119624335925 1350 }
MACRUM 0:119624335925 1351
MACRUM 0:119624335925 1352 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1353
MACRUM 0:119624335925 1354 return MCR20Drv_IndirectAccessSPIRead(_RNG);
MACRUM 0:119624335925 1355 }
MACRUM 0:119624335925 1356
MACRUM 0:119624335925 1357 /*
MACRUM 0:119624335925 1358 * \brief Function converts LQI into RSSI.
MACRUM 0:119624335925 1359 *
MACRUM 0:119624335925 1360 * \param LQI
MACRUM 0:119624335925 1361 *
MACRUM 0:119624335925 1362 * \return RSSI
MACRUM 0:119624335925 1363 */
MACRUM 0:119624335925 1364 static int8_t rf_convert_LQI_to_RSSI(uint8_t lqi)
MACRUM 0:119624335925 1365 {
MACRUM 0:119624335925 1366 int32_t rssi = (50*lqi - 16820) / 163;
MACRUM 0:119624335925 1367 return (int8_t)rssi;
MACRUM 0:119624335925 1368 }
MACRUM 0:119624335925 1369
MACRUM 0:119624335925 1370 /*
MACRUM 0:119624335925 1371 * \brief Function scale the LQI value reported by RF into a 0-255 value.
MACRUM 0:119624335925 1372 *
MACRUM 0:119624335925 1373 * \param hwLqi - the LQI value reported by RF
MACRUM 0:119624335925 1374 *
MACRUM 0:119624335925 1375 * \return scaled LQI
MACRUM 0:119624335925 1376 */
MACRUM 0:119624335925 1377 static uint8_t rf_convert_LQI(uint8_t hwLqi)
MACRUM 0:119624335925 1378 {
MACRUM 0:119624335925 1379 uint32_t tmpLQI;
MACRUM 0:119624335925 1380
MACRUM 0:119624335925 1381 /* LQI Saturation Level */
MACRUM 0:119624335925 1382 if (hwLqi >= 230)
MACRUM 0:119624335925 1383 {
MACRUM 0:119624335925 1384 return 0xFF;
MACRUM 0:119624335925 1385 }
MACRUM 0:119624335925 1386 else if (hwLqi <= 9)
MACRUM 0:119624335925 1387 {
MACRUM 0:119624335925 1388 return 0;
MACRUM 0:119624335925 1389 }
MACRUM 0:119624335925 1390 else
MACRUM 0:119624335925 1391 {
MACRUM 0:119624335925 1392 /* Rescale the LQI values from min to saturation to the 0x00 - 0xFF range */
MACRUM 0:119624335925 1393 /* The LQI value mst be multiplied by ~1.1087 */
MACRUM 0:119624335925 1394 /* tmpLQI = hwLqi * 7123 ~= hwLqi * 65536 * 0.1087 = hwLqi * 2^16 * 0.1087*/
MACRUM 0:119624335925 1395 tmpLQI = ((uint32_t)hwLqi * (uint32_t)7123 );
MACRUM 0:119624335925 1396 /* tmpLQI = (tmpLQI / 2^16) + hwLqi */
MACRUM 0:119624335925 1397 tmpLQI = (uint32_t)(tmpLQI >> 16) + (uint32_t)hwLqi;
MACRUM 0:119624335925 1398
MACRUM 0:119624335925 1399 return (uint8_t)tmpLQI;
MACRUM 0:119624335925 1400 }
MACRUM 0:119624335925 1401 }
MACRUM 0:119624335925 1402
MACRUM 0:119624335925 1403 /*
MACRUM 0:119624335925 1404 * \brief Function enables/disables Rx promiscuous mode.
MACRUM 0:119624335925 1405 *
MACRUM 0:119624335925 1406 * \param state of XCVR promiscuous mode
MACRUM 0:119624335925 1407 *
MACRUM 0:119624335925 1408 * \return none
MACRUM 0:119624335925 1409 */
MACRUM 0:119624335925 1410 static void rf_promiscuous(uint8_t state)
MACRUM 0:119624335925 1411 {
MACRUM 0:119624335925 1412 uint8_t rxFrameFltReg, phyCtrl4Reg;
MACRUM 0:119624335925 1413
MACRUM 0:119624335925 1414 rxFrameFltReg = MCR20Drv_IndirectAccessSPIRead(RX_FRAME_FILTER);
MACRUM 0:119624335925 1415 phyCtrl4Reg = MCR20Drv_DirectAccessSPIRead(PHY_CTRL4);
MACRUM 0:119624335925 1416
MACRUM 0:119624335925 1417 if( state )
MACRUM 0:119624335925 1418 {
MACRUM 0:119624335925 1419 /* FRM_VER[1:0] = b00. 00: Any FrameVersion accepted (0,1,2 & 3) */
MACRUM 0:119624335925 1420 /* All frame types accepted*/
MACRUM 0:119624335925 1421 phyCtrl4Reg |= cPHY_CTRL4_PROMISCUOUS;
MACRUM 0:119624335925 1422 rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
MACRUM 0:119624335925 1423 rxFrameFltReg |= (cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT);
MACRUM 0:119624335925 1424 }
MACRUM 0:119624335925 1425 else
MACRUM 0:119624335925 1426 {
MACRUM 0:119624335925 1427 phyCtrl4Reg &= ~cPHY_CTRL4_PROMISCUOUS;
MACRUM 0:119624335925 1428 /* FRM_VER[1:0] = b11. Accept FrameVersion 0 and 1 packets, reject all others */
MACRUM 0:119624335925 1429 /* Beacon, Data and MAC command frame types accepted */
MACRUM 0:119624335925 1430 rxFrameFltReg &= ~(cRX_FRAME_FLT_FRM_VER);
MACRUM 0:119624335925 1431 rxFrameFltReg |= (0x03 << cRX_FRAME_FLT_FRM_VER_Shift_c);
MACRUM 0:119624335925 1432 rxFrameFltReg &= ~(cRX_FRAME_FLT_ACK_FT | cRX_FRAME_FLT_NS_FT);
MACRUM 0:119624335925 1433 }
MACRUM 0:119624335925 1434
MACRUM 0:119624335925 1435 MCR20Drv_IndirectAccessSPIWrite(RX_FRAME_FILTER, rxFrameFltReg);
MACRUM 0:119624335925 1436 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, phyCtrl4Reg);
MACRUM 0:119624335925 1437 }
MACRUM 0:119624335925 1438
MACRUM 0:119624335925 1439 /*
MACRUM 0:119624335925 1440 * \brief Function used to switch XCVR power state.
MACRUM 0:119624335925 1441 *
MACRUM 0:119624335925 1442 * \param state The XCVR power mode
MACRUM 0:119624335925 1443 *
MACRUM 0:119624335925 1444 * \return none
MACRUM 0:119624335925 1445 */
MACRUM 0:119624335925 1446 static void rf_set_power_state(xcvrPwrMode_t newState)
MACRUM 0:119624335925 1447 {
MACRUM 0:119624335925 1448 uint8_t pwrMode;
MACRUM 0:119624335925 1449 uint8_t xtalState;
MACRUM 0:119624335925 1450
MACRUM 0:119624335925 1451 if( mPwrState == newState )
MACRUM 0:119624335925 1452 {
MACRUM 0:119624335925 1453 return;
MACRUM 0:119624335925 1454 }
MACRUM 0:119624335925 1455
MACRUM 0:119624335925 1456 /* Read power settings from RF */
MACRUM 0:119624335925 1457 pwrMode = MCR20Drv_DirectAccessSPIRead(PWR_MODES);
MACRUM 0:119624335925 1458 xtalState = pwrMode & cPWR_MODES_XTALEN;
MACRUM 0:119624335925 1459
MACRUM 0:119624335925 1460 switch( newState )
MACRUM 0:119624335925 1461 {
MACRUM 0:119624335925 1462 case gXcvrPwrIdle_c:
MACRUM 0:119624335925 1463 pwrMode &= ~(cPWR_MODES_AUTODOZE);
MACRUM 0:119624335925 1464 pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_PMC_MODE);
MACRUM 0:119624335925 1465 break;
MACRUM 0:119624335925 1466 case gXcvrPwrAutodoze_c:
MACRUM 0:119624335925 1467 pwrMode |= (cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
MACRUM 0:119624335925 1468 break;
MACRUM 0:119624335925 1469 case gXcvrPwrDoze_c:
MACRUM 0:119624335925 1470 pwrMode &= ~(cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
MACRUM 0:119624335925 1471 pwrMode |= cPWR_MODES_XTALEN;
MACRUM 0:119624335925 1472 break;
MACRUM 0:119624335925 1473 case gXcvrPwrHibernate_c:
MACRUM 0:119624335925 1474 pwrMode &= ~(cPWR_MODES_XTALEN | cPWR_MODES_AUTODOZE | cPWR_MODES_PMC_MODE);
MACRUM 0:119624335925 1475 break;
MACRUM 0:119624335925 1476 default:
MACRUM 0:119624335925 1477 return;
MACRUM 0:119624335925 1478 }
MACRUM 0:119624335925 1479
MACRUM 0:119624335925 1480 mPwrState = newState;
MACRUM 0:119624335925 1481 MCR20Drv_DirectAccessSPIWrite(PWR_MODES, pwrMode);
MACRUM 0:119624335925 1482
MACRUM 0:119624335925 1483 if( !xtalState && (pwrMode & cPWR_MODES_XTALEN))
MACRUM 0:119624335925 1484 {
MACRUM 0:119624335925 1485 /* wait for crystal oscillator to complet its warmup */
MACRUM 0:119624335925 1486 while( ( MCR20Drv_DirectAccessSPIRead(PWR_MODES) & cPWR_MODES_XTAL_READY ) != cPWR_MODES_XTAL_READY);
MACRUM 0:119624335925 1487 /* wait for radio wakeup from hibernate interrupt */
MACRUM 0:119624335925 1488 while( ( MCR20Drv_DirectAccessSPIRead(IRQSTS2) & (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) ) != (cIRQSTS2_WAKE_IRQ | cIRQSTS2_TMRSTATUS) );
MACRUM 0:119624335925 1489
MACRUM 0:119624335925 1490 MCR20Drv_DirectAccessSPIWrite(IRQSTS2, cIRQSTS2_WAKE_IRQ);
MACRUM 0:119624335925 1491 }
MACRUM 0:119624335925 1492 }
MACRUM 0:119624335925 1493
MACRUM 0:119624335925 1494 /*
MACRUM 0:119624335925 1495 * \brief Function reads the energy level on the preselected channel.
MACRUM 0:119624335925 1496 *
MACRUM 0:119624335925 1497 * \return energy level
MACRUM 0:119624335925 1498 */
MACRUM 0:119624335925 1499 static uint8_t rf_get_channel_energy(void)
MACRUM 0:119624335925 1500 {
MACRUM 0:119624335925 1501 uint8_t ccaMode;
MACRUM 0:119624335925 1502
MACRUM 0:119624335925 1503 MCR20Drv_IRQ_Disable();
MACRUM 0:119624335925 1504 /* RX can start only from Idle state */
MACRUM 0:119624335925 1505 if( mPhySeqState != gIdle_c )
MACRUM 0:119624335925 1506 {
MACRUM 0:119624335925 1507 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1508 return 0;
MACRUM 0:119624335925 1509 }
MACRUM 0:119624335925 1510
MACRUM 0:119624335925 1511 /* Set XCVR power state in run mode */
MACRUM 0:119624335925 1512 rf_set_power_state(gXcvrRunState_d);
MACRUM 0:119624335925 1513
MACRUM 0:119624335925 1514 /* Switch to ED mode */
MACRUM 0:119624335925 1515 ccaMode = (mStatusAndControlRegs[PHY_CTRL4] >> cPHY_CTRL4_CCATYPE_Shift_c) & cPHY_CTRL4_CCATYPE;
MACRUM 0:119624335925 1516 if( ccaMode != gCcaED_c )
MACRUM 0:119624335925 1517 {
MACRUM 0:119624335925 1518 mStatusAndControlRegs[PHY_CTRL4] &= ~(cPHY_CTRL4_CCATYPE << cPHY_CTRL4_CCATYPE_Shift_c);
MACRUM 0:119624335925 1519 mStatusAndControlRegs[PHY_CTRL4] |= gCcaED_c << cPHY_CTRL4_CCATYPE_Shift_c;
MACRUM 0:119624335925 1520 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL4, mStatusAndControlRegs[PHY_CTRL4]);
MACRUM 0:119624335925 1521 }
MACRUM 0:119624335925 1522
MACRUM 0:119624335925 1523 /* Start ED sequence */
MACRUM 0:119624335925 1524 mStatusAndControlRegs[PHY_CTRL1] |= gCCA_c;
MACRUM 0:119624335925 1525 MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ | cIRQSTS1_SEQIRQ);
MACRUM 0:119624335925 1526 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 1527 /* Wait for sequence to finish */
MACRUM 0:119624335925 1528 while ( !(MCR20Drv_DirectAccessSPIRead(IRQSTS1) & cIRQSTS1_SEQIRQ));
MACRUM 0:119624335925 1529 /* Set XCVR to Idle */
MACRUM 0:119624335925 1530 mStatusAndControlRegs[PHY_CTRL1] &= ~(cPHY_CTRL1_XCVSEQ);
MACRUM 0:119624335925 1531 MCR20Drv_DirectAccessSPIWrite(PHY_CTRL1, mStatusAndControlRegs[PHY_CTRL1]);
MACRUM 0:119624335925 1532 MCR20Drv_DirectAccessSPIWrite(IRQSTS1, cIRQSTS1_CCAIRQ | cIRQSTS1_SEQIRQ);
MACRUM 0:119624335925 1533
MACRUM 0:119624335925 1534 MCR20Drv_IRQ_Enable();
MACRUM 0:119624335925 1535
MACRUM 0:119624335925 1536 return rf_convert_energy_level(MCR20Drv_DirectAccessSPIRead(CCA1_ED_FNL));
MACRUM 0:119624335925 1537 }
MACRUM 0:119624335925 1538
MACRUM 0:119624335925 1539 /*
MACRUM 0:119624335925 1540 * \brief Function converts the energy level from dBm to a 0-255 value.
MACRUM 0:119624335925 1541 *
MACRUM 0:119624335925 1542 * \param energyLevel in dBm
MACRUM 0:119624335925 1543 *
MACRUM 0:119624335925 1544 * \return energy level (0-255)
MACRUM 0:119624335925 1545 */
MACRUM 0:119624335925 1546 static uint8_t rf_convert_energy_level(uint8_t energyLevel)
MACRUM 0:119624335925 1547 {
MACRUM 0:119624335925 1548 if(energyLevel >= 90)
MACRUM 0:119624335925 1549 {
MACRUM 0:119624335925 1550 /* ED value is below minimum. Return 0x00. */
MACRUM 0:119624335925 1551 energyLevel = 0x00;
MACRUM 0:119624335925 1552 }
MACRUM 0:119624335925 1553 else if(energyLevel <= 26)
MACRUM 0:119624335925 1554 {
MACRUM 0:119624335925 1555 /* ED value is above maximum. Return 0xFF. */
MACRUM 0:119624335925 1556 energyLevel = 0xFF;
MACRUM 0:119624335925 1557 }
MACRUM 0:119624335925 1558 else
MACRUM 0:119624335925 1559 {
MACRUM 0:119624335925 1560 /* Energy level (-90 dBm to -26 dBm ) --> varies form 0 to 64 */
MACRUM 0:119624335925 1561 energyLevel = (90 - energyLevel);
MACRUM 0:119624335925 1562 /* Rescale the energy level values to the 0x00-0xff range (0 to 64 translates in 0 to 255) */
MACRUM 0:119624335925 1563 /* energyLevel * 3.9844 ~= 4 */
MACRUM 0:119624335925 1564 /* Multiply with 4=2^2 by shifting left.
MACRUM 0:119624335925 1565 The multiplication will not overflow beacause energyLevel has values between 0 and 63 */
MACRUM 0:119624335925 1566 energyLevel <<= 2;
MACRUM 0:119624335925 1567 }
MACRUM 0:119624335925 1568
MACRUM 0:119624335925 1569 return energyLevel;
MACRUM 0:119624335925 1570 }
MACRUM 0:119624335925 1571
MACRUM 0:119624335925 1572 static uint8_t rf_scale_lqi(int8_t rssi)
MACRUM 0:119624335925 1573 {
MACRUM 0:119624335925 1574 uint8_t scaled_lqi;
MACRUM 0:119624335925 1575 /*Worst case sensitivity*/
MACRUM 0:119624335925 1576 const int8_t rf_sensitivity = -98;
MACRUM 0:119624335925 1577
MACRUM 0:119624335925 1578 /*rssi < RF sensitivity*/
MACRUM 0:119624335925 1579 if(rssi < rf_sensitivity)
MACRUM 0:119624335925 1580 scaled_lqi=0;
MACRUM 0:119624335925 1581 /*-91 dBm < rssi < -81 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1582 /*-90 dBm < rssi < -80 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1583 else if(rssi < (rf_sensitivity + 10))
MACRUM 0:119624335925 1584 scaled_lqi=31;
MACRUM 0:119624335925 1585 /*-81 dBm < rssi < -71 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1586 /*-80 dBm < rssi < -70 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1587 else if(rssi < (rf_sensitivity + 20))
MACRUM 0:119624335925 1588 scaled_lqi=207;
MACRUM 0:119624335925 1589 /*-71 dBm < rssi < -61 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1590 /*-70 dBm < rssi < -60 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1591 else if(rssi < (rf_sensitivity + 30))
MACRUM 0:119624335925 1592 scaled_lqi=255;
MACRUM 0:119624335925 1593 /*-61 dBm < rssi < -51 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1594 /*-60 dBm < rssi < -50 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1595 else if(rssi < (rf_sensitivity + 40))
MACRUM 0:119624335925 1596 scaled_lqi=255;
MACRUM 0:119624335925 1597 /*-51 dBm < rssi < -41 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1598 /*-50 dBm < rssi < -40 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1599 else if(rssi < (rf_sensitivity + 50))
MACRUM 0:119624335925 1600 scaled_lqi=255;
MACRUM 0:119624335925 1601 /*-41 dBm < rssi < -31 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1602 /*-40 dBm < rssi < -30 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1603 else if(rssi < (rf_sensitivity + 60))
MACRUM 0:119624335925 1604 scaled_lqi=255;
MACRUM 0:119624335925 1605 /*-31 dBm < rssi < -21 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1606 /*-30 dBm < rssi < -20 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1607 else if(rssi < (rf_sensitivity + 70))
MACRUM 0:119624335925 1608 scaled_lqi=255;
MACRUM 0:119624335925 1609 /*rssi > RF saturation*/
MACRUM 0:119624335925 1610 else if(rssi > (rf_sensitivity + 80))
MACRUM 0:119624335925 1611 scaled_lqi=111;
MACRUM 0:119624335925 1612 /*-21 dBm < rssi < -11 dBm (AT86RF233 XPro)*/
MACRUM 0:119624335925 1613 /*-20 dBm < rssi < -10 dBm (AT86RF212B XPro)*/
MACRUM 0:119624335925 1614 else
MACRUM 0:119624335925 1615 scaled_lqi=255;
MACRUM 0:119624335925 1616
MACRUM 0:119624335925 1617 return scaled_lqi;
MACRUM 0:119624335925 1618 }
MACRUM 0:119624335925 1619
MACRUM 0:119624335925 1620
MACRUM 0:119624335925 1621 /*****************************************************************************/
MACRUM 0:119624335925 1622 /* Layer porting to the Freescale driver */
MACRUM 0:119624335925 1623 /*****************************************************************************/
MACRUM 0:119624335925 1624 extern "C" void xcvr_spi_init(uint32_t instance)
MACRUM 0:119624335925 1625 {
MACRUM 0:119624335925 1626 (void)instance;
MACRUM 0:119624335925 1627 }
MACRUM 0:119624335925 1628
MACRUM 0:119624335925 1629 extern "C" void RF_IRQ_Init(void) {
MACRUM 0:119624335925 1630 MBED_ASSERT(irq != NULL);
MACRUM 0:119624335925 1631 irq->mode(PullUp);
MACRUM 0:119624335925 1632 irq->fall(&PHY_InterruptHandler);
MACRUM 0:119624335925 1633 }
MACRUM 0:119624335925 1634
MACRUM 0:119624335925 1635 extern "C" void RF_IRQ_Enable(void) {
MACRUM 0:119624335925 1636 MBED_ASSERT(irq != NULL);
MACRUM 0:119624335925 1637 irq->enable_irq();
MACRUM 0:119624335925 1638 }
MACRUM 0:119624335925 1639
MACRUM 0:119624335925 1640 extern "C" void RF_IRQ_Disable(void) {
MACRUM 0:119624335925 1641 MBED_ASSERT(irq != NULL);
MACRUM 0:119624335925 1642 irq->disable_irq();
MACRUM 0:119624335925 1643 }
MACRUM 0:119624335925 1644
MACRUM 0:119624335925 1645 extern "C" uint8_t RF_isIRQ_Pending(void) {
MACRUM 0:119624335925 1646 MBED_ASSERT(rf != NULL);
MACRUM 0:119624335925 1647 return !irq_pin->read();
MACRUM 0:119624335925 1648 }
MACRUM 0:119624335925 1649
MACRUM 0:119624335925 1650 extern "C" void RF_RST_Set(int state) {
MACRUM 0:119624335925 1651 MBED_ASSERT(rst != NULL);
MACRUM 0:119624335925 1652 *rst = state;
MACRUM 0:119624335925 1653 }
MACRUM 0:119624335925 1654
MACRUM 0:119624335925 1655 extern "C" void gXcvrAssertCS_d(void)
MACRUM 0:119624335925 1656 {
MACRUM 0:119624335925 1657 MBED_ASSERT(cs != NULL);
MACRUM 0:119624335925 1658 *cs = 0;
MACRUM 0:119624335925 1659 }
MACRUM 0:119624335925 1660
MACRUM 0:119624335925 1661 extern "C" void gXcvrDeassertCS_d(void)
MACRUM 0:119624335925 1662 {
MACRUM 0:119624335925 1663 MBED_ASSERT(cs != NULL);
MACRUM 0:119624335925 1664 *cs = 1;
MACRUM 0:119624335925 1665 }
MACRUM 0:119624335925 1666
MACRUM 0:119624335925 1667 extern "C" void xcvr_spi_configure_speed(uint32_t instance, uint32_t freq)
MACRUM 0:119624335925 1668 {
MACRUM 0:119624335925 1669 MBED_ASSERT(spi != NULL);
MACRUM 0:119624335925 1670 (void)instance;
MACRUM 0:119624335925 1671 spi->frequency(freq);
MACRUM 0:119624335925 1672 }
MACRUM 0:119624335925 1673
MACRUM 0:119624335925 1674 extern "C" void xcvr_spi_transfer(uint32_t instance,
MACRUM 0:119624335925 1675 uint8_t * sendBuffer,
MACRUM 0:119624335925 1676 uint8_t * receiveBuffer,
MACRUM 0:119624335925 1677 size_t transferByteCount)
MACRUM 0:119624335925 1678 {
MACRUM 0:119624335925 1679 MBED_ASSERT(spi != NULL);
MACRUM 0:119624335925 1680 (void)instance;
MACRUM 0:119624335925 1681 volatile uint8_t dummy;
MACRUM 0:119624335925 1682
MACRUM 0:119624335925 1683 if( !transferByteCount )
MACRUM 0:119624335925 1684 return;
MACRUM 0:119624335925 1685
MACRUM 0:119624335925 1686 if( !sendBuffer && !receiveBuffer )
MACRUM 0:119624335925 1687 return;
MACRUM 0:119624335925 1688
MACRUM 0:119624335925 1689 while( transferByteCount-- )
MACRUM 0:119624335925 1690 {
MACRUM 0:119624335925 1691 if( sendBuffer )
MACRUM 0:119624335925 1692 {
MACRUM 0:119624335925 1693 dummy = *sendBuffer;
MACRUM 0:119624335925 1694 sendBuffer++;
MACRUM 0:119624335925 1695 }
MACRUM 0:119624335925 1696 else
MACRUM 0:119624335925 1697 {
MACRUM 0:119624335925 1698 dummy = 0xFF;
MACRUM 0:119624335925 1699 }
MACRUM 0:119624335925 1700
MACRUM 0:119624335925 1701 dummy = spi->write(dummy);
MACRUM 0:119624335925 1702
MACRUM 0:119624335925 1703 if( receiveBuffer )
MACRUM 0:119624335925 1704 {
MACRUM 0:119624335925 1705 *receiveBuffer = dummy;
MACRUM 0:119624335925 1706 receiveBuffer++;
MACRUM 0:119624335925 1707 }
MACRUM 0:119624335925 1708 }
MACRUM 0:119624335925 1709 }
MACRUM 0:119624335925 1710
MACRUM 0:119624335925 1711 /*****************************************************************************/
MACRUM 0:119624335925 1712 /*****************************************************************************/
MACRUM 0:119624335925 1713
MACRUM 0:119624335925 1714 static void rf_if_lock(void)
MACRUM 0:119624335925 1715 {
MACRUM 0:119624335925 1716 platform_enter_critical();
MACRUM 0:119624335925 1717 }
MACRUM 0:119624335925 1718
MACRUM 0:119624335925 1719 static void rf_if_unlock(void)
MACRUM 0:119624335925 1720 {
MACRUM 0:119624335925 1721 platform_exit_critical();
MACRUM 0:119624335925 1722 }
MACRUM 0:119624335925 1723
MACRUM 0:119624335925 1724 NanostackRfPhyMcr20a::NanostackRfPhyMcr20a(PinName spi_mosi, PinName spi_miso,
MACRUM 0:119624335925 1725 PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_irq)
MACRUM 0:119624335925 1726 : _spi(spi_mosi, spi_miso, spi_sclk), _rf_cs(spi_cs), _rf_rst(spi_rst, 1),
MACRUM 0:119624335925 1727 _rf_irq(spi_irq), _rf_irq_pin(spi_irq)
MACRUM 0:119624335925 1728 {
MACRUM 0:119624335925 1729 // Do nothing
MACRUM 0:119624335925 1730 }
MACRUM 0:119624335925 1731
MACRUM 0:119624335925 1732 NanostackRfPhyMcr20a::~NanostackRfPhyMcr20a()
MACRUM 0:119624335925 1733 {
MACRUM 0:119624335925 1734 // Do nothing
MACRUM 0:119624335925 1735 }
MACRUM 0:119624335925 1736
MACRUM 0:119624335925 1737 int8_t NanostackRfPhyMcr20a::rf_register()
MACRUM 0:119624335925 1738 {
MACRUM 0:119624335925 1739
MACRUM 0:119624335925 1740 rf_if_lock();
MACRUM 0:119624335925 1741
MACRUM 0:119624335925 1742 if (rf != NULL) {
MACRUM 0:119624335925 1743 rf_if_unlock();
MACRUM 0:119624335925 1744 error("Multiple registrations of NanostackRfPhyMcr20a not supported");
MACRUM 0:119624335925 1745 return -1;
MACRUM 0:119624335925 1746 }
MACRUM 0:119624335925 1747
MACRUM 0:119624335925 1748 irq_thread.start(mbed::callback(PHY_InterruptThread));
MACRUM 0:119624335925 1749
MACRUM 0:119624335925 1750 _pins_set();
MACRUM 0:119624335925 1751 int8_t radio_id = rf_device_register();
MACRUM 0:119624335925 1752 if (radio_id < 0) {
MACRUM 0:119624335925 1753 _pins_clear();
MACRUM 0:119624335925 1754 rf = NULL;
MACRUM 0:119624335925 1755 }
MACRUM 0:119624335925 1756
MACRUM 0:119624335925 1757 rf_if_unlock();
MACRUM 0:119624335925 1758 return radio_id;
MACRUM 0:119624335925 1759 }
MACRUM 0:119624335925 1760
MACRUM 0:119624335925 1761 void NanostackRfPhyMcr20a::rf_unregister()
MACRUM 0:119624335925 1762 {
MACRUM 0:119624335925 1763 rf_if_lock();
MACRUM 0:119624335925 1764
MACRUM 0:119624335925 1765 if (rf != this) {
MACRUM 0:119624335925 1766 rf_if_unlock();
MACRUM 0:119624335925 1767 return;
MACRUM 0:119624335925 1768 }
MACRUM 0:119624335925 1769
MACRUM 0:119624335925 1770 rf_device_unregister();
MACRUM 0:119624335925 1771 rf = NULL;
MACRUM 0:119624335925 1772 _pins_clear();
MACRUM 0:119624335925 1773
MACRUM 0:119624335925 1774 rf_if_unlock();
MACRUM 0:119624335925 1775 }
MACRUM 0:119624335925 1776
MACRUM 0:119624335925 1777 void NanostackRfPhyMcr20a::get_mac_address(uint8_t *mac)
MACRUM 0:119624335925 1778 {
MACRUM 0:119624335925 1779 rf_if_lock();
MACRUM 0:119624335925 1780
MACRUM 0:119624335925 1781 memcpy((void*)mac, (void*)MAC_address, sizeof(MAC_address));
MACRUM 0:119624335925 1782
MACRUM 0:119624335925 1783 rf_if_unlock();
MACRUM 0:119624335925 1784 }
MACRUM 0:119624335925 1785
MACRUM 0:119624335925 1786 void NanostackRfPhyMcr20a::set_mac_address(uint8_t *mac)
MACRUM 0:119624335925 1787 {
MACRUM 0:119624335925 1788 rf_if_lock();
MACRUM 0:119624335925 1789
MACRUM 0:119624335925 1790 if (NULL != rf) {
MACRUM 0:119624335925 1791 error("NanostackRfPhyAtmel cannot change mac address when running");
MACRUM 0:119624335925 1792 rf_if_unlock();
MACRUM 0:119624335925 1793 return;
MACRUM 0:119624335925 1794 }
MACRUM 0:119624335925 1795 memcpy((void*)MAC_address, (void*)mac, sizeof(MAC_address));
MACRUM 0:119624335925 1796
MACRUM 0:119624335925 1797 rf_if_unlock();
MACRUM 0:119624335925 1798 }
MACRUM 0:119624335925 1799
MACRUM 0:119624335925 1800 void NanostackRfPhyMcr20a::_pins_set()
MACRUM 0:119624335925 1801 {
MACRUM 0:119624335925 1802 spi = &_spi;
MACRUM 0:119624335925 1803 cs = &_rf_cs;
MACRUM 0:119624335925 1804 rst = &_rf_rst;
MACRUM 0:119624335925 1805 irq = &_rf_irq;
MACRUM 0:119624335925 1806 irq_pin = &_rf_irq_pin;
MACRUM 0:119624335925 1807 }
MACRUM 0:119624335925 1808
MACRUM 0:119624335925 1809 void NanostackRfPhyMcr20a::_pins_clear()
MACRUM 0:119624335925 1810 {
MACRUM 0:119624335925 1811 spi = NULL;
MACRUM 0:119624335925 1812 cs = NULL;
MACRUM 0:119624335925 1813 rst = NULL;
MACRUM 0:119624335925 1814 irq = NULL;
MACRUM 0:119624335925 1815 irq_pin = NULL;
MACRUM 0:119624335925 1816 }
MACRUM 0:119624335925 1817
MACRUM 0:119624335925 1818 #endif // MBED_CONF_NANOSTACK_CONFIGURATION