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INIT_HW/INIT_HW.cpp@21:e5f1a43ea6f9, 2019-09-09 (annotated)
- Committer:
- Lightvalve
- Date:
- Mon Sep 09 10:10:31 2019 +0000
- Revision:
- 21:e5f1a43ea6f9
- Parent:
- 20:806196fda269
- Child:
- 23:59218d4a256d
190909_19_10
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GiJeongKim | 0:51c43836c1d7 | 1 | #include "mbed.h" |
GiJeongKim | 0:51c43836c1d7 | 2 | #include "FastPWM.h" |
GiJeongKim | 0:51c43836c1d7 | 3 | #include "setting.h" |
GiJeongKim | 0:51c43836c1d7 | 4 | |
GiJeongKim | 0:51c43836c1d7 | 5 | void Init_ADC(void){ |
GiJeongKim | 0:51c43836c1d7 | 6 | // ADC Setup |
GiJeongKim | 0:51c43836c1d7 | 7 | RCC->APB2ENR |= RCC_APB2ENR_ADC3EN; // clock for ADC3 |
GiJeongKim | 0:51c43836c1d7 | 8 | RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2 |
GiJeongKim | 0:51c43836c1d7 | 9 | RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1 |
GiJeongKim | 0:51c43836c1d7 | 10 | |
GiJeongKim | 0:51c43836c1d7 | 11 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // Enable clock for GPIOC |
GiJeongKim | 0:51c43836c1d7 | 12 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // Enable clock for GPIOA |
GiJeongKim | 0:51c43836c1d7 | 13 | |
GiJeongKim | 0:51c43836c1d7 | 14 | ADC->CCR = 0x00000016; // Regular simultaneous mode only |
GiJeongKim | 0:51c43836c1d7 | 15 | ADC1->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC1 ON |
GiJeongKim | 0:51c43836c1d7 | 16 | ADC1->SQR3 = 0x0000000E; //channel // use PC_4 as input- ADC1_IN14 |
GiJeongKim | 0:51c43836c1d7 | 17 | ADC2->CR2 |= ADC_CR2_ADON;//0x00000001; // ADC2 ON |
GiJeongKim | 0:51c43836c1d7 | 18 | ADC2->SQR3 = 0x00000008; // use PB_0 as input - ADC2_IN8 |
GiJeongKim | 0:51c43836c1d7 | 19 | ADC3->CR2 |= ADC_CR2_ADON; // ADC3 ON |
GiJeongKim | 0:51c43836c1d7 | 20 | ADC3->SQR3 = 0x0000000B; // use PC_1, - ADC3_IN11 |
GiJeongKim | 0:51c43836c1d7 | 21 | GPIOC->MODER |= 0b1100001100; //each channel // PC_4, PC_1 are analog inputs |
GiJeongKim | 0:51c43836c1d7 | 22 | GPIOB->MODER |= 0x3; // PB_0 as analog input |
GiJeongKim | 0:51c43836c1d7 | 23 | |
jobuuu | 2:a1c0a37df760 | 24 | ADC1->SMPR1 |= 0x00001000; // 15 cycles on CH_14, 0b0001000000000000 |
jobuuu | 2:a1c0a37df760 | 25 | ADC2->SMPR2 |= 0x01000000; // 15 cycles on CH_8, 0b0000000100000000<<16 |
jobuuu | 2:a1c0a37df760 | 26 | ADC3->SMPR1 |= 0x00000008; // 15 cycles on CH_11, 0b0000000000001000 |
GiJeongKim | 0:51c43836c1d7 | 27 | |
GiJeongKim | 0:51c43836c1d7 | 28 | } |
GiJeongKim | 0:51c43836c1d7 | 29 | |
GiJeongKim | 0:51c43836c1d7 | 30 | void Init_PWM(){ |
GiJeongKim | 0:51c43836c1d7 | 31 | |
GiJeongKim | 0:51c43836c1d7 | 32 | RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // enable TIM4 clock |
GiJeongKim | 0:51c43836c1d7 | 33 | FastPWM pwm_v(PIN_V); |
GiJeongKim | 0:51c43836c1d7 | 34 | FastPWM pwm_w(PIN_W); |
GiJeongKim | 0:51c43836c1d7 | 35 | |
GiJeongKim | 0:51c43836c1d7 | 36 | //ISR Setup |
GiJeongKim | 0:51c43836c1d7 | 37 | |
GiJeongKim | 0:51c43836c1d7 | 38 | NVIC_EnableIRQ(TIM4_IRQn); //Enable TIM4 IRQ |
GiJeongKim | 0:51c43836c1d7 | 39 | |
GiJeongKim | 0:51c43836c1d7 | 40 | TIM4->DIER |= TIM_DIER_UIE; // enable update interrupt |
GiJeongKim | 0:51c43836c1d7 | 41 | TIM4->CR1 = 0x40; // CMS = 10, interrupt only when counting up // Center-aligned mode |
GiJeongKim | 0:51c43836c1d7 | 42 | TIM4->CR1 |= TIM_CR1_UDIS; |
GiJeongKim | 0:51c43836c1d7 | 43 | TIM4->CR1 |= TIM_CR1_ARPE; // autoreload on, |
GiJeongKim | 0:51c43836c1d7 | 44 | TIM4->RCR |= 0x001; // update event once per up/down count of TIM4 |
GiJeongKim | 0:51c43836c1d7 | 45 | TIM4->EGR |= TIM_EGR_UG; |
GiJeongKim | 0:51c43836c1d7 | 46 | |
GiJeongKim | 0:51c43836c1d7 | 47 | //PWM Setup |
GiJeongKim | 0:51c43836c1d7 | 48 | |
GiJeongKim | 0:51c43836c1d7 | 49 | TIM4->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock |
GiJeongKim | 0:51c43836c1d7 | 50 | TIM4->ARR = PWM_ARR; // set auto reload, 40 khz |
GiJeongKim | 0:51c43836c1d7 | 51 | TIM4->CCER |= ~(TIM_CCER_CC1NP); // Interupt when low side is on. |
GiJeongKim | 0:51c43836c1d7 | 52 | TIM4->CR1 |= TIM_CR1_CEN; // enable TIM4 |
GiJeongKim | 0:51c43836c1d7 | 53 | |
GiJeongKim | 0:51c43836c1d7 | 54 | } |
Lightvalve | 11:82d8768d7351 | 55 | |
Lightvalve | 11:82d8768d7351 | 56 | void Init_TMR3(){ |
Lightvalve | 11:82d8768d7351 | 57 | RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // enable TIM3 clock |
Lightvalve | 11:82d8768d7351 | 58 | |
Lightvalve | 11:82d8768d7351 | 59 | //ISR Setup |
Lightvalve | 11:82d8768d7351 | 60 | |
Lightvalve | 11:82d8768d7351 | 61 | NVIC_EnableIRQ(TIM3_IRQn); //Enable TIM3 IRQ |
Lightvalve | 11:82d8768d7351 | 62 | |
Lightvalve | 11:82d8768d7351 | 63 | TIM3->DIER |= TIM_DIER_UIE; // enable update interrupt |
Lightvalve | 11:82d8768d7351 | 64 | TIM3->CR1 = 0x40; // CMS = 10, interrupt only when counting up // Center-aligned mode |
Lightvalve | 11:82d8768d7351 | 65 | TIM3->CR1 |= TIM_CR1_UDIS; |
Lightvalve | 11:82d8768d7351 | 66 | TIM3->CR1 |= TIM_CR1_ARPE; // autoreload on, |
Lightvalve | 11:82d8768d7351 | 67 | TIM3->RCR |= 0x001; // update event once per up/down count of TIM3 |
Lightvalve | 11:82d8768d7351 | 68 | TIM3->EGR |= TIM_EGR_UG; |
Lightvalve | 11:82d8768d7351 | 69 | |
Lightvalve | 11:82d8768d7351 | 70 | TIM3->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock |
Lightvalve | 15:bd0d12728506 | 71 | TIM3->ARR = TMR3_COUNT; // set auto reload, 5 khz |
Lightvalve | 11:82d8768d7351 | 72 | TIM3->CCER |= ~(TIM_CCER_CC1NP); // Interupt when low side is on. |
Lightvalve | 11:82d8768d7351 | 73 | TIM3->CR1 |= TIM_CR1_CEN; // enable TIM4 |
Lightvalve | 20:806196fda269 | 74 | } |
Lightvalve | 20:806196fda269 | 75 | |
Lightvalve | 20:806196fda269 | 76 | void Init_TMR5(){ |
Lightvalve | 20:806196fda269 | 77 | RCC->APB1ENR |= RCC_APB1ENR_TIM5EN; // enable TIM5 clock |
Lightvalve | 20:806196fda269 | 78 | |
Lightvalve | 20:806196fda269 | 79 | //ISR Setup |
Lightvalve | 20:806196fda269 | 80 | |
Lightvalve | 20:806196fda269 | 81 | NVIC_EnableIRQ(TIM5_IRQn); //Enable TIM5 IRQ |
Lightvalve | 20:806196fda269 | 82 | |
Lightvalve | 20:806196fda269 | 83 | TIM5->DIER |= TIM_DIER_UIE; // enable update interrupt |
Lightvalve | 20:806196fda269 | 84 | TIM5->CR1 = 0x40; // CMS = 10, interrupt only when counting up // Center-aligned mode |
Lightvalve | 20:806196fda269 | 85 | TIM5->CR1 |= TIM_CR1_UDIS; |
Lightvalve | 20:806196fda269 | 86 | TIM5->CR1 |= TIM_CR1_ARPE; // autoreload on, |
Lightvalve | 20:806196fda269 | 87 | TIM5->RCR |= 0x001; // update event once per up/down count of TIM5 |
Lightvalve | 20:806196fda269 | 88 | TIM5->EGR |= TIM_EGR_UG; |
Lightvalve | 20:806196fda269 | 89 | |
Lightvalve | 21:e5f1a43ea6f9 | 90 | TIM5->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock |
Lightvalve | 20:806196fda269 | 91 | TIM5->ARR = TMR5_COUNT; // set auto reload, 5 khz |
Lightvalve | 20:806196fda269 | 92 | TIM5->CCER |= ~(TIM_CCER_CC1NP); // Interupt when low side is on. |
Lightvalve | 20:806196fda269 | 93 | TIM5->CR1 |= TIM_CR1_CEN; // enable TIM5 |
Lightvalve | 11:82d8768d7351 | 94 | } |