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Diff: system_LPC17xx.c
- Revision:
- 46:2670fa0fcebc
- Parent:
- 44:80289a836583
- Child:
- 49:53277d871197
diff -r cbc955aecebe -r 2670fa0fcebc system_LPC17xx.c --- a/system_LPC17xx.c Tue Feb 09 13:47:26 2016 +0000 +++ b/system_LPC17xx.c Wed Feb 10 03:02:35 2016 +0000 @@ -387,7 +387,17 @@ // </e> */ #define FLASH_SETUP 1 -#define FLASHCFG_Val 0x0000303A +//Flash Accelerator Configuration Register +// 11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A +// 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. 0x3 +// 0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. +// 0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. +// 0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. +// 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. +// 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. +// 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices. +// 31:16 - Reserved. The value read from a reserved bit is not defined. NA +#define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access /* //-------- <<< end of configuration section >>> ------------------------------