Dmitry Kovalev
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Dmitry Kovalev
host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c@23:12e6183f04d4, 2016-02-03 (annotated)
- Committer:
- Kovalev_D
- Date:
- Wed Feb 03 10:44:42 2016 +0300
- Revision:
- 23:12e6183f04d4
[thyz
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kovalev_D |
23:12e6183f04d4 | 1 | /**************************************************************************//** |
| Kovalev_D |
23:12e6183f04d4 | 2 | * @file system_LPC17xx.c |
| Kovalev_D |
23:12e6183f04d4 | 3 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File |
| Kovalev_D |
23:12e6183f04d4 | 4 | * for the NXP LPC17xx Device Series |
| Kovalev_D |
23:12e6183f04d4 | 5 | * @version V1.03 |
| Kovalev_D |
23:12e6183f04d4 | 6 | * @date 07. October 2009 |
| Kovalev_D |
23:12e6183f04d4 | 7 | * |
| Kovalev_D |
23:12e6183f04d4 | 8 | * @note |
| Kovalev_D |
23:12e6183f04d4 | 9 | * Copyright (C) 2009 ARM Limited. All rights reserved. |
| Kovalev_D |
23:12e6183f04d4 | 10 | * |
| Kovalev_D |
23:12e6183f04d4 | 11 | * @par |
| Kovalev_D |
23:12e6183f04d4 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| Kovalev_D |
23:12e6183f04d4 | 13 | * processor based microcontrollers. This file can be freely distributed |
| Kovalev_D |
23:12e6183f04d4 | 14 | * within development tools that are supporting such ARM based processors. |
| Kovalev_D |
23:12e6183f04d4 | 15 | * |
| Kovalev_D |
23:12e6183f04d4 | 16 | * @par |
| Kovalev_D |
23:12e6183f04d4 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| Kovalev_D |
23:12e6183f04d4 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| Kovalev_D |
23:12e6183f04d4 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| Kovalev_D |
23:12e6183f04d4 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| Kovalev_D |
23:12e6183f04d4 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| Kovalev_D |
23:12e6183f04d4 | 22 | * |
| Kovalev_D |
23:12e6183f04d4 | 23 | ******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 24 | |
| Kovalev_D |
23:12e6183f04d4 | 25 | |
| Kovalev_D |
23:12e6183f04d4 | 26 | #include <stdint.h> |
| Kovalev_D |
23:12e6183f04d4 | 27 | #include "LPC17xx.h" |
| Kovalev_D |
23:12e6183f04d4 | 28 | |
| Kovalev_D |
23:12e6183f04d4 | 29 | /* |
| Kovalev_D |
23:12e6183f04d4 | 30 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| Kovalev_D |
23:12e6183f04d4 | 31 | */ |
| Kovalev_D |
23:12e6183f04d4 | 32 | |
| Kovalev_D |
23:12e6183f04d4 | 33 | /*--------------------- Clock Configuration ---------------------------------- |
| Kovalev_D |
23:12e6183f04d4 | 34 | // |
| Kovalev_D |
23:12e6183f04d4 | 35 | // <e> Clock Configuration |
| Kovalev_D |
23:12e6183f04d4 | 36 | // <h> System Controls and Status Register (SCS) |
| Kovalev_D |
23:12e6183f04d4 | 37 | // <o1.4> OSCRANGE: Main Oscillator Range Select |
| Kovalev_D |
23:12e6183f04d4 | 38 | // <0=> 1 MHz to 20 MHz |
| Kovalev_D |
23:12e6183f04d4 | 39 | // <1=> 15 MHz to 24 MHz |
| Kovalev_D |
23:12e6183f04d4 | 40 | // <e1.5> OSCEN: Main Oscillator Enable |
| Kovalev_D |
23:12e6183f04d4 | 41 | // </e> |
| Kovalev_D |
23:12e6183f04d4 | 42 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 43 | // |
| Kovalev_D |
23:12e6183f04d4 | 44 | // <h> Clock Source Select Register (CLKSRCSEL) |
| Kovalev_D |
23:12e6183f04d4 | 45 | // <o2.0..1> CLKSRC: PLL Clock Source Selection |
| Kovalev_D |
23:12e6183f04d4 | 46 | // <0=> Internal RC oscillator |
| Kovalev_D |
23:12e6183f04d4 | 47 | // <1=> Main oscillator |
| Kovalev_D |
23:12e6183f04d4 | 48 | // <2=> RTC oscillator |
| Kovalev_D |
23:12e6183f04d4 | 49 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 50 | // |
| Kovalev_D |
23:12e6183f04d4 | 51 | // <e3> PLL0 Configuration (Main PLL) |
| Kovalev_D |
23:12e6183f04d4 | 52 | // <h> PLL0 Configuration Register (PLL0CFG) |
| Kovalev_D |
23:12e6183f04d4 | 53 | // <i> F_cco0 = (2 * M * F_in) / N |
| Kovalev_D |
23:12e6183f04d4 | 54 | // <i> F_in must be in the range of 32 kHz to 50 MHz |
| Kovalev_D |
23:12e6183f04d4 | 55 | // <i> F_cco0 must be in the range of 275 MHz to 550 MHz |
| Kovalev_D |
23:12e6183f04d4 | 56 | // <o4.0..14> MSEL: PLL Multiplier Selection |
| Kovalev_D |
23:12e6183f04d4 | 57 | // <6-32768><#-1> |
| Kovalev_D |
23:12e6183f04d4 | 58 | // <i> M Value |
| Kovalev_D |
23:12e6183f04d4 | 59 | // <o4.16..23> NSEL: PLL Divider Selection |
| Kovalev_D |
23:12e6183f04d4 | 60 | // <1-256><#-1> |
| Kovalev_D |
23:12e6183f04d4 | 61 | // <i> N Value |
| Kovalev_D |
23:12e6183f04d4 | 62 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 63 | // </e> |
| Kovalev_D |
23:12e6183f04d4 | 64 | // |
| Kovalev_D |
23:12e6183f04d4 | 65 | // <e5> PLL1 Configuration (USB PLL) |
| Kovalev_D |
23:12e6183f04d4 | 66 | // <h> PLL1 Configuration Register (PLL1CFG) |
| Kovalev_D |
23:12e6183f04d4 | 67 | // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) |
| Kovalev_D |
23:12e6183f04d4 | 68 | // <i> F_cco1 = F_osc * M * 2 * P |
| Kovalev_D |
23:12e6183f04d4 | 69 | // <i> F_cco1 must be in the range of 156 MHz to 320 MHz |
| Kovalev_D |
23:12e6183f04d4 | 70 | // <o6.0..4> MSEL: PLL Multiplier Selection |
| Kovalev_D |
23:12e6183f04d4 | 71 | // <1-32><#-1> |
| Kovalev_D |
23:12e6183f04d4 | 72 | // <i> M Value (for USB maximum value is 4) |
| Kovalev_D |
23:12e6183f04d4 | 73 | // <o6.5..6> PSEL: PLL Divider Selection |
| Kovalev_D |
23:12e6183f04d4 | 74 | // <0=> 1 |
| Kovalev_D |
23:12e6183f04d4 | 75 | // <1=> 2 |
| Kovalev_D |
23:12e6183f04d4 | 76 | // <2=> 4 |
| Kovalev_D |
23:12e6183f04d4 | 77 | // <3=> 8 |
| Kovalev_D |
23:12e6183f04d4 | 78 | // <i> P Value |
| Kovalev_D |
23:12e6183f04d4 | 79 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 80 | // </e> |
| Kovalev_D |
23:12e6183f04d4 | 81 | // |
| Kovalev_D |
23:12e6183f04d4 | 82 | // <h> CPU Clock Configuration Register (CCLKCFG) |
| Kovalev_D |
23:12e6183f04d4 | 83 | // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 |
| Kovalev_D |
23:12e6183f04d4 | 84 | // <3-256><#-1> |
| Kovalev_D |
23:12e6183f04d4 | 85 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 86 | // |
| Kovalev_D |
23:12e6183f04d4 | 87 | // <h> USB Clock Configuration Register (USBCLKCFG) |
| Kovalev_D |
23:12e6183f04d4 | 88 | // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 |
| Kovalev_D |
23:12e6183f04d4 | 89 | // <0-15> |
| Kovalev_D |
23:12e6183f04d4 | 90 | // <i> Divide is USBSEL + 1 |
| Kovalev_D |
23:12e6183f04d4 | 91 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 92 | // |
| Kovalev_D |
23:12e6183f04d4 | 93 | // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) |
| Kovalev_D |
23:12e6183f04d4 | 94 | // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT |
| Kovalev_D |
23:12e6183f04d4 | 95 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 96 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 97 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 98 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 99 | // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 |
| Kovalev_D |
23:12e6183f04d4 | 100 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 101 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 102 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 103 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 104 | // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 |
| Kovalev_D |
23:12e6183f04d4 | 105 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 106 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 107 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 108 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 109 | // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 |
| Kovalev_D |
23:12e6183f04d4 | 110 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 111 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 112 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 113 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 114 | // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 |
| Kovalev_D |
23:12e6183f04d4 | 115 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 116 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 117 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 118 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 119 | // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 |
| Kovalev_D |
23:12e6183f04d4 | 120 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 121 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 122 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 123 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 124 | // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 |
| Kovalev_D |
23:12e6183f04d4 | 125 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 126 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 127 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 128 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 129 | // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI |
| Kovalev_D |
23:12e6183f04d4 | 130 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 131 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 132 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 133 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 134 | // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 |
| Kovalev_D |
23:12e6183f04d4 | 135 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 136 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 137 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 138 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 139 | // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC |
| Kovalev_D |
23:12e6183f04d4 | 140 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 141 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 142 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 143 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 144 | // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC |
| Kovalev_D |
23:12e6183f04d4 | 145 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 146 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 147 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 148 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 149 | // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 |
| Kovalev_D |
23:12e6183f04d4 | 150 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 151 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 152 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 153 | // <3=> Pclk = Hclk / 6 |
| Kovalev_D |
23:12e6183f04d4 | 154 | // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 |
| Kovalev_D |
23:12e6183f04d4 | 155 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 156 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 157 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 158 | // <3=> Pclk = Hclk / 6 |
| Kovalev_D |
23:12e6183f04d4 | 159 | // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF |
| Kovalev_D |
23:12e6183f04d4 | 160 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 161 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 162 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 163 | // <3=> Pclk = Hclk / 6 |
| Kovalev_D |
23:12e6183f04d4 | 164 | // </h> |
| Kovalev_D |
23:12e6183f04d4 | 165 | // |
| Kovalev_D |
23:12e6183f04d4 | 166 | // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) |
| Kovalev_D |
23:12e6183f04d4 | 167 | // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface |
| Kovalev_D |
23:12e6183f04d4 | 168 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 169 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 170 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 171 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 172 | // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs |
| Kovalev_D |
23:12e6183f04d4 | 173 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 174 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 175 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 176 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 177 | // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block |
| Kovalev_D |
23:12e6183f04d4 | 178 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 179 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 180 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 181 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 182 | // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 |
| Kovalev_D |
23:12e6183f04d4 | 183 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 184 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 185 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 186 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 187 | // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 |
| Kovalev_D |
23:12e6183f04d4 | 188 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 189 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 190 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 191 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 192 | // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 |
| Kovalev_D |
23:12e6183f04d4 | 193 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 194 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 195 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 196 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 197 | // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 |
| Kovalev_D |
23:12e6183f04d4 | 198 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 199 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 200 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 201 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 202 | // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 |
| Kovalev_D |
23:12e6183f04d4 | 203 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 204 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 205 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 206 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 207 | // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 |
| Kovalev_D |
23:12e6183f04d4 | 208 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 209 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 210 | // <2=> Pclk = Cclk / 2 |
| Kovalev_D |
23:12e6183f04d4 | 211 | // <3=> Pclk = Hclk / 8 |
| Kovalev_D |
23:12e6183f04d4 | 212 | // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 |
| Kovalev_D |
23:12e6183f04d4 | 213 | // <0=> Pclk = Cclk / 4 |
| Kovalev_D |
23:12e6183f04d4 | 214 | // <1=> Pclk = Cclk |
| Kovalev_D |
23:12e6183f04d4 | 215 | // <2=> Pclk = Cclk / 2 |
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23:12e6183f04d4 | 216 | // <3=> Pclk = Hclk / 8 |
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23:12e6183f04d4 | 217 | // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S |
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23:12e6183f04d4 | 218 | // <0=> Pclk = Cclk / 4 |
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23:12e6183f04d4 | 219 | // <1=> Pclk = Cclk |
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23:12e6183f04d4 | 220 | // <2=> Pclk = Cclk / 2 |
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23:12e6183f04d4 | 221 | // <3=> Pclk = Hclk / 8 |
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23:12e6183f04d4 | 222 | // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer |
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23:12e6183f04d4 | 223 | // <0=> Pclk = Cclk / 4 |
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23:12e6183f04d4 | 224 | // <1=> Pclk = Cclk |
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23:12e6183f04d4 | 225 | // <2=> Pclk = Cclk / 2 |
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23:12e6183f04d4 | 226 | // <3=> Pclk = Hclk / 8 |
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23:12e6183f04d4 | 227 | // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block |
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23:12e6183f04d4 | 228 | // <0=> Pclk = Cclk / 4 |
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23:12e6183f04d4 | 229 | // <1=> Pclk = Cclk |
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23:12e6183f04d4 | 230 | // <2=> Pclk = Cclk / 2 |
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23:12e6183f04d4 | 231 | // <3=> Pclk = Hclk / 8 |
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23:12e6183f04d4 | 232 | // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM |
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23:12e6183f04d4 | 233 | // <0=> Pclk = Cclk / 4 |
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23:12e6183f04d4 | 234 | // <1=> Pclk = Cclk |
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23:12e6183f04d4 | 235 | // <2=> Pclk = Cclk / 2 |
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23:12e6183f04d4 | 236 | // <3=> Pclk = Hclk / 8 |
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23:12e6183f04d4 | 237 | // </h> |
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23:12e6183f04d4 | 238 | // |
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23:12e6183f04d4 | 239 | // <h> Power Control for Peripherals Register (PCONP) |
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23:12e6183f04d4 | 240 | // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable |
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23:12e6183f04d4 | 241 | // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable |
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23:12e6183f04d4 | 242 | // <o11.3> PCUART0: UART 0 power/clock enable |
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23:12e6183f04d4 | 243 | // <o11.4> PCUART1: UART 1 power/clock enable |
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23:12e6183f04d4 | 244 | // <o11.6> PCPWM1: PWM 1 power/clock enable |
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23:12e6183f04d4 | 245 | // <o11.7> PCI2C0: I2C interface 0 power/clock enable |
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23:12e6183f04d4 | 246 | // <o11.8> PCSPI: SPI interface power/clock enable |
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23:12e6183f04d4 | 247 | // <o11.9> PCRTC: RTC power/clock enable |
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23:12e6183f04d4 | 248 | // <o11.10> PCSSP1: SSP interface 1 power/clock enable |
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23:12e6183f04d4 | 249 | // <o11.12> PCAD: A/D converter power/clock enable |
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23:12e6183f04d4 | 250 | // <o11.13> PCCAN1: CAN controller 1 power/clock enable |
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23:12e6183f04d4 | 251 | // <o11.14> PCCAN2: CAN controller 2 power/clock enable |
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23:12e6183f04d4 | 252 | // <o11.15> PCGPIO: GPIOs power/clock enable |
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23:12e6183f04d4 | 253 | // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable |
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23:12e6183f04d4 | 254 | // <o11.17> PCMC: Motor control PWM power/clock enable |
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23:12e6183f04d4 | 255 | // <o11.18> PCQEI: Quadrature encoder interface power/clock enable |
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23:12e6183f04d4 | 256 | // <o11.19> PCI2C1: I2C interface 1 power/clock enable |
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23:12e6183f04d4 | 257 | // <o11.21> PCSSP0: SSP interface 0 power/clock enable |
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23:12e6183f04d4 | 258 | // <o11.22> PCTIM2: Timer 2 power/clock enable |
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23:12e6183f04d4 | 259 | // <o11.23> PCTIM3: Timer 3 power/clock enable |
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23:12e6183f04d4 | 260 | // <o11.24> PCUART2: UART 2 power/clock enable |
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23:12e6183f04d4 | 261 | // <o11.25> PCUART3: UART 3 power/clock enable |
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23:12e6183f04d4 | 262 | // <o11.26> PCI2C2: I2C interface 2 power/clock enable |
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23:12e6183f04d4 | 263 | // <o11.27> PCI2S: I2S interface power/clock enable |
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23:12e6183f04d4 | 264 | // <o11.29> PCGPDMA: GP DMA function power/clock enable |
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23:12e6183f04d4 | 265 | // <o11.30> PCENET: Ethernet block power/clock enable |
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23:12e6183f04d4 | 266 | // <o11.31> PCUSB: USB interface power/clock enable |
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23:12e6183f04d4 | 267 | // </h> |
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23:12e6183f04d4 | 268 | // |
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23:12e6183f04d4 | 269 | // <h> Clock Output Configuration Register (CLKOUTCFG) |
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23:12e6183f04d4 | 270 | // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT |
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23:12e6183f04d4 | 271 | // <0=> CPU clock |
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23:12e6183f04d4 | 272 | // <1=> Main oscillator |
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23:12e6183f04d4 | 273 | // <2=> Internal RC oscillator |
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23:12e6183f04d4 | 274 | // <3=> USB clock |
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23:12e6183f04d4 | 275 | // <4=> RTC oscillator |
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23:12e6183f04d4 | 276 | // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT |
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23:12e6183f04d4 | 277 | // <1-16><#-1> |
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23:12e6183f04d4 | 278 | // <o12.8> CLKOUT_EN: CLKOUT enable control |
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23:12e6183f04d4 | 279 | // </h> |
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23:12e6183f04d4 | 280 | // |
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23:12e6183f04d4 | 281 | // </e> |
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23:12e6183f04d4 | 282 | */ |
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23:12e6183f04d4 | 283 | #define CLOCK_SETUP 1 |
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23:12e6183f04d4 | 284 | #define SCS_Val 0x00000020 |
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23:12e6183f04d4 | 285 | #define CLKSRCSEL_Val 0x00000001 |
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23:12e6183f04d4 | 286 | #define PLL0_SETUP 1 |
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23:12e6183f04d4 | 287 | #define PLL0CFG_Val 0x00050063 |
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23:12e6183f04d4 | 288 | #define PLL1_SETUP 1 |
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23:12e6183f04d4 | 289 | #define PLL1CFG_Val 0x00000023 |
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23:12e6183f04d4 | 290 | #define CCLKCFG_Val 0x00000003 |
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23:12e6183f04d4 | 291 | #define USBCLKCFG_Val 0x00000000 |
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23:12e6183f04d4 | 292 | #define PCLKSEL0_Val 0x00000010 |
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23:12e6183f04d4 | 293 | #define PCLKSEL1_Val 0x00000000 |
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23:12e6183f04d4 | 294 | #define PCONP_Val 0x046887DE |
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23:12e6183f04d4 | 295 | #define CLKOUTCFG_Val 0x00000000 |
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23:12e6183f04d4 | 296 | |
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23:12e6183f04d4 | 297 | |
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23:12e6183f04d4 | 298 | /*--------------------- Flash Accelerator Configuration ---------------------- |
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23:12e6183f04d4 | 299 | // |
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23:12e6183f04d4 | 300 | // <e> Flash Accelerator Configuration |
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23:12e6183f04d4 | 301 | // <o1.0..1> FETCHCFG: Fetch Configuration |
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23:12e6183f04d4 | 302 | // <0=> Instruction fetches from flash are not buffered |
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23:12e6183f04d4 | 303 | // <1=> One buffer is used for all instruction fetch buffering |
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23:12e6183f04d4 | 304 | // <2=> All buffers may be used for instruction fetch buffering |
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23:12e6183f04d4 | 305 | // <3=> Reserved (do not use this setting) |
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23:12e6183f04d4 | 306 | // <o1.2..3> DATACFG: Data Configuration |
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23:12e6183f04d4 | 307 | // <0=> Data accesses from flash are not buffered |
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23:12e6183f04d4 | 308 | // <1=> One buffer is used for all data access buffering |
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23:12e6183f04d4 | 309 | // <2=> All buffers may be used for data access buffering |
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23:12e6183f04d4 | 310 | // <3=> Reserved (do not use this setting) |
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23:12e6183f04d4 | 311 | // <o1.4> ACCEL: Acceleration Enable |
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23:12e6183f04d4 | 312 | // <o1.5> PREFEN: Prefetch Enable |
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23:12e6183f04d4 | 313 | // <o1.6> PREFOVR: Prefetch Override |
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23:12e6183f04d4 | 314 | // <o1.12..15> FLASHTIM: Flash Access Time |
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23:12e6183f04d4 | 315 | // <0=> 1 CPU clock (for CPU clock up to 20 MHz) |
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23:12e6183f04d4 | 316 | // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) |
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23:12e6183f04d4 | 317 | // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) |
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23:12e6183f04d4 | 318 | // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) |
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23:12e6183f04d4 | 319 | // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) |
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23:12e6183f04d4 | 320 | // <5=> 6 CPU clocks (for any CPU clock) |
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23:12e6183f04d4 | 321 | // </e> |
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23:12e6183f04d4 | 322 | */ |
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23:12e6183f04d4 | 323 | #define FLASH_SETUP 1 |
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23:12e6183f04d4 | 324 | #define FLASHCFG_Val 0x0000303A |
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23:12e6183f04d4 | 325 | |
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23:12e6183f04d4 | 326 | /* |
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23:12e6183f04d4 | 327 | //-------- <<< end of configuration section >>> ------------------------------ |
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23:12e6183f04d4 | 328 | */ |
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23:12e6183f04d4 | 329 | |
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23:12e6183f04d4 | 330 | /*---------------------------------------------------------------------------- |
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23:12e6183f04d4 | 331 | Check the register settings |
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23:12e6183f04d4 | 332 | *----------------------------------------------------------------------------*/ |
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23:12e6183f04d4 | 333 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
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23:12e6183f04d4 | 334 | #define CHECK_RSVD(val, mask) (val & mask) |
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23:12e6183f04d4 | 335 | |
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23:12e6183f04d4 | 336 | /* Clock Configuration -------------------------------------------------------*/ |
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23:12e6183f04d4 | 337 | #if (CHECK_RSVD((SCS_Val), ~0x00000030)) |
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23:12e6183f04d4 | 338 | #error "SCS: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 339 | #endif |
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23:12e6183f04d4 | 340 | |
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23:12e6183f04d4 | 341 | #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) |
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23:12e6183f04d4 | 342 | #error "CLKSRCSEL: Value out of range!" |
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23:12e6183f04d4 | 343 | #endif |
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23:12e6183f04d4 | 344 | |
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23:12e6183f04d4 | 345 | #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) |
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23:12e6183f04d4 | 346 | #error "PLL0CFG: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 347 | #endif |
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23:12e6183f04d4 | 348 | |
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23:12e6183f04d4 | 349 | #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) |
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23:12e6183f04d4 | 350 | #error "PLL1CFG: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 351 | #endif |
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23:12e6183f04d4 | 352 | |
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23:12e6183f04d4 | 353 | #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) |
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23:12e6183f04d4 | 354 | #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" |
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23:12e6183f04d4 | 355 | #endif |
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23:12e6183f04d4 | 356 | |
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23:12e6183f04d4 | 357 | #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) |
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23:12e6183f04d4 | 358 | #error "USBCLKCFG: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 359 | #endif |
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23:12e6183f04d4 | 360 | |
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23:12e6183f04d4 | 361 | #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) |
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23:12e6183f04d4 | 362 | #error "PCLKSEL0: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 363 | #endif |
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23:12e6183f04d4 | 364 | |
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23:12e6183f04d4 | 365 | #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) |
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23:12e6183f04d4 | 366 | #error "PCLKSEL1: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 367 | #endif |
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23:12e6183f04d4 | 368 | |
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23:12e6183f04d4 | 369 | #if (CHECK_RSVD((PCONP_Val), 0x10100821)) |
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23:12e6183f04d4 | 370 | #error "PCONP: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 371 | #endif |
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23:12e6183f04d4 | 372 | |
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23:12e6183f04d4 | 373 | #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) |
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23:12e6183f04d4 | 374 | #error "CLKOUTCFG: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 375 | #endif |
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23:12e6183f04d4 | 376 | |
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23:12e6183f04d4 | 377 | /* Flash Accelerator Configuration -------------------------------------------*/ |
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23:12e6183f04d4 | 378 | #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) |
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23:12e6183f04d4 | 379 | #error "FLASHCFG: Invalid values of reserved bits!" |
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23:12e6183f04d4 | 380 | #endif |
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23:12e6183f04d4 | 381 | |
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23:12e6183f04d4 | 382 | |
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23:12e6183f04d4 | 383 | /*---------------------------------------------------------------------------- |
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23:12e6183f04d4 | 384 | DEFINES |
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23:12e6183f04d4 | 385 | *----------------------------------------------------------------------------*/ |
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23:12e6183f04d4 | 386 | |
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23:12e6183f04d4 | 387 | /*---------------------------------------------------------------------------- |
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23:12e6183f04d4 | 388 | Define clocks |
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23:12e6183f04d4 | 389 | *----------------------------------------------------------------------------*/ |
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23:12e6183f04d4 | 390 | #define XTAL (12000000UL) /* Oscillator frequency */ |
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23:12e6183f04d4 | 391 | #define OSC_CLK ( XTAL) /* Main oscillator frequency */ |
| Kovalev_D |
23:12e6183f04d4 | 392 | #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ |
| Kovalev_D |
23:12e6183f04d4 | 393 | #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ |
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23:12e6183f04d4 | 394 | |
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23:12e6183f04d4 | 395 | |
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23:12e6183f04d4 | 396 | /* F_cco0 = (2 * M * F_in) / N */ |
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23:12e6183f04d4 | 397 | #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) |
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23:12e6183f04d4 | 398 | #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) |
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23:12e6183f04d4 | 399 | #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) |
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23:12e6183f04d4 | 400 | #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) |
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23:12e6183f04d4 | 401 | |
| Kovalev_D |
23:12e6183f04d4 | 402 | /* Determine core clock frequency according to settings */ |
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23:12e6183f04d4 | 403 | #if (PLL0_SETUP) |
| Kovalev_D |
23:12e6183f04d4 | 404 | #if ((CLKSRCSEL_Val & 0x03) == 1) |
| Kovalev_D |
23:12e6183f04d4 | 405 | #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) |
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23:12e6183f04d4 | 406 | #elif ((CLKSRCSEL_Val & 0x03) == 2) |
| Kovalev_D |
23:12e6183f04d4 | 407 | #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) |
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23:12e6183f04d4 | 408 | #else |
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23:12e6183f04d4 | 409 | #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) |
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23:12e6183f04d4 | 410 | #endif |
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23:12e6183f04d4 | 411 | #else |
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23:12e6183f04d4 | 412 | #if ((CLKSRCSEL_Val & 0x03) == 1) |
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23:12e6183f04d4 | 413 | #define __CORE_CLK (OSC_CLK / __CCLK_DIV) |
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23:12e6183f04d4 | 414 | #elif ((CLKSRCSEL_Val & 0x03) == 2) |
| Kovalev_D |
23:12e6183f04d4 | 415 | #define __CORE_CLK (RTC_CLK / __CCLK_DIV) |
| Kovalev_D |
23:12e6183f04d4 | 416 | #else |
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23:12e6183f04d4 | 417 | #define __CORE_CLK (IRC_OSC / __CCLK_DIV) |
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23:12e6183f04d4 | 418 | #endif |
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23:12e6183f04d4 | 419 | #endif |
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23:12e6183f04d4 | 420 | |
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23:12e6183f04d4 | 421 | |
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23:12e6183f04d4 | 422 | /*---------------------------------------------------------------------------- |
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23:12e6183f04d4 | 423 | Clock Variable definitions |
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23:12e6183f04d4 | 424 | *----------------------------------------------------------------------------*/ |
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23:12e6183f04d4 | 425 | uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ |
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23:12e6183f04d4 | 426 | |
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23:12e6183f04d4 | 427 | |
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23:12e6183f04d4 | 428 | /*---------------------------------------------------------------------------- |
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23:12e6183f04d4 | 429 | Clock functions |
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23:12e6183f04d4 | 430 | *----------------------------------------------------------------------------*/ |
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23:12e6183f04d4 | 431 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
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23:12e6183f04d4 | 432 | { |
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23:12e6183f04d4 | 433 | /* Determine clock frequency according to clock register values */ |
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23:12e6183f04d4 | 434 | if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ |
| Kovalev_D |
23:12e6183f04d4 | 435 | switch (LPC_SC->CLKSRCSEL & 0x03) { |
| Kovalev_D |
23:12e6183f04d4 | 436 | case 0: /* Int. RC oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 437 | case 3: /* Reserved, default to Int. RC */ |
| Kovalev_D |
23:12e6183f04d4 | 438 | SystemCoreClock = (IRC_OSC * |
| Kovalev_D |
23:12e6183f04d4 | 439 | ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / |
| Kovalev_D |
23:12e6183f04d4 | 440 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / |
| Kovalev_D |
23:12e6183f04d4 | 441 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); |
| Kovalev_D |
23:12e6183f04d4 | 442 | break; |
| Kovalev_D |
23:12e6183f04d4 | 443 | case 1: /* Main oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 444 | SystemCoreClock = (OSC_CLK * //it is our case osc_clk = 12 MHz |
| Kovalev_D |
23:12e6183f04d4 | 445 | ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value |
| Kovalev_D |
23:12e6183f04d4 | 446 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider |
| Kovalev_D |
23:12e6183f04d4 | 447 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock) |
| Kovalev_D |
23:12e6183f04d4 | 448 | break; |
| Kovalev_D |
23:12e6183f04d4 | 449 | case 2: /* RTC oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 450 | SystemCoreClock = (RTC_CLK * |
| Kovalev_D |
23:12e6183f04d4 | 451 | ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / |
| Kovalev_D |
23:12e6183f04d4 | 452 | (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / |
| Kovalev_D |
23:12e6183f04d4 | 453 | ((LPC_SC->CCLKCFG & 0xFF)+ 1)); |
| Kovalev_D |
23:12e6183f04d4 | 454 | break; |
| Kovalev_D |
23:12e6183f04d4 | 455 | } |
| Kovalev_D |
23:12e6183f04d4 | 456 | } else { |
| Kovalev_D |
23:12e6183f04d4 | 457 | switch (LPC_SC->CLKSRCSEL & 0x03) { |
| Kovalev_D |
23:12e6183f04d4 | 458 | case 0: /* Int. RC oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 459 | case 3: /* Reserved, default to Int. RC */ |
| Kovalev_D |
23:12e6183f04d4 | 460 | SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); |
| Kovalev_D |
23:12e6183f04d4 | 461 | break; |
| Kovalev_D |
23:12e6183f04d4 | 462 | case 1: /* Main oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 463 | SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); |
| Kovalev_D |
23:12e6183f04d4 | 464 | break; |
| Kovalev_D |
23:12e6183f04d4 | 465 | case 2: /* RTC oscillator => PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 466 | SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); |
| Kovalev_D |
23:12e6183f04d4 | 467 | break; |
| Kovalev_D |
23:12e6183f04d4 | 468 | } |
| Kovalev_D |
23:12e6183f04d4 | 469 | } |
| Kovalev_D |
23:12e6183f04d4 | 470 | |
| Kovalev_D |
23:12e6183f04d4 | 471 | } |
| Kovalev_D |
23:12e6183f04d4 | 472 | |
| Kovalev_D |
23:12e6183f04d4 | 473 | /** |
| Kovalev_D |
23:12e6183f04d4 | 474 | * Initialize the system |
| Kovalev_D |
23:12e6183f04d4 | 475 | * |
| Kovalev_D |
23:12e6183f04d4 | 476 | * @param none |
| Kovalev_D |
23:12e6183f04d4 | 477 | * @return none |
| Kovalev_D |
23:12e6183f04d4 | 478 | * |
| Kovalev_D |
23:12e6183f04d4 | 479 | * @brief Setup the microcontroller system. |
| Kovalev_D |
23:12e6183f04d4 | 480 | * Initialize the System. |
| Kovalev_D |
23:12e6183f04d4 | 481 | */ |
| Kovalev_D |
23:12e6183f04d4 | 482 | void SystemInit (void) |
| Kovalev_D |
23:12e6183f04d4 | 483 | { |
| Kovalev_D |
23:12e6183f04d4 | 484 | #if (CLOCK_SETUP) /* Clock Setup */ |
| Kovalev_D |
23:12e6183f04d4 | 485 | LPC_SC->SCS = SCS_Val; |
| Kovalev_D |
23:12e6183f04d4 | 486 | if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ |
| Kovalev_D |
23:12e6183f04d4 | 487 | while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ |
| Kovalev_D |
23:12e6183f04d4 | 488 | } |
| Kovalev_D |
23:12e6183f04d4 | 489 | |
| Kovalev_D |
23:12e6183f04d4 | 490 | LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ |
| Kovalev_D |
23:12e6183f04d4 | 491 | |
| Kovalev_D |
23:12e6183f04d4 | 492 | #if (PLL0_SETUP) |
| Kovalev_D |
23:12e6183f04d4 | 493 | LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 494 | |
| Kovalev_D |
23:12e6183f04d4 | 495 | LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ |
| Kovalev_D |
23:12e6183f04d4 | 496 | LPC_SC->PLL0FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 497 | LPC_SC->PLL0FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 498 | |
| Kovalev_D |
23:12e6183f04d4 | 499 | LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ |
| Kovalev_D |
23:12e6183f04d4 | 500 | LPC_SC->PLL0FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 501 | LPC_SC->PLL0FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 502 | while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ |
| Kovalev_D |
23:12e6183f04d4 | 503 | |
| Kovalev_D |
23:12e6183f04d4 | 504 | LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ |
| Kovalev_D |
23:12e6183f04d4 | 505 | LPC_SC->PLL0FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 506 | LPC_SC->PLL0FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 507 | while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */ |
| Kovalev_D |
23:12e6183f04d4 | 508 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 509 | |
| Kovalev_D |
23:12e6183f04d4 | 510 | #if (PLL1_SETUP) |
| Kovalev_D |
23:12e6183f04d4 | 511 | LPC_SC->PLL1CFG = PLL1CFG_Val; |
| Kovalev_D |
23:12e6183f04d4 | 512 | LPC_SC->PLL1FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 513 | LPC_SC->PLL1FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 514 | |
| Kovalev_D |
23:12e6183f04d4 | 515 | LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ |
| Kovalev_D |
23:12e6183f04d4 | 516 | LPC_SC->PLL1FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 517 | LPC_SC->PLL1FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 518 | while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ |
| Kovalev_D |
23:12e6183f04d4 | 519 | |
| Kovalev_D |
23:12e6183f04d4 | 520 | LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ |
| Kovalev_D |
23:12e6183f04d4 | 521 | LPC_SC->PLL1FEED = 0xAA; |
| Kovalev_D |
23:12e6183f04d4 | 522 | LPC_SC->PLL1FEED = 0x55; |
| Kovalev_D |
23:12e6183f04d4 | 523 | while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ |
| Kovalev_D |
23:12e6183f04d4 | 524 | #else |
| Kovalev_D |
23:12e6183f04d4 | 525 | LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ |
| Kovalev_D |
23:12e6183f04d4 | 526 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 527 | |
| Kovalev_D |
23:12e6183f04d4 | 528 | LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ |
| Kovalev_D |
23:12e6183f04d4 | 529 | LPC_SC->PCLKSEL1 = PCLKSEL1_Val; |
| Kovalev_D |
23:12e6183f04d4 | 530 | |
| Kovalev_D |
23:12e6183f04d4 | 531 | LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ |
| Kovalev_D |
23:12e6183f04d4 | 532 | |
| Kovalev_D |
23:12e6183f04d4 | 533 | LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ |
| Kovalev_D |
23:12e6183f04d4 | 534 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 535 | |
| Kovalev_D |
23:12e6183f04d4 | 536 | #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ |
| Kovalev_D |
23:12e6183f04d4 | 537 | LPC_SC->FLASHCFG = FLASHCFG_Val; |
| Kovalev_D |
23:12e6183f04d4 | 538 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 539 | } |