Dmitry Kovalev
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Dmitry Kovalev
host/Source/CMSIS/CM3/DeviceSupport/NXP/LPC13xx/LPC13xx.h@23:12e6183f04d4, 2016-02-03 (annotated)
- Committer:
- Kovalev_D
- Date:
- Wed Feb 03 10:44:42 2016 +0300
- Revision:
- 23:12e6183f04d4
[thyz
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kovalev_D |
23:12e6183f04d4 | 1 | /**************************************************************************//** |
| Kovalev_D |
23:12e6183f04d4 | 2 | * @file LPC13xx.h |
| Kovalev_D |
23:12e6183f04d4 | 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for |
| Kovalev_D |
23:12e6183f04d4 | 4 | * NXP LPC13xx Device Series |
| Kovalev_D |
23:12e6183f04d4 | 5 | * @version V1.01 |
| Kovalev_D |
23:12e6183f04d4 | 6 | * @date 19. October 2009 |
| Kovalev_D |
23:12e6183f04d4 | 7 | * |
| Kovalev_D |
23:12e6183f04d4 | 8 | * @note |
| Kovalev_D |
23:12e6183f04d4 | 9 | * Copyright (C) 2009 ARM Limited. All rights reserved. |
| Kovalev_D |
23:12e6183f04d4 | 10 | * |
| Kovalev_D |
23:12e6183f04d4 | 11 | * @par |
| Kovalev_D |
23:12e6183f04d4 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| Kovalev_D |
23:12e6183f04d4 | 13 | * processor based microcontrollers. This file can be freely distributed |
| Kovalev_D |
23:12e6183f04d4 | 14 | * within development tools that are supporting such ARM based processors. |
| Kovalev_D |
23:12e6183f04d4 | 15 | * |
| Kovalev_D |
23:12e6183f04d4 | 16 | * @par |
| Kovalev_D |
23:12e6183f04d4 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| Kovalev_D |
23:12e6183f04d4 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| Kovalev_D |
23:12e6183f04d4 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| Kovalev_D |
23:12e6183f04d4 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| Kovalev_D |
23:12e6183f04d4 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| Kovalev_D |
23:12e6183f04d4 | 22 | * |
| Kovalev_D |
23:12e6183f04d4 | 23 | ******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 24 | |
| Kovalev_D |
23:12e6183f04d4 | 25 | |
| Kovalev_D |
23:12e6183f04d4 | 26 | #ifndef __LPC13xx_H__ |
| Kovalev_D |
23:12e6183f04d4 | 27 | #define __LPC13xx_H__ |
| Kovalev_D |
23:12e6183f04d4 | 28 | |
| Kovalev_D |
23:12e6183f04d4 | 29 | /* |
| Kovalev_D |
23:12e6183f04d4 | 30 | * ========================================================================== |
| Kovalev_D |
23:12e6183f04d4 | 31 | * ---------- Interrupt Number Definition ----------------------------------- |
| Kovalev_D |
23:12e6183f04d4 | 32 | * ========================================================================== |
| Kovalev_D |
23:12e6183f04d4 | 33 | */ |
| Kovalev_D |
23:12e6183f04d4 | 34 | |
| Kovalev_D |
23:12e6183f04d4 | 35 | typedef enum IRQn |
| Kovalev_D |
23:12e6183f04d4 | 36 | { |
| Kovalev_D |
23:12e6183f04d4 | 37 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 38 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 39 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 40 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 41 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 42 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 43 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 44 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 45 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 46 | |
| Kovalev_D |
23:12e6183f04d4 | 47 | /****** LPC13xx Specific Interrupt Numbers *******************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 48 | WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ |
| Kovalev_D |
23:12e6183f04d4 | 49 | WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ |
| Kovalev_D |
23:12e6183f04d4 | 50 | WAKEUP2_IRQn = 2, |
| Kovalev_D |
23:12e6183f04d4 | 51 | WAKEUP3_IRQn = 3, |
| Kovalev_D |
23:12e6183f04d4 | 52 | WAKEUP4_IRQn = 4, |
| Kovalev_D |
23:12e6183f04d4 | 53 | WAKEUP5_IRQn = 5, |
| Kovalev_D |
23:12e6183f04d4 | 54 | WAKEUP6_IRQn = 6, |
| Kovalev_D |
23:12e6183f04d4 | 55 | WAKEUP7_IRQn = 7, |
| Kovalev_D |
23:12e6183f04d4 | 56 | WAKEUP8_IRQn = 8, |
| Kovalev_D |
23:12e6183f04d4 | 57 | WAKEUP9_IRQn = 9, |
| Kovalev_D |
23:12e6183f04d4 | 58 | WAKEUP10_IRQn = 10, |
| Kovalev_D |
23:12e6183f04d4 | 59 | WAKEUP11_IRQn = 11, |
| Kovalev_D |
23:12e6183f04d4 | 60 | WAKEUP12_IRQn = 12, |
| Kovalev_D |
23:12e6183f04d4 | 61 | WAKEUP13_IRQn = 13, |
| Kovalev_D |
23:12e6183f04d4 | 62 | WAKEUP14_IRQn = 14, |
| Kovalev_D |
23:12e6183f04d4 | 63 | WAKEUP15_IRQn = 15, |
| Kovalev_D |
23:12e6183f04d4 | 64 | WAKEUP16_IRQn = 16, |
| Kovalev_D |
23:12e6183f04d4 | 65 | WAKEUP17_IRQn = 17, |
| Kovalev_D |
23:12e6183f04d4 | 66 | WAKEUP18_IRQn = 18, |
| Kovalev_D |
23:12e6183f04d4 | 67 | WAKEUP19_IRQn = 19, |
| Kovalev_D |
23:12e6183f04d4 | 68 | WAKEUP20_IRQn = 20, |
| Kovalev_D |
23:12e6183f04d4 | 69 | WAKEUP21_IRQn = 21, |
| Kovalev_D |
23:12e6183f04d4 | 70 | WAKEUP22_IRQn = 22, |
| Kovalev_D |
23:12e6183f04d4 | 71 | WAKEUP23_IRQn = 23, |
| Kovalev_D |
23:12e6183f04d4 | 72 | WAKEUP24_IRQn = 24, |
| Kovalev_D |
23:12e6183f04d4 | 73 | WAKEUP25_IRQn = 25, |
| Kovalev_D |
23:12e6183f04d4 | 74 | WAKEUP26_IRQn = 26, |
| Kovalev_D |
23:12e6183f04d4 | 75 | WAKEUP27_IRQn = 27, |
| Kovalev_D |
23:12e6183f04d4 | 76 | WAKEUP28_IRQn = 28, |
| Kovalev_D |
23:12e6183f04d4 | 77 | WAKEUP29_IRQn = 29, |
| Kovalev_D |
23:12e6183f04d4 | 78 | WAKEUP30_IRQn = 30, |
| Kovalev_D |
23:12e6183f04d4 | 79 | WAKEUP31_IRQn = 31, |
| Kovalev_D |
23:12e6183f04d4 | 80 | WAKEUP32_IRQn = 32, |
| Kovalev_D |
23:12e6183f04d4 | 81 | WAKEUP33_IRQn = 33, |
| Kovalev_D |
23:12e6183f04d4 | 82 | WAKEUP34_IRQn = 34, |
| Kovalev_D |
23:12e6183f04d4 | 83 | WAKEUP35_IRQn = 35, |
| Kovalev_D |
23:12e6183f04d4 | 84 | WAKEUP36_IRQn = 36, |
| Kovalev_D |
23:12e6183f04d4 | 85 | WAKEUP37_IRQn = 37, |
| Kovalev_D |
23:12e6183f04d4 | 86 | WAKEUP38_IRQn = 38, |
| Kovalev_D |
23:12e6183f04d4 | 87 | WAKEUP39_IRQn = 39, |
| Kovalev_D |
23:12e6183f04d4 | 88 | I2C_IRQn = 40, /*!< I2C Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 89 | TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 90 | TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 91 | TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 92 | TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 93 | SSP_IRQn = 45, /*!< SSP Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 94 | UART_IRQn = 46, /*!< UART Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 95 | USB_IRQn = 47, /*!< USB Regular Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 96 | USB_FIQn = 48, /*!< USB Fast Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 97 | ADC_IRQn = 49, /*!< A/D Converter Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 98 | WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 99 | BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 100 | EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 101 | EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 102 | EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 103 | EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ |
| Kovalev_D |
23:12e6183f04d4 | 104 | } IRQn_Type; |
| Kovalev_D |
23:12e6183f04d4 | 105 | |
| Kovalev_D |
23:12e6183f04d4 | 106 | |
| Kovalev_D |
23:12e6183f04d4 | 107 | /* |
| Kovalev_D |
23:12e6183f04d4 | 108 | * ========================================================================== |
| Kovalev_D |
23:12e6183f04d4 | 109 | * ----------- Processor and Core Peripheral Section ------------------------ |
| Kovalev_D |
23:12e6183f04d4 | 110 | * ========================================================================== |
| Kovalev_D |
23:12e6183f04d4 | 111 | */ |
| Kovalev_D |
23:12e6183f04d4 | 112 | |
| Kovalev_D |
23:12e6183f04d4 | 113 | /* Configuration of the Cortex-M3 Processor and Core Peripherals */ |
| Kovalev_D |
23:12e6183f04d4 | 114 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
| Kovalev_D |
23:12e6183f04d4 | 115 | #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ |
| Kovalev_D |
23:12e6183f04d4 | 116 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| Kovalev_D |
23:12e6183f04d4 | 117 | |
| Kovalev_D |
23:12e6183f04d4 | 118 | |
| Kovalev_D |
23:12e6183f04d4 | 119 | #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ |
| Kovalev_D |
23:12e6183f04d4 | 120 | #include "system_LPC13xx.h" /* System Header */ |
| Kovalev_D |
23:12e6183f04d4 | 121 | |
| Kovalev_D |
23:12e6183f04d4 | 122 | |
| Kovalev_D |
23:12e6183f04d4 | 123 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 124 | /* Device Specific Peripheral registers structures */ |
| Kovalev_D |
23:12e6183f04d4 | 125 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 126 | |
| Kovalev_D |
23:12e6183f04d4 | 127 | #if defined ( __CC_ARM ) |
| Kovalev_D |
23:12e6183f04d4 | 128 | #pragma anon_unions |
| Kovalev_D |
23:12e6183f04d4 | 129 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 130 | |
| Kovalev_D |
23:12e6183f04d4 | 131 | /*------------- System Control (SYSCON) --------------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 132 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 133 | { |
| Kovalev_D |
23:12e6183f04d4 | 134 | __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ |
| Kovalev_D |
23:12e6183f04d4 | 135 | __IO uint32_t PRESETCTRL; |
| Kovalev_D |
23:12e6183f04d4 | 136 | __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ |
| Kovalev_D |
23:12e6183f04d4 | 137 | __IO uint32_t SYSPLLSTAT; |
| Kovalev_D |
23:12e6183f04d4 | 138 | __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ |
| Kovalev_D |
23:12e6183f04d4 | 139 | __IO uint32_t USBPLLSTAT; |
| Kovalev_D |
23:12e6183f04d4 | 140 | uint32_t RESERVED0[2]; |
| Kovalev_D |
23:12e6183f04d4 | 141 | |
| Kovalev_D |
23:12e6183f04d4 | 142 | __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ |
| Kovalev_D |
23:12e6183f04d4 | 143 | __IO uint32_t WDTOSCCTRL; |
| Kovalev_D |
23:12e6183f04d4 | 144 | __IO uint32_t IRCCTRL; |
| Kovalev_D |
23:12e6183f04d4 | 145 | uint32_t RESERVED1[1]; |
| Kovalev_D |
23:12e6183f04d4 | 146 | __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ |
| Kovalev_D |
23:12e6183f04d4 | 147 | uint32_t RESERVED2[3]; |
| Kovalev_D |
23:12e6183f04d4 | 148 | __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ |
| Kovalev_D |
23:12e6183f04d4 | 149 | __IO uint32_t SYSPLLCLKUEN; |
| Kovalev_D |
23:12e6183f04d4 | 150 | __IO uint32_t USBPLLCLKSEL; |
| Kovalev_D |
23:12e6183f04d4 | 151 | __IO uint32_t USBPLLCLKUEN; |
| Kovalev_D |
23:12e6183f04d4 | 152 | uint32_t RESERVED3[8]; |
| Kovalev_D |
23:12e6183f04d4 | 153 | |
| Kovalev_D |
23:12e6183f04d4 | 154 | __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ |
| Kovalev_D |
23:12e6183f04d4 | 155 | __IO uint32_t MAINCLKUEN; |
| Kovalev_D |
23:12e6183f04d4 | 156 | __IO uint32_t SYSAHBCLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 157 | uint32_t RESERVED4[1]; |
| Kovalev_D |
23:12e6183f04d4 | 158 | |
| Kovalev_D |
23:12e6183f04d4 | 159 | __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ |
| Kovalev_D |
23:12e6183f04d4 | 160 | uint32_t RESERVED5[4]; |
| Kovalev_D |
23:12e6183f04d4 | 161 | __IO uint32_t SSPCLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 162 | __IO uint32_t UARTCLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 163 | uint32_t RESERVED6[4]; |
| Kovalev_D |
23:12e6183f04d4 | 164 | __IO uint32_t TRACECLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 165 | |
| Kovalev_D |
23:12e6183f04d4 | 166 | __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ |
| Kovalev_D |
23:12e6183f04d4 | 167 | uint32_t RESERVED7[3]; |
| Kovalev_D |
23:12e6183f04d4 | 168 | |
| Kovalev_D |
23:12e6183f04d4 | 169 | __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ |
| Kovalev_D |
23:12e6183f04d4 | 170 | __IO uint32_t USBCLKUEN; |
| Kovalev_D |
23:12e6183f04d4 | 171 | __IO uint32_t USBCLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 172 | uint32_t RESERVED8[1]; |
| Kovalev_D |
23:12e6183f04d4 | 173 | __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ |
| Kovalev_D |
23:12e6183f04d4 | 174 | __IO uint32_t WDTCLKUEN; |
| Kovalev_D |
23:12e6183f04d4 | 175 | __IO uint32_t WDTCLKDIV; |
| Kovalev_D |
23:12e6183f04d4 | 176 | uint32_t RESERVED9[1]; |
| Kovalev_D |
23:12e6183f04d4 | 177 | __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ |
| Kovalev_D |
23:12e6183f04d4 | 178 | __IO uint32_t CLKOUTUEN; |
| Kovalev_D |
23:12e6183f04d4 | 179 | __IO uint32_t CLKOUTDIV; |
| Kovalev_D |
23:12e6183f04d4 | 180 | uint32_t RESERVED10[5]; |
| Kovalev_D |
23:12e6183f04d4 | 181 | |
| Kovalev_D |
23:12e6183f04d4 | 182 | __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ |
| Kovalev_D |
23:12e6183f04d4 | 183 | __IO uint32_t PIOPORCAP1; |
| Kovalev_D |
23:12e6183f04d4 | 184 | uint32_t RESERVED11[18]; |
| Kovalev_D |
23:12e6183f04d4 | 185 | |
| Kovalev_D |
23:12e6183f04d4 | 186 | __IO uint32_t BODCTRL; /* Offset 0x150 */ |
| Kovalev_D |
23:12e6183f04d4 | 187 | uint32_t RESERVED12[1]; |
| Kovalev_D |
23:12e6183f04d4 | 188 | __IO uint32_t SYSTCKCAL; |
| Kovalev_D |
23:12e6183f04d4 | 189 | uint32_t RESERVED13[41]; |
| Kovalev_D |
23:12e6183f04d4 | 190 | |
| Kovalev_D |
23:12e6183f04d4 | 191 | __IO uint32_t STARTAPRP0; /* Offset 0x200 */ |
| Kovalev_D |
23:12e6183f04d4 | 192 | __IO uint32_t STARTERP0; |
| Kovalev_D |
23:12e6183f04d4 | 193 | __IO uint32_t STARTRSRP0CLR; |
| Kovalev_D |
23:12e6183f04d4 | 194 | __IO uint32_t STARTSRP0; |
| Kovalev_D |
23:12e6183f04d4 | 195 | __IO uint32_t STARTAPRP1; |
| Kovalev_D |
23:12e6183f04d4 | 196 | __IO uint32_t STARTERP1; |
| Kovalev_D |
23:12e6183f04d4 | 197 | __IO uint32_t STARTRSRP1CLR; |
| Kovalev_D |
23:12e6183f04d4 | 198 | __IO uint32_t STARTSRP1; |
| Kovalev_D |
23:12e6183f04d4 | 199 | uint32_t RESERVED14[4]; |
| Kovalev_D |
23:12e6183f04d4 | 200 | |
| Kovalev_D |
23:12e6183f04d4 | 201 | __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ |
| Kovalev_D |
23:12e6183f04d4 | 202 | __IO uint32_t PDAWAKECFG; |
| Kovalev_D |
23:12e6183f04d4 | 203 | __IO uint32_t PDRUNCFG; |
| Kovalev_D |
23:12e6183f04d4 | 204 | uint32_t RESERVED15[110]; |
| Kovalev_D |
23:12e6183f04d4 | 205 | __I uint32_t DEVICE_ID; |
| Kovalev_D |
23:12e6183f04d4 | 206 | } LPC_SYSCON_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 207 | |
| Kovalev_D |
23:12e6183f04d4 | 208 | |
| Kovalev_D |
23:12e6183f04d4 | 209 | /*------------- Pin Connect Block (IOCON) --------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 210 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 211 | { |
| Kovalev_D |
23:12e6183f04d4 | 212 | __IO uint32_t PIO2_6; |
| Kovalev_D |
23:12e6183f04d4 | 213 | uint32_t RESERVED0[1]; |
| Kovalev_D |
23:12e6183f04d4 | 214 | __IO uint32_t PIO2_0; |
| Kovalev_D |
23:12e6183f04d4 | 215 | __IO uint32_t RESET_PIO0_0; |
| Kovalev_D |
23:12e6183f04d4 | 216 | __IO uint32_t PIO0_1; |
| Kovalev_D |
23:12e6183f04d4 | 217 | __IO uint32_t PIO1_8; |
| Kovalev_D |
23:12e6183f04d4 | 218 | uint32_t RESERVED1[1]; |
| Kovalev_D |
23:12e6183f04d4 | 219 | __IO uint32_t PIO0_2; |
| Kovalev_D |
23:12e6183f04d4 | 220 | |
| Kovalev_D |
23:12e6183f04d4 | 221 | __IO uint32_t PIO2_7; |
| Kovalev_D |
23:12e6183f04d4 | 222 | __IO uint32_t PIO2_8; |
| Kovalev_D |
23:12e6183f04d4 | 223 | __IO uint32_t PIO2_1; |
| Kovalev_D |
23:12e6183f04d4 | 224 | __IO uint32_t PIO0_3; |
| Kovalev_D |
23:12e6183f04d4 | 225 | __IO uint32_t PIO0_4; |
| Kovalev_D |
23:12e6183f04d4 | 226 | __IO uint32_t PIO0_5; |
| Kovalev_D |
23:12e6183f04d4 | 227 | __IO uint32_t PIO1_9; |
| Kovalev_D |
23:12e6183f04d4 | 228 | __IO uint32_t PIO3_4; |
| Kovalev_D |
23:12e6183f04d4 | 229 | |
| Kovalev_D |
23:12e6183f04d4 | 230 | __IO uint32_t PIO2_4; |
| Kovalev_D |
23:12e6183f04d4 | 231 | __IO uint32_t PIO2_5; |
| Kovalev_D |
23:12e6183f04d4 | 232 | __IO uint32_t PIO3_5; |
| Kovalev_D |
23:12e6183f04d4 | 233 | __IO uint32_t PIO0_6; |
| Kovalev_D |
23:12e6183f04d4 | 234 | __IO uint32_t PIO0_7; |
| Kovalev_D |
23:12e6183f04d4 | 235 | __IO uint32_t PIO2_9; |
| Kovalev_D |
23:12e6183f04d4 | 236 | __IO uint32_t PIO2_10; |
| Kovalev_D |
23:12e6183f04d4 | 237 | __IO uint32_t PIO2_2; |
| Kovalev_D |
23:12e6183f04d4 | 238 | |
| Kovalev_D |
23:12e6183f04d4 | 239 | __IO uint32_t PIO0_8; |
| Kovalev_D |
23:12e6183f04d4 | 240 | __IO uint32_t PIO0_9; |
| Kovalev_D |
23:12e6183f04d4 | 241 | __IO uint32_t JTAG_TCK_PIO0_10; |
| Kovalev_D |
23:12e6183f04d4 | 242 | __IO uint32_t PIO1_10; |
| Kovalev_D |
23:12e6183f04d4 | 243 | __IO uint32_t PIO2_11; |
| Kovalev_D |
23:12e6183f04d4 | 244 | __IO uint32_t JTAG_TDI_PIO0_11; |
| Kovalev_D |
23:12e6183f04d4 | 245 | __IO uint32_t JTAG_TMS_PIO1_0; |
| Kovalev_D |
23:12e6183f04d4 | 246 | __IO uint32_t JTAG_TDO_PIO1_1; |
| Kovalev_D |
23:12e6183f04d4 | 247 | |
| Kovalev_D |
23:12e6183f04d4 | 248 | __IO uint32_t JTAG_nTRST_PIO1_2; |
| Kovalev_D |
23:12e6183f04d4 | 249 | __IO uint32_t PIO3_0; |
| Kovalev_D |
23:12e6183f04d4 | 250 | __IO uint32_t PIO3_1; |
| Kovalev_D |
23:12e6183f04d4 | 251 | __IO uint32_t PIO2_3; |
| Kovalev_D |
23:12e6183f04d4 | 252 | __IO uint32_t ARM_SWDIO_PIO1_3; |
| Kovalev_D |
23:12e6183f04d4 | 253 | __IO uint32_t PIO1_4; |
| Kovalev_D |
23:12e6183f04d4 | 254 | __IO uint32_t PIO1_11; |
| Kovalev_D |
23:12e6183f04d4 | 255 | __IO uint32_t PIO3_2; |
| Kovalev_D |
23:12e6183f04d4 | 256 | |
| Kovalev_D |
23:12e6183f04d4 | 257 | __IO uint32_t PIO1_5; |
| Kovalev_D |
23:12e6183f04d4 | 258 | __IO uint32_t PIO1_6; |
| Kovalev_D |
23:12e6183f04d4 | 259 | __IO uint32_t PIO1_7; |
| Kovalev_D |
23:12e6183f04d4 | 260 | __IO uint32_t PIO3_3; |
| Kovalev_D |
23:12e6183f04d4 | 261 | __IO uint32_t SCKLOC; /* For HB1 only, new feature */ |
| Kovalev_D |
23:12e6183f04d4 | 262 | } LPC_IOCON_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 263 | |
| Kovalev_D |
23:12e6183f04d4 | 264 | |
| Kovalev_D |
23:12e6183f04d4 | 265 | /*------------- Power Management Unit (PMU) --------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 266 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 267 | { |
| Kovalev_D |
23:12e6183f04d4 | 268 | __IO uint32_t PCON; |
| Kovalev_D |
23:12e6183f04d4 | 269 | __IO uint32_t GPREG0; |
| Kovalev_D |
23:12e6183f04d4 | 270 | __IO uint32_t GPREG1; |
| Kovalev_D |
23:12e6183f04d4 | 271 | __IO uint32_t GPREG2; |
| Kovalev_D |
23:12e6183f04d4 | 272 | __IO uint32_t GPREG3; |
| Kovalev_D |
23:12e6183f04d4 | 273 | __IO uint32_t GPREG4; |
| Kovalev_D |
23:12e6183f04d4 | 274 | } LPC_PMU_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 275 | |
| Kovalev_D |
23:12e6183f04d4 | 276 | |
| Kovalev_D |
23:12e6183f04d4 | 277 | /*------------- General Purpose Input/Output (GPIO) --------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 278 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 279 | { |
| Kovalev_D |
23:12e6183f04d4 | 280 | union { |
| Kovalev_D |
23:12e6183f04d4 | 281 | __IO uint32_t MASKED_ACCESS[4096]; |
| Kovalev_D |
23:12e6183f04d4 | 282 | struct { |
| Kovalev_D |
23:12e6183f04d4 | 283 | uint32_t RESERVED0[4095]; |
| Kovalev_D |
23:12e6183f04d4 | 284 | __IO uint32_t DATA; |
| Kovalev_D |
23:12e6183f04d4 | 285 | }; |
| Kovalev_D |
23:12e6183f04d4 | 286 | }; |
| Kovalev_D |
23:12e6183f04d4 | 287 | uint32_t RESERVED1[4096]; |
| Kovalev_D |
23:12e6183f04d4 | 288 | __IO uint32_t DIR; |
| Kovalev_D |
23:12e6183f04d4 | 289 | __IO uint32_t IS; |
| Kovalev_D |
23:12e6183f04d4 | 290 | __IO uint32_t IBE; |
| Kovalev_D |
23:12e6183f04d4 | 291 | __IO uint32_t IEV; |
| Kovalev_D |
23:12e6183f04d4 | 292 | __IO uint32_t IE; |
| Kovalev_D |
23:12e6183f04d4 | 293 | __IO uint32_t RIS; |
| Kovalev_D |
23:12e6183f04d4 | 294 | __IO uint32_t MIS; |
| Kovalev_D |
23:12e6183f04d4 | 295 | __IO uint32_t IC; |
| Kovalev_D |
23:12e6183f04d4 | 296 | } LPC_GPIO_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 297 | |
| Kovalev_D |
23:12e6183f04d4 | 298 | |
| Kovalev_D |
23:12e6183f04d4 | 299 | /*------------- Timer (TMR) --------------------------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 300 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 301 | { |
| Kovalev_D |
23:12e6183f04d4 | 302 | __IO uint32_t IR; |
| Kovalev_D |
23:12e6183f04d4 | 303 | __IO uint32_t TCR; |
| Kovalev_D |
23:12e6183f04d4 | 304 | __IO uint32_t TC; |
| Kovalev_D |
23:12e6183f04d4 | 305 | __IO uint32_t PR; |
| Kovalev_D |
23:12e6183f04d4 | 306 | __IO uint32_t PC; |
| Kovalev_D |
23:12e6183f04d4 | 307 | __IO uint32_t MCR; |
| Kovalev_D |
23:12e6183f04d4 | 308 | __IO uint32_t MR0; |
| Kovalev_D |
23:12e6183f04d4 | 309 | __IO uint32_t MR1; |
| Kovalev_D |
23:12e6183f04d4 | 310 | __IO uint32_t MR2; |
| Kovalev_D |
23:12e6183f04d4 | 311 | __IO uint32_t MR3; |
| Kovalev_D |
23:12e6183f04d4 | 312 | __IO uint32_t CCR; |
| Kovalev_D |
23:12e6183f04d4 | 313 | __I uint32_t CR0; |
| Kovalev_D |
23:12e6183f04d4 | 314 | uint32_t RESERVED1[3]; |
| Kovalev_D |
23:12e6183f04d4 | 315 | __IO uint32_t EMR; |
| Kovalev_D |
23:12e6183f04d4 | 316 | uint32_t RESERVED2[12]; |
| Kovalev_D |
23:12e6183f04d4 | 317 | __IO uint32_t CTCR; |
| Kovalev_D |
23:12e6183f04d4 | 318 | __IO uint32_t PWMC; |
| Kovalev_D |
23:12e6183f04d4 | 319 | } LPC_TMR_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 320 | |
| Kovalev_D |
23:12e6183f04d4 | 321 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
| Kovalev_D |
23:12e6183f04d4 | 322 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 323 | { |
| Kovalev_D |
23:12e6183f04d4 | 324 | union { |
| Kovalev_D |
23:12e6183f04d4 | 325 | __I uint32_t RBR; |
| Kovalev_D |
23:12e6183f04d4 | 326 | __O uint32_t THR; |
| Kovalev_D |
23:12e6183f04d4 | 327 | __IO uint32_t DLL; |
| Kovalev_D |
23:12e6183f04d4 | 328 | }; |
| Kovalev_D |
23:12e6183f04d4 | 329 | union { |
| Kovalev_D |
23:12e6183f04d4 | 330 | __IO uint32_t DLM; |
| Kovalev_D |
23:12e6183f04d4 | 331 | __IO uint32_t IER; |
| Kovalev_D |
23:12e6183f04d4 | 332 | }; |
| Kovalev_D |
23:12e6183f04d4 | 333 | union { |
| Kovalev_D |
23:12e6183f04d4 | 334 | __I uint32_t IIR; |
| Kovalev_D |
23:12e6183f04d4 | 335 | __O uint32_t FCR; |
| Kovalev_D |
23:12e6183f04d4 | 336 | }; |
| Kovalev_D |
23:12e6183f04d4 | 337 | __IO uint32_t LCR; |
| Kovalev_D |
23:12e6183f04d4 | 338 | __IO uint32_t MCR; |
| Kovalev_D |
23:12e6183f04d4 | 339 | __I uint32_t LSR; |
| Kovalev_D |
23:12e6183f04d4 | 340 | __I uint32_t MSR; |
| Kovalev_D |
23:12e6183f04d4 | 341 | __IO uint32_t SCR; |
| Kovalev_D |
23:12e6183f04d4 | 342 | __IO uint32_t ACR; |
| Kovalev_D |
23:12e6183f04d4 | 343 | __IO uint32_t ICR; |
| Kovalev_D |
23:12e6183f04d4 | 344 | __IO uint32_t FDR; |
| Kovalev_D |
23:12e6183f04d4 | 345 | uint32_t RESERVED0; |
| Kovalev_D |
23:12e6183f04d4 | 346 | __IO uint32_t TER; |
| Kovalev_D |
23:12e6183f04d4 | 347 | uint32_t RESERVED1[6]; |
| Kovalev_D |
23:12e6183f04d4 | 348 | __IO uint32_t RS485CTRL; |
| Kovalev_D |
23:12e6183f04d4 | 349 | __IO uint32_t ADRMATCH; |
| Kovalev_D |
23:12e6183f04d4 | 350 | __IO uint32_t RS485DLY; |
| Kovalev_D |
23:12e6183f04d4 | 351 | __I uint32_t FIFOLVL; |
| Kovalev_D |
23:12e6183f04d4 | 352 | } LPC_UART_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 353 | |
| Kovalev_D |
23:12e6183f04d4 | 354 | /*------------- Synchronous Serial Communication (SSP) -----------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 355 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 356 | { |
| Kovalev_D |
23:12e6183f04d4 | 357 | __IO uint32_t CR0; |
| Kovalev_D |
23:12e6183f04d4 | 358 | __IO uint32_t CR1; |
| Kovalev_D |
23:12e6183f04d4 | 359 | __IO uint32_t DR; |
| Kovalev_D |
23:12e6183f04d4 | 360 | __I uint32_t SR; |
| Kovalev_D |
23:12e6183f04d4 | 361 | __IO uint32_t CPSR; |
| Kovalev_D |
23:12e6183f04d4 | 362 | __IO uint32_t IMSC; |
| Kovalev_D |
23:12e6183f04d4 | 363 | __IO uint32_t RIS; |
| Kovalev_D |
23:12e6183f04d4 | 364 | __IO uint32_t MIS; |
| Kovalev_D |
23:12e6183f04d4 | 365 | __IO uint32_t ICR; |
| Kovalev_D |
23:12e6183f04d4 | 366 | } LPC_SSP_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 367 | |
| Kovalev_D |
23:12e6183f04d4 | 368 | /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 369 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 370 | { |
| Kovalev_D |
23:12e6183f04d4 | 371 | __IO uint32_t CONSET; |
| Kovalev_D |
23:12e6183f04d4 | 372 | __I uint32_t STAT; |
| Kovalev_D |
23:12e6183f04d4 | 373 | __IO uint32_t DAT; |
| Kovalev_D |
23:12e6183f04d4 | 374 | __IO uint32_t ADR0; |
| Kovalev_D |
23:12e6183f04d4 | 375 | __IO uint32_t SCLH; |
| Kovalev_D |
23:12e6183f04d4 | 376 | __IO uint32_t SCLL; |
| Kovalev_D |
23:12e6183f04d4 | 377 | __O uint32_t CONCLR; |
| Kovalev_D |
23:12e6183f04d4 | 378 | __IO uint32_t MMCTRL; |
| Kovalev_D |
23:12e6183f04d4 | 379 | __IO uint32_t ADR1; |
| Kovalev_D |
23:12e6183f04d4 | 380 | __IO uint32_t ADR2; |
| Kovalev_D |
23:12e6183f04d4 | 381 | __IO uint32_t ADR3; |
| Kovalev_D |
23:12e6183f04d4 | 382 | __I uint32_t DATA_BUFFER; |
| Kovalev_D |
23:12e6183f04d4 | 383 | __IO uint32_t MASK0; |
| Kovalev_D |
23:12e6183f04d4 | 384 | __IO uint32_t MASK1; |
| Kovalev_D |
23:12e6183f04d4 | 385 | __IO uint32_t MASK2; |
| Kovalev_D |
23:12e6183f04d4 | 386 | __IO uint32_t MASK3; |
| Kovalev_D |
23:12e6183f04d4 | 387 | } LPC_I2C_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 388 | |
| Kovalev_D |
23:12e6183f04d4 | 389 | /*------------- Watchdog Timer (WDT) -----------------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 390 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 391 | { |
| Kovalev_D |
23:12e6183f04d4 | 392 | __IO uint32_t MOD; |
| Kovalev_D |
23:12e6183f04d4 | 393 | __IO uint32_t TC; |
| Kovalev_D |
23:12e6183f04d4 | 394 | __O uint32_t FEED; |
| Kovalev_D |
23:12e6183f04d4 | 395 | __I uint32_t TV; |
| Kovalev_D |
23:12e6183f04d4 | 396 | } LPC_WDT_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 397 | |
| Kovalev_D |
23:12e6183f04d4 | 398 | /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 399 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 400 | { |
| Kovalev_D |
23:12e6183f04d4 | 401 | __IO uint32_t CR; |
| Kovalev_D |
23:12e6183f04d4 | 402 | __IO uint32_t GDR; |
| Kovalev_D |
23:12e6183f04d4 | 403 | uint32_t RESERVED0; |
| Kovalev_D |
23:12e6183f04d4 | 404 | __IO uint32_t INTEN; |
| Kovalev_D |
23:12e6183f04d4 | 405 | __I uint32_t DR0; |
| Kovalev_D |
23:12e6183f04d4 | 406 | __I uint32_t DR1; |
| Kovalev_D |
23:12e6183f04d4 | 407 | __I uint32_t DR2; |
| Kovalev_D |
23:12e6183f04d4 | 408 | __I uint32_t DR3; |
| Kovalev_D |
23:12e6183f04d4 | 409 | __I uint32_t DR4; |
| Kovalev_D |
23:12e6183f04d4 | 410 | __I uint32_t DR5; |
| Kovalev_D |
23:12e6183f04d4 | 411 | __I uint32_t DR6; |
| Kovalev_D |
23:12e6183f04d4 | 412 | __I uint32_t DR7; |
| Kovalev_D |
23:12e6183f04d4 | 413 | __I uint32_t STAT; |
| Kovalev_D |
23:12e6183f04d4 | 414 | } LPC_ADC_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 415 | |
| Kovalev_D |
23:12e6183f04d4 | 416 | |
| Kovalev_D |
23:12e6183f04d4 | 417 | /*------------- Universal Serial Bus (USB) -----------------------------------*/ |
| Kovalev_D |
23:12e6183f04d4 | 418 | typedef struct |
| Kovalev_D |
23:12e6183f04d4 | 419 | { |
| Kovalev_D |
23:12e6183f04d4 | 420 | __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ |
| Kovalev_D |
23:12e6183f04d4 | 421 | __IO uint32_t DevIntEn; |
| Kovalev_D |
23:12e6183f04d4 | 422 | __O uint32_t DevIntClr; |
| Kovalev_D |
23:12e6183f04d4 | 423 | __O uint32_t DevIntSet; |
| Kovalev_D |
23:12e6183f04d4 | 424 | |
| Kovalev_D |
23:12e6183f04d4 | 425 | __O uint32_t CmdCode; /* USB Device SIE Command Registers */ |
| Kovalev_D |
23:12e6183f04d4 | 426 | __I uint32_t CmdData; |
| Kovalev_D |
23:12e6183f04d4 | 427 | |
| Kovalev_D |
23:12e6183f04d4 | 428 | __I uint32_t RxData; /* USB Device Transfer Registers */ |
| Kovalev_D |
23:12e6183f04d4 | 429 | __O uint32_t TxData; |
| Kovalev_D |
23:12e6183f04d4 | 430 | __I uint32_t RxPLen; |
| Kovalev_D |
23:12e6183f04d4 | 431 | __O uint32_t TxPLen; |
| Kovalev_D |
23:12e6183f04d4 | 432 | __IO uint32_t Ctrl; |
| Kovalev_D |
23:12e6183f04d4 | 433 | __O uint32_t DevFIQSel; |
| Kovalev_D |
23:12e6183f04d4 | 434 | } LPC_USB_TypeDef; |
| Kovalev_D |
23:12e6183f04d4 | 435 | |
| Kovalev_D |
23:12e6183f04d4 | 436 | #if defined ( __CC_ARM ) |
| Kovalev_D |
23:12e6183f04d4 | 437 | #pragma no_anon_unions |
| Kovalev_D |
23:12e6183f04d4 | 438 | #endif |
| Kovalev_D |
23:12e6183f04d4 | 439 | |
| Kovalev_D |
23:12e6183f04d4 | 440 | |
| Kovalev_D |
23:12e6183f04d4 | 441 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 442 | /* Peripheral memory map */ |
| Kovalev_D |
23:12e6183f04d4 | 443 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 444 | /* Base addresses */ |
| Kovalev_D |
23:12e6183f04d4 | 445 | #define LPC_FLASH_BASE (0x00000000UL) |
| Kovalev_D |
23:12e6183f04d4 | 446 | #define LPC_RAM_BASE (0x10000000UL) |
| Kovalev_D |
23:12e6183f04d4 | 447 | #define LPC_APB0_BASE (0x40000000UL) |
| Kovalev_D |
23:12e6183f04d4 | 448 | #define LPC_AHB_BASE (0x50000000UL) |
| Kovalev_D |
23:12e6183f04d4 | 449 | |
| Kovalev_D |
23:12e6183f04d4 | 450 | /* APB0 peripherals */ |
| Kovalev_D |
23:12e6183f04d4 | 451 | #define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) |
| Kovalev_D |
23:12e6183f04d4 | 452 | #define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) |
| Kovalev_D |
23:12e6183f04d4 | 453 | #define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) |
| Kovalev_D |
23:12e6183f04d4 | 454 | #define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) |
| Kovalev_D |
23:12e6183f04d4 | 455 | #define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) |
| Kovalev_D |
23:12e6183f04d4 | 456 | #define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) |
| Kovalev_D |
23:12e6183f04d4 | 457 | #define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) |
| Kovalev_D |
23:12e6183f04d4 | 458 | #define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) |
| Kovalev_D |
23:12e6183f04d4 | 459 | #define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) |
| Kovalev_D |
23:12e6183f04d4 | 460 | #define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) |
| Kovalev_D |
23:12e6183f04d4 | 461 | #define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) |
| Kovalev_D |
23:12e6183f04d4 | 462 | #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) |
| Kovalev_D |
23:12e6183f04d4 | 463 | #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) |
| Kovalev_D |
23:12e6183f04d4 | 464 | |
| Kovalev_D |
23:12e6183f04d4 | 465 | /* AHB peripherals */ |
| Kovalev_D |
23:12e6183f04d4 | 466 | #define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) |
| Kovalev_D |
23:12e6183f04d4 | 467 | #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) |
| Kovalev_D |
23:12e6183f04d4 | 468 | #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) |
| Kovalev_D |
23:12e6183f04d4 | 469 | #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) |
| Kovalev_D |
23:12e6183f04d4 | 470 | #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) |
| Kovalev_D |
23:12e6183f04d4 | 471 | |
| Kovalev_D |
23:12e6183f04d4 | 472 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 473 | /* Peripheral declaration */ |
| Kovalev_D |
23:12e6183f04d4 | 474 | /******************************************************************************/ |
| Kovalev_D |
23:12e6183f04d4 | 475 | #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 476 | #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 477 | #define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 478 | #define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) |
| Kovalev_D |
23:12e6183f04d4 | 479 | #define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) |
| Kovalev_D |
23:12e6183f04d4 | 480 | #define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) |
| Kovalev_D |
23:12e6183f04d4 | 481 | #define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) |
| Kovalev_D |
23:12e6183f04d4 | 482 | #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 483 | #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 484 | #define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 485 | #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 486 | #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) |
| Kovalev_D |
23:12e6183f04d4 | 487 | #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 488 | #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 489 | #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 490 | #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 491 | #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) |
| Kovalev_D |
23:12e6183f04d4 | 492 | |
| Kovalev_D |
23:12e6183f04d4 | 493 | #endif // __LPC13xx_H__ |