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host/Source/App/core_cm3.h~RF1c0a0ba.TMP@23:12e6183f04d4, 2016-02-03 (annotated)

Committer:
Kovalev_D
Date:
Wed Feb 03 10:44:42 2016 +0300
Revision:
23:12e6183f04d4
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Kovalev_D 23:12e6183f04d4 1 /**************************************************************************//**
Kovalev_D 23:12e6183f04d4 2 * @file core_cm3.h
Kovalev_D 23:12e6183f04d4 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kovalev_D 23:12e6183f04d4 4 * @version V2.01
Kovalev_D 23:12e6183f04d4 5 * @date 06. December 2010
Kovalev_D 23:12e6183f04d4 6 *
Kovalev_D 23:12e6183f04d4 7 * @note
Kovalev_D 23:12e6183f04d4 8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
Kovalev_D 23:12e6183f04d4 9 *
Kovalev_D 23:12e6183f04d4 10 * @par
Kovalev_D 23:12e6183f04d4 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Kovalev_D 23:12e6183f04d4 12 * processor based microcontrollers. This file can be freely distributed
Kovalev_D 23:12e6183f04d4 13 * within development tools that are supporting such ARM based processors.
Kovalev_D 23:12e6183f04d4 14 *
Kovalev_D 23:12e6183f04d4 15 * @par
Kovalev_D 23:12e6183f04d4 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Kovalev_D 23:12e6183f04d4 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Kovalev_D 23:12e6183f04d4 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Kovalev_D 23:12e6183f04d4 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Kovalev_D 23:12e6183f04d4 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Kovalev_D 23:12e6183f04d4 21 *
Kovalev_D 23:12e6183f04d4 22 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 23 #if defined ( __ICCARM__ )
Kovalev_D 23:12e6183f04d4 24 #pragma system_include /* treat file as system include file for MISRA check */
Kovalev_D 23:12e6183f04d4 25 #endif
Kovalev_D 23:12e6183f04d4 26
Kovalev_D 23:12e6183f04d4 27 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 28 extern "C" {
Kovalev_D 23:12e6183f04d4 29 #endif
Kovalev_D 23:12e6183f04d4 30
Kovalev_D 23:12e6183f04d4 31 #ifndef __CORE_CM3_H_GENERIC
Kovalev_D 23:12e6183f04d4 32 #define __CORE_CM3_H_GENERIC
Kovalev_D 23:12e6183f04d4 33
Kovalev_D 23:12e6183f04d4 34
Kovalev_D 23:12e6183f04d4 35 /** \mainpage CMSIS Cortex-M3
Kovalev_D 23:12e6183f04d4 36
Kovalev_D 23:12e6183f04d4 37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
Kovalev_D 23:12e6183f04d4 38 It consists of:
Kovalev_D 23:12e6183f04d4 39
Kovalev_D 23:12e6183f04d4 40 - Cortex-M Core Register Definitions
Kovalev_D 23:12e6183f04d4 41 - Cortex-M functions
Kovalev_D 23:12e6183f04d4 42 - Cortex-M instructions
Kovalev_D 23:12e6183f04d4 43
Kovalev_D 23:12e6183f04d4 44 The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
Kovalev_D 23:12e6183f04d4 45 access to the Cortex-M Core
Kovalev_D 23:12e6183f04d4 46 */
Kovalev_D 23:12e6183f04d4 47
Kovalev_D 23:12e6183f04d4 48 /** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
Kovalev_D 23:12e6183f04d4 49 List of Lint messages which will be suppressed and not shown:
Kovalev_D 23:12e6183f04d4 50 - not yet checked
Kovalev_D 23:12e6183f04d4 51 .
Kovalev_D 23:12e6183f04d4 52 Note: To re-enable a Message, insert a space before 'lint' *
Kovalev_D 23:12e6183f04d4 53
Kovalev_D 23:12e6183f04d4 54 */
Kovalev_D 23:12e6183f04d4 55
Kovalev_D 23:12e6183f04d4 56
Kovalev_D 23:12e6183f04d4 57 /*******************************************************************************
Kovalev_D 23:12e6183f04d4 58 * CMSIS definitions
Kovalev_D 23:12e6183f04d4 59 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 60 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
Kovalev_D 23:12e6183f04d4 61 This file defines all structures and symbols for CMSIS core:
Kovalev_D 23:12e6183f04d4 62 - CMSIS version number
Kovalev_D 23:12e6183f04d4 63 - Cortex-M core
Kovalev_D 23:12e6183f04d4 64 - Cortex-M core Revision Number
Kovalev_D 23:12e6183f04d4 65 @{
Kovalev_D 23:12e6183f04d4 66 */
Kovalev_D 23:12e6183f04d4 67
Kovalev_D 23:12e6183f04d4 68 /* CMSIS CM3 definitions */
Kovalev_D 23:12e6183f04d4 69 #define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
Kovalev_D 23:12e6183f04d4 70 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kovalev_D 23:12e6183f04d4 71 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kovalev_D 23:12e6183f04d4 72
Kovalev_D 23:12e6183f04d4 73 #define __CORTEX_M (0x03) /*!< Cortex core */
Kovalev_D 23:12e6183f04d4 74
Kovalev_D 23:12e6183f04d4 75
Kovalev_D 23:12e6183f04d4 76 #if defined ( __CC_ARM )
Kovalev_D 23:12e6183f04d4 77 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kovalev_D 23:12e6183f04d4 78 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kovalev_D 23:12e6183f04d4 79
Kovalev_D 23:12e6183f04d4 80 #elif defined ( __ICCARM__ )
Kovalev_D 23:12e6183f04d4 81 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kovalev_D 23:12e6183f04d4 82 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
Kovalev_D 23:12e6183f04d4 83
Kovalev_D 23:12e6183f04d4 84 #elif defined ( __GNUC__ )
Kovalev_D 23:12e6183f04d4 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kovalev_D 23:12e6183f04d4 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kovalev_D 23:12e6183f04d4 87
Kovalev_D 23:12e6183f04d4 88 #elif defined ( __TASKING__ )
Kovalev_D 23:12e6183f04d4 89 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kovalev_D 23:12e6183f04d4 90 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kovalev_D 23:12e6183f04d4 91
Kovalev_D 23:12e6183f04d4 92 #endif
Kovalev_D 23:12e6183f04d4 93
Kovalev_D 23:12e6183f04d4 94 #include <stdint.h> /*!< standard types definitions */
Kovalev_D 23:12e6183f04d4 95 #include "core_cmInstr.h" /*!< Core Instruction Access */
Kovalev_D 23:12e6183f04d4 96 #include "core_cmFunc.h" /*!< Core Function Access */
Kovalev_D 23:12e6183f04d4 97
Kovalev_D 23:12e6183f04d4 98 #endif /* __CORE_CM3_H_GENERIC */
Kovalev_D 23:12e6183f04d4 99
Kovalev_D 23:12e6183f04d4 100
Kovalev_D 23:12e6183f04d4 101 #ifndef __CMSIS_GENERIC
Kovalev_D 23:12e6183f04d4 102
Kovalev_D 23:12e6183f04d4 103 #ifndef __CORE_CM3_H_DEPENDANT
Kovalev_D 23:12e6183f04d4 104 #define __CORE_CM3_H_DEPENDANT
Kovalev_D 23:12e6183f04d4 105
Kovalev_D 23:12e6183f04d4 106 /* IO definitions (access restrictions to peripheral registers) */
Kovalev_D 23:12e6183f04d4 107 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 108 #define __I volatile /*!< defines 'read only' permissions */
Kovalev_D 23:12e6183f04d4 109 #else
Kovalev_D 23:12e6183f04d4 110 #define __I volatile const /*!< defines 'read only' permissions */
Kovalev_D 23:12e6183f04d4 111 #endif
Kovalev_D 23:12e6183f04d4 112 #define __O volatile /*!< defines 'write only' permissions */
Kovalev_D 23:12e6183f04d4 113 #define __IO volatile /*!< defines 'read / write' permissions */
Kovalev_D 23:12e6183f04d4 114
Kovalev_D 23:12e6183f04d4 115 /*@} end of group CMSIS_core_definitions */
Kovalev_D 23:12e6183f04d4 116
Kovalev_D 23:12e6183f04d4 117
Kovalev_D 23:12e6183f04d4 118
Kovalev_D 23:12e6183f04d4 119 /*******************************************************************************
Kovalev_D 23:12e6183f04d4 120 * Register Abstraction
Kovalev_D 23:12e6183f04d4 121 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 122 /** \defgroup CMSIS_core_register CMSIS Core Register
Kovalev_D 23:12e6183f04d4 123 Core Register contain:
Kovalev_D 23:12e6183f04d4 124 - Core Register
Kovalev_D 23:12e6183f04d4 125 - Core NVIC Register
Kovalev_D 23:12e6183f04d4 126 - Core SCB Register
Kovalev_D 23:12e6183f04d4 127 - Core SysTick Register
Kovalev_D 23:12e6183f04d4 128 - Core Debug Register
Kovalev_D 23:12e6183f04d4 129 - Core MPU Register
Kovalev_D 23:12e6183f04d4 130 */
Kovalev_D 23:12e6183f04d4 131
Kovalev_D 23:12e6183f04d4 132 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 133 \defgroup CMSIS_CORE CMSIS Core
Kovalev_D 23:12e6183f04d4 134 Type definitions for the Cortex-M Core Registers
Kovalev_D 23:12e6183f04d4 135 @{
Kovalev_D 23:12e6183f04d4 136 */
Kovalev_D 23:12e6183f04d4 137
Kovalev_D 23:12e6183f04d4 138 /** \brief Union type to access the Application Program Status Register (APSR).
Kovalev_D 23:12e6183f04d4 139 */
Kovalev_D 23:12e6183f04d4 140 typedef union
Kovalev_D 23:12e6183f04d4 141 {
Kovalev_D 23:12e6183f04d4 142 struct
Kovalev_D 23:12e6183f04d4 143 {
Kovalev_D 23:12e6183f04d4 144 #if (__CORTEX_M != 0x04)
Kovalev_D 23:12e6183f04d4 145 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kovalev_D 23:12e6183f04d4 146 #else
Kovalev_D 23:12e6183f04d4 147 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kovalev_D 23:12e6183f04d4 148 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kovalev_D 23:12e6183f04d4 149 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kovalev_D 23:12e6183f04d4 150 #endif
Kovalev_D 23:12e6183f04d4 151 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kovalev_D 23:12e6183f04d4 152 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kovalev_D 23:12e6183f04d4 153 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kovalev_D 23:12e6183f04d4 154 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kovalev_D 23:12e6183f04d4 155 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kovalev_D 23:12e6183f04d4 156 } b; /*!< Structure used for bit access */
Kovalev_D 23:12e6183f04d4 157 uint32_t w; /*!< Type used for word access */
Kovalev_D 23:12e6183f04d4 158 } APSR_Type;
Kovalev_D 23:12e6183f04d4 159
Kovalev_D 23:12e6183f04d4 160
Kovalev_D 23:12e6183f04d4 161 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kovalev_D 23:12e6183f04d4 162 */
Kovalev_D 23:12e6183f04d4 163 typedef union
Kovalev_D 23:12e6183f04d4 164 {
Kovalev_D 23:12e6183f04d4 165 struct
Kovalev_D 23:12e6183f04d4 166 {
Kovalev_D 23:12e6183f04d4 167 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kovalev_D 23:12e6183f04d4 168 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kovalev_D 23:12e6183f04d4 169 } b; /*!< Structure used for bit access */
Kovalev_D 23:12e6183f04d4 170 uint32_t w; /*!< Type used for word access */
Kovalev_D 23:12e6183f04d4 171 } IPSR_Type;
Kovalev_D 23:12e6183f04d4 172
Kovalev_D 23:12e6183f04d4 173
Kovalev_D 23:12e6183f04d4 174 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kovalev_D 23:12e6183f04d4 175 */
Kovalev_D 23:12e6183f04d4 176 typedef union
Kovalev_D 23:12e6183f04d4 177 {
Kovalev_D 23:12e6183f04d4 178 struct
Kovalev_D 23:12e6183f04d4 179 {
Kovalev_D 23:12e6183f04d4 180 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kovalev_D 23:12e6183f04d4 181 #if (__CORTEX_M != 0x04)
Kovalev_D 23:12e6183f04d4 182 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kovalev_D 23:12e6183f04d4 183 #else
Kovalev_D 23:12e6183f04d4 184 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kovalev_D 23:12e6183f04d4 185 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kovalev_D 23:12e6183f04d4 186 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kovalev_D 23:12e6183f04d4 187 #endif
Kovalev_D 23:12e6183f04d4 188 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kovalev_D 23:12e6183f04d4 189 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kovalev_D 23:12e6183f04d4 190 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kovalev_D 23:12e6183f04d4 191 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kovalev_D 23:12e6183f04d4 192 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kovalev_D 23:12e6183f04d4 193 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kovalev_D 23:12e6183f04d4 194 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kovalev_D 23:12e6183f04d4 195 } b; /*!< Structure used for bit access */
Kovalev_D 23:12e6183f04d4 196 uint32_t w; /*!< Type used for word access */
Kovalev_D 23:12e6183f04d4 197 } xPSR_Type;
Kovalev_D 23:12e6183f04d4 198
Kovalev_D 23:12e6183f04d4 199
Kovalev_D 23:12e6183f04d4 200 /** \brief Union type to access the Control Registers (CONTROL).
Kovalev_D 23:12e6183f04d4 201 */
Kovalev_D 23:12e6183f04d4 202 typedef union
Kovalev_D 23:12e6183f04d4 203 {
Kovalev_D 23:12e6183f04d4 204 struct
Kovalev_D 23:12e6183f04d4 205 {
Kovalev_D 23:12e6183f04d4 206 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kovalev_D 23:12e6183f04d4 207 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kovalev_D 23:12e6183f04d4 208 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kovalev_D 23:12e6183f04d4 209 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kovalev_D 23:12e6183f04d4 210 } b; /*!< Structure used for bit access */
Kovalev_D 23:12e6183f04d4 211 uint32_t w; /*!< Type used for word access */
Kovalev_D 23:12e6183f04d4 212 } CONTROL_Type;
Kovalev_D 23:12e6183f04d4 213
Kovalev_D 23:12e6183f04d4 214 /*@} end of group CMSIS_CORE */
Kovalev_D 23:12e6183f04d4 215
Kovalev_D 23:12e6183f04d4 216
Kovalev_D 23:12e6183f04d4 217 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 218 \defgroup CMSIS_NVIC CMSIS NVIC
Kovalev_D 23:12e6183f04d4 219 Type definitions for the Cortex-M NVIC Registers
Kovalev_D 23:12e6183f04d4 220 @{
Kovalev_D 23:12e6183f04d4 221 */
Kovalev_D 23:12e6183f04d4 222
Kovalev_D 23:12e6183f04d4 223 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kovalev_D 23:12e6183f04d4 224 */
Kovalev_D 23:12e6183f04d4 225 typedef struct
Kovalev_D 23:12e6183f04d4 226 {
Kovalev_D 23:12e6183f04d4 227 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kovalev_D 23:12e6183f04d4 228 uint32_t RESERVED0[24];
Kovalev_D 23:12e6183f04d4 229 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kovalev_D 23:12e6183f04d4 230 uint32_t RSERVED1[24];
Kovalev_D 23:12e6183f04d4 231 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kovalev_D 23:12e6183f04d4 232 uint32_t RESERVED2[24];
Kovalev_D 23:12e6183f04d4 233 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kovalev_D 23:12e6183f04d4 234 uint32_t RESERVED3[24];
Kovalev_D 23:12e6183f04d4 235 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kovalev_D 23:12e6183f04d4 236 uint32_t RESERVED4[56];
Kovalev_D 23:12e6183f04d4 237 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kovalev_D 23:12e6183f04d4 238 uint32_t RESERVED5[644];
Kovalev_D 23:12e6183f04d4 239 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kovalev_D 23:12e6183f04d4 240 } NVIC_Type;
Kovalev_D 23:12e6183f04d4 241
Kovalev_D 23:12e6183f04d4 242 /*@} end of group CMSIS_NVIC */
Kovalev_D 23:12e6183f04d4 243
Kovalev_D 23:12e6183f04d4 244
Kovalev_D 23:12e6183f04d4 245 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 246 \defgroup CMSIS_SCB CMSIS SCB
Kovalev_D 23:12e6183f04d4 247 Type definitions for the Cortex-M System Control Block Registers
Kovalev_D 23:12e6183f04d4 248 @{
Kovalev_D 23:12e6183f04d4 249 */
Kovalev_D 23:12e6183f04d4 250
Kovalev_D 23:12e6183f04d4 251 /** \brief Structure type to access the System Control Block (SCB).
Kovalev_D 23:12e6183f04d4 252 */
Kovalev_D 23:12e6183f04d4 253 typedef struct
Kovalev_D 23:12e6183f04d4 254 {
Kovalev_D 23:12e6183f04d4 255 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
Kovalev_D 23:12e6183f04d4 256 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
Kovalev_D 23:12e6183f04d4 257 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kovalev_D 23:12e6183f04d4 258 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
Kovalev_D 23:12e6183f04d4 259 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kovalev_D 23:12e6183f04d4 260 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kovalev_D 23:12e6183f04d4 261 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kovalev_D 23:12e6183f04d4 262 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kovalev_D 23:12e6183f04d4 263 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kovalev_D 23:12e6183f04d4 264 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
Kovalev_D 23:12e6183f04d4 265 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kovalev_D 23:12e6183f04d4 266 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
Kovalev_D 23:12e6183f04d4 267 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
Kovalev_D 23:12e6183f04d4 268 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kovalev_D 23:12e6183f04d4 269 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kovalev_D 23:12e6183f04d4 270 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kovalev_D 23:12e6183f04d4 271 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kovalev_D 23:12e6183f04d4 272 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kovalev_D 23:12e6183f04d4 273 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
Kovalev_D 23:12e6183f04d4 274 } SCB_Type;
Kovalev_D 23:12e6183f04d4 275
Kovalev_D 23:12e6183f04d4 276 /* SCB CPUID Register Definitions */
Kovalev_D 23:12e6183f04d4 277 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kovalev_D 23:12e6183f04d4 278 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kovalev_D 23:12e6183f04d4 279
Kovalev_D 23:12e6183f04d4 280 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kovalev_D 23:12e6183f04d4 281 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kovalev_D 23:12e6183f04d4 282
Kovalev_D 23:12e6183f04d4 283 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kovalev_D 23:12e6183f04d4 284 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kovalev_D 23:12e6183f04d4 285
Kovalev_D 23:12e6183f04d4 286 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kovalev_D 23:12e6183f04d4 287 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kovalev_D 23:12e6183f04d4 288
Kovalev_D 23:12e6183f04d4 289 /* SCB Interrupt Control State Register Definitions */
Kovalev_D 23:12e6183f04d4 290 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kovalev_D 23:12e6183f04d4 291 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kovalev_D 23:12e6183f04d4 292
Kovalev_D 23:12e6183f04d4 293 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kovalev_D 23:12e6183f04d4 294 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kovalev_D 23:12e6183f04d4 295
Kovalev_D 23:12e6183f04d4 296 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kovalev_D 23:12e6183f04d4 297 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kovalev_D 23:12e6183f04d4 298
Kovalev_D 23:12e6183f04d4 299 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kovalev_D 23:12e6183f04d4 300 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kovalev_D 23:12e6183f04d4 301
Kovalev_D 23:12e6183f04d4 302 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kovalev_D 23:12e6183f04d4 303 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kovalev_D 23:12e6183f04d4 304
Kovalev_D 23:12e6183f04d4 305 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kovalev_D 23:12e6183f04d4 306 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kovalev_D 23:12e6183f04d4 307
Kovalev_D 23:12e6183f04d4 308 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kovalev_D 23:12e6183f04d4 309 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kovalev_D 23:12e6183f04d4 310
Kovalev_D 23:12e6183f04d4 311 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kovalev_D 23:12e6183f04d4 312 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kovalev_D 23:12e6183f04d4 313
Kovalev_D 23:12e6183f04d4 314 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kovalev_D 23:12e6183f04d4 315 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kovalev_D 23:12e6183f04d4 316
Kovalev_D 23:12e6183f04d4 317 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kovalev_D 23:12e6183f04d4 318 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kovalev_D 23:12e6183f04d4 319
Kovalev_D 23:12e6183f04d4 320 /* SCB Interrupt Control State Register Definitions */
Kovalev_D 23:12e6183f04d4 321 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kovalev_D 23:12e6183f04d4 322 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kovalev_D 23:12e6183f04d4 323
Kovalev_D 23:12e6183f04d4 324 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kovalev_D 23:12e6183f04d4 325 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kovalev_D 23:12e6183f04d4 326
Kovalev_D 23:12e6183f04d4 327 /* SCB Application Interrupt and Reset Control Register Definitions */
Kovalev_D 23:12e6183f04d4 328 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kovalev_D 23:12e6183f04d4 329 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kovalev_D 23:12e6183f04d4 330
Kovalev_D 23:12e6183f04d4 331 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kovalev_D 23:12e6183f04d4 332 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kovalev_D 23:12e6183f04d4 333
Kovalev_D 23:12e6183f04d4 334 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kovalev_D 23:12e6183f04d4 335 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kovalev_D 23:12e6183f04d4 336
Kovalev_D 23:12e6183f04d4 337 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kovalev_D 23:12e6183f04d4 338 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kovalev_D 23:12e6183f04d4 339
Kovalev_D 23:12e6183f04d4 340 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kovalev_D 23:12e6183f04d4 341 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kovalev_D 23:12e6183f04d4 342
Kovalev_D 23:12e6183f04d4 343 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kovalev_D 23:12e6183f04d4 344 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kovalev_D 23:12e6183f04d4 345
Kovalev_D 23:12e6183f04d4 346 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kovalev_D 23:12e6183f04d4 347 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
Kovalev_D 23:12e6183f04d4 348
Kovalev_D 23:12e6183f04d4 349 /* SCB System Control Register Definitions */
Kovalev_D 23:12e6183f04d4 350 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kovalev_D 23:12e6183f04d4 351 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kovalev_D 23:12e6183f04d4 352
Kovalev_D 23:12e6183f04d4 353 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kovalev_D 23:12e6183f04d4 354 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kovalev_D 23:12e6183f04d4 355
Kovalev_D 23:12e6183f04d4 356 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kovalev_D 23:12e6183f04d4 357 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kovalev_D 23:12e6183f04d4 358
Kovalev_D 23:12e6183f04d4 359 /* SCB Configuration Control Register Definitions */
Kovalev_D 23:12e6183f04d4 360 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kovalev_D 23:12e6183f04d4 361 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kovalev_D 23:12e6183f04d4 362
Kovalev_D 23:12e6183f04d4 363 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kovalev_D 23:12e6183f04d4 364 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kovalev_D 23:12e6183f04d4 365
Kovalev_D 23:12e6183f04d4 366 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kovalev_D 23:12e6183f04d4 367 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kovalev_D 23:12e6183f04d4 368
Kovalev_D 23:12e6183f04d4 369 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kovalev_D 23:12e6183f04d4 370 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kovalev_D 23:12e6183f04d4 371
Kovalev_D 23:12e6183f04d4 372 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kovalev_D 23:12e6183f04d4 373 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kovalev_D 23:12e6183f04d4 374
Kovalev_D 23:12e6183f04d4 375 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kovalev_D 23:12e6183f04d4 376 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
Kovalev_D 23:12e6183f04d4 377
Kovalev_D 23:12e6183f04d4 378 /* SCB System Handler Control and State Register Definitions */
Kovalev_D 23:12e6183f04d4 379 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kovalev_D 23:12e6183f04d4 380 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 381
Kovalev_D 23:12e6183f04d4 382 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kovalev_D 23:12e6183f04d4 383 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 384
Kovalev_D 23:12e6183f04d4 385 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kovalev_D 23:12e6183f04d4 386 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kovalev_D 23:12e6183f04d4 387
Kovalev_D 23:12e6183f04d4 388 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kovalev_D 23:12e6183f04d4 389 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kovalev_D 23:12e6183f04d4 390
Kovalev_D 23:12e6183f04d4 391 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 392 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 393
Kovalev_D 23:12e6183f04d4 394 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 395 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 396
Kovalev_D 23:12e6183f04d4 397 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kovalev_D 23:12e6183f04d4 398 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kovalev_D 23:12e6183f04d4 399
Kovalev_D 23:12e6183f04d4 400 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kovalev_D 23:12e6183f04d4 401 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kovalev_D 23:12e6183f04d4 402
Kovalev_D 23:12e6183f04d4 403 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kovalev_D 23:12e6183f04d4 404 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kovalev_D 23:12e6183f04d4 405
Kovalev_D 23:12e6183f04d4 406 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kovalev_D 23:12e6183f04d4 407 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kovalev_D 23:12e6183f04d4 408
Kovalev_D 23:12e6183f04d4 409 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kovalev_D 23:12e6183f04d4 410 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kovalev_D 23:12e6183f04d4 411
Kovalev_D 23:12e6183f04d4 412 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kovalev_D 23:12e6183f04d4 413 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 414
Kovalev_D 23:12e6183f04d4 415 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kovalev_D 23:12e6183f04d4 416 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 417
Kovalev_D 23:12e6183f04d4 418 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kovalev_D 23:12e6183f04d4 419 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kovalev_D 23:12e6183f04d4 420
Kovalev_D 23:12e6183f04d4 421 /* SCB Configurable Fault Status Registers Definitions */
Kovalev_D 23:12e6183f04d4 422 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 423 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 424
Kovalev_D 23:12e6183f04d4 425 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 426 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 427
Kovalev_D 23:12e6183f04d4 428 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kovalev_D 23:12e6183f04d4 429 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kovalev_D 23:12e6183f04d4 430
Kovalev_D 23:12e6183f04d4 431 /* SCB Hard Fault Status Registers Definitions */
Kovalev_D 23:12e6183f04d4 432 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kovalev_D 23:12e6183f04d4 433 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kovalev_D 23:12e6183f04d4 434
Kovalev_D 23:12e6183f04d4 435 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kovalev_D 23:12e6183f04d4 436 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kovalev_D 23:12e6183f04d4 437
Kovalev_D 23:12e6183f04d4 438 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kovalev_D 23:12e6183f04d4 439 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kovalev_D 23:12e6183f04d4 440
Kovalev_D 23:12e6183f04d4 441 /* SCB Debug Fault Status Register Definitions */
Kovalev_D 23:12e6183f04d4 442 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kovalev_D 23:12e6183f04d4 443 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kovalev_D 23:12e6183f04d4 444
Kovalev_D 23:12e6183f04d4 445 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kovalev_D 23:12e6183f04d4 446 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kovalev_D 23:12e6183f04d4 447
Kovalev_D 23:12e6183f04d4 448 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kovalev_D 23:12e6183f04d4 449 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kovalev_D 23:12e6183f04d4 450
Kovalev_D 23:12e6183f04d4 451 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kovalev_D 23:12e6183f04d4 452 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kovalev_D 23:12e6183f04d4 453
Kovalev_D 23:12e6183f04d4 454 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kovalev_D 23:12e6183f04d4 455 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
Kovalev_D 23:12e6183f04d4 456
Kovalev_D 23:12e6183f04d4 457 /*@} end of group CMSIS_SCB */
Kovalev_D 23:12e6183f04d4 458
Kovalev_D 23:12e6183f04d4 459
Kovalev_D 23:12e6183f04d4 460 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 461 \defgroup CMSIS_SysTick CMSIS SysTick
Kovalev_D 23:12e6183f04d4 462 Type definitions for the Cortex-M System Timer Registers
Kovalev_D 23:12e6183f04d4 463 @{
Kovalev_D 23:12e6183f04d4 464 */
Kovalev_D 23:12e6183f04d4 465
Kovalev_D 23:12e6183f04d4 466 /** \brief Structure type to access the System Timer (SysTick).
Kovalev_D 23:12e6183f04d4 467 */
Kovalev_D 23:12e6183f04d4 468 typedef struct
Kovalev_D 23:12e6183f04d4 469 {
Kovalev_D 23:12e6183f04d4 470 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kovalev_D 23:12e6183f04d4 471 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kovalev_D 23:12e6183f04d4 472 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kovalev_D 23:12e6183f04d4 473 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kovalev_D 23:12e6183f04d4 474 } SysTick_Type;
Kovalev_D 23:12e6183f04d4 475
Kovalev_D 23:12e6183f04d4 476 /* SysTick Control / Status Register Definitions */
Kovalev_D 23:12e6183f04d4 477 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kovalev_D 23:12e6183f04d4 478 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kovalev_D 23:12e6183f04d4 479
Kovalev_D 23:12e6183f04d4 480 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kovalev_D 23:12e6183f04d4 481 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kovalev_D 23:12e6183f04d4 482
Kovalev_D 23:12e6183f04d4 483 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kovalev_D 23:12e6183f04d4 484 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kovalev_D 23:12e6183f04d4 485
Kovalev_D 23:12e6183f04d4 486 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kovalev_D 23:12e6183f04d4 487 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kovalev_D 23:12e6183f04d4 488
Kovalev_D 23:12e6183f04d4 489 /* SysTick Reload Register Definitions */
Kovalev_D 23:12e6183f04d4 490 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kovalev_D 23:12e6183f04d4 491 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kovalev_D 23:12e6183f04d4 492
Kovalev_D 23:12e6183f04d4 493 /* SysTick Current Register Definitions */
Kovalev_D 23:12e6183f04d4 494 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kovalev_D 23:12e6183f04d4 495 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kovalev_D 23:12e6183f04d4 496
Kovalev_D 23:12e6183f04d4 497 /* SysTick Calibration Register Definitions */
Kovalev_D 23:12e6183f04d4 498 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kovalev_D 23:12e6183f04d4 499 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kovalev_D 23:12e6183f04d4 500
Kovalev_D 23:12e6183f04d4 501 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kovalev_D 23:12e6183f04d4 502 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kovalev_D 23:12e6183f04d4 503
Kovalev_D 23:12e6183f04d4 504 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kovalev_D 23:12e6183f04d4 505 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kovalev_D 23:12e6183f04d4 506
Kovalev_D 23:12e6183f04d4 507 /*@} end of group CMSIS_SysTick */
Kovalev_D 23:12e6183f04d4 508
Kovalev_D 23:12e6183f04d4 509
Kovalev_D 23:12e6183f04d4 510 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 511 \defgroup CMSIS_ITM CMSIS ITM
Kovalev_D 23:12e6183f04d4 512 Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
Kovalev_D 23:12e6183f04d4 513 @{
Kovalev_D 23:12e6183f04d4 514 */
Kovalev_D 23:12e6183f04d4 515
Kovalev_D 23:12e6183f04d4 516 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kovalev_D 23:12e6183f04d4 517 */
Kovalev_D 23:12e6183f04d4 518 typedef struct
Kovalev_D 23:12e6183f04d4 519 {
Kovalev_D 23:12e6183f04d4 520 __O union
Kovalev_D 23:12e6183f04d4 521 {
Kovalev_D 23:12e6183f04d4 522 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kovalev_D 23:12e6183f04d4 523 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kovalev_D 23:12e6183f04d4 524 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kovalev_D 23:12e6183f04d4 525 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kovalev_D 23:12e6183f04d4 526 uint32_t RESERVED0[864];
Kovalev_D 23:12e6183f04d4 527 __IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
Kovalev_D 23:12e6183f04d4 528 uint32_t RESERVED1[15];
Kovalev_D 23:12e6183f04d4 529 __IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
Kovalev_D 23:12e6183f04d4 530 uint32_t RESERVED2[15];
Kovalev_D 23:12e6183f04d4 531 __IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
Kovalev_D 23:12e6183f04d4 532 uint32_t RESERVED3[29];
Kovalev_D 23:12e6183f04d4 533 __IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
Kovalev_D 23:12e6183f04d4 534 __IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
Kovalev_D 23:12e6183f04d4 535 __IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
Kovalev_D 23:12e6183f04d4 536 uint32_t RESERVED4[43];
Kovalev_D 23:12e6183f04d4 537 __IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
Kovalev_D 23:12e6183f04d4 538 __IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
Kovalev_D 23:12e6183f04d4 539 uint32_t RESERVED5[6];
Kovalev_D 23:12e6183f04d4 540 __I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
Kovalev_D 23:12e6183f04d4 541 __I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
Kovalev_D 23:12e6183f04d4 542 __I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
Kovalev_D 23:12e6183f04d4 543 __I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */
Kovalev_D 23:12e6183f04d4 544 __I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */
Kovalev_D 23:12e6183f04d4 545 __I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */
Kovalev_D 23:12e6183f04d4 546 __I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */
Kovalev_D 23:12e6183f04d4 547 __I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */
Kovalev_D 23:12e6183f04d4 548 __I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */
Kovalev_D 23:12e6183f04d4 549 __I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
Kovalev_D 23:12e6183f04d4 550 __I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
Kovalev_D 23:12e6183f04d4 551 __I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
Kovalev_D 23:12e6183f04d4 552 } ITM_Type;
Kovalev_D 23:12e6183f04d4 553
Kovalev_D 23:12e6183f04d4 554 /* ITM Trace Privilege Register Definitions */
Kovalev_D 23:12e6183f04d4 555 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kovalev_D 23:12e6183f04d4 556 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
Kovalev_D 23:12e6183f04d4 557
Kovalev_D 23:12e6183f04d4 558 /* ITM Trace Control Register Definitions */
Kovalev_D 23:12e6183f04d4 559 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kovalev_D 23:12e6183f04d4 560 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kovalev_D 23:12e6183f04d4 561
Kovalev_D 23:12e6183f04d4 562 #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
Kovalev_D 23:12e6183f04d4 563 #define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
Kovalev_D 23:12e6183f04d4 564
Kovalev_D 23:12e6183f04d4 565 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kovalev_D 23:12e6183f04d4 566 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kovalev_D 23:12e6183f04d4 567
Kovalev_D 23:12e6183f04d4 568 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kovalev_D 23:12e6183f04d4 569 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kovalev_D 23:12e6183f04d4 570
Kovalev_D 23:12e6183f04d4 571 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kovalev_D 23:12e6183f04d4 572 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kovalev_D 23:12e6183f04d4 573
Kovalev_D 23:12e6183f04d4 574 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kovalev_D 23:12e6183f04d4 575 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kovalev_D 23:12e6183f04d4 576
Kovalev_D 23:12e6183f04d4 577 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kovalev_D 23:12e6183f04d4 578 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kovalev_D 23:12e6183f04d4 579
Kovalev_D 23:12e6183f04d4 580 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kovalev_D 23:12e6183f04d4 581 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
Kovalev_D 23:12e6183f04d4 582
Kovalev_D 23:12e6183f04d4 583 /* ITM Integration Write Register Definitions */
Kovalev_D 23:12e6183f04d4 584 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kovalev_D 23:12e6183f04d4 585 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
Kovalev_D 23:12e6183f04d4 586
Kovalev_D 23:12e6183f04d4 587 /* ITM Integration Read Register Definitions */
Kovalev_D 23:12e6183f04d4 588 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kovalev_D 23:12e6183f04d4 589 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
Kovalev_D 23:12e6183f04d4 590
Kovalev_D 23:12e6183f04d4 591 /* ITM Integration Mode Control Register Definitions */
Kovalev_D 23:12e6183f04d4 592 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kovalev_D 23:12e6183f04d4 593 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
Kovalev_D 23:12e6183f04d4 594
Kovalev_D 23:12e6183f04d4 595 /* ITM Lock Status Register Definitions */
Kovalev_D 23:12e6183f04d4 596 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kovalev_D 23:12e6183f04d4 597 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kovalev_D 23:12e6183f04d4 598
Kovalev_D 23:12e6183f04d4 599 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kovalev_D 23:12e6183f04d4 600 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kovalev_D 23:12e6183f04d4 601
Kovalev_D 23:12e6183f04d4 602 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kovalev_D 23:12e6183f04d4 603 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
Kovalev_D 23:12e6183f04d4 604
Kovalev_D 23:12e6183f04d4 605 /*@}*/ /* end of group CMSIS_ITM */
Kovalev_D 23:12e6183f04d4 606
Kovalev_D 23:12e6183f04d4 607
Kovalev_D 23:12e6183f04d4 608 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 609 \defgroup CMSIS_InterruptType CMSIS Interrupt Type
Kovalev_D 23:12e6183f04d4 610 Type definitions for the Cortex-M Interrupt Type Register
Kovalev_D 23:12e6183f04d4 611 @{
Kovalev_D 23:12e6183f04d4 612 */
Kovalev_D 23:12e6183f04d4 613
Kovalev_D 23:12e6183f04d4 614 /** \brief Structure type to access the Interrupt Type Register.
Kovalev_D 23:12e6183f04d4 615 */
Kovalev_D 23:12e6183f04d4 616 typedef struct
Kovalev_D 23:12e6183f04d4 617 {
Kovalev_D 23:12e6183f04d4 618 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 619 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */
Kovalev_D 23:12e6183f04d4 620 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kovalev_D 23:12e6183f04d4 621 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kovalev_D 23:12e6183f04d4 622 #else
Kovalev_D 23:12e6183f04d4 623 uint32_t RESERVED1;
Kovalev_D 23:12e6183f04d4 624 #endif
Kovalev_D 23:12e6183f04d4 625 } InterruptType_Type;
Kovalev_D 23:12e6183f04d4 626
Kovalev_D 23:12e6183f04d4 627 /* Interrupt Controller Type Register Definitions */
Kovalev_D 23:12e6183f04d4 628 #define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
Kovalev_D 23:12e6183f04d4 629 #define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
Kovalev_D 23:12e6183f04d4 630
Kovalev_D 23:12e6183f04d4 631 /* Auxiliary Control Register Definitions */
Kovalev_D 23:12e6183f04d4 632 #define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
Kovalev_D 23:12e6183f04d4 633 #define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
Kovalev_D 23:12e6183f04d4 634
Kovalev_D 23:12e6183f04d4 635 #define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
Kovalev_D 23:12e6183f04d4 636 #define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
Kovalev_D 23:12e6183f04d4 637
Kovalev_D 23:12e6183f04d4 638 #define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
Kovalev_D 23:12e6183f04d4 639 #define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
Kovalev_D 23:12e6183f04d4 640
Kovalev_D 23:12e6183f04d4 641 /*@}*/ /* end of group CMSIS_InterruptType */
Kovalev_D 23:12e6183f04d4 642
Kovalev_D 23:12e6183f04d4 643
Kovalev_D 23:12e6183f04d4 644 #if (__MPU_PRESENT == 1)
Kovalev_D 23:12e6183f04d4 645 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 646 \defgroup CMSIS_MPU CMSIS MPU
Kovalev_D 23:12e6183f04d4 647 Type definitions for the Cortex-M Memory Protection Unit (MPU)
Kovalev_D 23:12e6183f04d4 648 @{
Kovalev_D 23:12e6183f04d4 649 */
Kovalev_D 23:12e6183f04d4 650
Kovalev_D 23:12e6183f04d4 651 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kovalev_D 23:12e6183f04d4 652 */
Kovalev_D 23:12e6183f04d4 653 typedef struct
Kovalev_D 23:12e6183f04d4 654 {
Kovalev_D 23:12e6183f04d4 655 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kovalev_D 23:12e6183f04d4 656 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kovalev_D 23:12e6183f04d4 657 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kovalev_D 23:12e6183f04d4 658 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kovalev_D 23:12e6183f04d4 659 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 660 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 661 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 662 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 663 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 664 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kovalev_D 23:12e6183f04d4 665 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 666 } MPU_Type;
Kovalev_D 23:12e6183f04d4 667
Kovalev_D 23:12e6183f04d4 668 /* MPU Type Register */
Kovalev_D 23:12e6183f04d4 669 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kovalev_D 23:12e6183f04d4 670 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kovalev_D 23:12e6183f04d4 671
Kovalev_D 23:12e6183f04d4 672 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kovalev_D 23:12e6183f04d4 673 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kovalev_D 23:12e6183f04d4 674
Kovalev_D 23:12e6183f04d4 675 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kovalev_D 23:12e6183f04d4 676 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kovalev_D 23:12e6183f04d4 677
Kovalev_D 23:12e6183f04d4 678 /* MPU Control Register */
Kovalev_D 23:12e6183f04d4 679 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kovalev_D 23:12e6183f04d4 680 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kovalev_D 23:12e6183f04d4 681
Kovalev_D 23:12e6183f04d4 682 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kovalev_D 23:12e6183f04d4 683 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kovalev_D 23:12e6183f04d4 684
Kovalev_D 23:12e6183f04d4 685 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kovalev_D 23:12e6183f04d4 686 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kovalev_D 23:12e6183f04d4 687
Kovalev_D 23:12e6183f04d4 688 /* MPU Region Number Register */
Kovalev_D 23:12e6183f04d4 689 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kovalev_D 23:12e6183f04d4 690 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kovalev_D 23:12e6183f04d4 691
Kovalev_D 23:12e6183f04d4 692 /* MPU Region Base Address Register */
Kovalev_D 23:12e6183f04d4 693 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kovalev_D 23:12e6183f04d4 694 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kovalev_D 23:12e6183f04d4 695
Kovalev_D 23:12e6183f04d4 696 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kovalev_D 23:12e6183f04d4 697 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kovalev_D 23:12e6183f04d4 698
Kovalev_D 23:12e6183f04d4 699 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kovalev_D 23:12e6183f04d4 700 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kovalev_D 23:12e6183f04d4 701
Kovalev_D 23:12e6183f04d4 702 /* MPU Region Attribute and Size Register */
Kovalev_D 23:12e6183f04d4 703 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
Kovalev_D 23:12e6183f04d4 704 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
Kovalev_D 23:12e6183f04d4 705
Kovalev_D 23:12e6183f04d4 706 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
Kovalev_D 23:12e6183f04d4 707 #define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
Kovalev_D 23:12e6183f04d4 708
Kovalev_D 23:12e6183f04d4 709 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
Kovalev_D 23:12e6183f04d4 710 #define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
Kovalev_D 23:12e6183f04d4 711
Kovalev_D 23:12e6183f04d4 712 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
Kovalev_D 23:12e6183f04d4 713 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
Kovalev_D 23:12e6183f04d4 714
Kovalev_D 23:12e6183f04d4 715 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
Kovalev_D 23:12e6183f04d4 716 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
Kovalev_D 23:12e6183f04d4 717
Kovalev_D 23:12e6183f04d4 718 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
Kovalev_D 23:12e6183f04d4 719 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
Kovalev_D 23:12e6183f04d4 720
Kovalev_D 23:12e6183f04d4 721 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kovalev_D 23:12e6183f04d4 722 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kovalev_D 23:12e6183f04d4 723
Kovalev_D 23:12e6183f04d4 724 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kovalev_D 23:12e6183f04d4 725 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kovalev_D 23:12e6183f04d4 726
Kovalev_D 23:12e6183f04d4 727 #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kovalev_D 23:12e6183f04d4 728 #define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kovalev_D 23:12e6183f04d4 729
Kovalev_D 23:12e6183f04d4 730 /*@} end of group CMSIS_MPU */
Kovalev_D 23:12e6183f04d4 731 #endif
Kovalev_D 23:12e6183f04d4 732
Kovalev_D 23:12e6183f04d4 733
Kovalev_D 23:12e6183f04d4 734 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 735 \defgroup CMSIS_CoreDebug CMSIS Core Debug
Kovalev_D 23:12e6183f04d4 736 Type definitions for the Cortex-M Core Debug Registers
Kovalev_D 23:12e6183f04d4 737 @{
Kovalev_D 23:12e6183f04d4 738 */
Kovalev_D 23:12e6183f04d4 739
Kovalev_D 23:12e6183f04d4 740 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kovalev_D 23:12e6183f04d4 741 */
Kovalev_D 23:12e6183f04d4 742 typedef struct
Kovalev_D 23:12e6183f04d4 743 {
Kovalev_D 23:12e6183f04d4 744 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kovalev_D 23:12e6183f04d4 745 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kovalev_D 23:12e6183f04d4 746 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kovalev_D 23:12e6183f04d4 747 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kovalev_D 23:12e6183f04d4 748 } CoreDebug_Type;
Kovalev_D 23:12e6183f04d4 749
Kovalev_D 23:12e6183f04d4 750 /* Debug Halting Control and Status Register */
Kovalev_D 23:12e6183f04d4 751 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kovalev_D 23:12e6183f04d4 752 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kovalev_D 23:12e6183f04d4 753
Kovalev_D 23:12e6183f04d4 754 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kovalev_D 23:12e6183f04d4 755 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kovalev_D 23:12e6183f04d4 756
Kovalev_D 23:12e6183f04d4 757 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kovalev_D 23:12e6183f04d4 758 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kovalev_D 23:12e6183f04d4 759
Kovalev_D 23:12e6183f04d4 760 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kovalev_D 23:12e6183f04d4 761 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kovalev_D 23:12e6183f04d4 762
Kovalev_D 23:12e6183f04d4 763 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kovalev_D 23:12e6183f04d4 764 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kovalev_D 23:12e6183f04d4 765
Kovalev_D 23:12e6183f04d4 766 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kovalev_D 23:12e6183f04d4 767 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kovalev_D 23:12e6183f04d4 768
Kovalev_D 23:12e6183f04d4 769 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kovalev_D 23:12e6183f04d4 770 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kovalev_D 23:12e6183f04d4 771
Kovalev_D 23:12e6183f04d4 772 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kovalev_D 23:12e6183f04d4 773 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kovalev_D 23:12e6183f04d4 774
Kovalev_D 23:12e6183f04d4 775 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kovalev_D 23:12e6183f04d4 776 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kovalev_D 23:12e6183f04d4 777
Kovalev_D 23:12e6183f04d4 778 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kovalev_D 23:12e6183f04d4 779 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kovalev_D 23:12e6183f04d4 780
Kovalev_D 23:12e6183f04d4 781 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kovalev_D 23:12e6183f04d4 782 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kovalev_D 23:12e6183f04d4 783
Kovalev_D 23:12e6183f04d4 784 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kovalev_D 23:12e6183f04d4 785 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kovalev_D 23:12e6183f04d4 786
Kovalev_D 23:12e6183f04d4 787 /* Debug Core Register Selector Register */
Kovalev_D 23:12e6183f04d4 788 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kovalev_D 23:12e6183f04d4 789 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kovalev_D 23:12e6183f04d4 790
Kovalev_D 23:12e6183f04d4 791 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kovalev_D 23:12e6183f04d4 792 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
Kovalev_D 23:12e6183f04d4 793
Kovalev_D 23:12e6183f04d4 794 /* Debug Exception and Monitor Control Register */
Kovalev_D 23:12e6183f04d4 795 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kovalev_D 23:12e6183f04d4 796 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kovalev_D 23:12e6183f04d4 797
Kovalev_D 23:12e6183f04d4 798 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kovalev_D 23:12e6183f04d4 799 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kovalev_D 23:12e6183f04d4 800
Kovalev_D 23:12e6183f04d4 801 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kovalev_D 23:12e6183f04d4 802 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kovalev_D 23:12e6183f04d4 803
Kovalev_D 23:12e6183f04d4 804 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kovalev_D 23:12e6183f04d4 805 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kovalev_D 23:12e6183f04d4 806
Kovalev_D 23:12e6183f04d4 807 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kovalev_D 23:12e6183f04d4 808 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kovalev_D 23:12e6183f04d4 809
Kovalev_D 23:12e6183f04d4 810 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kovalev_D 23:12e6183f04d4 811 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kovalev_D 23:12e6183f04d4 812
Kovalev_D 23:12e6183f04d4 813 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kovalev_D 23:12e6183f04d4 814 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kovalev_D 23:12e6183f04d4 815
Kovalev_D 23:12e6183f04d4 816 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kovalev_D 23:12e6183f04d4 817 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kovalev_D 23:12e6183f04d4 818
Kovalev_D 23:12e6183f04d4 819 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kovalev_D 23:12e6183f04d4 820 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kovalev_D 23:12e6183f04d4 821
Kovalev_D 23:12e6183f04d4 822 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kovalev_D 23:12e6183f04d4 823 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kovalev_D 23:12e6183f04d4 824
Kovalev_D 23:12e6183f04d4 825 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kovalev_D 23:12e6183f04d4 826 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kovalev_D 23:12e6183f04d4 827
Kovalev_D 23:12e6183f04d4 828 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kovalev_D 23:12e6183f04d4 829 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kovalev_D 23:12e6183f04d4 830
Kovalev_D 23:12e6183f04d4 831 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kovalev_D 23:12e6183f04d4 832 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kovalev_D 23:12e6183f04d4 833
Kovalev_D 23:12e6183f04d4 834 /*@} end of group CMSIS_CoreDebug */
Kovalev_D 23:12e6183f04d4 835
Kovalev_D 23:12e6183f04d4 836
Kovalev_D 23:12e6183f04d4 837 /** \ingroup CMSIS_core_register
Kovalev_D 23:12e6183f04d4 838 @{
Kovalev_D 23:12e6183f04d4 839 */
Kovalev_D 23:12e6183f04d4 840
Kovalev_D 23:12e6183f04d4 841 /* Memory mapping of Cortex-M3 Hardware */
Kovalev_D 23:12e6183f04d4 842 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kovalev_D 23:12e6183f04d4 843 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kovalev_D 23:12e6183f04d4 844 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kovalev_D 23:12e6183f04d4 845 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kovalev_D 23:12e6183f04d4 846 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kovalev_D 23:12e6183f04d4 847 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kovalev_D 23:12e6183f04d4 848
Kovalev_D 23:12e6183f04d4 849 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
Kovalev_D 23:12e6183f04d4 850 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
Kovalev_D 23:12e6183f04d4 851 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
Kovalev_D 23:12e6183f04d4 852 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
Kovalev_D 23:12e6183f04d4 853 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
Kovalev_D 23:12e6183f04d4 854 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kovalev_D 23:12e6183f04d4 855
Kovalev_D 23:12e6183f04d4 856 #if (__MPU_PRESENT == 1)
Kovalev_D 23:12e6183f04d4 857 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kovalev_D 23:12e6183f04d4 858 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
Kovalev_D 23:12e6183f04d4 859 #endif
Kovalev_D 23:12e6183f04d4 860
Kovalev_D 23:12e6183f04d4 861 /*@} */
Kovalev_D 23:12e6183f04d4 862
Kovalev_D 23:12e6183f04d4 863
Kovalev_D 23:12e6183f04d4 864
Kovalev_D 23:12e6183f04d4 865 /*******************************************************************************
Kovalev_D 23:12e6183f04d4 866 * Hardware Abstraction Layer
Kovalev_D 23:12e6183f04d4 867 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 868 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Kovalev_D 23:12e6183f04d4 869 Core Function Interface contains:
Kovalev_D 23:12e6183f04d4 870 - Core NVIC Functions
Kovalev_D 23:12e6183f04d4 871 - Core SysTick Functions
Kovalev_D 23:12e6183f04d4 872 - Core Debug Functions
Kovalev_D 23:12e6183f04d4 873 - Core Register Access Functions
Kovalev_D 23:12e6183f04d4 874 */
Kovalev_D 23:12e6183f04d4 875
Kovalev_D 23:12e6183f04d4 876
Kovalev_D 23:12e6183f04d4 877
Kovalev_D 23:12e6183f04d4 878 /* ########################## NVIC functions #################################### */
Kovalev_D 23:12e6183f04d4 879 /** \ingroup CMSIS_Core_FunctionInterface
Kovalev_D 23:12e6183f04d4 880 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
Kovalev_D 23:12e6183f04d4 881 @{
Kovalev_D 23:12e6183f04d4 882 */
Kovalev_D 23:12e6183f04d4 883
Kovalev_D 23:12e6183f04d4 884 /** \brief Set Priority Grouping
Kovalev_D 23:12e6183f04d4 885
Kovalev_D 23:12e6183f04d4 886 This function sets the priority grouping field using the required unlock sequence.
Kovalev_D 23:12e6183f04d4 887 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kovalev_D 23:12e6183f04d4 888 Only values from 0..7 are used.
Kovalev_D 23:12e6183f04d4 889 In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 890 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kovalev_D 23:12e6183f04d4 891
Kovalev_D 23:12e6183f04d4 892 \param [in] PriorityGroup Priority grouping field
Kovalev_D 23:12e6183f04d4 893 */
Kovalev_D 23:12e6183f04d4 894 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kovalev_D 23:12e6183f04d4 895 {
Kovalev_D 23:12e6183f04d4 896 uint32_t reg_value;
Kovalev_D 23:12e6183f04d4 897 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 898
Kovalev_D 23:12e6183f04d4 899 reg_value = SCB->AIRCR; /* read old register configuration */
Kovalev_D 23:12e6183f04d4 900 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Kovalev_D 23:12e6183f04d4 901 reg_value = (reg_value |
Kovalev_D 23:12e6183f04d4 902 (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kovalev_D 23:12e6183f04d4 903 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Kovalev_D 23:12e6183f04d4 904 SCB->AIRCR = reg_value;
Kovalev_D 23:12e6183f04d4 905 }
Kovalev_D 23:12e6183f04d4 906
Kovalev_D 23:12e6183f04d4 907
Kovalev_D 23:12e6183f04d4 908 /** \brief Get Priority Grouping
Kovalev_D 23:12e6183f04d4 909
Kovalev_D 23:12e6183f04d4 910 This function gets the priority grouping from NVIC Interrupt Controller.
Kovalev_D 23:12e6183f04d4 911 Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
Kovalev_D 23:12e6183f04d4 912
Kovalev_D 23:12e6183f04d4 913 \return Priority grouping field
Kovalev_D 23:12e6183f04d4 914 */
Kovalev_D 23:12e6183f04d4 915 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kovalev_D 23:12e6183f04d4 916 {
Kovalev_D 23:12e6183f04d4 917 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Kovalev_D 23:12e6183f04d4 918 }
Kovalev_D 23:12e6183f04d4 919
Kovalev_D 23:12e6183f04d4 920
Kovalev_D 23:12e6183f04d4 921 /** \brief Enable External Interrupt
Kovalev_D 23:12e6183f04d4 922
Kovalev_D 23:12e6183f04d4 923 This function enables a device specific interupt in the NVIC interrupt controller.
Kovalev_D 23:12e6183f04d4 924 The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 925
Kovalev_D 23:12e6183f04d4 926 \param [in] IRQn Number of the external interrupt to enable
Kovalev_D 23:12e6183f04d4 927 */
Kovalev_D 23:12e6183f04d4 928 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 929 {
Kovalev_D 23:12e6183f04d4 930 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Kovalev_D 23:12e6183f04d4 931 }
Kovalev_D 23:12e6183f04d4 932
Kovalev_D 23:12e6183f04d4 933
Kovalev_D 23:12e6183f04d4 934 /** \brief Disable External Interrupt
Kovalev_D 23:12e6183f04d4 935
Kovalev_D 23:12e6183f04d4 936 This function disables a device specific interupt in the NVIC interrupt controller.
Kovalev_D 23:12e6183f04d4 937 The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 938
Kovalev_D 23:12e6183f04d4 939 \param [in] IRQn Number of the external interrupt to disable
Kovalev_D 23:12e6183f04d4 940 */
Kovalev_D 23:12e6183f04d4 941 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 942 {
Kovalev_D 23:12e6183f04d4 943 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Kovalev_D 23:12e6183f04d4 944 }
Kovalev_D 23:12e6183f04d4 945
Kovalev_D 23:12e6183f04d4 946
Kovalev_D 23:12e6183f04d4 947 /** \brief Get Pending Interrupt
Kovalev_D 23:12e6183f04d4 948
Kovalev_D 23:12e6183f04d4 949 This function reads the pending register in the NVIC and returns the pending bit
Kovalev_D 23:12e6183f04d4 950 for the specified interrupt.
Kovalev_D 23:12e6183f04d4 951
Kovalev_D 23:12e6183f04d4 952 \param [in] IRQn Number of the interrupt for get pending
Kovalev_D 23:12e6183f04d4 953 \return 0 Interrupt status is not pending
Kovalev_D 23:12e6183f04d4 954 \return 1 Interrupt status is pending
Kovalev_D 23:12e6183f04d4 955 */
Kovalev_D 23:12e6183f04d4 956 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 957 {
Kovalev_D 23:12e6183f04d4 958 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Kovalev_D 23:12e6183f04d4 959 }
Kovalev_D 23:12e6183f04d4 960
Kovalev_D 23:12e6183f04d4 961
Kovalev_D 23:12e6183f04d4 962 /** \brief Set Pending Interrupt
Kovalev_D 23:12e6183f04d4 963
Kovalev_D 23:12e6183f04d4 964 This function sets the pending bit for the specified interrupt.
Kovalev_D 23:12e6183f04d4 965 The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 966
Kovalev_D 23:12e6183f04d4 967 \param [in] IRQn Number of the interrupt for set pending
Kovalev_D 23:12e6183f04d4 968 */
Kovalev_D 23:12e6183f04d4 969 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 970 {
Kovalev_D 23:12e6183f04d4 971 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Kovalev_D 23:12e6183f04d4 972 }
Kovalev_D 23:12e6183f04d4 973
Kovalev_D 23:12e6183f04d4 974
Kovalev_D 23:12e6183f04d4 975 /** \brief Clear Pending Interrupt
Kovalev_D 23:12e6183f04d4 976
Kovalev_D 23:12e6183f04d4 977 This function clears the pending bit for the specified interrupt.
Kovalev_D 23:12e6183f04d4 978 The interrupt number cannot be a negative value.
Kovalev_D 23:12e6183f04d4 979
Kovalev_D 23:12e6183f04d4 980 \param [in] IRQn Number of the interrupt for clear pending
Kovalev_D 23:12e6183f04d4 981 */
Kovalev_D 23:12e6183f04d4 982 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 983 {
Kovalev_D 23:12e6183f04d4 984 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kovalev_D 23:12e6183f04d4 985 }
Kovalev_D 23:12e6183f04d4 986
Kovalev_D 23:12e6183f04d4 987
Kovalev_D 23:12e6183f04d4 988 /** \brief Get Active Interrupt
Kovalev_D 23:12e6183f04d4 989
Kovalev_D 23:12e6183f04d4 990 This function reads the active register in NVIC and returns the active bit.
Kovalev_D 23:12e6183f04d4 991 \param [in] IRQn Number of the interrupt for get active
Kovalev_D 23:12e6183f04d4 992 \return 0 Interrupt status is not active
Kovalev_D 23:12e6183f04d4 993 \return 1 Interrupt status is active
Kovalev_D 23:12e6183f04d4 994 */
Kovalev_D 23:12e6183f04d4 995 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 996 {
Kovalev_D 23:12e6183f04d4 997 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Kovalev_D 23:12e6183f04d4 998 }
Kovalev_D 23:12e6183f04d4 999
Kovalev_D 23:12e6183f04d4 1000
Kovalev_D 23:12e6183f04d4 1001 /** \brief Set Interrupt Priority
Kovalev_D 23:12e6183f04d4 1002
Kovalev_D 23:12e6183f04d4 1003 This function sets the priority for the specified interrupt. The interrupt
Kovalev_D 23:12e6183f04d4 1004 number can be positive to specify an external (device specific)
Kovalev_D 23:12e6183f04d4 1005 interrupt, or negative to specify an internal (core) interrupt.
Kovalev_D 23:12e6183f04d4 1006
Kovalev_D 23:12e6183f04d4 1007 Note: The priority cannot be set for every core interrupt.
Kovalev_D 23:12e6183f04d4 1008
Kovalev_D 23:12e6183f04d4 1009 \param [in] IRQn Number of the interrupt for set priority
Kovalev_D 23:12e6183f04d4 1010 \param [in] priority Priority to set
Kovalev_D 23:12e6183f04d4 1011 */
Kovalev_D 23:12e6183f04d4 1012 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kovalev_D 23:12e6183f04d4 1013 {
Kovalev_D 23:12e6183f04d4 1014 if(IRQn < 0) {
Kovalev_D 23:12e6183f04d4 1015 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Kovalev_D 23:12e6183f04d4 1016 else {
Kovalev_D 23:12e6183f04d4 1017 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Kovalev_D 23:12e6183f04d4 1018 }
Kovalev_D 23:12e6183f04d4 1019
Kovalev_D 23:12e6183f04d4 1020
Kovalev_D 23:12e6183f04d4 1021 /** \brief Get Interrupt Priority
Kovalev_D 23:12e6183f04d4 1022
Kovalev_D 23:12e6183f04d4 1023 This function reads the priority for the specified interrupt. The interrupt
Kovalev_D 23:12e6183f04d4 1024 number can be positive to specify an external (device specific)
Kovalev_D 23:12e6183f04d4 1025 interrupt, or negative to specify an internal (core) interrupt.
Kovalev_D 23:12e6183f04d4 1026
Kovalev_D 23:12e6183f04d4 1027 The returned priority value is automatically aligned to the implemented
Kovalev_D 23:12e6183f04d4 1028 priority bits of the microcontroller.
Kovalev_D 23:12e6183f04d4 1029
Kovalev_D 23:12e6183f04d4 1030 \param [in] IRQn Number of the interrupt for get priority
Kovalev_D 23:12e6183f04d4 1031 \return Interrupt Priority
Kovalev_D 23:12e6183f04d4 1032 */
Kovalev_D 23:12e6183f04d4 1033 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kovalev_D 23:12e6183f04d4 1034 {
Kovalev_D 23:12e6183f04d4 1035
Kovalev_D 23:12e6183f04d4 1036 if(IRQn < 0) {
Kovalev_D 23:12e6183f04d4 1037 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Kovalev_D 23:12e6183f04d4 1038 else {
Kovalev_D 23:12e6183f04d4 1039 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kovalev_D 23:12e6183f04d4 1040 }
Kovalev_D 23:12e6183f04d4 1041
Kovalev_D 23:12e6183f04d4 1042
Kovalev_D 23:12e6183f04d4 1043 /** \brief Encode Priority
Kovalev_D 23:12e6183f04d4 1044
Kovalev_D 23:12e6183f04d4 1045 This function encodes the priority for an interrupt with the given priority group,
Kovalev_D 23:12e6183f04d4 1046 preemptive priority value and sub priority value.
Kovalev_D 23:12e6183f04d4 1047 In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 1048 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kovalev_D 23:12e6183f04d4 1049
Kovalev_D 23:12e6183f04d4 1050 The returned priority value can be used for NVIC_SetPriority(...) function
Kovalev_D 23:12e6183f04d4 1051
Kovalev_D 23:12e6183f04d4 1052 \param [in] PriorityGroup Used priority group
Kovalev_D 23:12e6183f04d4 1053 \param [in] PreemptPriority Preemptive priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1054 \param [in] SubPriority Sub priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1055 \return Encoded priority for the interrupt
Kovalev_D 23:12e6183f04d4 1056 */
Kovalev_D 23:12e6183f04d4 1057 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kovalev_D 23:12e6183f04d4 1058 {
Kovalev_D 23:12e6183f04d4 1059 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 1060 uint32_t PreemptPriorityBits;
Kovalev_D 23:12e6183f04d4 1061 uint32_t SubPriorityBits;
Kovalev_D 23:12e6183f04d4 1062
Kovalev_D 23:12e6183f04d4 1063 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kovalev_D 23:12e6183f04d4 1064 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kovalev_D 23:12e6183f04d4 1065
Kovalev_D 23:12e6183f04d4 1066 return (
Kovalev_D 23:12e6183f04d4 1067 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
Kovalev_D 23:12e6183f04d4 1068 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Kovalev_D 23:12e6183f04d4 1069 );
Kovalev_D 23:12e6183f04d4 1070 }
Kovalev_D 23:12e6183f04d4 1071
Kovalev_D 23:12e6183f04d4 1072
Kovalev_D 23:12e6183f04d4 1073 /** \brief Decode Priority
Kovalev_D 23:12e6183f04d4 1074
Kovalev_D 23:12e6183f04d4 1075 This function decodes an interrupt priority value with the given priority group to
Kovalev_D 23:12e6183f04d4 1076 preemptive priority value and sub priority value.
Kovalev_D 23:12e6183f04d4 1077 In case of a conflict between priority grouping and available
Kovalev_D 23:12e6183f04d4 1078 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kovalev_D 23:12e6183f04d4 1079
Kovalev_D 23:12e6183f04d4 1080 The priority value can be retrieved with NVIC_GetPriority(...) function
Kovalev_D 23:12e6183f04d4 1081
Kovalev_D 23:12e6183f04d4 1082 \param [in] Priority Priority value
Kovalev_D 23:12e6183f04d4 1083 \param [in] PriorityGroup Used priority group
Kovalev_D 23:12e6183f04d4 1084 \param [out] pPreemptPriority Preemptive priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1085 \param [out] pSubPriority Sub priority value (starting from 0)
Kovalev_D 23:12e6183f04d4 1086 */
Kovalev_D 23:12e6183f04d4 1087 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kovalev_D 23:12e6183f04d4 1088 {
Kovalev_D 23:12e6183f04d4 1089 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kovalev_D 23:12e6183f04d4 1090 uint32_t PreemptPriorityBits;
Kovalev_D 23:12e6183f04d4 1091 uint32_t SubPriorityBits;
Kovalev_D 23:12e6183f04d4 1092
Kovalev_D 23:12e6183f04d4 1093 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kovalev_D 23:12e6183f04d4 1094 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kovalev_D 23:12e6183f04d4 1095
Kovalev_D 23:12e6183f04d4 1096 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Kovalev_D 23:12e6183f04d4 1097 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Kovalev_D 23:12e6183f04d4 1098 }
Kovalev_D 23:12e6183f04d4 1099
Kovalev_D 23:12e6183f04d4 1100
Kovalev_D 23:12e6183f04d4 1101 /** \brief System Reset
Kovalev_D 23:12e6183f04d4 1102
Kovalev_D 23:12e6183f04d4 1103 This function initiate a system reset request to reset the MCU.
Kovalev_D 23:12e6183f04d4 1104 */
Kovalev_D 23:12e6183f04d4 1105 static __INLINE void NVIC_SystemReset(void)
Kovalev_D 23:12e6183f04d4 1106 {
Kovalev_D 23:12e6183f04d4 1107 __DSB(); /* Ensure all outstanding memory accesses included
Kovalev_D 23:12e6183f04d4 1108 buffered write are completed before reset */
Kovalev_D 23:12e6183f04d4 1109 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kovalev_D 23:12e6183f04d4 1110 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kovalev_D 23:12e6183f04d4 1111 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Kovalev_D 23:12e6183f04d4 1112 __DSB(); /* Ensure completion of memory access */
Kovalev_D 23:12e6183f04d4 1113 while(1); /* wait until reset */
Kovalev_D 23:12e6183f04d4 1114 }
Kovalev_D 23:12e6183f04d4 1115
Kovalev_D 23:12e6183f04d4 1116 /*@} end of CMSIS_Core_NVICFunctions */
Kovalev_D 23:12e6183f04d4 1117
Kovalev_D 23:12e6183f04d4 1118
Kovalev_D 23:12e6183f04d4 1119
Kovalev_D 23:12e6183f04d4 1120 /* ################################## SysTick function ############################################ */
Kovalev_D 23:12e6183f04d4 1121 /** \ingroup CMSIS_Core_FunctionInterface
Kovalev_D 23:12e6183f04d4 1122 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
Kovalev_D 23:12e6183f04d4 1123 @{
Kovalev_D 23:12e6183f04d4 1124 */
Kovalev_D 23:12e6183f04d4 1125
Kovalev_D 23:12e6183f04d4 1126 #if (__Vendor_SysTickConfig == 0)
Kovalev_D 23:12e6183f04d4 1127
Kovalev_D 23:12e6183f04d4 1128 /** \brief System Tick Configuration
Kovalev_D 23:12e6183f04d4 1129
Kovalev_D 23:12e6183f04d4 1130 This function initialises the system tick timer and its interrupt and start the system tick timer.
Kovalev_D 23:12e6183f04d4 1131 Counter is in free running mode to generate periodical interrupts.
Kovalev_D 23:12e6183f04d4 1132
Kovalev_D 23:12e6183f04d4 1133 \param [in] ticks Number of ticks between two interrupts
Kovalev_D 23:12e6183f04d4 1134 \return 0 Function succeeded
Kovalev_D 23:12e6183f04d4 1135 \return 1 Function failed
Kovalev_D 23:12e6183f04d4 1136 */
Kovalev_D 23:12e6183f04d4 1137 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
Kovalev_D 23:12e6183f04d4 1138 {
Kovalev_D 23:12e6183f04d4 1139 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kovalev_D 23:12e6183f04d4 1140
Kovalev_D 23:12e6183f04d4 1141 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
Kovalev_D 23:12e6183f04d4 1142 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
Kovalev_D 23:12e6183f04d4 1143 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kovalev_D 23:12e6183f04d4 1144 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kovalev_D 23:12e6183f04d4 1145 SysTick_CTRL_TICKINT_Msk |
Kovalev_D 23:12e6183f04d4 1146 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kovalev_D 23:12e6183f04d4 1147 return (0); /* Function successful */
Kovalev_D 23:12e6183f04d4 1148 }
Kovalev_D 23:12e6183f04d4 1149
Kovalev_D 23:12e6183f04d4 1150 #endif
Kovalev_D 23:12e6183f04d4 1151
Kovalev_D 23:12e6183f04d4 1152 /*@} end of CMSIS_Core_SysTickFunctions */
Kovalev_D 23:12e6183f04d4 1153
Kovalev_D 23:12e6183f04d4 1154
Kovalev_D 23:12e6183f04d4 1155
Kovalev_D 23:12e6183f04d4 1156 /* ##################################### Debug In/Output function ########################################### */
Kovalev_D 23:12e6183f04d4 1157 /** \ingroup CMSIS_Core_FunctionInterface
Kovalev_D 23:12e6183f04d4 1158 \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
Kovalev_D 23:12e6183f04d4 1159 @{
Kovalev_D 23:12e6183f04d4 1160 */
Kovalev_D 23:12e6183f04d4 1161
Kovalev_D 23:12e6183f04d4 1162 extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
Kovalev_D 23:12e6183f04d4 1163 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
Kovalev_D 23:12e6183f04d4 1164
Kovalev_D 23:12e6183f04d4 1165
Kovalev_D 23:12e6183f04d4 1166 /** \brief ITM Send Character
Kovalev_D 23:12e6183f04d4 1167
Kovalev_D 23:12e6183f04d4 1168 This function transmits a character via the ITM channel 0.
Kovalev_D 23:12e6183f04d4 1169 It just returns when no debugger is connected that has booked the output.
Kovalev_D 23:12e6183f04d4 1170 It is blocking when a debugger is connected, but the previous character send is not transmitted.
Kovalev_D 23:12e6183f04d4 1171
Kovalev_D 23:12e6183f04d4 1172 \param [in] ch Character to transmit
Kovalev_D 23:12e6183f04d4 1173 \return Character to transmit
Kovalev_D 23:12e6183f04d4 1174 */
Kovalev_D 23:12e6183f04d4 1175 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
Kovalev_D 23:12e6183f04d4 1176 {
Kovalev_D 23:12e6183f04d4 1177 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
Kovalev_D 23:12e6183f04d4 1178 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Kovalev_D 23:12e6183f04d4 1179 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Kovalev_D 23:12e6183f04d4 1180 {
Kovalev_D 23:12e6183f04d4 1181 while (ITM->PORT[0].u32 == 0);
Kovalev_D 23:12e6183f04d4 1182 ITM->PORT[0].u8 = (uint8_t) ch;
Kovalev_D 23:12e6183f04d4 1183 }
Kovalev_D 23:12e6183f04d4 1184 return (ch);
Kovalev_D 23:12e6183f04d4 1185 }
Kovalev_D 23:12e6183f04d4 1186
Kovalev_D 23:12e6183f04d4 1187
Kovalev_D 23:12e6183f04d4 1188 /** \brief ITM Receive Character
Kovalev_D 23:12e6183f04d4 1189
Kovalev_D 23:12e6183f04d4 1190 This function inputs a character via external variable ITM_RxBuffer.
Kovalev_D 23:12e6183f04d4 1191 It just returns when no debugger is connected that has booked the output.
Kovalev_D 23:12e6183f04d4 1192 It is blocking when a debugger is connected, but the previous character send is not transmitted.
Kovalev_D 23:12e6183f04d4 1193
Kovalev_D 23:12e6183f04d4 1194 \return Received character
Kovalev_D 23:12e6183f04d4 1195 \return -1 No character received
Kovalev_D 23:12e6183f04d4 1196 */
Kovalev_D 23:12e6183f04d4 1197 static __INLINE int32_t ITM_ReceiveChar (void) {
Kovalev_D 23:12e6183f04d4 1198 int32_t ch = -1; /* no character available */
Kovalev_D 23:12e6183f04d4 1199
Kovalev_D 23:12e6183f04d4 1200 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kovalev_D 23:12e6183f04d4 1201 ch = ITM_RxBuffer;
Kovalev_D 23:12e6183f04d4 1202 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kovalev_D 23:12e6183f04d4 1203 }
Kovalev_D 23:12e6183f04d4 1204
Kovalev_D 23:12e6183f04d4 1205 return (ch);
Kovalev_D 23:12e6183f04d4 1206 }
Kovalev_D 23:12e6183f04d4 1207
Kovalev_D 23:12e6183f04d4 1208
Kovalev_D 23:12e6183f04d4 1209 /** \brief ITM Check Character
Kovalev_D 23:12e6183f04d4 1210
Kovalev_D 23:12e6183f04d4 1211 This function checks external variable ITM_RxBuffer whether a character is available or not.
Kovalev_D 23:12e6183f04d4 1212 It returns '1' if a character is available and '0' if no character is available.
Kovalev_D 23:12e6183f04d4 1213
Kovalev_D 23:12e6183f04d4 1214 \return 0 No character available
Kovalev_D 23:12e6183f04d4 1215 \return 1 Character available
Kovalev_D 23:12e6183f04d4 1216 */
Kovalev_D 23:12e6183f04d4 1217 static __INLINE int32_t ITM_CheckChar (void) {
Kovalev_D 23:12e6183f04d4 1218
Kovalev_D 23:12e6183f04d4 1219 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kovalev_D 23:12e6183f04d4 1220 return (0); /* no character available */
Kovalev_D 23:12e6183f04d4 1221 } else {
Kovalev_D 23:12e6183f04d4 1222 return (1); /* character available */
Kovalev_D 23:12e6183f04d4 1223 }
Kovalev_D 23:12e6183f04d4 1224 }
Kovalev_D 23:12e6183f04d4 1225
Kovalev_D 23:12e6183f04d4 1226 /*@} end of CMSIS_core_DebugFunctions */
Kovalev_D 23:12e6183f04d4 1227
Kovalev_D 23:12e6183f04d4 1228 #endif /* __CORE_CM3_H_DEPENDANT */
Kovalev_D 23:12e6183f04d4 1229
Kovalev_D 23:12e6183f04d4 1230 #endif /* __CMSIS_GENERIC */
Kovalev_D 23:12e6183f04d4 1231
Kovalev_D 23:12e6183f04d4 1232 #ifdef __cplusplus
Kovalev_D 23:12e6183f04d4 1233 }
Kovalev_D 23:12e6183f04d4 1234 #endif
Kovalev_D 23:12e6183f04d4 1235
Kovalev_D 23:12e6183f04d4 1236 /*lint -restore */