Dmitry Kovalev
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core_cmInstr.h@23:12e6183f04d4, 2016-02-03 (annotated)
- Committer:
- Kovalev_D
- Date:
- Wed Feb 03 10:44:42 2016 +0300
- Revision:
- 23:12e6183f04d4
- Parent:
- 1:f2adcae3d304
[thyz
Who changed what in which revision?
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igor_v | 0:8ad47e2b6f00 | 1 | /**************************************************************************//** |
igor_v | 0:8ad47e2b6f00 | 2 | * @file core_cmInstr.h |
igor_v | 0:8ad47e2b6f00 | 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File |
igor_v | 0:8ad47e2b6f00 | 4 | * @version V2.01 |
igor_v | 0:8ad47e2b6f00 | 5 | * @date 06. December 2010 |
igor_v | 0:8ad47e2b6f00 | 6 | * |
igor_v | 0:8ad47e2b6f00 | 7 | * @note |
igor_v | 0:8ad47e2b6f00 | 8 | * Copyright (C) 2009-2010 ARM Limited. All rights reserved. |
igor_v | 0:8ad47e2b6f00 | 9 | * |
igor_v | 0:8ad47e2b6f00 | 10 | * @par |
igor_v | 1:f2adcae3d304 | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
igor_v | 1:f2adcae3d304 | 12 | * processor based microcontrollers. This file can be freely distributed |
igor_v | 1:f2adcae3d304 | 13 | * within development tools that are supporting such ARM based processors. |
igor_v | 0:8ad47e2b6f00 | 14 | * |
igor_v | 0:8ad47e2b6f00 | 15 | * @par |
igor_v | 0:8ad47e2b6f00 | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
igor_v | 0:8ad47e2b6f00 | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
igor_v | 0:8ad47e2b6f00 | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
igor_v | 0:8ad47e2b6f00 | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
igor_v | 0:8ad47e2b6f00 | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
igor_v | 0:8ad47e2b6f00 | 21 | * |
igor_v | 0:8ad47e2b6f00 | 22 | ******************************************************************************/ |
igor_v | 0:8ad47e2b6f00 | 23 | |
igor_v | 0:8ad47e2b6f00 | 24 | #ifndef __CORE_CMINSTR_H__ |
igor_v | 0:8ad47e2b6f00 | 25 | #define __CORE_CMINSTR_H__ |
igor_v | 0:8ad47e2b6f00 | 26 | |
igor_v | 0:8ad47e2b6f00 | 27 | |
igor_v | 0:8ad47e2b6f00 | 28 | /* ########################## Core Instruction Access ######################### */ |
igor_v | 0:8ad47e2b6f00 | 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
igor_v | 0:8ad47e2b6f00 | 30 | Access to dedicated instructions |
igor_v | 0:8ad47e2b6f00 | 31 | @{ |
igor_v | 0:8ad47e2b6f00 | 32 | */ |
igor_v | 0:8ad47e2b6f00 | 33 | |
igor_v | 0:8ad47e2b6f00 | 34 | #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ |
igor_v | 0:8ad47e2b6f00 | 35 | /* ARM armcc specific functions */ |
igor_v | 0:8ad47e2b6f00 | 36 | |
igor_v | 0:8ad47e2b6f00 | 37 | /** \brief No Operation |
igor_v | 0:8ad47e2b6f00 | 38 | |
igor_v | 0:8ad47e2b6f00 | 39 | No Operation does nothing. This instruction can be used for code alignment purposes. |
igor_v | 0:8ad47e2b6f00 | 40 | */ |
igor_v | 0:8ad47e2b6f00 | 41 | #define __NOP __nop |
igor_v | 0:8ad47e2b6f00 | 42 | |
igor_v | 0:8ad47e2b6f00 | 43 | |
igor_v | 0:8ad47e2b6f00 | 44 | /** \brief Wait For Interrupt |
igor_v | 0:8ad47e2b6f00 | 45 | |
igor_v | 0:8ad47e2b6f00 | 46 | Wait For Interrupt is a hint instruction that suspends execution |
igor_v | 0:8ad47e2b6f00 | 47 | until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 48 | */ |
igor_v | 0:8ad47e2b6f00 | 49 | #define __WFI __wfi |
igor_v | 0:8ad47e2b6f00 | 50 | |
igor_v | 0:8ad47e2b6f00 | 51 | |
igor_v | 0:8ad47e2b6f00 | 52 | /** \brief Wait For Event |
igor_v | 0:8ad47e2b6f00 | 53 | |
igor_v | 0:8ad47e2b6f00 | 54 | Wait For Event is a hint instruction that permits the processor to enter |
igor_v | 0:8ad47e2b6f00 | 55 | a low-power state until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 56 | */ |
igor_v | 0:8ad47e2b6f00 | 57 | #define __WFE __wfe |
igor_v | 0:8ad47e2b6f00 | 58 | |
igor_v | 0:8ad47e2b6f00 | 59 | |
igor_v | 0:8ad47e2b6f00 | 60 | /** \brief Send Event |
igor_v | 0:8ad47e2b6f00 | 61 | |
igor_v | 0:8ad47e2b6f00 | 62 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
igor_v | 0:8ad47e2b6f00 | 63 | */ |
igor_v | 0:8ad47e2b6f00 | 64 | #define __SEV __sev |
igor_v | 0:8ad47e2b6f00 | 65 | |
igor_v | 0:8ad47e2b6f00 | 66 | |
igor_v | 0:8ad47e2b6f00 | 67 | /** \brief Instruction Synchronization Barrier |
igor_v | 0:8ad47e2b6f00 | 68 | |
igor_v | 1:f2adcae3d304 | 69 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
igor_v | 1:f2adcae3d304 | 70 | so that all instructions following the ISB are fetched from cache or |
igor_v | 0:8ad47e2b6f00 | 71 | memory, after the instruction has been completed. |
igor_v | 0:8ad47e2b6f00 | 72 | */ |
igor_v | 0:8ad47e2b6f00 | 73 | #define __ISB() __isb(0xF) |
igor_v | 0:8ad47e2b6f00 | 74 | |
igor_v | 0:8ad47e2b6f00 | 75 | |
igor_v | 0:8ad47e2b6f00 | 76 | /** \brief Data Synchronization Barrier |
igor_v | 0:8ad47e2b6f00 | 77 | |
igor_v | 1:f2adcae3d304 | 78 | This function acts as a special kind of Data Memory Barrier. |
igor_v | 0:8ad47e2b6f00 | 79 | It completes when all explicit memory accesses before this instruction complete. |
igor_v | 0:8ad47e2b6f00 | 80 | */ |
igor_v | 0:8ad47e2b6f00 | 81 | #define __DSB() __dsb(0xF) |
igor_v | 0:8ad47e2b6f00 | 82 | |
igor_v | 0:8ad47e2b6f00 | 83 | |
igor_v | 0:8ad47e2b6f00 | 84 | /** \brief Data Memory Barrier |
igor_v | 0:8ad47e2b6f00 | 85 | |
igor_v | 1:f2adcae3d304 | 86 | This function ensures the apparent order of the explicit memory operations before |
igor_v | 0:8ad47e2b6f00 | 87 | and after the instruction, without ensuring their completion. |
igor_v | 0:8ad47e2b6f00 | 88 | */ |
igor_v | 0:8ad47e2b6f00 | 89 | #define __DMB() __dmb(0xF) |
igor_v | 0:8ad47e2b6f00 | 90 | |
igor_v | 0:8ad47e2b6f00 | 91 | |
igor_v | 0:8ad47e2b6f00 | 92 | /** \brief Reverse byte order (32 bit) |
igor_v | 0:8ad47e2b6f00 | 93 | |
igor_v | 0:8ad47e2b6f00 | 94 | This function reverses the byte order in integer value. |
igor_v | 0:8ad47e2b6f00 | 95 | |
igor_v | 0:8ad47e2b6f00 | 96 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 97 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 98 | */ |
igor_v | 0:8ad47e2b6f00 | 99 | #define __REV __rev |
igor_v | 0:8ad47e2b6f00 | 100 | |
igor_v | 0:8ad47e2b6f00 | 101 | |
igor_v | 0:8ad47e2b6f00 | 102 | /** \brief Reverse byte order (16 bit) |
igor_v | 0:8ad47e2b6f00 | 103 | |
igor_v | 0:8ad47e2b6f00 | 104 | This function reverses the byte order in two unsigned short values. |
igor_v | 0:8ad47e2b6f00 | 105 | |
igor_v | 0:8ad47e2b6f00 | 106 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 107 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 108 | */ |
igor_v | 0:8ad47e2b6f00 | 109 | #if (__ARMCC_VERSION < 400677) |
igor_v | 0:8ad47e2b6f00 | 110 | extern uint32_t __REV16(uint32_t value); |
igor_v | 0:8ad47e2b6f00 | 111 | #else /* (__ARMCC_VERSION >= 400677) */ |
igor_v | 0:8ad47e2b6f00 | 112 | static __INLINE __ASM uint32_t __REV16(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 113 | { |
igor_v | 1:f2adcae3d304 | 114 | rev16 r0, r0 |
igor_v | 1:f2adcae3d304 | 115 | bx lr |
igor_v | 0:8ad47e2b6f00 | 116 | } |
igor_v | 1:f2adcae3d304 | 117 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 118 | |
igor_v | 0:8ad47e2b6f00 | 119 | |
igor_v | 0:8ad47e2b6f00 | 120 | /** \brief Reverse byte order in signed short value |
igor_v | 0:8ad47e2b6f00 | 121 | |
igor_v | 0:8ad47e2b6f00 | 122 | This function reverses the byte order in a signed short value with sign extension to integer. |
igor_v | 0:8ad47e2b6f00 | 123 | |
igor_v | 0:8ad47e2b6f00 | 124 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 125 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 126 | */ |
igor_v | 0:8ad47e2b6f00 | 127 | #if (__ARMCC_VERSION < 400677) |
igor_v | 0:8ad47e2b6f00 | 128 | extern int32_t __REVSH(int32_t value); |
igor_v | 0:8ad47e2b6f00 | 129 | #else /* (__ARMCC_VERSION >= 400677) */ |
igor_v | 0:8ad47e2b6f00 | 130 | static __INLINE __ASM int32_t __REVSH(int32_t value) |
igor_v | 0:8ad47e2b6f00 | 131 | { |
igor_v | 1:f2adcae3d304 | 132 | revsh r0, r0 |
igor_v | 1:f2adcae3d304 | 133 | bx lr |
igor_v | 0:8ad47e2b6f00 | 134 | } |
igor_v | 1:f2adcae3d304 | 135 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 136 | |
igor_v | 0:8ad47e2b6f00 | 137 | |
igor_v | 0:8ad47e2b6f00 | 138 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 139 | |
igor_v | 0:8ad47e2b6f00 | 140 | /** \brief Reverse bit order of value |
igor_v | 0:8ad47e2b6f00 | 141 | |
igor_v | 0:8ad47e2b6f00 | 142 | This function reverses the bit order of the given value. |
igor_v | 0:8ad47e2b6f00 | 143 | |
igor_v | 0:8ad47e2b6f00 | 144 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 145 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 146 | */ |
igor_v | 0:8ad47e2b6f00 | 147 | #define __RBIT __rbit |
igor_v | 0:8ad47e2b6f00 | 148 | |
igor_v | 0:8ad47e2b6f00 | 149 | |
igor_v | 0:8ad47e2b6f00 | 150 | /** \brief LDR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 151 | |
igor_v | 0:8ad47e2b6f00 | 152 | This function performs a exclusive LDR command for 8 bit value. |
igor_v | 0:8ad47e2b6f00 | 153 | |
igor_v | 0:8ad47e2b6f00 | 154 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 155 | \return value of type uint8_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 156 | */ |
igor_v | 0:8ad47e2b6f00 | 157 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
igor_v | 0:8ad47e2b6f00 | 158 | |
igor_v | 0:8ad47e2b6f00 | 159 | |
igor_v | 0:8ad47e2b6f00 | 160 | /** \brief LDR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 161 | |
igor_v | 0:8ad47e2b6f00 | 162 | This function performs a exclusive LDR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 163 | |
igor_v | 0:8ad47e2b6f00 | 164 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 165 | \return value of type uint16_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 166 | */ |
igor_v | 0:8ad47e2b6f00 | 167 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
igor_v | 0:8ad47e2b6f00 | 168 | |
igor_v | 0:8ad47e2b6f00 | 169 | |
igor_v | 0:8ad47e2b6f00 | 170 | /** \brief LDR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 171 | |
igor_v | 0:8ad47e2b6f00 | 172 | This function performs a exclusive LDR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 173 | |
igor_v | 0:8ad47e2b6f00 | 174 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 175 | \return value of type uint32_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 176 | */ |
igor_v | 0:8ad47e2b6f00 | 177 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
igor_v | 0:8ad47e2b6f00 | 178 | |
igor_v | 0:8ad47e2b6f00 | 179 | |
igor_v | 0:8ad47e2b6f00 | 180 | /** \brief STR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 181 | |
igor_v | 0:8ad47e2b6f00 | 182 | This function performs a exclusive STR command for 8 bit values. |
igor_v | 0:8ad47e2b6f00 | 183 | |
igor_v | 0:8ad47e2b6f00 | 184 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 185 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 186 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 187 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 188 | */ |
igor_v | 0:8ad47e2b6f00 | 189 | #define __STREXB(value, ptr) __strex(value, ptr) |
igor_v | 0:8ad47e2b6f00 | 190 | |
igor_v | 0:8ad47e2b6f00 | 191 | |
igor_v | 0:8ad47e2b6f00 | 192 | /** \brief STR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 193 | |
igor_v | 0:8ad47e2b6f00 | 194 | This function performs a exclusive STR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 195 | |
igor_v | 0:8ad47e2b6f00 | 196 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 197 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 198 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 199 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 200 | */ |
igor_v | 0:8ad47e2b6f00 | 201 | #define __STREXH(value, ptr) __strex(value, ptr) |
igor_v | 0:8ad47e2b6f00 | 202 | |
igor_v | 0:8ad47e2b6f00 | 203 | |
igor_v | 0:8ad47e2b6f00 | 204 | /** \brief STR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 205 | |
igor_v | 0:8ad47e2b6f00 | 206 | This function performs a exclusive STR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 207 | |
igor_v | 0:8ad47e2b6f00 | 208 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 209 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 210 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 211 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 212 | */ |
igor_v | 0:8ad47e2b6f00 | 213 | #define __STREXW(value, ptr) __strex(value, ptr) |
igor_v | 0:8ad47e2b6f00 | 214 | |
igor_v | 0:8ad47e2b6f00 | 215 | |
igor_v | 0:8ad47e2b6f00 | 216 | /** \brief Remove the exclusive lock |
igor_v | 0:8ad47e2b6f00 | 217 | |
igor_v | 0:8ad47e2b6f00 | 218 | This function removes the exclusive lock which is created by LDREX. |
igor_v | 0:8ad47e2b6f00 | 219 | |
igor_v | 0:8ad47e2b6f00 | 220 | */ |
igor_v | 0:8ad47e2b6f00 | 221 | #if (__ARMCC_VERSION < 400000) |
igor_v | 0:8ad47e2b6f00 | 222 | extern void __CLREX(void); |
igor_v | 0:8ad47e2b6f00 | 223 | #else /* (__ARMCC_VERSION >= 400000) */ |
igor_v | 0:8ad47e2b6f00 | 224 | #define __CLREX __clrex |
igor_v | 1:f2adcae3d304 | 225 | #endif /* __ARMCC_VERSION */ |
igor_v | 0:8ad47e2b6f00 | 226 | |
igor_v | 0:8ad47e2b6f00 | 227 | |
igor_v | 0:8ad47e2b6f00 | 228 | /** \brief Signed Saturate |
igor_v | 0:8ad47e2b6f00 | 229 | |
igor_v | 0:8ad47e2b6f00 | 230 | This function saturates a signed value. |
igor_v | 0:8ad47e2b6f00 | 231 | |
igor_v | 0:8ad47e2b6f00 | 232 | \param [in] value Value to be saturated |
igor_v | 0:8ad47e2b6f00 | 233 | \param [in] sat Bit position to saturate to (1..32) |
igor_v | 0:8ad47e2b6f00 | 234 | \return Saturated value |
igor_v | 0:8ad47e2b6f00 | 235 | */ |
igor_v | 0:8ad47e2b6f00 | 236 | #define __SSAT __ssat |
igor_v | 0:8ad47e2b6f00 | 237 | |
igor_v | 0:8ad47e2b6f00 | 238 | |
igor_v | 0:8ad47e2b6f00 | 239 | /** \brief Unsigned Saturate |
igor_v | 0:8ad47e2b6f00 | 240 | |
igor_v | 0:8ad47e2b6f00 | 241 | This function saturates an unsigned value. |
igor_v | 0:8ad47e2b6f00 | 242 | |
igor_v | 0:8ad47e2b6f00 | 243 | \param [in] value Value to be saturated |
igor_v | 0:8ad47e2b6f00 | 244 | \param [in] sat Bit position to saturate to (0..31) |
igor_v | 0:8ad47e2b6f00 | 245 | \return Saturated value |
igor_v | 0:8ad47e2b6f00 | 246 | */ |
igor_v | 0:8ad47e2b6f00 | 247 | #define __USAT __usat |
igor_v | 0:8ad47e2b6f00 | 248 | |
igor_v | 0:8ad47e2b6f00 | 249 | |
igor_v | 0:8ad47e2b6f00 | 250 | /** \brief Count leading zeros |
igor_v | 0:8ad47e2b6f00 | 251 | |
igor_v | 0:8ad47e2b6f00 | 252 | This function counts the number of leading zeros of a data value. |
igor_v | 0:8ad47e2b6f00 | 253 | |
igor_v | 0:8ad47e2b6f00 | 254 | \param [in] value Value to count the leading zeros |
igor_v | 0:8ad47e2b6f00 | 255 | \return number of leading zeros in value |
igor_v | 0:8ad47e2b6f00 | 256 | */ |
igor_v | 1:f2adcae3d304 | 257 | #define __CLZ __clz |
igor_v | 0:8ad47e2b6f00 | 258 | |
igor_v | 0:8ad47e2b6f00 | 259 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 260 | |
igor_v | 0:8ad47e2b6f00 | 261 | |
igor_v | 0:8ad47e2b6f00 | 262 | |
igor_v | 0:8ad47e2b6f00 | 263 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
igor_v | 0:8ad47e2b6f00 | 264 | /* IAR iccarm specific functions */ |
igor_v | 0:8ad47e2b6f00 | 265 | |
igor_v | 0:8ad47e2b6f00 | 266 | #include <intrinsics.h> /* IAR Intrinsics */ |
igor_v | 0:8ad47e2b6f00 | 267 | |
igor_v | 0:8ad47e2b6f00 | 268 | #pragma diag_suppress=Pe940 |
igor_v | 0:8ad47e2b6f00 | 269 | |
igor_v | 0:8ad47e2b6f00 | 270 | /** \brief No Operation |
igor_v | 0:8ad47e2b6f00 | 271 | |
igor_v | 0:8ad47e2b6f00 | 272 | No Operation does nothing. This instruction can be used for code alignment purposes. |
igor_v | 0:8ad47e2b6f00 | 273 | */ |
igor_v | 0:8ad47e2b6f00 | 274 | #define __NOP __no_operation |
igor_v | 0:8ad47e2b6f00 | 275 | |
igor_v | 0:8ad47e2b6f00 | 276 | |
igor_v | 0:8ad47e2b6f00 | 277 | /** \brief Wait For Interrupt |
igor_v | 0:8ad47e2b6f00 | 278 | |
igor_v | 0:8ad47e2b6f00 | 279 | Wait For Interrupt is a hint instruction that suspends execution |
igor_v | 0:8ad47e2b6f00 | 280 | until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 281 | */ |
igor_v | 0:8ad47e2b6f00 | 282 | static __INLINE void __WFI(void) |
igor_v | 0:8ad47e2b6f00 | 283 | { |
igor_v | 1:f2adcae3d304 | 284 | __ASM ("wfi"); |
igor_v | 0:8ad47e2b6f00 | 285 | } |
igor_v | 0:8ad47e2b6f00 | 286 | |
igor_v | 0:8ad47e2b6f00 | 287 | |
igor_v | 0:8ad47e2b6f00 | 288 | /** \brief Wait For Event |
igor_v | 0:8ad47e2b6f00 | 289 | |
igor_v | 0:8ad47e2b6f00 | 290 | Wait For Event is a hint instruction that permits the processor to enter |
igor_v | 0:8ad47e2b6f00 | 291 | a low-power state until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 292 | */ |
igor_v | 0:8ad47e2b6f00 | 293 | static __INLINE void __WFE(void) |
igor_v | 0:8ad47e2b6f00 | 294 | { |
igor_v | 1:f2adcae3d304 | 295 | __ASM ("wfe"); |
igor_v | 0:8ad47e2b6f00 | 296 | } |
igor_v | 0:8ad47e2b6f00 | 297 | |
igor_v | 0:8ad47e2b6f00 | 298 | |
igor_v | 0:8ad47e2b6f00 | 299 | /** \brief Send Event |
igor_v | 0:8ad47e2b6f00 | 300 | |
igor_v | 0:8ad47e2b6f00 | 301 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
igor_v | 0:8ad47e2b6f00 | 302 | */ |
igor_v | 0:8ad47e2b6f00 | 303 | static __INLINE void __SEV(void) |
igor_v | 0:8ad47e2b6f00 | 304 | { |
igor_v | 1:f2adcae3d304 | 305 | __ASM ("sev"); |
igor_v | 0:8ad47e2b6f00 | 306 | } |
igor_v | 0:8ad47e2b6f00 | 307 | |
igor_v | 0:8ad47e2b6f00 | 308 | |
igor_v | 0:8ad47e2b6f00 | 309 | /* intrinsic void __ISB(void) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 310 | /* intrinsic void __DSB(void) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 311 | /* intrinsic void __DMB(void) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 312 | /* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 313 | /* intrinsic __SSAT (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 314 | /* intrinsic __USAT (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 315 | |
igor_v | 0:8ad47e2b6f00 | 316 | |
igor_v | 0:8ad47e2b6f00 | 317 | /** \brief Reverse byte order (16 bit) |
igor_v | 0:8ad47e2b6f00 | 318 | |
igor_v | 0:8ad47e2b6f00 | 319 | This function reverses the byte order in two unsigned short values. |
igor_v | 0:8ad47e2b6f00 | 320 | |
igor_v | 0:8ad47e2b6f00 | 321 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 322 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 323 | */ |
igor_v | 0:8ad47e2b6f00 | 324 | static uint32_t __REV16(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 325 | { |
igor_v | 1:f2adcae3d304 | 326 | __ASM("rev16 r0, r0"); |
igor_v | 0:8ad47e2b6f00 | 327 | } |
igor_v | 0:8ad47e2b6f00 | 328 | |
igor_v | 0:8ad47e2b6f00 | 329 | |
igor_v | 0:8ad47e2b6f00 | 330 | /* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ |
igor_v | 0:8ad47e2b6f00 | 331 | |
igor_v | 0:8ad47e2b6f00 | 332 | |
igor_v | 0:8ad47e2b6f00 | 333 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 334 | |
igor_v | 0:8ad47e2b6f00 | 335 | /** \brief Reverse bit order of value |
igor_v | 0:8ad47e2b6f00 | 336 | |
igor_v | 0:8ad47e2b6f00 | 337 | This function reverses the bit order of the given value. |
igor_v | 0:8ad47e2b6f00 | 338 | |
igor_v | 0:8ad47e2b6f00 | 339 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 340 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 341 | */ |
igor_v | 0:8ad47e2b6f00 | 342 | static uint32_t __RBIT(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 343 | { |
igor_v | 1:f2adcae3d304 | 344 | __ASM("rbit r0, r0"); |
igor_v | 0:8ad47e2b6f00 | 345 | } |
igor_v | 0:8ad47e2b6f00 | 346 | |
igor_v | 0:8ad47e2b6f00 | 347 | |
igor_v | 0:8ad47e2b6f00 | 348 | /** \brief LDR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 349 | |
igor_v | 0:8ad47e2b6f00 | 350 | This function performs a exclusive LDR command for 8 bit value. |
igor_v | 0:8ad47e2b6f00 | 351 | |
igor_v | 0:8ad47e2b6f00 | 352 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 353 | \return value of type uint8_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 354 | */ |
igor_v | 0:8ad47e2b6f00 | 355 | static uint8_t __LDREXB(volatile uint8_t *addr) |
igor_v | 0:8ad47e2b6f00 | 356 | { |
igor_v | 1:f2adcae3d304 | 357 | __ASM("ldrexb r0, [r0]"); |
igor_v | 0:8ad47e2b6f00 | 358 | } |
igor_v | 0:8ad47e2b6f00 | 359 | |
igor_v | 0:8ad47e2b6f00 | 360 | |
igor_v | 0:8ad47e2b6f00 | 361 | /** \brief LDR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 362 | |
igor_v | 0:8ad47e2b6f00 | 363 | This function performs a exclusive LDR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 364 | |
igor_v | 0:8ad47e2b6f00 | 365 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 366 | \return value of type uint16_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 367 | */ |
igor_v | 0:8ad47e2b6f00 | 368 | static uint16_t __LDREXH(volatile uint16_t *addr) |
igor_v | 0:8ad47e2b6f00 | 369 | { |
igor_v | 1:f2adcae3d304 | 370 | __ASM("ldrexh r0, [r0]"); |
igor_v | 0:8ad47e2b6f00 | 371 | } |
igor_v | 0:8ad47e2b6f00 | 372 | |
igor_v | 0:8ad47e2b6f00 | 373 | |
igor_v | 0:8ad47e2b6f00 | 374 | /** \brief LDR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 375 | |
igor_v | 0:8ad47e2b6f00 | 376 | This function performs a exclusive LDR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 377 | |
igor_v | 0:8ad47e2b6f00 | 378 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 379 | \return value of type uint32_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 380 | */ |
igor_v | 0:8ad47e2b6f00 | 381 | /* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 382 | static uint32_t __LDREXW(volatile uint32_t *addr) |
igor_v | 0:8ad47e2b6f00 | 383 | { |
igor_v | 1:f2adcae3d304 | 384 | __ASM("ldrex r0, [r0]"); |
igor_v | 0:8ad47e2b6f00 | 385 | } |
igor_v | 0:8ad47e2b6f00 | 386 | |
igor_v | 0:8ad47e2b6f00 | 387 | |
igor_v | 0:8ad47e2b6f00 | 388 | /** \brief STR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 389 | |
igor_v | 0:8ad47e2b6f00 | 390 | This function performs a exclusive STR command for 8 bit values. |
igor_v | 0:8ad47e2b6f00 | 391 | |
igor_v | 0:8ad47e2b6f00 | 392 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 393 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 394 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 395 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 396 | */ |
igor_v | 0:8ad47e2b6f00 | 397 | static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
igor_v | 0:8ad47e2b6f00 | 398 | { |
igor_v | 1:f2adcae3d304 | 399 | __ASM("strexb r0, r0, [r1]"); |
igor_v | 0:8ad47e2b6f00 | 400 | } |
igor_v | 0:8ad47e2b6f00 | 401 | |
igor_v | 0:8ad47e2b6f00 | 402 | |
igor_v | 0:8ad47e2b6f00 | 403 | /** \brief STR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 404 | |
igor_v | 0:8ad47e2b6f00 | 405 | This function performs a exclusive STR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 406 | |
igor_v | 0:8ad47e2b6f00 | 407 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 408 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 409 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 410 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 411 | */ |
igor_v | 0:8ad47e2b6f00 | 412 | static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
igor_v | 0:8ad47e2b6f00 | 413 | { |
igor_v | 1:f2adcae3d304 | 414 | __ASM("strexh r0, r0, [r1]"); |
igor_v | 0:8ad47e2b6f00 | 415 | } |
igor_v | 0:8ad47e2b6f00 | 416 | |
igor_v | 0:8ad47e2b6f00 | 417 | |
igor_v | 0:8ad47e2b6f00 | 418 | /** \brief STR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 419 | |
igor_v | 0:8ad47e2b6f00 | 420 | This function performs a exclusive STR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 421 | |
igor_v | 0:8ad47e2b6f00 | 422 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 423 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 424 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 425 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 426 | */ |
igor_v | 0:8ad47e2b6f00 | 427 | /* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/ |
igor_v | 0:8ad47e2b6f00 | 428 | static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
igor_v | 0:8ad47e2b6f00 | 429 | { |
igor_v | 1:f2adcae3d304 | 430 | __ASM("strex r0, r0, [r1]"); |
igor_v | 0:8ad47e2b6f00 | 431 | } |
igor_v | 0:8ad47e2b6f00 | 432 | |
igor_v | 0:8ad47e2b6f00 | 433 | |
igor_v | 0:8ad47e2b6f00 | 434 | /** \brief Remove the exclusive lock |
igor_v | 0:8ad47e2b6f00 | 435 | |
igor_v | 0:8ad47e2b6f00 | 436 | This function removes the exclusive lock which is created by LDREX. |
igor_v | 0:8ad47e2b6f00 | 437 | |
igor_v | 0:8ad47e2b6f00 | 438 | */ |
igor_v | 0:8ad47e2b6f00 | 439 | static __INLINE void __CLREX(void) |
igor_v | 0:8ad47e2b6f00 | 440 | { |
igor_v | 1:f2adcae3d304 | 441 | __ASM ("clrex"); |
igor_v | 0:8ad47e2b6f00 | 442 | } |
igor_v | 0:8ad47e2b6f00 | 443 | |
igor_v | 0:8ad47e2b6f00 | 444 | /* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */ |
igor_v | 0:8ad47e2b6f00 | 445 | |
igor_v | 0:8ad47e2b6f00 | 446 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 447 | |
igor_v | 0:8ad47e2b6f00 | 448 | #pragma diag_default=Pe940 |
igor_v | 0:8ad47e2b6f00 | 449 | |
igor_v | 0:8ad47e2b6f00 | 450 | |
igor_v | 0:8ad47e2b6f00 | 451 | |
igor_v | 0:8ad47e2b6f00 | 452 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
igor_v | 0:8ad47e2b6f00 | 453 | /* GNU gcc specific functions */ |
igor_v | 0:8ad47e2b6f00 | 454 | |
igor_v | 0:8ad47e2b6f00 | 455 | /** \brief No Operation |
igor_v | 0:8ad47e2b6f00 | 456 | |
igor_v | 0:8ad47e2b6f00 | 457 | No Operation does nothing. This instruction can be used for code alignment purposes. |
igor_v | 0:8ad47e2b6f00 | 458 | */ |
igor_v | 0:8ad47e2b6f00 | 459 | __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) |
igor_v | 0:8ad47e2b6f00 | 460 | { |
igor_v | 1:f2adcae3d304 | 461 | __ASM volatile ("nop"); |
igor_v | 0:8ad47e2b6f00 | 462 | } |
igor_v | 0:8ad47e2b6f00 | 463 | |
igor_v | 0:8ad47e2b6f00 | 464 | |
igor_v | 0:8ad47e2b6f00 | 465 | /** \brief Wait For Interrupt |
igor_v | 0:8ad47e2b6f00 | 466 | |
igor_v | 0:8ad47e2b6f00 | 467 | Wait For Interrupt is a hint instruction that suspends execution |
igor_v | 0:8ad47e2b6f00 | 468 | until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 469 | */ |
igor_v | 0:8ad47e2b6f00 | 470 | __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) |
igor_v | 0:8ad47e2b6f00 | 471 | { |
igor_v | 1:f2adcae3d304 | 472 | __ASM volatile ("wfi"); |
igor_v | 0:8ad47e2b6f00 | 473 | } |
igor_v | 0:8ad47e2b6f00 | 474 | |
igor_v | 0:8ad47e2b6f00 | 475 | |
igor_v | 0:8ad47e2b6f00 | 476 | /** \brief Wait For Event |
igor_v | 0:8ad47e2b6f00 | 477 | |
igor_v | 0:8ad47e2b6f00 | 478 | Wait For Event is a hint instruction that permits the processor to enter |
igor_v | 0:8ad47e2b6f00 | 479 | a low-power state until one of a number of events occurs. |
igor_v | 0:8ad47e2b6f00 | 480 | */ |
igor_v | 0:8ad47e2b6f00 | 481 | __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) |
igor_v | 0:8ad47e2b6f00 | 482 | { |
igor_v | 1:f2adcae3d304 | 483 | __ASM volatile ("wfe"); |
igor_v | 0:8ad47e2b6f00 | 484 | } |
igor_v | 0:8ad47e2b6f00 | 485 | |
igor_v | 0:8ad47e2b6f00 | 486 | |
igor_v | 0:8ad47e2b6f00 | 487 | /** \brief Send Event |
igor_v | 0:8ad47e2b6f00 | 488 | |
igor_v | 0:8ad47e2b6f00 | 489 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
igor_v | 0:8ad47e2b6f00 | 490 | */ |
igor_v | 0:8ad47e2b6f00 | 491 | __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) |
igor_v | 0:8ad47e2b6f00 | 492 | { |
igor_v | 1:f2adcae3d304 | 493 | __ASM volatile ("sev"); |
igor_v | 0:8ad47e2b6f00 | 494 | } |
igor_v | 0:8ad47e2b6f00 | 495 | |
igor_v | 0:8ad47e2b6f00 | 496 | |
igor_v | 0:8ad47e2b6f00 | 497 | /** \brief Instruction Synchronization Barrier |
igor_v | 0:8ad47e2b6f00 | 498 | |
igor_v | 1:f2adcae3d304 | 499 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
igor_v | 1:f2adcae3d304 | 500 | so that all instructions following the ISB are fetched from cache or |
igor_v | 0:8ad47e2b6f00 | 501 | memory, after the instruction has been completed. |
igor_v | 0:8ad47e2b6f00 | 502 | */ |
igor_v | 0:8ad47e2b6f00 | 503 | __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) |
igor_v | 0:8ad47e2b6f00 | 504 | { |
igor_v | 1:f2adcae3d304 | 505 | __ASM volatile ("isb"); |
igor_v | 0:8ad47e2b6f00 | 506 | } |
igor_v | 0:8ad47e2b6f00 | 507 | |
igor_v | 0:8ad47e2b6f00 | 508 | |
igor_v | 0:8ad47e2b6f00 | 509 | /** \brief Data Synchronization Barrier |
igor_v | 0:8ad47e2b6f00 | 510 | |
igor_v | 1:f2adcae3d304 | 511 | This function acts as a special kind of Data Memory Barrier. |
igor_v | 0:8ad47e2b6f00 | 512 | It completes when all explicit memory accesses before this instruction complete. |
igor_v | 0:8ad47e2b6f00 | 513 | */ |
igor_v | 0:8ad47e2b6f00 | 514 | __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) |
igor_v | 0:8ad47e2b6f00 | 515 | { |
igor_v | 1:f2adcae3d304 | 516 | __ASM volatile ("dsb"); |
igor_v | 0:8ad47e2b6f00 | 517 | } |
igor_v | 0:8ad47e2b6f00 | 518 | |
igor_v | 0:8ad47e2b6f00 | 519 | |
igor_v | 0:8ad47e2b6f00 | 520 | /** \brief Data Memory Barrier |
igor_v | 0:8ad47e2b6f00 | 521 | |
igor_v | 1:f2adcae3d304 | 522 | This function ensures the apparent order of the explicit memory operations before |
igor_v | 0:8ad47e2b6f00 | 523 | and after the instruction, without ensuring their completion. |
igor_v | 0:8ad47e2b6f00 | 524 | */ |
igor_v | 0:8ad47e2b6f00 | 525 | __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) |
igor_v | 0:8ad47e2b6f00 | 526 | { |
igor_v | 1:f2adcae3d304 | 527 | __ASM volatile ("dmb"); |
igor_v | 0:8ad47e2b6f00 | 528 | } |
igor_v | 0:8ad47e2b6f00 | 529 | |
igor_v | 0:8ad47e2b6f00 | 530 | |
igor_v | 0:8ad47e2b6f00 | 531 | /** \brief Reverse byte order (32 bit) |
igor_v | 0:8ad47e2b6f00 | 532 | |
igor_v | 0:8ad47e2b6f00 | 533 | This function reverses the byte order in integer value. |
igor_v | 0:8ad47e2b6f00 | 534 | |
igor_v | 0:8ad47e2b6f00 | 535 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 536 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 537 | */ |
igor_v | 0:8ad47e2b6f00 | 538 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 539 | { |
igor_v | 1:f2adcae3d304 | 540 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 541 | |
igor_v | 1:f2adcae3d304 | 542 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 1:f2adcae3d304 | 543 | return(result); |
igor_v | 0:8ad47e2b6f00 | 544 | } |
igor_v | 0:8ad47e2b6f00 | 545 | |
igor_v | 0:8ad47e2b6f00 | 546 | |
igor_v | 0:8ad47e2b6f00 | 547 | /** \brief Reverse byte order (16 bit) |
igor_v | 0:8ad47e2b6f00 | 548 | |
igor_v | 0:8ad47e2b6f00 | 549 | This function reverses the byte order in two unsigned short values. |
igor_v | 0:8ad47e2b6f00 | 550 | |
igor_v | 0:8ad47e2b6f00 | 551 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 552 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 553 | */ |
igor_v | 0:8ad47e2b6f00 | 554 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 555 | { |
igor_v | 1:f2adcae3d304 | 556 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 557 | |
igor_v | 1:f2adcae3d304 | 558 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 1:f2adcae3d304 | 559 | return(result); |
igor_v | 0:8ad47e2b6f00 | 560 | } |
igor_v | 0:8ad47e2b6f00 | 561 | |
igor_v | 0:8ad47e2b6f00 | 562 | |
igor_v | 0:8ad47e2b6f00 | 563 | /** \brief Reverse byte order in signed short value |
igor_v | 0:8ad47e2b6f00 | 564 | |
igor_v | 0:8ad47e2b6f00 | 565 | This function reverses the byte order in a signed short value with sign extension to integer. |
igor_v | 0:8ad47e2b6f00 | 566 | |
igor_v | 0:8ad47e2b6f00 | 567 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 568 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 569 | */ |
igor_v | 0:8ad47e2b6f00 | 570 | __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) |
igor_v | 0:8ad47e2b6f00 | 571 | { |
igor_v | 1:f2adcae3d304 | 572 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 573 | |
igor_v | 1:f2adcae3d304 | 574 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 1:f2adcae3d304 | 575 | return(result); |
igor_v | 0:8ad47e2b6f00 | 576 | } |
igor_v | 0:8ad47e2b6f00 | 577 | |
igor_v | 0:8ad47e2b6f00 | 578 | |
igor_v | 0:8ad47e2b6f00 | 579 | #if (__CORTEX_M >= 0x03) |
igor_v | 0:8ad47e2b6f00 | 580 | |
igor_v | 0:8ad47e2b6f00 | 581 | /** \brief Reverse bit order of value |
igor_v | 0:8ad47e2b6f00 | 582 | |
igor_v | 0:8ad47e2b6f00 | 583 | This function reverses the bit order of the given value. |
igor_v | 0:8ad47e2b6f00 | 584 | |
igor_v | 0:8ad47e2b6f00 | 585 | \param [in] value Value to reverse |
igor_v | 0:8ad47e2b6f00 | 586 | \return Reversed value |
igor_v | 0:8ad47e2b6f00 | 587 | */ |
igor_v | 0:8ad47e2b6f00 | 588 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 589 | { |
igor_v | 1:f2adcae3d304 | 590 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 591 | |
igor_v | 1:f2adcae3d304 | 592 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 1:f2adcae3d304 | 593 | return(result); |
igor_v | 0:8ad47e2b6f00 | 594 | } |
igor_v | 0:8ad47e2b6f00 | 595 | |
igor_v | 0:8ad47e2b6f00 | 596 | |
igor_v | 0:8ad47e2b6f00 | 597 | /** \brief LDR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 598 | |
igor_v | 0:8ad47e2b6f00 | 599 | This function performs a exclusive LDR command for 8 bit value. |
igor_v | 0:8ad47e2b6f00 | 600 | |
igor_v | 0:8ad47e2b6f00 | 601 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 602 | \return value of type uint8_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 603 | */ |
igor_v | 0:8ad47e2b6f00 | 604 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) |
igor_v | 0:8ad47e2b6f00 | 605 | { |
igor_v | 0:8ad47e2b6f00 | 606 | uint8_t result; |
igor_v | 1:f2adcae3d304 | 607 | |
igor_v | 1:f2adcae3d304 | 608 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 1:f2adcae3d304 | 609 | return(result); |
igor_v | 0:8ad47e2b6f00 | 610 | } |
igor_v | 0:8ad47e2b6f00 | 611 | |
igor_v | 0:8ad47e2b6f00 | 612 | |
igor_v | 0:8ad47e2b6f00 | 613 | /** \brief LDR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 614 | |
igor_v | 0:8ad47e2b6f00 | 615 | This function performs a exclusive LDR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 616 | |
igor_v | 0:8ad47e2b6f00 | 617 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 618 | \return value of type uint16_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 619 | */ |
igor_v | 0:8ad47e2b6f00 | 620 | __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) |
igor_v | 0:8ad47e2b6f00 | 621 | { |
igor_v | 0:8ad47e2b6f00 | 622 | uint16_t result; |
igor_v | 1:f2adcae3d304 | 623 | |
igor_v | 1:f2adcae3d304 | 624 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 1:f2adcae3d304 | 625 | return(result); |
igor_v | 0:8ad47e2b6f00 | 626 | } |
igor_v | 0:8ad47e2b6f00 | 627 | |
igor_v | 0:8ad47e2b6f00 | 628 | |
igor_v | 0:8ad47e2b6f00 | 629 | /** \brief LDR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 630 | |
igor_v | 0:8ad47e2b6f00 | 631 | This function performs a exclusive LDR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 632 | |
igor_v | 0:8ad47e2b6f00 | 633 | \param [in] ptr Pointer to data |
igor_v | 0:8ad47e2b6f00 | 634 | \return value of type uint32_t at (*ptr) |
igor_v | 0:8ad47e2b6f00 | 635 | */ |
igor_v | 0:8ad47e2b6f00 | 636 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) |
igor_v | 0:8ad47e2b6f00 | 637 | { |
igor_v | 0:8ad47e2b6f00 | 638 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 639 | |
igor_v | 1:f2adcae3d304 | 640 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
igor_v | 1:f2adcae3d304 | 641 | return(result); |
igor_v | 0:8ad47e2b6f00 | 642 | } |
igor_v | 0:8ad47e2b6f00 | 643 | |
igor_v | 0:8ad47e2b6f00 | 644 | |
igor_v | 0:8ad47e2b6f00 | 645 | /** \brief STR Exclusive (8 bit) |
igor_v | 0:8ad47e2b6f00 | 646 | |
igor_v | 0:8ad47e2b6f00 | 647 | This function performs a exclusive STR command for 8 bit values. |
igor_v | 0:8ad47e2b6f00 | 648 | |
igor_v | 0:8ad47e2b6f00 | 649 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 650 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 651 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 652 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 653 | */ |
igor_v | 0:8ad47e2b6f00 | 654 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
igor_v | 0:8ad47e2b6f00 | 655 | { |
igor_v | 1:f2adcae3d304 | 656 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 657 | |
igor_v | 1:f2adcae3d304 | 658 | __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 1:f2adcae3d304 | 659 | return(result); |
igor_v | 0:8ad47e2b6f00 | 660 | } |
igor_v | 0:8ad47e2b6f00 | 661 | |
igor_v | 0:8ad47e2b6f00 | 662 | |
igor_v | 0:8ad47e2b6f00 | 663 | /** \brief STR Exclusive (16 bit) |
igor_v | 0:8ad47e2b6f00 | 664 | |
igor_v | 0:8ad47e2b6f00 | 665 | This function performs a exclusive STR command for 16 bit values. |
igor_v | 0:8ad47e2b6f00 | 666 | |
igor_v | 0:8ad47e2b6f00 | 667 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 668 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 669 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 670 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 671 | */ |
igor_v | 0:8ad47e2b6f00 | 672 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
igor_v | 0:8ad47e2b6f00 | 673 | { |
igor_v | 1:f2adcae3d304 | 674 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 675 | |
igor_v | 1:f2adcae3d304 | 676 | __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 1:f2adcae3d304 | 677 | return(result); |
igor_v | 0:8ad47e2b6f00 | 678 | } |
igor_v | 0:8ad47e2b6f00 | 679 | |
igor_v | 0:8ad47e2b6f00 | 680 | |
igor_v | 0:8ad47e2b6f00 | 681 | /** \brief STR Exclusive (32 bit) |
igor_v | 0:8ad47e2b6f00 | 682 | |
igor_v | 0:8ad47e2b6f00 | 683 | This function performs a exclusive STR command for 32 bit values. |
igor_v | 0:8ad47e2b6f00 | 684 | |
igor_v | 0:8ad47e2b6f00 | 685 | \param [in] value Value to store |
igor_v | 0:8ad47e2b6f00 | 686 | \param [in] ptr Pointer to location |
igor_v | 0:8ad47e2b6f00 | 687 | \return 0 Function succeeded |
igor_v | 0:8ad47e2b6f00 | 688 | \return 1 Function failed |
igor_v | 0:8ad47e2b6f00 | 689 | */ |
igor_v | 0:8ad47e2b6f00 | 690 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
igor_v | 0:8ad47e2b6f00 | 691 | { |
igor_v | 1:f2adcae3d304 | 692 | uint32_t result; |
igor_v | 1:f2adcae3d304 | 693 | |
igor_v | 1:f2adcae3d304 | 694 | __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); |
igor_v | 1:f2adcae3d304 | 695 | return(result); |
igor_v | 0:8ad47e2b6f00 | 696 | } |
igor_v | 0:8ad47e2b6f00 | 697 | |
igor_v | 0:8ad47e2b6f00 | 698 | |
igor_v | 0:8ad47e2b6f00 | 699 | /** \brief Remove the exclusive lock |
igor_v | 0:8ad47e2b6f00 | 700 | |
igor_v | 0:8ad47e2b6f00 | 701 | This function removes the exclusive lock which is created by LDREX. |
igor_v | 0:8ad47e2b6f00 | 702 | |
igor_v | 0:8ad47e2b6f00 | 703 | */ |
igor_v | 0:8ad47e2b6f00 | 704 | __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) |
igor_v | 0:8ad47e2b6f00 | 705 | { |
igor_v | 1:f2adcae3d304 | 706 | __ASM volatile ("clrex"); |
igor_v | 0:8ad47e2b6f00 | 707 | } |
igor_v | 0:8ad47e2b6f00 | 708 | |
igor_v | 0:8ad47e2b6f00 | 709 | |
igor_v | 0:8ad47e2b6f00 | 710 | /** \brief Signed Saturate |
igor_v | 0:8ad47e2b6f00 | 711 | |
igor_v | 0:8ad47e2b6f00 | 712 | This function saturates a signed value. |
igor_v | 0:8ad47e2b6f00 | 713 | |
igor_v | 0:8ad47e2b6f00 | 714 | \param [in] value Value to be saturated |
igor_v | 0:8ad47e2b6f00 | 715 | \param [in] sat Bit position to saturate to (1..32) |
igor_v | 0:8ad47e2b6f00 | 716 | \return Saturated value |
igor_v | 0:8ad47e2b6f00 | 717 | */ |
igor_v | 0:8ad47e2b6f00 | 718 | #define __SSAT(ARG1,ARG2) \ |
igor_v | 0:8ad47e2b6f00 | 719 | ({ \ |
igor_v | 0:8ad47e2b6f00 | 720 | uint32_t __RES, __ARG1 = (ARG1); \ |
igor_v | 0:8ad47e2b6f00 | 721 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
igor_v | 0:8ad47e2b6f00 | 722 | __RES; \ |
igor_v | 0:8ad47e2b6f00 | 723 | }) |
igor_v | 0:8ad47e2b6f00 | 724 | |
igor_v | 0:8ad47e2b6f00 | 725 | |
igor_v | 0:8ad47e2b6f00 | 726 | /** \brief Unsigned Saturate |
igor_v | 0:8ad47e2b6f00 | 727 | |
igor_v | 0:8ad47e2b6f00 | 728 | This function saturates an unsigned value. |
igor_v | 0:8ad47e2b6f00 | 729 | |
igor_v | 0:8ad47e2b6f00 | 730 | \param [in] value Value to be saturated |
igor_v | 0:8ad47e2b6f00 | 731 | \param [in] sat Bit position to saturate to (0..31) |
igor_v | 0:8ad47e2b6f00 | 732 | \return Saturated value |
igor_v | 0:8ad47e2b6f00 | 733 | */ |
igor_v | 0:8ad47e2b6f00 | 734 | #define __USAT(ARG1,ARG2) \ |
igor_v | 0:8ad47e2b6f00 | 735 | ({ \ |
igor_v | 0:8ad47e2b6f00 | 736 | uint32_t __RES, __ARG1 = (ARG1); \ |
igor_v | 0:8ad47e2b6f00 | 737 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
igor_v | 0:8ad47e2b6f00 | 738 | __RES; \ |
igor_v | 0:8ad47e2b6f00 | 739 | }) |
igor_v | 0:8ad47e2b6f00 | 740 | |
igor_v | 0:8ad47e2b6f00 | 741 | |
igor_v | 0:8ad47e2b6f00 | 742 | /** \brief Count leading zeros |
igor_v | 0:8ad47e2b6f00 | 743 | |
igor_v | 0:8ad47e2b6f00 | 744 | This function counts the number of leading zeros of a data value. |
igor_v | 0:8ad47e2b6f00 | 745 | |
igor_v | 0:8ad47e2b6f00 | 746 | \param [in] value Value to count the leading zeros |
igor_v | 0:8ad47e2b6f00 | 747 | \return number of leading zeros in value |
igor_v | 0:8ad47e2b6f00 | 748 | */ |
igor_v | 0:8ad47e2b6f00 | 749 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) |
igor_v | 0:8ad47e2b6f00 | 750 | { |
igor_v | 1:f2adcae3d304 | 751 | uint8_t result; |
igor_v | 1:f2adcae3d304 | 752 | |
igor_v | 1:f2adcae3d304 | 753 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); |
igor_v | 1:f2adcae3d304 | 754 | return(result); |
igor_v | 0:8ad47e2b6f00 | 755 | } |
igor_v | 0:8ad47e2b6f00 | 756 | |
igor_v | 0:8ad47e2b6f00 | 757 | #endif /* (__CORTEX_M >= 0x03) */ |
igor_v | 0:8ad47e2b6f00 | 758 | |
igor_v | 0:8ad47e2b6f00 | 759 | |
igor_v | 0:8ad47e2b6f00 | 760 | |
igor_v | 0:8ad47e2b6f00 | 761 | |
igor_v | 0:8ad47e2b6f00 | 762 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ |
igor_v | 0:8ad47e2b6f00 | 763 | /* TASKING carm specific functions */ |
igor_v | 0:8ad47e2b6f00 | 764 | |
igor_v | 0:8ad47e2b6f00 | 765 | /* |
igor_v | 0:8ad47e2b6f00 | 766 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
igor_v | 0:8ad47e2b6f00 | 767 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
igor_v | 0:8ad47e2b6f00 | 768 | * Including the CMSIS ones. |
igor_v | 0:8ad47e2b6f00 | 769 | */ |
igor_v | 0:8ad47e2b6f00 | 770 | |
igor_v | 0:8ad47e2b6f00 | 771 | #endif |
igor_v | 0:8ad47e2b6f00 | 772 | |
igor_v | 0:8ad47e2b6f00 | 773 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
igor_v | 0:8ad47e2b6f00 | 774 | |
igor_v | 0:8ad47e2b6f00 | 775 | #endif /* __CORE_CMINSTR_H__ */ |
igor_v | 0:8ad47e2b6f00 | 776 |