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LPC_UART1_TypeDef Struct Reference
Data Fields

LPC_UART1_TypeDef Struct Reference
[LPC17xx_System]

Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition. More...

#include <LPC17xx.h>

Data Fields

__IO uint32_t LCR
__IO uint32_t MCR
__I uint32_t LSR
__I uint32_t MSR
__IO uint32_t SCR
__IO uint32_t ACR
__IO uint32_t FDR
__IO uint32_t TER
__IO uint32_t RS485CTRL
__IO uint32_t ADRMATCH
__IO uint32_t RS485DLY
__I uint32_t RBR
__O uint32_t THR
__IO uint32_t DLL
__IO uint32_t DLM
__IO uint32_t IER
__I uint32_t IIR
__O uint32_t FCR

Detailed Description

Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition.

Definition at line 371 of file LPC17xx.h.

Field Documentation

__IO uint32_t ACR

Offset: 0x020 Auto-baud Control Register (R/W)

Definition at line 391 of file LPC17xx.h.

__IO uint32_t ADRMATCH

Offset: 0x050 RS-485/EIA-485 address match Register (R/W)

Definition at line 398 of file LPC17xx.h.

__IO uint32_t DLL

Offset: 0x000 Divisor Latch LSB (R/W)

Definition at line 376 of file LPC17xx.h.

__IO uint32_t DLM

Offset: 0x004 Divisor Latch MSB (R/W)

Definition at line 379 of file LPC17xx.h.

__O uint32_t FCR

Offset: 0x008 FIFO Control Register ( /W)

Definition at line 384 of file LPC17xx.h.

__IO uint32_t FDR

Offset: 0x028 Fractional Divider Register (R/W)

Definition at line 393 of file LPC17xx.h.

__IO uint32_t IER

Offset: 0x000 Interrupt Enable Register (R/W)

Definition at line 380 of file LPC17xx.h.

__I uint32_t IIR

Offset: 0x008 Interrupt ID Register (R/ )

Definition at line 383 of file LPC17xx.h.

__IO uint32_t LCR

Offset: 0x00C Line Control Register (R/W)

Definition at line 386 of file LPC17xx.h.

__I uint32_t LSR

Offset: 0x014 Line Status Register (R/ )

Definition at line 388 of file LPC17xx.h.

__IO uint32_t MCR

Offset: 0x010 Modem control Register (R/W)

Definition at line 387 of file LPC17xx.h.

__I uint32_t MSR

Offset: 0x018 Modem status Register (R/ )

Definition at line 389 of file LPC17xx.h.

__I uint32_t RBR

Offset: 0x000 Receiver Buffer Register (R/ )

Definition at line 374 of file LPC17xx.h.

__IO uint32_t RS485CTRL

Offset: 0x04C RS-485/EIA-485 Control Register (R/W)

Definition at line 397 of file LPC17xx.h.

__IO uint32_t RS485DLY

Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W)

Definition at line 399 of file LPC17xx.h.

__IO uint32_t SCR

Offset: 0x01C Scratch Pad Register (R/W)

Definition at line 390 of file LPC17xx.h.

__IO uint32_t TER

Offset: 0x030 Transmit Enable Register (R/W)

Definition at line 395 of file LPC17xx.h.

__O uint32_t THR

Offset: 0x000 Transmit Holding Register ( /W)

Definition at line 375 of file LPC17xx.h.

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