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LPC_SSP_TypeDef Struct Reference
Data Fields

LPC_SSP_TypeDef Struct Reference
[LPC17xx_System]

Synchronous Serial Communication (SSP) register structure definition. More...

#include <LPC17xx.h>

Data Fields

__IO uint32_t CR0
__IO uint32_t CR1
__IO uint32_t DR
__I uint32_t SR
__IO uint32_t CPSR
__IO uint32_t IMSC
__IO uint32_t RIS
__IO uint32_t MIS
__IO uint32_t ICR
__IO uint32_t DMACR

Detailed Description

Synchronous Serial Communication (SSP) register structure definition.

Definition at line 416 of file LPC17xx.h.

Field Documentation

__IO uint32_t CPSR

Offset: 0x010 (R/W) Clock Prescale Register

Definition at line 422 of file LPC17xx.h.

__IO uint32_t CR0

Offset: 0x000 (R/W) Control Register 0

Definition at line 418 of file LPC17xx.h.

__IO uint32_t CR1

Offset: 0x004 (R/W) Control Register 1

Definition at line 419 of file LPC17xx.h.

__IO uint32_t DMACR

Offset: 0x024 (R/W) DMA Control Register

Definition at line 427 of file LPC17xx.h.

__IO uint32_t DR

Offset: 0x008 (R/W) Data Register

Definition at line 420 of file LPC17xx.h.

__IO uint32_t ICR

Offset: 0x020 (R/W) SSPICR Interrupt Clear Register

Definition at line 426 of file LPC17xx.h.

__IO uint32_t IMSC

Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register

Definition at line 423 of file LPC17xx.h.

__IO uint32_t MIS

Offset: 0x01C (R/W) Masked Interrupt Status Register

Definition at line 425 of file LPC17xx.h.

__IO uint32_t RIS

Offset: 0x018 (R/W) Raw Interrupt Status Register

Definition at line 424 of file LPC17xx.h.

__I uint32_t SR

Offset: 0x00C (R/ ) Status Register

Definition at line 421 of file LPC17xx.h.

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