LPC_MCPWM_TypeDef Struct Reference
[LPC17xx_System]

Offset: 0x044 (R/W) Capture Register, channel 0

Definition at line 574 of file LPC17xx.h.

Offset: 0x048 (R/W) Capture Register, channel 1

Definition at line 575 of file LPC17xx.h.

Offset: 0x04C (R/W) Capture Register, channel 2

Definition at line 576 of file LPC17xx.h.

Offset: 0x074 ( /W) Capture clear address Register

Definition at line 586 of file LPC17xx.h.

Offset: 0x00C (R/ ) Capture Control read address Register

Definition at line 560 of file LPC17xx.h.

Offset: 0x014 ( /W) Event Control clear address Register

Definition at line 562 of file LPC17xx.h.

Offset: 0x010 ( /W) Capture Control set address Register

Definition at line 561 of file LPC17xx.h.

Offset: 0x05C (R/ ) Count Control read address Register

Definition at line 580 of file LPC17xx.h.

Offset: 0x064 ( /W) Count Control clear address Register

Definition at line 582 of file LPC17xx.h.

Offset: 0x060 ( /W) Count Control set address Register

Definition at line 581 of file LPC17xx.h.

Offset: 0x000 (R/ ) PWM Control read address Register

Definition at line 557 of file LPC17xx.h.

Offset: 0x008 ( /W) PWM Control clear address Register

Definition at line 559 of file LPC17xx.h.

Offset: 0x004 ( /W) PWM Control set address Register

Definition at line 558 of file LPC17xx.h.

Offset: 0x040 (R/W) Commutation Pattern Register

Definition at line 573 of file LPC17xx.h.

Offset: 0x03C (R/W) Dead time Register

Definition at line 572 of file LPC17xx.h.

Offset: 0x050 (R/ ) Interrupt Enable read Register

Definition at line 577 of file LPC17xx.h.

Offset: 0x058 ( /W) Interrupt Enable clear address Register

Definition at line 579 of file LPC17xx.h.

Offset: 0x054 ( /W) Interrupt Enable set address Register

Definition at line 578 of file LPC17xx.h.

Offset: 0x068 (R/ ) Interrupt flags read address Register

Definition at line 583 of file LPC17xx.h.

Offset: 0x070 ( /W) Interrupt flags clear address Register

Definition at line 585 of file LPC17xx.h.

Offset: 0x06C ( /W) Interrupt flags set address Register

Definition at line 584 of file LPC17xx.h.

Offset: 0x024 (R/W) Limit Register, channel 0

Definition at line 566 of file LPC17xx.h.

Offset: 0x028 (R/W) Limit Register, channel 1

Definition at line 567 of file LPC17xx.h.

Offset: 0x02C (R/W) Limit Register, channel 2

Definition at line 568 of file LPC17xx.h.

Offset: 0x030 (R/W) Match Register, channel 0

Definition at line 569 of file LPC17xx.h.

Offset: 0x034 (R/W) Match Register, channel 1

Definition at line 570 of file LPC17xx.h.

Offset: 0x038 (R/W) Match Register, channel 2

Definition at line 571 of file LPC17xx.h.

Offset: 0x018 (R/W) Timer Counter Register, channel 0

Definition at line 563 of file LPC17xx.h.

Offset: 0x01C (R/W) Timer Counter Register, channel 1

Definition at line 564 of file LPC17xx.h.

Offset: 0x020 (R/W) Timer Counter Register, channel 2

Definition at line 565 of file LPC17xx.h.