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LPC_I2S_TypeDef Struct Reference
Inter IC Sound (I2S) register structure definition.
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#include <LPC17xx.h >
Detailed Description
Inter IC Sound (I2S) register structure definition.
Definition at line 454 of file LPC17xx.h .
Field Documentation
Offset: 0x004 (R/W) Digital Audio Input Register
Definition at line 457 of file LPC17xx.h .
Offset: 0x000 (R/W) Digital Audio Output Register
Definition at line 456 of file LPC17xx.h .
Offset: 0x014 (R/W) DMA Configuration Register 1
Definition at line 461 of file LPC17xx.h .
Offset: 0x018 (R/W) DMA Configuration Register 2
Definition at line 462 of file LPC17xx.h .
Offset: 0x01C (R/W) Interrupt Request Control Register
Definition at line 463 of file LPC17xx.h .
Offset: 0x02C (R/W) Receive bit rate divider Register
Definition at line 467 of file LPC17xx.h .
Offset: 0x00C (R/ ) Receive FIFO
Definition at line 459 of file LPC17xx.h .
Offset: 0x034 (R/W) Receive mode control Register
Definition at line 469 of file LPC17xx.h .
Offset: 0x024 (R/W) Receive reference clock divider Register
Definition at line 465 of file LPC17xx.h .
Offset: 0x010 (R/W) Status Feedback Register
Definition at line 460 of file LPC17xx.h .
Offset: 0x028 (R/W) Transmit bit rate divider Register
Definition at line 466 of file LPC17xx.h .
Offset: 0x008 ( /W) Transmit FIFO
Definition at line 458 of file LPC17xx.h .
Offset: 0x030 (R/W) Transmit mode control Register
Definition at line 468 of file LPC17xx.h .
Offset: 0x020 (R/W) Transmit reference clock divider Register
Definition at line 464 of file LPC17xx.h .