LPC_EMAC_TypeDef Struct Reference
[LPC17xx_System]

Offset: 0x010 (R/W) Collision Window / Retry Register

Definition at line 821 of file LPC17xx.h.

Offset: 0x100 (R/W) Command Register

Definition at line 836 of file LPC17xx.h.

Offset: 0x170 (R/W) Flow Control Counter Register

Definition at line 853 of file LPC17xx.h.

Offset: 0x174 (R/ ) Flow Control Status egister

Definition at line 854 of file LPC17xx.h.

Offset: 0x214 (R/W) Hash Filter Table MSBs Register

Definition at line 861 of file LPC17xx.h.

Offset: 0x210 (R/W) Hash Filter Table LSBs Register

Definition at line 860 of file LPC17xx.h.

Offset: 0xFE8 ( /W) Interrupt Clear Register

Definition at line 865 of file LPC17xx.h.

Offset: 0xFE4 (R/W) Interrupt Enable Register

Definition at line 864 of file LPC17xx.h.

Offset: 0xFEC ( /W) Interrupt Set Register

Definition at line 866 of file LPC17xx.h.

Offset: 0xFE0 (R/ ) Interrupt Status Register

Definition at line 863 of file LPC17xx.h.

Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register

Definition at line 820 of file LPC17xx.h.

Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register

Definition at line 819 of file LPC17xx.h.

Offset: 0x000 (R/W) MAC Configuration Register 1

Definition at line 817 of file LPC17xx.h.

Offset: 0x004 (R/W) MAC Configuration Register 2

Definition at line 818 of file LPC17xx.h.

Offset: 0x028 (R/W) MII Mgmt Address Register

Definition at line 827 of file LPC17xx.h.

Offset: 0x014 (R/W) Maximum Frame Register

Definition at line 822 of file LPC17xx.h.

Offset: 0x020 (R/W) MII Mgmt Configuration Register

Definition at line 825 of file LPC17xx.h.

Offset: 0x024 (R/W) MII Mgmt Command Register

Definition at line 826 of file LPC17xx.h.

Offset: 0x034 (R/ ) MII Mgmt Indicators Register

Definition at line 830 of file LPC17xx.h.

Offset: 0x030 (R/ ) MII Mgmt Read Data Register

Definition at line 829 of file LPC17xx.h.

Offset: 0x02C ( /W) MII Mgmt Write Data Register

Definition at line 828 of file LPC17xx.h.

Offset: 0xFF4 (R/W) Power-Down Register

Definition at line 868 of file LPC17xx.h.

Offset: 0x160 (R/ ) Receive Status Vector Register

Definition at line 851 of file LPC17xx.h.

Offset: 0x118 (R/W) Receive Consume Index Register

Definition at line 842 of file LPC17xx.h.

Offset: 0x108 (R/W) Receive Descriptor Base Address Register

Definition at line 838 of file LPC17xx.h.

Offset: 0x110 (R/W) Receive Number of Descriptors Register

Definition at line 840 of file LPC17xx.h.

Offset: 0x200 (R/W) Receive Filter Control Register

Definition at line 856 of file LPC17xx.h.

Offset: 0x208 ( /W) Receive Filter WoL Clear Register

Definition at line 858 of file LPC17xx.h.

Offset: 0x204 (R/ ) Receive Filter WoL Status Register

Definition at line 857 of file LPC17xx.h.

Offset: 0x114 (R/ ) Receive Produce Index Register

Definition at line 841 of file LPC17xx.h.

Offset: 0x10C (R/W) Receive Status Base Address Register

Definition at line 839 of file LPC17xx.h.

Offset: 0x040 (R/W) Station Address 0 Register

Definition at line 832 of file LPC17xx.h.

Offset: 0x044 (R/W) Station Address 1 Register

Definition at line 833 of file LPC17xx.h.

Offset: 0x048 (R/W) Station Address 2 Register

Definition at line 834 of file LPC17xx.h.

Offset: 0x104 (R/ ) Status Register

Definition at line 837 of file LPC17xx.h.

Offset: 0x018 (R/W) PHY Support Register

Definition at line 823 of file LPC17xx.h.

Offset: 0x01C (R/W) Test Register

Definition at line 824 of file LPC17xx.h.

Offset: 0x158 (R/ ) Transmit Status Vector 0 Register

Definition at line 849 of file LPC17xx.h.

Offset: 0x15C (R/ ) Transmit Status Vector 1 Register

Definition at line 850 of file LPC17xx.h.

Offset: 0x12C (R/ ) Transmit Consume Index Register

Definition at line 847 of file LPC17xx.h.

Offset: 0x11C (R/W) Transmit Descriptor Base Address Register

Definition at line 843 of file LPC17xx.h.

Offset: 0x124 (R/W) Transmit Number of Descriptors Register

Definition at line 845 of file LPC17xx.h.

Offset: 0x128 (R/W) Transmit Produce Index Register

Definition at line 846 of file LPC17xx.h.

Offset: 0x120 (R/W) Transmit Status Base Address Register

Definition at line 844 of file LPC17xx.h.