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Diff: system_LPC17xx.c
- Revision:
- 136:19b9e6abb86f
- Parent:
- 135:c1e30e0e8949
- Child:
- 150:29c9f7671bac
diff -r c1e30e0e8949 -r 19b9e6abb86f system_LPC17xx.c --- a/system_LPC17xx.c Thu Apr 14 16:48:48 2016 +0000 +++ b/system_LPC17xx.c Fri Apr 15 14:20:15 2016 +0000 @@ -463,7 +463,7 @@ // 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices. // 31:16 - Reserved. The value read from a reserved bit is not defined. NA -#define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access 30720 +#define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access /* //-------- <<< end of configuration section >>> ------------------------------ @@ -702,106 +702,6 @@ -void SystemInitDef1 (void) -{ - - -#if (CLOCK_SETUP) /* Clock Setup */ - LPC_SC->SCS = SCS_Val; - if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ - while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ - } - - LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ - - LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ - LPC_SC->PCLKSEL1 = PCLKSEL1_Val; - -#if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ - LPC_SC->PLL0CFG = PLL0CFG_Val; - LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ - - LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; -#endif - -#if (PLL1_SETUP) - LPC_SC->PLL1CFG = PLL1CFG_Val; - LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ - - LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; -#else - LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ -#endif - - LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ - - LPC_SC->CLKOUTCFG = 0x0000303A;//CLKOUTCFG_Val; /* Clock Output Configuration */ -#endif - - /* Determine clock frequency according to clock register values */ - if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */ - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Internal RC oscillator => PLL0 */ - case 3: /* Reserved, default to Internal RC */ - SystemFrequency = (IRC_OSC * - (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 1: /* Main oscillator => PLL0 */ - SystemFrequency = (OSC_CLK * - (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemFrequency = (RTC_CLK * - (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); - break; - } - } else { - switch (LPC_SC->CLKSRCSEL & 0x03) { - case 0: /* Internal RC oscillator => PLL0 */ - case 3: /* Reserved, default to Internal RC */ - SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 1: /* Main oscillator => PLL0 */ - SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - case 2: /* RTC oscillator => PLL0 */ - SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); - break; - } - } - -#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ - LPC_SC->FLASHCFG = FLASHCFG_Val; -#endif - -} - - - - - - - - - - void SystemInitDef (void) @@ -820,7 +720,7 @@ LPC_SC->PCLKSEL1 = PCLKSEL1_Val; #if (PLL0_SETUP) - LPC_SC->CLKSRCSEL = 0; CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ + LPC_SC->CLKSRCSEL = 0;// CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ LPC_SC->PLL0CFG = PLL0CFG_Val; LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ LPC_SC->PLL0FEED = 0xAA; @@ -858,8 +758,8 @@ case 3: /* Reserved, default to Internal RC */ SystemFrequency = (IRC_OSC * (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / - (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / - ((LPC_SC->CCLKCFG & 0xFF)+ 1)); + (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / + ((LPC_SC->CCLKCFG & 0xFF)+ 1)); break; case 1: /* Main oscillator => PLL0 */ SystemFrequency = (OSC_CLK *