Dmitry Kovalev
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LGfiltr
forkd
Fork of LGstaandart by
Diff: system_LPC17xx.c
- Revision:
- 49:53277d871197
- Parent:
- 46:2670fa0fcebc
- Child:
- 116:66f1f0ff2dab
--- a/system_LPC17xx.c Wed Feb 10 15:58:16 2016 +0000 +++ b/system_LPC17xx.c Thu Feb 11 02:55:35 2016 +0000 @@ -338,7 +338,7 @@ // 01 PCLK_peripheral = CCLK // 10 PCLK_peripheral = CCLK/2 // 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6. -#define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK +#define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4 //Peripheral Clock Selection register 1 // 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00 // 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 @@ -356,9 +356,53 @@ // 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00 // 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00 // 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x046887DE -#define CLKOUTCFG_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000//CCLK/4 +//Power Control for Peripherals register +//0 - Reserved. NA +//1 PCTIM0 Timer/Counter 0 power/clock control bit. 1 +//2 PCTIM1 Timer/Counter 1 power/clock control bit. 1 +//3 PCUART0 UART0 power/clock control bit. 1 +//4 PCUART1 UART1 power/clock control bit. 1 +//5 - Reserved. NA +//6 PCPWM1 PWM1 power/clock control bit. 1 +//7 PCI2C0 The I2C0 interface power/clock control bit. 1 +//8 PCSPI The SPI interface power/clock control bit. 1 +//9 PCRTC The RTC power/clock control bit. 1 +//10 PCSSP1 The SSP 1 interface power/clock control bit. 1 +//11 - Reserved. NA +//12 PCADC A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. 0 +//13 PCCAN1 CAN Controller 1 power/clock control bit. 0 +//14 PCCAN2 CAN Controller 2 power/clock control bit. 0 +//15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1 +//16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0 +//17 PCMCPWM Motor Control PWM 0 +//18 PCQEI Quadrature Encoder Interface power/clock control bit. 0 +//19 PCI2C1 The I2C1 interface power/clock control bit. 1 +//20 - Reserved. NA +//21 PCSSP0 The SSP0 interface power/clock control bit. 1 +//22 PCTIM2 Timer 2 power/clock control bit. 0 +//23 PCTIM3 Timer 3 power/clock control bit. 0 +//24 PCUART2 UART 2 power/clock control bit. 0 +//25 PCUART3 UART 3 power/clock control bit. 0 +//26 PCI2C2 I2C interface 2 power/clock control bit. 1 +#define PCONP_Val 0x046887DE//ADC,CAN1/2,RIT,Timer3,UART2,UART3 disabled +//Clock Output Configuration register +// 3:0 CLKOUTSEL Selects the clock source for the CLKOUT function. 0 +// 0000 Selects the CPU clock as the CLKOUT source. +// 0001 Selects the main oscillator as the CLKOUT source. +// 0010 Selects the Internal RC oscillator as the CLKOUT source. +// 0011 Selects the USB clock as the CLKOUT source. +// 0100 Selects the RTC oscillator as the CLKOUT source. +// Others Reserved, do not use these settings. +// 7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0 +// 0000 Clock is divided by 1. +// 0001 Clock is divided by 2. +// 0010 Clock is divided by 3. +// ... ... +// 1111 Clock is divided by 16. +// 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. 0 +// 9 CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. +#define CLKOUTCFG_Val 0x00000000//Host4: CLKOUT pin not used /*--------------------- Flash Accelerator Configuration ----------------------